reset_state();
m_state = S_STARTED;
atomic receivingPacket = FALSE;
+ /* Note:
+ We use the falling edge because the FIFOP polarity is reversed.
+ This is done in CC2420Power.startOscillator from CC2420ControlP.nc.
+ */
call InterruptFIFOP.enableFallingEdge();
}
return SUCCESS;
call SpiResource.release();
}
- if ( m_timestamp_size ) {
- if ( rxFrameLength > 10 ) {
- call PacketTimeStamp.set(m_p_rx_buf, m_timestamp_queue[ m_timestamp_head ]);
+ //new packet is buffered up, or we don't have timestamp in fifo, or ack
+ if ( ( m_missed_packets && call FIFO.get() ) || !call FIFOP.get()
+ || !m_timestamp_size
+ || rxFrameLength <= 10) {
+ call PacketTimeStamp.clear(m_p_rx_buf);
+ }
+ else {
+ if (m_timestamp_size==1)
+ call PacketTimeStamp.set(m_p_rx_buf, m_timestamp_queue[ m_timestamp_head ]);
m_timestamp_head = ( m_timestamp_head + 1 ) % TIMESTAMP_QUEUE_SIZE;
m_timestamp_size--;
- }
- } else {
- call PacketTimeStamp.clear(m_p_rx_buf);
+
+ if (m_timestamp_size>0) {
+ call PacketTimeStamp.clear(m_p_rx_buf);
+ m_timestamp_head = 0;
+ m_timestamp_size = 0;
+ }
}
-
+
// We may have received an ack that should be processed by Transmit
// buf[rxFrameLength] >> 7 checks the CRC
if ( ( buf[ rxFrameLength ] >> 7 ) && rx_buf ) {