provides interface HplMsp430GeneralIO as Port57;
#endif
-#if defined(__MSP430_HAS_PORT6_) || defined(__MSP430_HAS_PORT6_R__)
+#if defined(__MSP430_HAS_PORT6__) || defined(__MSP430_HAS_PORT6_R__)
provides interface HplMsp430GeneralIO as Port60;
provides interface HplMsp430GeneralIO as Port61;
provides interface HplMsp430GeneralIO as Port62;
#endif
// Interfaces for USCI0, ports A and B
-#if defined(__MSP430_HAS_USCI_AB0__)
+#if defined(__MSP430_HAS_USCI_AB0__) || defined(__MSP430_HAS_USCI__)
provides interface HplMsp430GeneralIO as UCA0CLK;
provides interface HplMsp430GeneralIO as UCA0STE;
provides interface HplMsp430GeneralIO as UCA0TXD;
URXD1 = P37;
#endif
-#if defined(__MSP430_HAS_USCI_AB0__)
+#if defined(__MSP430_HAS_USCI_AB0__) || defined(__MSP430_HAS_USCI__)
+ /* TODO: these mappings are broken for many parts defining
+ * __MSP430_HAS_USCI__. For example, the MSP420F2112 has USCI pin
+ * assignements different than below. Further, the pin assignements vary
+ * by package.
+ */
UCA0CLK = P30;
UCA0STE = P33;
UCA0TXD = P34;