Comment about USCI pin mapping problems.

[tinyos-2.x.git] / tos / chips / msp430 / pins / HplMsp430GeneralIOC.nc

diff --git a/tos/chips/msp430/pins/HplMsp430GeneralIOC.nc b/tos/chips/msp430/pins/HplMsp430GeneralIOC.nc
index b174dbf915bb5edecb7d03dc9608ea8e578ac6a5..0defab4eca56074b255256c9792995ebb35f7721 100644 (file)
--- a/tos/chips/msp430/pins/HplMsp430GeneralIOC.nc
+++ b/tos/chips/msp430/pins/HplMsp430GeneralIOC.nc
@@ -164,7 +164,7 @@ configuration HplMsp430GeneralIOC
 #endif
 
   // Interfaces for USCI0, ports A and B
-#if defined(__MSP430_HAS_USCI_AB0__)
+#if defined(__MSP430_HAS_USCI_AB0__) || defined(__MSP430_HAS_USCI__)
   provides interface HplMsp430GeneralIO as UCA0CLK;
   provides interface HplMsp430GeneralIO as UCA0STE;
   provides interface HplMsp430GeneralIO as UCA0TXD;
@@ -547,7 +547,12 @@ implementation
   URXD1 = P37;
 #endif
 
-#if defined(__MSP430_HAS_USCI_AB0__)
+#if defined(__MSP430_HAS_USCI_AB0__) || defined(__MSP430_HAS_USCI__)
+  /* TODO: these mappings are broken for many parts defining
+   * __MSP430_HAS_USCI__.  For example, the MSP420F2112 has USCI pin
+   * assignements different than below.  Further, the pin assignements vary
+   * by package.
+   */
   UCA0CLK = P30;
   UCA0STE = P33;
   UCA0TXD = P34;