-/*
- * Copyright (c) 2004-2005, Technische Universitat Berlin
+/**
+ * Copyright (c) 2005-2006 Arched Rock Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of the Arched Rock Corporation nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * ARCHED ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE
+ */
+
+/**
+ * Copyright (c) 2004-2005, Technische Universitaet Berlin
* All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- * - Neither the name of the Technische Universitat Berlin nor the names
+ * - Neither the name of the Technische Universitaet Berlin nor the names
* of its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
- * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * - Revision -------------------------------------------------------------
- * $Revision$
- * $Date$
- * ========================================================================
*/
+#include "msp430usart.h"
/**
- * Implementation of USART0 lowlevel functionality - stateless.
+ * Implementation of USART1 lowlevel functionality - stateless.
* Setting a mode will by default disable USART-Interrupts.
*
- * @author Jan Hauer (hauer@tkn.tu-berlin.de)
- * @author Joe Polastre
+ * @author: Jan Hauer <hauer@tkn.tu-berlin.de>
+ * @author: Jonathan Hui <jhui@archedrock.com>
+ * @author: Vlado Handziski <handzisk@tkn.tu-berlin.de>
+ * @author: Joe Polastre
+ * @version $Revision$ $Date$
*/
module HplMsp430Usart1P {
+ provides interface AsyncStdControl;
provides interface HplMsp430Usart as Usart;
- provides interface HplMsp430UsartInterrupts as UsartInterrupts;
+ provides interface HplMsp430UsartInterrupts as Interrupts;
uses interface HplMsp430GeneralIO as SIMO;
uses interface HplMsp430GeneralIO as SOMI;
uses interface HplMsp430GeneralIO as UCLK;
uses interface HplMsp430GeneralIO as URXD;
uses interface HplMsp430GeneralIO as UTXD;
+ uses interface HplMsp430InterruptSig as SIGNAL_UART1RX_VECTOR;
+ uses interface HplMsp430InterruptSig as SIGNAL_UART1TX_VECTOR;
}
+
implementation
{
MSP430REG_NORACE(IE2);
MSP430REG_NORACE(ME2);
MSP430REG_NORACE(IFG2);
MSP430REG_NORACE(U1TCTL);
+ MSP430REG_NORACE(U1RCTL);
MSP430REG_NORACE(U1TXBUF);
-
- uint16_t l_br;
- uint8_t l_mctl;
- uint8_t l_ssel;
-
- TOSH_SIGNAL(UART1RX_VECTOR) {
+
+ inline async event void SIGNAL_UART1RX_VECTOR.fired() {
uint8_t temp = U1RXBUF;
- signal UsartInterrupts.rxDone(temp);
+ signal Interrupts.rxDone(temp);
}
- TOSH_SIGNAL(UART1TX_VECTOR) {
- signal UsartInterrupts.txDone();
+ inline async event void SIGNAL_UART1TX_VECTOR.fired() {
+ signal Interrupts.txDone();
}
- async command bool Usart.isSPI() {
- bool _ret = FALSE;
- atomic{
- if (ME2 & USPIE1)
- _ret = TRUE;
+ async command error_t AsyncStdControl.start() {
+ return SUCCESS;
+ }
+
+ async command error_t AsyncStdControl.stop() {
+ call Usart.disableSpi();
+ call Usart.disableUart();
+ return SUCCESS;
+ }
+
+
+ async command void Usart.setUctl(msp430_uctl_t control) {
+ U1CTL=uctl2int(control);
+ }
+
+ async command msp430_uctl_t Usart.getUctl() {
+ return int2uctl(U0CTL);
+ }
+
+ async command void Usart.setUtctl(msp430_utctl_t control) {
+ U1TCTL=utctl2int(control);
+ }
+
+ async command msp430_utctl_t Usart.getUtctl() {
+ return int2utctl(U1TCTL);
+ }
+
+ async command void Usart.setUrctl(msp430_urctl_t control) {
+ U1RCTL=urctl2int(control);
+ }
+
+ async command msp430_urctl_t Usart.getUrctl() {
+ return int2urctl(U1RCTL);
+ }
+
+ async command void Usart.setUbr(uint16_t control) {
+ atomic {
+ U1BR0 = control & 0x00FF;
+ U1BR1 = (control >> 8) & 0x00FF;
}
- return _ret;
}
-
- async command bool Usart.isUART() {
- bool _ret = FALSE;
+
+ async command uint16_t Usart.getUbr() {
+ return (U1BR1 << 8) + U1BR0;
+ }
+
+ async command void Usart.setUmctl(uint8_t control) {
+ U1MCTL=control;
+ }
+
+ async command uint8_t Usart.getUmctl() {
+ return U1MCTL;
+ }
+
+ async command void Usart.resetUsart(bool reset) {
+ if (reset)
+ U1CTL = SWRST;
+ else
+ CLR_FLAG(U1CTL, SWRST);
+ }
+
+ async command bool Usart.isSpi() {
atomic {
- if ((ME2 & UTXE1) && (ME2 & URXE1))
- _ret = TRUE;
+ return (U1CTL & SYNC) && (ME2 & USPIE1);
}
- return _ret;
}
-
- async command bool Usart.isUARTtx() {
- bool _ret = FALSE;
+
+ async command bool Usart.isUart() {
atomic {
- if (ME2 & UTXE1)
- _ret = TRUE;
+ return !(U1CTL & SYNC) && ((ME2 & UTXE1) && (ME2 & URXE1));
}
- return _ret;
}
-
- async command bool Usart.isUARTrx() {
- bool _ret = FALSE;
+
+ async command bool Usart.isUartTx() {
atomic {
- if (ME2 & URXE1)
- _ret = TRUE;
+ return !(U1CTL & SYNC) && (ME2 & UTXE1);
}
- return _ret;
}
-
- async command bool Usart.isI2C() {
- return FALSE;
+
+ async command bool Usart.isUartRx() {
+ atomic {
+ return !(U1CTL & SYNC) && (ME2 & URXE1);
+ }
}
-
+
async command msp430_usartmode_t Usart.getMode() {
- if (call Usart.isUART())
+ if (call Usart.isUart())
return USART_UART;
- else if (call Usart.isUARTrx())
+ else if (call Usart.isUartRx())
return USART_UART_RX;
- else if (call Usart.isUARTtx())
+ else if (call Usart.isUartTx())
return USART_UART_TX;
- else if (call Usart.isSPI())
+ else if (call Usart.isSpi())
return USART_SPI;
- else if (call Usart.isI2C())
- return USART_I2C;
else
return USART_NONE;
}
-
- /**
- * Sets the USART mode to one of the options from msp430_usartmode_t
- * defined in MSP430Usart.h
- */
- async command void Usart.setMode(msp430_usartmode_t _mode) {
- switch (_mode) {
- case USART_UART:
- call Usart.setModeUART();
- break;
- case USART_UART_RX:
- call Usart.setModeUART_RX();
- break;
- case USART_UART_TX:
- call Usart.setModeUART_TX();
- break;
- case USART_SPI:
- call Usart.setModeSPI();
- break;
- default:
- break;
+
+ async command void Usart.enableUart() {
+ atomic{
+ call UTXD.selectModuleFunc();
+ call URXD.selectModuleFunc();
}
- }
-
- async command void Usart.enableUART() {
-// TOSH_SEL_UTXD1_MODFUNC();
-// TOSH_SEL_URXD1_MODFUNC();
ME2 |= (UTXE1 | URXE1); // USART1 UART module enable
}
-
- async command void Usart.disableUART() {
- ME2 &= ~(UTXE1 | URXE1); // USART0 UART module enable
- call UTXD.selectIOFunc();
- call URXD.selectIOFunc();
+
+ async command void Usart.disableUart() {
+ atomic {
+ ME2 &= ~(UTXE1 | URXE1); // USART1 UART module enable
+ call UTXD.selectIOFunc();
+ call URXD.selectIOFunc();
+ }
+
}
-
- async command void Usart.enableUARTTx() {
- ME2 |= UTXE1; // USART0 UART Tx module enable
+
+ async command void Usart.enableUartTx() {
+ call UTXD.selectModuleFunc();
+ ME2 |= UTXE1; // USART1 UART Tx module enable
}
-
- async command void Usart.disableUARTTx() {
- ME2 &= ~UTXE1; // USART0 UART Tx module enable
+
+ async command void Usart.disableUartTx() {
+ ME2 &= ~UTXE1; // USART1 UART Tx module enable
call UTXD.selectIOFunc();
+
}
-
- async command void Usart.enableUARTRx() {
- ME2 |= URXE1; // USART0 UART Rx module enable
+
+ async command void Usart.enableUartRx() {
+ call URXD.selectModuleFunc();
+ ME2 |= URXE1; // USART1 UART Rx module enable
}
-
- async command void Usart.disableUARTRx() {
- ME2 &= ~URXE1; // USART0 UART Rx module disable
+
+ async command void Usart.disableUartRx() {
+ ME2 &= ~URXE1; // USART1 UART Rx module disable
call URXD.selectIOFunc();
- }
- async command void Usart.enableSPI() {
- ME2 |= USPIE1; // USART0 SPI module enable
- }
-
- async command void Usart.disableSPI() {
- ME2 &= ~USPIE1; // USART0 SPI module disable
- call SIMO.selectIOFunc();
- call SOMI.selectIOFunc();
- call UCLK.selectIOFunc();
}
-
- async command void Usart.enableI2C() { }
-
- async command void Usart.disableI2C() { }
- async command void Usart.setModeSPI() {
- // check if we are already in SPI mode
- if (call Usart.getMode() == USART_SPI)
- return;
-
- call Usart.disableUART();
- call Usart.disableI2C();
-
+ async command void Usart.enableSpi() {
atomic {
call SIMO.selectModuleFunc();
call SOMI.selectModuleFunc();
call UCLK.selectModuleFunc();
-
- IE2 &= ~(UTXIE1 | URXIE1); // interrupt disable
-
- U1CTL = SWRST;
- U1CTL |= CHAR | SYNC | MM; // 8-bit char, SPI-mode, USART as master
- U1CTL &= ~(0x20);
-
- U1TCTL = STC ; // 3-pin
- U1TCTL |= CKPH; // half-cycle delayed UCLK
-
- if (l_ssel & 0x80) {
- U1TCTL &= ~(SSEL_0 | SSEL_1 | SSEL_2 | SSEL_3);
- U1TCTL |= (l_ssel & 0x7F);
- }
- else {
- U1TCTL &= ~(SSEL_0 | SSEL_1 | SSEL_2 | SSEL_3);
- U1TCTL |= SSEL_SMCLK; // use SMCLK, assuming 1MHz
- }
-
- if (l_br != 0) {
- U1BR0 = l_br & 0x0FF;
- U1BR1 = (l_br >> 8) & 0x0FF;
- }
- else {
- U1BR0 = 0x02; // as fast as possible
- U1BR1 = 0x00;
- }
- U1MCTL = 0;
-
- ME2 &= ~(UTXE1 | URXE1); //USART UART module disable
- ME2 |= USPIE1; // USART SPI module enable
- U1CTL &= ~SWRST;
-
- IFG2 &= ~(UTXIFG1 | URXIFG1);
- IE2 &= ~(UTXIE1 | URXIE1); // interrupt disabled
}
- return;
+ ME2 |= USPIE1; // USART1 SPI module enable
}
-
- void setUARTModeCommon() {
- atomic {
- U1CTL = SWRST;
- U1CTL |= CHAR; // 8-bit char, UART-mode
-
- U1RCTL &= ~URXEIE; // even erroneous characters trigger interrupts
-
-
- U1CTL = SWRST;
- U1CTL |= CHAR; // 8-bit char, UART-mode
-
- if (l_ssel & 0x80) {
- U1TCTL &= ~(SSEL_0 | SSEL_1 | SSEL_2 | SSEL_3);
- U1TCTL |= (l_ssel & 0x7F);
- }
- else {
- U1TCTL &= ~(SSEL_0 | SSEL_1 | SSEL_2 | SSEL_3);
- U1TCTL |= SSEL_ACLK; // use ACLK, assuming 32khz
- }
-
- if ((l_mctl != 0) || (l_br != 0)) {
- U1BR0 = l_br & 0x0FF;
- U1BR1 = (l_br >> 8) & 0x0FF;
- U1MCTL = l_mctl;
- }
- else {
- U1BR0 = 0x03; // 9600 baud
- U1BR1 = 0x00;
- U1MCTL = 0x4A;
- }
-
- ME2 &= ~USPIE1; // USART0 SPI module disable
- ME2 |= (UTXE1 | URXE1); //USART0 UART module enable;
-
- U1CTL &= ~SWRST;
- IFG2 &= ~(UTXIFG1 | URXIFG1);
- IE2 &= ~(UTXIE1 | URXIE1); // interrupt disabled
+ async command void Usart.disableSpi() {
+ atomic {
+ ME2 &= ~USPIE1; // USART1 SPI module disable
+ call SIMO.selectIOFunc();
+ call SOMI.selectIOFunc();
+ call UCLK.selectIOFunc();
}
- return;
}
-
- async command void Usart.setModeUART_TX() {
- // check if we are already in UART mode
- if (call Usart.getMode() == USART_UART_TX)
- return;
- call Usart.disableSPI();
- call Usart.disableI2C();
- call Usart.disableUART();
+ void configSpi(msp430_spi_union_config_t* config) {
+ U1CTL = (config->spiRegisters.uctl) | SYNC | SWRST;
+ U1TCTL = config->spiRegisters.utctl;
- atomic {
- call UTXD.selectModuleFunc();
- call URXD.selectIOFunc();
- }
- setUARTModeCommon();
- return;
+ call Usart.setUbr(config->spiRegisters.ubr);
+ call Usart.setUmctl(0x00);
}
-
- async command void Usart.setModeUART_RX() {
- // check if we are already in UART mode
- if (call Usart.getMode() == USART_UART_RX)
- return;
- call Usart.disableSPI();
- call Usart.disableI2C();
- call Usart.disableUART();
+ async command void Usart.setModeSpi(msp430_spi_union_config_t* config) {
atomic {
- call UTXD.selectIOFunc();
- call URXD.selectModuleFunc();
- }
- setUARTModeCommon();
- return;
- }
-
- async command void Usart.setModeUART() {
- // check if we are already in UART mode
- if (call Usart.getMode() == USART_UART)
- return;
-
- call Usart.disableSPI();
- call Usart.disableI2C();
- call Usart.disableUART();
-
- atomic {
- call UTXD.selectModuleFunc();
- call URXD.selectModuleFunc();
- }
- setUARTModeCommon();
+ call Usart.resetUsart(TRUE);
+ call Usart.disableUart();
+ configSpi(config);
+ call Usart.enableSpi();
+ call Usart.resetUsart(FALSE);
+ call Usart.clrIntr();
+ call Usart.disableIntr();
+ }
return;
}
- // i2c enable bit is not set by default
- async command void Usart.setModeI2C() {
- // check if we are already in I2C mode
- if (call Usart.getMode() == USART_I2C)
- return;
- call Usart.disableUART();
- call Usart.disableSPI();
+ void configUart(msp430_uart_union_config_t* config) {
- atomic {
- call SIMO.makeInput();
- call UCLK.makeInput();
- call SIMO.selectModuleFunc();
- call UCLK.selectModuleFunc();
-
- IE2 &= ~(UTXIE1 | URXIE1); // interrupt disable
-
- U1CTL = SWRST;
- U1CTL |= SYNC | I2C; // 7-bit addr, I2C-mode, USART as master
- U1CTL &= ~I2CEN;
-
- U1CTL |= MST;
-
- I2CTCTL = I2CSSEL_2; // use 1MHz SMCLK as the I2C reference
-
- I2CPSC = 0x00; // I2C CLK runs at 1MHz/10 = 100kHz
- I2CSCLH = 0x03;
- I2CSCLL = 0x03;
-
- I2CIE = 0; // clear all I2C interrupt enables
- I2CIFG = 0; // clear all I2C interrupt flags
+ U1CTL = (config->uartRegisters.uctl & ~SYNC) | SWRST;
+ U1TCTL = config->uartRegisters.utctl;
+ U1RCTL = config->uartRegisters.urctl;
+
+ call Usart.setUbr(config->uartRegisters.ubr);
+ call Usart.setUmctl(config->uartRegisters.umctl);
+ }
+
+ async command void Usart.setModeUart(msp430_uart_union_config_t* config) {
+
+ atomic {
+ call Usart.resetUsart(TRUE);
+ call Usart.disableSpi();
+ configUart(config);
+ if ((config->uartConfig.utxe == 1) && (config->uartConfig.urxe == 1)) {
+ call Usart.enableUart();
+ } else if ((config->uartConfig.utxe == 0) && (config->uartConfig.urxe == 1)) {
+ call Usart.disableUartTx();
+ call Usart.enableUartRx();
+ } else if ((config->uartConfig.utxe == 1) && (config->uartConfig.urxe == 0)){
+ call Usart.disableUartRx();
+ call Usart.enableUartTx();
+ } else {
+ call Usart.disableUart();
+ }
+ call Usart.resetUsart(FALSE);
+ call Usart.clrIntr();
+ call Usart.disableIntr();
}
+
return;
}
-
- async command void Usart.setClockSource(uint8_t source) {
- atomic {
- l_ssel = source | 0x80;
- U1TCTL &= ~(SSEL_0 | SSEL_1 | SSEL_2 | SSEL_3);
- U1TCTL |= (l_ssel & 0x7F);
- }
- }
-
- async command void Usart.setClockRate(uint16_t baudrate, uint8_t mctl) {
- atomic {
- l_br = baudrate;
- l_mctl = mctl;
- U1BR0 = baudrate & 0x0FF;
- U1BR1 = (baudrate >> 8) & 0x0FF;
- U1MCTL = mctl;
- }
- }
async command bool Usart.isTxIntrPending(){
if (IFG2 & UTXIFG1){
- IFG2 &= ~UTXIFG1;
return TRUE;
}
return FALSE;
}
return FALSE;
}
-
+
async command bool Usart.isRxIntrPending(){
if (IFG2 & URXIFG1){
- IFG2 &= ~URXIFG1;
return TRUE;
}
return FALSE;
}
-
- async command error_t Usart.clrTxIntr(){
- IFG1 &= ~UTXIFG0;
- return SUCCESS;
+
+ async command void Usart.clrTxIntr(){
+ IFG2 &= ~UTXIFG1;
}
- async command error_t Usart.clrRxIntr() {
- IFG1 &= ~URXIFG0;
- return SUCCESS;
+ async command void Usart.clrRxIntr() {
+ IFG2 &= ~URXIFG1;
}
-
- async command void Usart.disableRxIntr(){
- IE2 &= ~URXIE1;
+
+ async command void Usart.clrIntr() {
+ IFG2 &= ~(UTXIFG1 | URXIFG1);
}
-
- async command void Usart.disableTxIntr(){
- IE2 &= ~UTXIE1;
+
+ async command void Usart.disableRxIntr() {
+ IE2 &= ~URXIE1;
}
-
- async command void Usart.enableRxIntr(){
+
+ async command void Usart.disableTxIntr() {
+ IE2 &= ~UTXIE1;
+ }
+
+ async command void Usart.disableIntr() {
+ IE2 &= ~(UTXIE1 | URXIE1);
+ }
+
+ async command void Usart.enableRxIntr() {
atomic {
IFG2 &= ~URXIFG1;
- IE2 |= URXIE1;
+ IE2 |= URXIE1;
}
}
- async command void Usart.enableTxIntr(){
+ async command void Usart.enableTxIntr() {
atomic {
IFG2 &= ~UTXIFG1;
IE2 |= UTXIE1;
}
}
-
- async command void Usart.tx(uint8_t data){
+
+ async command void Usart.enableIntr() {
+ atomic {
+ IFG2 &= ~(UTXIFG1 | URXIFG1);
+ IE2 |= (UTXIE1 | URXIE1);
+ }
+ }
+
+ async command void Usart.tx(uint8_t data) {
atomic U1TXBUF = data;
}
-
- async command uint8_t Usart.rx(){
+
+ async command uint8_t Usart.rx() {
uint8_t value;
atomic value = U1RXBUF;
return value;
projects / tinyos-2.x.git / blobdiff