*
* TODO: Implement error checking via UCxxSTAT
*
- * @author R. Steve McKown <smckown@gmail.com>
+ * NOTE: Define NO_REN_ON_SPI to disable PxREN bits when SPI is acquired.
+ *
+ * @author R. Steve McKown <rsmckown@gmail.com>
*/
generic module Msp430SpiP(uint16_t blockSize) {
BLOCKSIZE_DEFAULT = 64,
/* Bit positions in m_pins */
- PINS_STE = 1,
+ PINS_STE = 0,
PINS_SOMI,
PINS_SIMO,
PINS_CLK,
+#ifdef NO_REN_ON_SPI
+ PINS_RENADDR, /* This gets added to store the PxREN bit */
+#endif
};
uint8_t m_pins;
/* Configure pins for SPI, saving prior pin states */
m_pins = 0;
+#ifdef NO_REN_ON_SPI
+ /* - First save off and disable PxREN bits */
+ if (is4pin() && call STE.isRen()) {
+ m_pins |= (1 << (PINS_STE + PINS_RENADDR));
+ call STE.disableRen();
+ }
+ if (call SOMI.isRen()) {
+ m_pins |= (1 << (PINS_SOMI + PINS_RENADDR));
+ call SOMI.disableRen();
+ }
+ if (call SIMO.isRen()) {
+ m_pins |= (1 << (PINS_SIMO + PINS_RENADDR));
+ call SIMO.disableRen();
+ }
+ if (call CLK.isRen()) {
+ m_pins |= (1 << (PINS_CLK + PINS_RENADDR));
+ call CLK.disableRen();
+ }
+#endif
+ /* - Then save off IOFunc state and enable ModuleFunc */
if (is4pin() && call STE.isIOFunc()) {
m_pins |= (1 << PINS_STE);
call STE.selectModuleFunc();
{
atomic {
/* Disable the device */
- call Registers.setCtl1(UCSYNC);
+ call Registers.setCtl1(UCSWRST);
/* Clear interrupts and interrupt flags. We only used Rx */
call Registers.clrIeRx();
call Registers.clrIfgRx();
/* Restore pins to their pre-configure state */
- if (is4pin() && (m_pins & PINS_STE))
+ /* - First restore IOFunc states */
+ if (is4pin() && (m_pins & (1 << PINS_STE)))
call STE.selectIOFunc();
- if (m_pins & PINS_SIMO)
+ if (m_pins & (1 << PINS_SIMO))
call SIMO.selectIOFunc();
- if (m_pins & PINS_SOMI)
+ if (m_pins & (1 << PINS_SOMI))
call SOMI.selectIOFunc();
- if (m_pins & PINS_CLK)
+ if (m_pins & (1 << PINS_CLK))
call CLK.selectIOFunc();
+ /* - Then restore PxREN bits */
+#ifdef NO_REN_ON_SPI
+ if (is4pin() && (m_pins & (1 << (PINS_STE + PINS_RENADDR))))
+ call STE.enableRen();
+ if (m_pins & (1 << (PINS_SIMO + PINS_RENADDR)))
+ call SIMO.enableRen();
+ if (m_pins & (1 << (PINS_SOMI + PINS_RENADDR)))
+ call SOMI.enableRen();
+ if (m_pins & (1 << (PINS_CLK + PINS_RENADDR)))
+ call CLK.enableRen();
+#endif
}
}
if (isBusy())
return 0;
else {
- while (!call Registers.getIfgTx());
+ while (!call Registers.getIfgTx() && !call Registers.getCtl1(UCSWRST));
call Registers.setTxbuf(byte);
- while(!call Registers.getIfgRx());
+ while(!call Registers.getIfgRx() && !call Registers.getCtl1(UCSWRST));
return call Registers.getRxbuf();
}
}
void sendData()
{
- /* We don't need to check Registers.getIfgTx() (aks UCxxTXIFG), as
- * sendData() is only called after peripheral init or receipt of the rx()
- * interrupt. SPI on msp430 guarantees UCxxTXIFG is asserted in both of
- * these cases.
- */
atomic {
uint16_t end = m_pos + (blockSize ? blockSize : BLOCKSIZE_DEFAULT);
uint8_t tmp;
if (end > m_len)
end = m_len;
- call Registers.setTxbuf((m_txBuf) ? m_txBuf[m_pos] : 0);
+ call Registers.setTxbuf(m_txBuf ? m_txBuf[m_pos] : 0);
while (++m_pos < end) {
- while (!call Registers.getIfgRx());
+ while (!call Registers.getIfgRx() && !call Registers.getCtl1(UCSWRST));
+ tmp = call Registers.getRxbuf();
if (m_rxBuf)
- m_rxBuf[m_pos - 1] = call Registers.getRxbuf();
- else
- tmp = call Registers.getRxbuf();
- call Registers.setTxbuf((m_txBuf) ? m_txBuf[m_pos] : 0);
+ m_rxBuf[m_pos - 1] = tmp;
+ while (!call Registers.getIfgTx() && !call Registers.getCtl1(UCSWRST));
+ call Registers.setTxbuf(m_txBuf ? m_txBuf[m_pos] : 0);
}
}
}
task void signalSendDone()
{
atomic {
- signal SpiPacket.sendDone(m_txBuf, m_rxBuf, m_len, SUCCESS);
+ uint16_t len = m_len;
m_len = 0;
+ signal SpiPacket.sendDone(m_txBuf, m_rxBuf, len, SUCCESS);
}
}
async event void Interrupts.rx(uint8_t byte)
{
if (m_rxBuf)
- m_rxBuf[m_pos - 1] = call Registers.getRxbuf();
- else
- call Registers.getRxbuf();
+ m_rxBuf[m_pos - 1] = byte;
if (m_pos < m_len)
sendData();