// $Id$
-/* tab:4
+/*
* IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
* downloading, copying, installing or using the software you agree to
* this license. If you do not agree to this license, do not download,
*
*
*/
-/* tab:4
+/*
*
*
* "Copyright (c) 2000-2002 The Regents of the University of California.
typedef uint32_t __nesc_atomic_t;
//NOTE...at the moment, these functions will ONLY disable the IRQ...FIQ is left alone
-inline __nesc_atomic_t __nesc_atomic_start(void) __attribute__((spontaneous))
+inline __nesc_atomic_t __nesc_atomic_start(void) @spontaneous()
{
uint32_t result = 0;
uint32_t temp = 0;
: "=r" (result) , "=r" (temp)
: "0" (result) , "1" (temp) , "i" (ARM_CPSR_INT_MASK)
);
+ asm volatile("" : : : "memory"); /* ensure atomic section effect visibility */
return result;
}
-inline void __nesc_atomic_end(__nesc_atomic_t oldState) __attribute__((spontaneous))
+inline void __nesc_atomic_end(__nesc_atomic_t oldState) @spontaneous()
{
uint32_t statusReg = 0;
//make sure that we only mess with the INT bit
+ asm volatile("" : : : "memory"); /* ensure atomic section effect visibility */
oldState &= ARM_CPSR_INT_MASK;
asm volatile (
"mrs %0,CPSR\n\t"