]> oss.titaniummirror.com Git - tinyos-2.x.git/commitdiff
Add a BusyWait interface for controlling SHT1X timing requirements.
authorsmckown <smckown@4bc1554a-c7f2-4f65-a403-e0be01f0239c>
Tue, 16 Sep 2008 14:17:50 +0000 (14:17 +0000)
committerR. Steve McKown <rsmckown@gmail.com>
Mon, 7 Dec 2009 17:56:28 +0000 (10:56 -0700)
The default implementation, which does nothing, is probably suitable for all
processors running at about 10 MHz or less.  Implement a platform specific
version to enforce the 5 us timing requirements as per the data sheet.


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