configuration HplMsp430GeneralIOC
{
// provides all the ports as raw ports
-#ifdef __msp430_have_port1
+#if defined(__MSP430_HAS_PORT1__) || defined(__MSP430_HAS_PORT1_R__)
provides interface HplMsp430GeneralIO as Port10;
provides interface HplMsp430GeneralIO as Port11;
provides interface HplMsp430GeneralIO as Port12;
provides interface HplMsp430GeneralIO as Port17;
#endif
-#ifdef __msp430_have_port2
+#if defined(__MSP430_HAS_PORT2__) || defined(__MSP430_HAS_PORT2_R__ )
provides interface HplMsp430GeneralIO as Port20;
provides interface HplMsp430GeneralIO as Port21;
provides interface HplMsp430GeneralIO as Port22;
provides interface HplMsp430GeneralIO as Port27;
#endif
-#ifdef __msp430_have_port3
+#if defined(__MSP430_HAS_PORT3__) || defined(__MSP430_HAS_PORT3_R__)
provides interface HplMsp430GeneralIO as Port30;
provides interface HplMsp430GeneralIO as Port31;
provides interface HplMsp430GeneralIO as Port32;
provides interface HplMsp430GeneralIO as Port37;
#endif
-#ifdef __msp430_have_port4
+#if defined(__MSP430_HAS_PORT4__) || defined(__MSP430_HAS_PORT4_R__)
provides interface HplMsp430GeneralIO as Port40;
provides interface HplMsp430GeneralIO as Port41;
provides interface HplMsp430GeneralIO as Port42;
provides interface HplMsp430GeneralIO as Port47;
#endif
-#ifdef __msp430_have_port5
+#if defined(__MSP430_HAS_PORT5__) || defined(__MSP430_HAS_PORT5_R__)
provides interface HplMsp430GeneralIO as Port50;
provides interface HplMsp430GeneralIO as Port51;
provides interface HplMsp430GeneralIO as Port52;
provides interface HplMsp430GeneralIO as Port57;
#endif
-#ifdef __msp430_have_port6
+#if defined(__MSP430_HAS_PORT6__) || defined(__MSP430_HAS_PORT6_R__)
provides interface HplMsp430GeneralIO as Port60;
provides interface HplMsp430GeneralIO as Port61;
provides interface HplMsp430GeneralIO as Port62;
provides interface HplMsp430GeneralIO as Port67;
#endif
- // provides special ports explicitly
- // this section of HplMsp430GeneralIOC supports the F14x series
-#ifdef __msp430x14x
- provides interface HplMsp430GeneralIO as STE0;
- provides interface HplMsp430GeneralIO as SIMO0;
- provides interface HplMsp430GeneralIO as SOMI0;
- provides interface HplMsp430GeneralIO as UCLK0;
- provides interface HplMsp430GeneralIO as UTXD0;
- provides interface HplMsp430GeneralIO as URXD0;
+#if defined(__MSP430_HAS_PORT7__) || defined(__MSP430_HAS_PORT7_R__)
+ provides interface HplMsp430GeneralIO as Port70;
+ provides interface HplMsp430GeneralIO as Port71;
+ provides interface HplMsp430GeneralIO as Port72;
+ provides interface HplMsp430GeneralIO as Port73;
+ provides interface HplMsp430GeneralIO as Port74;
+ provides interface HplMsp430GeneralIO as Port75;
+ provides interface HplMsp430GeneralIO as Port76;
+ provides interface HplMsp430GeneralIO as Port77;
+#endif
- provides interface HplMsp430GeneralIO as STE1;
- provides interface HplMsp430GeneralIO as SIMO1;
- provides interface HplMsp430GeneralIO as SOMI1;
- provides interface HplMsp430GeneralIO as UCLK1;
- provides interface HplMsp430GeneralIO as UTXD1;
- provides interface HplMsp430GeneralIO as URXD1;
+#if defined(__MSP430_HAS_PORT8__) || defined(__MSP430_HAS_PORT8_R__)
+ provides interface HplMsp430GeneralIO as Port80;
+ provides interface HplMsp430GeneralIO as Port81;
+ provides interface HplMsp430GeneralIO as Port82;
+ provides interface HplMsp430GeneralIO as Port83;
+ provides interface HplMsp430GeneralIO as Port84;
+ provides interface HplMsp430GeneralIO as Port85;
+ provides interface HplMsp430GeneralIO as Port86;
+ provides interface HplMsp430GeneralIO as Port87;
+#endif
- provides interface HplMsp430GeneralIO as ADC0;
- provides interface HplMsp430GeneralIO as ADC1;
- provides interface HplMsp430GeneralIO as ADC2;
- provides interface HplMsp430GeneralIO as ADC3;
- provides interface HplMsp430GeneralIO as ADC4;
- provides interface HplMsp430GeneralIO as ADC5;
- provides interface HplMsp430GeneralIO as ADC6;
- provides interface HplMsp430GeneralIO as ADC7;
+#if defined(__MSP430_HAS_PORT9__)
+ provides interface HplMsp430GeneralIO as Port90;
+ provides interface HplMsp430GeneralIO as Port91;
+ provides interface HplMsp430GeneralIO as Port92;
+ provides interface HplMsp430GeneralIO as Port93;
+ provides interface HplMsp430GeneralIO as Port94;
+ provides interface HplMsp430GeneralIO as Port95;
+ provides interface HplMsp430GeneralIO as Port96;
+ provides interface HplMsp430GeneralIO as Port97;
+#endif
+
+#if defined(__MSP430_HAS_PORT10__)
+ provides interface HplMsp430GeneralIO as Port100;
+ provides interface HplMsp430GeneralIO as Port101;
+ provides interface HplMsp430GeneralIO as Port102;
+ provides interface HplMsp430GeneralIO as Port103;
+ provides interface HplMsp430GeneralIO as Port104;
+ provides interface HplMsp430GeneralIO as Port105;
+ provides interface HplMsp430GeneralIO as Port106;
+ provides interface HplMsp430GeneralIO as Port107;
#endif
- // this section of HplMsp430GeneralIOC supports the F16x series
-#ifdef __msp430x16x
+ // Interfaces for UART0, with optional I2C
+#if defined(__MSP430_HAS_UART0__)
provides interface HplMsp430GeneralIO as STE0;
provides interface HplMsp430GeneralIO as SIMO0;
- provides interface HplMsp430GeneralIO as SDA;
provides interface HplMsp430GeneralIO as SOMI0;
provides interface HplMsp430GeneralIO as UCLK0;
- provides interface HplMsp430GeneralIO as SCL;
provides interface HplMsp430GeneralIO as UTXD0;
provides interface HplMsp430GeneralIO as URXD0;
+#if defined (__MSP430_HAS_I2C__)
+ provides interface HplMsp430GeneralIO as SDA;
+ provides interface HplMsp430GeneralIO as SCL;
+#endif
+#endif
+ // Interfaces for UART1, with optional I2C
+#if defined(__MSP430_HAS_UART1__)
provides interface HplMsp430GeneralIO as STE1;
provides interface HplMsp430GeneralIO as SIMO1;
provides interface HplMsp430GeneralIO as SOMI1;
provides interface HplMsp430GeneralIO as UCLK1;
provides interface HplMsp430GeneralIO as UTXD1;
provides interface HplMsp430GeneralIO as URXD1;
+#endif
+
+ // Interfaces for USCI0, ports A and B
+#if defined(__MSP430_HAS_USCI_AB0__) || defined(__MSP430_HAS_USCI__)
+ provides interface HplMsp430GeneralIO as UCA0CLK;
+ provides interface HplMsp430GeneralIO as UCA0STE;
+ provides interface HplMsp430GeneralIO as UCA0TXD;
+ provides interface HplMsp430GeneralIO as UCA0SIMO;
+ provides interface HplMsp430GeneralIO as UCA0RXD;
+ provides interface HplMsp430GeneralIO as UCA0SOMI;
+
+ provides interface HplMsp430GeneralIO as UCB0STE;
+ provides interface HplMsp430GeneralIO as UCB0SIMO;
+ provides interface HplMsp430GeneralIO as UCB0SDA;
+ provides interface HplMsp430GeneralIO as UCB0SOMI;
+ provides interface HplMsp430GeneralIO as UCB0SCL;
+ provides interface HplMsp430GeneralIO as UCB0CLK;
+#endif
+
+ // Interfaces for USCI1, ports A and B
+#if defined(__MSP430_HAS_USCI_AB1__)
+ provides interface HplMsp430GeneralIO as UCA1TXD;
+ provides interface HplMsp430GeneralIO as UCA1SIMO;
+ provides interface HplMsp430GeneralIO as UCA1RXD;
+ provides interface HplMsp430GeneralIO as UCA1SOMI;
+ provides interface HplMsp430GeneralIO as UCA1CLK;
+ provides interface HplMsp430GeneralIO as UCA1STE;
+
+ provides interface HplMsp430GeneralIO as UCB1STE;
+ provides interface HplMsp430GeneralIO as UCB1SIMO;
+ provides interface HplMsp430GeneralIO as UCB1SDA;
+ provides interface HplMsp430GeneralIO as UCB1SOMI;
+ provides interface HplMsp430GeneralIO as UCB1SCL;
+ provides interface HplMsp430GeneralIO as UCB1CLK;
+#endif
+ // Interfaces for ADC10 or ADC12
+#if defined(__MSP430_HAS_ADC10__) || defined(__MSP430_HAS_ADC12__)
provides interface HplMsp430GeneralIO as ADC0;
provides interface HplMsp430GeneralIO as ADC1;
provides interface HplMsp430GeneralIO as ADC2;
provides interface HplMsp430GeneralIO as ADC5;
provides interface HplMsp430GeneralIO as ADC6;
provides interface HplMsp430GeneralIO as ADC7;
+#endif
+ // Interfaces for DAC12
+#if defined(__MSP430_HAS_DAC12__) || defined(__MSP430_HAS_DAC12_1__) || defined(__MSP430_HAS_DAC12_3__)
provides interface HplMsp430GeneralIO as DAC0;
provides interface HplMsp430GeneralIO as DAC1;
+#endif
+ // Interfaces for SVS
+#if defined(__MSP430_HAS_SVS)
provides interface HplMsp430GeneralIO as SVSIN;
provides interface HplMsp430GeneralIO as SVSOUT;
#endif
}
implementation
{
+#if defined(__MSP430_HAS_PORT1__)
components
-#ifdef __msp430_have_port1
new HplMsp430GeneralIOP(P1IN_, P1OUT_, P1DIR_, P1SEL_, 0) as P10,
new HplMsp430GeneralIOP(P1IN_, P1OUT_, P1DIR_, P1SEL_, 1) as P11,
new HplMsp430GeneralIOP(P1IN_, P1OUT_, P1DIR_, P1SEL_, 2) as P12,
new HplMsp430GeneralIOP(P1IN_, P1OUT_, P1DIR_, P1SEL_, 4) as P14,
new HplMsp430GeneralIOP(P1IN_, P1OUT_, P1DIR_, P1SEL_, 5) as P15,
new HplMsp430GeneralIOP(P1IN_, P1OUT_, P1DIR_, P1SEL_, 6) as P16,
- new HplMsp430GeneralIOP(P1IN_, P1OUT_, P1DIR_, P1SEL_, 7) as P17,
+ new HplMsp430GeneralIOP(P1IN_, P1OUT_, P1DIR_, P1SEL_, 7) as P17;
+#endif
+#if defined(__MSP430_HAS_PORT1_R__)
+ components
+ new HplMsp430GeneralIORenP(P1IN_, P1OUT_, P1DIR_, P1SEL_, P1REN_, 0) as P10,
+ new HplMsp430GeneralIORenP(P1IN_, P1OUT_, P1DIR_, P1SEL_, P1REN_, 1) as P11,
+ new HplMsp430GeneralIORenP(P1IN_, P1OUT_, P1DIR_, P1SEL_, P1REN_, 2) as P12,
+ new HplMsp430GeneralIORenP(P1IN_, P1OUT_, P1DIR_, P1SEL_, P1REN_, 3) as P13,
+ new HplMsp430GeneralIORenP(P1IN_, P1OUT_, P1DIR_, P1SEL_, P1REN_, 4) as P14,
+ new HplMsp430GeneralIORenP(P1IN_, P1OUT_, P1DIR_, P1SEL_, P1REN_, 5) as P15,
+ new HplMsp430GeneralIORenP(P1IN_, P1OUT_, P1DIR_, P1SEL_, P1REN_, 6) as P16,
+ new HplMsp430GeneralIORenP(P1IN_, P1OUT_, P1DIR_, P1SEL_, P1REN_, 7) as P17;
#endif
-#ifdef __msp430_have_port2
+#if defined(__MSP430_HAS_PORT2__)
+ components
new HplMsp430GeneralIOP(P2IN_, P2OUT_, P2DIR_, P2SEL_, 0) as P20,
new HplMsp430GeneralIOP(P2IN_, P2OUT_, P2DIR_, P2SEL_, 1) as P21,
new HplMsp430GeneralIOP(P2IN_, P2OUT_, P2DIR_, P2SEL_, 2) as P22,
new HplMsp430GeneralIOP(P2IN_, P2OUT_, P2DIR_, P2SEL_, 4) as P24,
new HplMsp430GeneralIOP(P2IN_, P2OUT_, P2DIR_, P2SEL_, 5) as P25,
new HplMsp430GeneralIOP(P2IN_, P2OUT_, P2DIR_, P2SEL_, 6) as P26,
- new HplMsp430GeneralIOP(P2IN_, P2OUT_, P2DIR_, P2SEL_, 7) as P27,
+ new HplMsp430GeneralIOP(P2IN_, P2OUT_, P2DIR_, P2SEL_, 7) as P27;
+#endif
+#if defined(__MSP430_HAS_PORT2_R__)
+ components
+ new HplMsp430GeneralIORenP(P2IN_, P2OUT_, P2DIR_, P2SEL_, P2REN_, 0) as P20,
+ new HplMsp430GeneralIORenP(P2IN_, P2OUT_, P2DIR_, P2SEL_, P2REN_, 1) as P21,
+ new HplMsp430GeneralIORenP(P2IN_, P2OUT_, P2DIR_, P2SEL_, P2REN_, 2) as P22,
+ new HplMsp430GeneralIORenP(P2IN_, P2OUT_, P2DIR_, P2SEL_, P2REN_, 3) as P23,
+ new HplMsp430GeneralIORenP(P2IN_, P2OUT_, P2DIR_, P2SEL_, P2REN_, 4) as P24,
+ new HplMsp430GeneralIORenP(P2IN_, P2OUT_, P2DIR_, P2SEL_, P2REN_, 5) as P25,
+ new HplMsp430GeneralIORenP(P2IN_, P2OUT_, P2DIR_, P2SEL_, P2REN_, 6) as P26,
+ new HplMsp430GeneralIORenP(P2IN_, P2OUT_, P2DIR_, P2SEL_, P2REN_, 7) as P27;
#endif
-#ifdef __msp430_have_port3
+#if defined(__MSP430_HAS_PORT3__)
+ components
new HplMsp430GeneralIOP(P3IN_, P3OUT_, P3DIR_, P3SEL_, 0) as P30,
new HplMsp430GeneralIOP(P3IN_, P3OUT_, P3DIR_, P3SEL_, 1) as P31,
new HplMsp430GeneralIOP(P3IN_, P3OUT_, P3DIR_, P3SEL_, 2) as P32,
new HplMsp430GeneralIOP(P3IN_, P3OUT_, P3DIR_, P3SEL_, 4) as P34,
new HplMsp430GeneralIOP(P3IN_, P3OUT_, P3DIR_, P3SEL_, 5) as P35,
new HplMsp430GeneralIOP(P3IN_, P3OUT_, P3DIR_, P3SEL_, 6) as P36,
- new HplMsp430GeneralIOP(P3IN_, P3OUT_, P3DIR_, P3SEL_, 7) as P37,
+ new HplMsp430GeneralIOP(P3IN_, P3OUT_, P3DIR_, P3SEL_, 7) as P37;
+#endif
+#if defined(__MSP430_HAS_PORT3_R__)
+ components
+ new HplMsp430GeneralIORenP(P3IN_, P3OUT_, P3DIR_, P3SEL_, P3REN_, 0) as P30,
+ new HplMsp430GeneralIORenP(P3IN_, P3OUT_, P3DIR_, P3SEL_, P3REN_, 1) as P31,
+ new HplMsp430GeneralIORenP(P3IN_, P3OUT_, P3DIR_, P3SEL_, P3REN_, 2) as P32,
+ new HplMsp430GeneralIORenP(P3IN_, P3OUT_, P3DIR_, P3SEL_, P3REN_, 3) as P33,
+ new HplMsp430GeneralIORenP(P3IN_, P3OUT_, P3DIR_, P3SEL_, P3REN_, 4) as P34,
+ new HplMsp430GeneralIORenP(P3IN_, P3OUT_, P3DIR_, P3SEL_, P3REN_, 5) as P35,
+ new HplMsp430GeneralIORenP(P3IN_, P3OUT_, P3DIR_, P3SEL_, P3REN_, 6) as P36,
+ new HplMsp430GeneralIORenP(P3IN_, P3OUT_, P3DIR_, P3SEL_, P3REN_, 7) as P37;
#endif
-#ifdef __msp430_have_port4
+#if defined(__MSP430_HAS_PORT4__)
+ components
new HplMsp430GeneralIOP(P4IN_, P4OUT_, P4DIR_, P4SEL_, 0) as P40,
new HplMsp430GeneralIOP(P4IN_, P4OUT_, P4DIR_, P4SEL_, 1) as P41,
new HplMsp430GeneralIOP(P4IN_, P4OUT_, P4DIR_, P4SEL_, 2) as P42,
new HplMsp430GeneralIOP(P4IN_, P4OUT_, P4DIR_, P4SEL_, 4) as P44,
new HplMsp430GeneralIOP(P4IN_, P4OUT_, P4DIR_, P4SEL_, 5) as P45,
new HplMsp430GeneralIOP(P4IN_, P4OUT_, P4DIR_, P4SEL_, 6) as P46,
- new HplMsp430GeneralIOP(P4IN_, P4OUT_, P4DIR_, P4SEL_, 7) as P47,
+ new HplMsp430GeneralIOP(P4IN_, P4OUT_, P4DIR_, P4SEL_, 7) as P47;
+#endif
+#if defined(__MSP430_HAS_PORT4_R__)
+ components
+ new HplMsp430GeneralIORenP(P4IN_, P4OUT_, P4DIR_, P4SEL_, P4REN_, 0) as P40,
+ new HplMsp430GeneralIORenP(P4IN_, P4OUT_, P4DIR_, P4SEL_, P4REN_, 1) as P41,
+ new HplMsp430GeneralIORenP(P4IN_, P4OUT_, P4DIR_, P4SEL_, P4REN_, 2) as P42,
+ new HplMsp430GeneralIORenP(P4IN_, P4OUT_, P4DIR_, P4SEL_, P4REN_, 3) as P43,
+ new HplMsp430GeneralIORenP(P4IN_, P4OUT_, P4DIR_, P4SEL_, P4REN_, 4) as P44,
+ new HplMsp430GeneralIORenP(P4IN_, P4OUT_, P4DIR_, P4SEL_, P4REN_, 5) as P45,
+ new HplMsp430GeneralIORenP(P4IN_, P4OUT_, P4DIR_, P4SEL_, P4REN_, 6) as P46,
+ new HplMsp430GeneralIORenP(P4IN_, P4OUT_, P4DIR_, P4SEL_, P4REN_, 7) as P47;
#endif
-#ifdef __msp430_have_port5
+#if defined(__MSP430_HAS_PORT5__)
+ components
new HplMsp430GeneralIOP(P5IN_, P5OUT_, P5DIR_, P5SEL_, 0) as P50,
new HplMsp430GeneralIOP(P5IN_, P5OUT_, P5DIR_, P5SEL_, 1) as P51,
new HplMsp430GeneralIOP(P5IN_, P5OUT_, P5DIR_, P5SEL_, 2) as P52,
new HplMsp430GeneralIOP(P5IN_, P5OUT_, P5DIR_, P5SEL_, 4) as P54,
new HplMsp430GeneralIOP(P5IN_, P5OUT_, P5DIR_, P5SEL_, 5) as P55,
new HplMsp430GeneralIOP(P5IN_, P5OUT_, P5DIR_, P5SEL_, 6) as P56,
- new HplMsp430GeneralIOP(P5IN_, P5OUT_, P5DIR_, P5SEL_, 7) as P57,
+ new HplMsp430GeneralIOP(P5IN_, P5OUT_, P5DIR_, P5SEL_, 7) as P57;
+#endif
+#if defined(__MSP430_HAS_PORT5_R__)
+ components
+ new HplMsp430GeneralIORenP(P5IN_, P5OUT_, P5DIR_, P5SEL_, P5REN_, 0) as P50,
+ new HplMsp430GeneralIORenP(P5IN_, P5OUT_, P5DIR_, P5SEL_, P5REN_, 1) as P51,
+ new HplMsp430GeneralIORenP(P5IN_, P5OUT_, P5DIR_, P5SEL_, P5REN_, 2) as P52,
+ new HplMsp430GeneralIORenP(P5IN_, P5OUT_, P5DIR_, P5SEL_, P5REN_, 3) as P53,
+ new HplMsp430GeneralIORenP(P5IN_, P5OUT_, P5DIR_, P5SEL_, P5REN_, 4) as P54,
+ new HplMsp430GeneralIORenP(P5IN_, P5OUT_, P5DIR_, P5SEL_, P5REN_, 5) as P55,
+ new HplMsp430GeneralIORenP(P5IN_, P5OUT_, P5DIR_, P5SEL_, P5REN_, 6) as P56,
+ new HplMsp430GeneralIORenP(P5IN_, P5OUT_, P5DIR_, P5SEL_, P5REN_, 7) as P57;
#endif
-#ifdef __msp430_have_port6
+#if defined(__MSP430_HAS_PORT6__)
+ components
new HplMsp430GeneralIOP(P6IN_, P6OUT_, P6DIR_, P6SEL_, 0) as P60,
new HplMsp430GeneralIOP(P6IN_, P6OUT_, P6DIR_, P6SEL_, 1) as P61,
new HplMsp430GeneralIOP(P6IN_, P6OUT_, P6DIR_, P6SEL_, 2) as P62,
new HplMsp430GeneralIOP(P6IN_, P6OUT_, P6DIR_, P6SEL_, 4) as P64,
new HplMsp430GeneralIOP(P6IN_, P6OUT_, P6DIR_, P6SEL_, 5) as P65,
new HplMsp430GeneralIOP(P6IN_, P6OUT_, P6DIR_, P6SEL_, 6) as P66,
- new HplMsp430GeneralIOP(P6IN_, P6OUT_, P6DIR_, P6SEL_, 7) as P67
+ new HplMsp430GeneralIOP(P6IN_, P6OUT_, P6DIR_, P6SEL_, 7) as P67;
+#endif
+#if defined(__MSP430_HAS_PORT6_R__)
+ components
+ new HplMsp430GeneralIORenP(P6IN_, P6OUT_, P6DIR_, P6SEL_, P6REN_, 0) as P60,
+ new HplMsp430GeneralIORenP(P6IN_, P6OUT_, P6DIR_, P6SEL_, P6REN_, 1) as P61,
+ new HplMsp430GeneralIORenP(P6IN_, P6OUT_, P6DIR_, P6SEL_, P6REN_, 2) as P62,
+ new HplMsp430GeneralIORenP(P6IN_, P6OUT_, P6DIR_, P6SEL_, P6REN_, 3) as P63,
+ new HplMsp430GeneralIORenP(P6IN_, P6OUT_, P6DIR_, P6SEL_, P6REN_, 4) as P64,
+ new HplMsp430GeneralIORenP(P6IN_, P6OUT_, P6DIR_, P6SEL_, P6REN_, 5) as P65,
+ new HplMsp430GeneralIORenP(P6IN_, P6OUT_, P6DIR_, P6SEL_, P6REN_, 6) as P66,
+ new HplMsp430GeneralIORenP(P6IN_, P6OUT_, P6DIR_, P6SEL_, P6REN_, 7) as P67;
#endif
- ;
-#ifdef __msp430_have_port1
+#if defined(__MSP430_HAS_PORT7__)
+ components
+ new HplMsp430GeneralIOP(P7IN_, P7OUT_, P7DIR_, P7SEL_, 0) as P70,
+ new HplMsp430GeneralIOP(P7IN_, P7OUT_, P7DIR_, P7SEL_, 1) as P71,
+ new HplMsp430GeneralIOP(P7IN_, P7OUT_, P7DIR_, P7SEL_, 2) as P72,
+ new HplMsp430GeneralIOP(P7IN_, P7OUT_, P7DIR_, P7SEL_, 3) as P73,
+ new HplMsp430GeneralIOP(P7IN_, P7OUT_, P7DIR_, P7SEL_, 4) as P74,
+ new HplMsp430GeneralIOP(P7IN_, P7OUT_, P7DIR_, P7SEL_, 5) as P75,
+ new HplMsp430GeneralIOP(P7IN_, P7OUT_, P7DIR_, P7SEL_, 6) as P76,
+ new HplMsp430GeneralIOP(P7IN_, P7OUT_, P7DIR_, P7SEL_, 7) as P77;
+#endif
+#if defined(__MSP430_HAS_PORT7_R__)
+ components
+ new HplMsp430GeneralIORenP(P7IN_, P7OUT_, P7DIR_, P7SEL_, P7REN_, 0) as P70,
+ new HplMsp430GeneralIORenP(P7IN_, P7OUT_, P7DIR_, P7SEL_, P7REN_, 1) as P71,
+ new HplMsp430GeneralIORenP(P7IN_, P7OUT_, P7DIR_, P7SEL_, P7REN_, 2) as P72,
+ new HplMsp430GeneralIORenP(P7IN_, P7OUT_, P7DIR_, P7SEL_, P7REN_, 3) as P73,
+ new HplMsp430GeneralIORenP(P7IN_, P7OUT_, P7DIR_, P7SEL_, P7REN_, 4) as P74,
+ new HplMsp430GeneralIORenP(P7IN_, P7OUT_, P7DIR_, P7SEL_, P7REN_, 5) as P75,
+ new HplMsp430GeneralIORenP(P7IN_, P7OUT_, P7DIR_, P7SEL_, P7REN_, 6) as P76,
+ new HplMsp430GeneralIORenP(P7IN_, P7OUT_, P7DIR_, P7SEL_, P7REN_, 7) as P77;
+#endif
+
+#if defined(__MSP430_HAS_PORT8__)
+ components
+ new HplMsp430GeneralIOP(P8IN_, P8OUT_, P8DIR_, P8SEL_, 0) as P80,
+ new HplMsp430GeneralIOP(P8IN_, P8OUT_, P8DIR_, P8SEL_, 1) as P81,
+ new HplMsp430GeneralIOP(P8IN_, P8OUT_, P8DIR_, P8SEL_, 2) as P82,
+ new HplMsp430GeneralIOP(P8IN_, P8OUT_, P8DIR_, P8SEL_, 3) as P83,
+ new HplMsp430GeneralIOP(P8IN_, P8OUT_, P8DIR_, P8SEL_, 4) as P84,
+ new HplMsp430GeneralIOP(P8IN_, P8OUT_, P8DIR_, P8SEL_, 5) as P85,
+ new HplMsp430GeneralIOP(P8IN_, P8OUT_, P8DIR_, P8SEL_, 6) as P86,
+ new HplMsp430GeneralIOP(P8IN_, P8OUT_, P8DIR_, P8SEL_, 7) as P87;
+#endif
+#if defined(__MSP430_HAS_PORT8_R__)
+ components
+ new HplMsp430GeneralIORenP(P8IN_, P8OUT_, P8DIR_, P8SEL_, P8REN_, 0) as P80,
+ new HplMsp430GeneralIORenP(P8IN_, P8OUT_, P8DIR_, P8SEL_, P8REN_, 1) as P81,
+ new HplMsp430GeneralIORenP(P8IN_, P8OUT_, P8DIR_, P8SEL_, P8REN_, 2) as P82,
+ new HplMsp430GeneralIORenP(P8IN_, P8OUT_, P8DIR_, P8SEL_, P8REN_, 3) as P83,
+ new HplMsp430GeneralIORenP(P8IN_, P8OUT_, P8DIR_, P8SEL_, P8REN_, 4) as P84,
+ new HplMsp430GeneralIORenP(P8IN_, P8OUT_, P8DIR_, P8SEL_, P8REN_, 5) as P85,
+ new HplMsp430GeneralIORenP(P8IN_, P8OUT_, P8DIR_, P8SEL_, P8REN_, 6) as P86,
+ new HplMsp430GeneralIORenP(P8IN_, P8OUT_, P8DIR_, P8SEL_, P8REN_, 7) as P87;
+#endif
+
+#if defined(__MSP430_HAS_PORT9__)
+ components
+ new HplMsp430GeneralIOP(P9IN_, P9OUT_, P9DIR_, P9SEL_, 0) as P90,
+ new HplMsp430GeneralIOP(P9IN_, P9OUT_, P9DIR_, P9SEL_, 1) as P91,
+ new HplMsp430GeneralIOP(P9IN_, P9OUT_, P9DIR_, P9SEL_, 2) as P92,
+ new HplMsp430GeneralIOP(P9IN_, P9OUT_, P9DIR_, P9SEL_, 3) as P93,
+ new HplMsp430GeneralIOP(P9IN_, P9OUT_, P9DIR_, P9SEL_, 4) as P94,
+ new HplMsp430GeneralIOP(P9IN_, P9OUT_, P9DIR_, P9SEL_, 5) as P95,
+ new HplMsp430GeneralIOP(P9IN_, P9OUT_, P9DIR_, P9SEL_, 6) as P96,
+ new HplMsp430GeneralIOP(P9IN_, P9OUT_, P9DIR_, P9SEL_, 7) as P97;
+#endif
+
+#if defined(__MSP430_HAS_PORT10__)
+ components
+ new HplMsp430GeneralIOP(P10IN_, P10OUT_, P10DIR_, P10SEL_, 0) as P100,
+ new HplMsp430GeneralIOP(P10IN_, P10OUT_, P10DIR_, P10SEL_, 1) as P101,
+ new HplMsp430GeneralIOP(P10IN_, P10OUT_, P10DIR_, P10SEL_, 2) as P102,
+ new HplMsp430GeneralIOP(P10IN_, P10OUT_, P10DIR_, P10SEL_, 3) as P103,
+ new HplMsp430GeneralIOP(P10IN_, P10OUT_, P10DIR_, P10SEL_, 4) as P104,
+ new HplMsp430GeneralIOP(P10IN_, P10OUT_, P10DIR_, P10SEL_, 5) as P105,
+ new HplMsp430GeneralIOP(P10IN_, P10OUT_, P10DIR_, P10SEL_, 6) as P106,
+ new HplMsp430GeneralIOP(P10IN_, P10OUT_, P10DIR_, P10SEL_, 7) as P107;
+#endif
+
+#if defined(__MSP430_HAS_PORT1__) || defined(__MSP430_HAS_PORT1_R__)
Port10 = P10;
Port11 = P11;
Port12 = P12;
Port17 = P17;
#endif
-#ifdef __msp430_have_port2
+#if defined(__MSP430_HAS_PORT2__) || defined(__MSP430_HAS_PORT2_R__)
Port20 = P20;
Port21 = P21;
Port22 = P22;
Port27 = P27;
#endif
-#ifdef __msp430_have_port3
+#if defined(__MSP430_HAS_PORT3__) || defined(__MSP430_HAS_PORT3_R__)
Port30 = P30;
Port31 = P31;
Port32 = P32;
Port37 = P37;
#endif
-#ifdef __msp430_have_port4
+#if defined(__MSP430_HAS_PORT4__) || defined(__MSP430_HAS_PORT4_R__)
Port40 = P40;
Port41 = P41;
Port42 = P42;
Port47 = P47;
#endif
-#ifdef __msp430_have_port5
+#if defined(__MSP430_HAS_PORT5__) || defined(__MSP430_HAS_PORT5_R__)
Port50 = P50;
Port51 = P51;
Port52 = P52;
Port57 = P57;
#endif
-#ifdef __msp430_have_port6
+#if defined(__MSP430_HAS_PORT6__) || defined(__MSP430_HAS_PORT6_R__)
Port60 = P60;
Port61 = P61;
Port62 = P62;
Port67 = P67;
#endif
-#ifdef __msp430x14x
- STE0 = P30;
- SIMO0 = P31;
- SOMI0 = P32;
- UCLK0 = P33;
- UTXD0 = P34;
- URXD0 = P35;
+#if defined(__MSP430_HAS_PORT7__) || defined(__MSP430_HAS_PORT7_R__)
+ Port70 = P70;
+ Port71 = P71;
+ Port72 = P72;
+ Port73 = P73;
+ Port74 = P74;
+ Port75 = P75;
+ Port76 = P76;
+ Port77 = P77;
+#endif
- STE1 = P50;
- SIMO1 = P51;
- SOMI1 = P52;
- UCLK1 = P53;
- UTXD1 = P36;
- URXD1 = P37;
+#if defined(__MSP430_HAS_PORT8__) || defined(__MSP430_HAS_PORT8_R__)
+ Port80 = P80;
+ Port81 = P81;
+ Port82 = P62;
+ Port83 = P83;
+ Port84 = P84;
+ Port85 = P85;
+ Port86 = P86;
+ Port87 = P87;
+#endif
- ADC0 = P60;
- ADC1 = P61;
- ADC2 = P62;
- ADC3 = P63;
- ADC4 = P64;
- ADC5 = P65;
- ADC6 = P66;
- ADC7 = P67;
+#if defined(__MSP430_HAS_PORT9__)
+ Port90 = P90;
+ Port91 = P91;
+ Port92 = P92;
+ Port93 = P93;
+ Port94 = P94;
+ Port95 = P95;
+ Port96 = P96;
+ Port97 = P97;
#endif
-#ifdef __msp430x16x
+#if defined(__MSP430_HAS_PORT10__)
+ Port100 = P100;
+ Port101 = P101;
+ Port102 = P102;
+ Port103 = P103;
+ Port104 = P104;
+ Port105 = P105;
+ Port106 = P106;
+ Port107 = P107;
+#endif
+
+#if defined(__MSP430_HAS_UART0__)
STE0 = P30;
SIMO0 = P31;
- SDA = P31;
SOMI0 = P32;
UCLK0 = P33;
- SCL = P33;
UTXD0 = P34;
URXD0 = P35;
+#if defined (__MSP430_HAS_I2C__)
+ SDA = P31;
+ SCL = P33;
+#endif
+#endif
+#if defined(__MSP430_HAS_UART1__)
STE1 = P50;
SIMO1 = P51;
SOMI1 = P52;
UCLK1 = P53;
UTXD1 = P36;
URXD1 = P37;
+#endif
+#if defined(__MSP430_HAS_USCI_AB0__) || defined(__MSP430_HAS_USCI__)
+ /* TODO: these mappings are broken for many parts defining
+ * __MSP430_HAS_USCI__. For example, the MSP420F2112 has USCI pin
+ * assignements different than below. Further, the pin assignements vary
+ * by package.
+ */
+ UCA0CLK = P30;
+ UCA0STE = P33;
+ UCA0TXD = P34;
+ UCA0SIMO = P34;
+ UCA0RXD = P35;
+ UCA0SOMI = P35;
+
+ UCB0STE = P30;
+ UCB0SIMO = P31;
+ UCB0SDA = P31;
+ UCB0SOMI = P32;
+ UCB0SCL = P32;
+ UCB0CLK = P33;
+#endif
+
+ // Interfaces for USCI1, ports A and B
+#if defined(__MSP430_HAS_USCI_AB1__)
+ UCA1TXD = P36;
+ UCA1SIMO = P36;
+ UCA1RXD = P37;
+ UCA1SOMI = P37;
+ UCA1CLK = P50;
+ UCA1STE = P53;
+
+ UCB1STE = P50;
+ UCB1SIMO = P51;
+ UCB1SDA = P51;
+ UCB1SOMI = P52;
+ UCB1SCL = P52;
+ UCB1CLK = P53;
+#endif
+
+
+#if defined(__MSP430_HAS_ADC10__) || defined(__MSP430_HAS_ADC12__)
ADC0 = P60;
ADC1 = P61;
ADC2 = P62;
ADC5 = P65;
ADC6 = P66;
ADC7 = P67;
+#endif
+#if defined(__MSP430_HAS_DAC12__) || defined(__MSP430_HAS_DAC12_1__) || defined(__MSP430_HAS_DAC12_3__)
DAC0 = P66;
DAC1 = P67;
+#endif
+#if defined(__MSP430_HAS_SVS)
SVSIN = P67;
SVSOUT = P57;
#endif
projects / tinyos-2.x.git / blobdiff