+ //
+ // TinyOS upper layers assume SMCLK runs at 1 binary MHz, or 1,048,576HZ.
+ // If DCOCLK has been set to 1, 2, 4 or 8 binary MHz, we can correctly set
+ // SMCLK to the expected value. Platforms using different clocks should
+ // set the divider by overriding Msp430ClockInit.initClocks(), calling
+ // Msp430ClockInit.defaultInitClocks(), then massaging the DIVS bits as
+ // required.
+ if (divider >= 8)
+ BCSCTL2 = DIVS_3;
+ else if (divider >= 4)
+ BCSCTL2 = DIVS_2;
+ else if (divider >= 2)
+ BCSCTL2 = DIVS_1;
+ else
+ BCSCTL2 = DIVS_0;
+