Fix TMI copyright attributions

[tinyos-2.x.git] / tos / chips / msp430 / usci / Msp430SpiP.nc

diff --git a/tos/chips/msp430/usci/Msp430SpiP.nc b/tos/chips/msp430/usci/Msp430SpiP.nc
index b040053a252738a6eead2df2af4a9aaace7a1bbe..ed8b6743722994273d3d70816f4bad0e8cbf2d07 100644 (file)
--- a/tos/chips/msp430/usci/Msp430SpiP.nc
+++ b/tos/chips/msp430/usci/Msp430SpiP.nc
@@ -10,7 +10,7 @@
  * - Redistributions in binary form must reproduce the above copyright
  *   notice, this list of conditions and the following disclaimer in the
  *   documentation and/or other materials provided with the distribution.
- * - Neither the name of the Technische Universität Berlin nor the names
+ * - Neither the name of the Titanium Mirror, Inc. nor the names
  *   of its contributors may be used to endorse or promote products derived
  *   from this software without specific prior written permission.
  *
@@ -26,7 +26,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
- 
+
 /**
  * Spi implementation using a USCI device.  When being used as a SPI slave, the
  * CSn interface should be wired to the chip select driven by the SPI master so
@@ -38,7 +38,7 @@
  *
  * @author R. Steve McKown <rsmckown@gmail.com>
  */
- 
+
 generic module Msp430SpiP(uint16_t blockSize) {
   provides {
     interface SpiByte;
@@ -72,10 +72,10 @@ implementation {
   };
 
   uint8_t m_pins;
-  uint8_t* m_txBuf;
-  uint8_t* m_rxBuf;
-  uint16_t m_len;
-  uint16_t m_pos;
+  norace uint8_t* m_txBuf;
+  norace uint8_t* m_rxBuf;
+  norace uint16_t m_len;
+  norace uint16_t m_pos;
 
   inline bool is4pin() /* TRUE if the SPI bus is in 4-pin mode */
   {
@@ -163,12 +163,10 @@ implementation {
 
   task void signalSendDone()
   {
-    atomic {
-      error_t error = (m_pos == m_len) ? SUCCESS : FAIL;
+    error_t error = (m_pos == m_len) ? SUCCESS : FAIL;
 
-      m_len = 0;
-      signal SpiPacket.sendDone(m_txBuf, m_rxBuf, m_pos, error);
-    }
+    m_len = 0;
+    atomic signal SpiPacket.sendDone(m_txBuf, m_rxBuf, m_pos, error);
   }
 
   async command void ResourceConfigure.unconfigure()
@@ -231,17 +229,19 @@ implementation {
 
   async command uint8_t SpiByte.write(uint8_t byte)
   {
-    if (isBusy())
-      return 0;
-    else {
-      waitOnTx();
-      call Registers.setTxbuf(byte);
-      waitOnRx();
-      return call Registers.getRxbuf();
+    atomic {
+      if (isBusy())
+       return 0;
+      else {
+       waitOnTx();
+       call Registers.setTxbuf(byte);
+       waitOnRx();
+       return call Registers.getRxbuf();
+      }
     }
   }
 
-  /* Return FALSE if we are in reset, so callers can clean up as appropriate. */
+  /* If we are a slave, return FALSE if the master has unasserted CSn. */
   bool sendData()
   {
     atomic {
@@ -250,6 +250,7 @@ implementation {
 
       if (end > m_len)
        end = m_len;
+      waitOnTx(); /* Don't assume that the last tx is done already */
       call Registers.setTxbuf(m_txBuf ? m_txBuf[m_pos] : 0);
       while (++m_pos < end) {
        waitOnRx();
@@ -269,19 +270,15 @@ implementation {
     if (isBusy() || (!txBuf && !rxBuf) || len == 0)
       return FAIL;
     else {
-      atomic {
-       m_txBuf = txBuf;
-       m_rxBuf = rxBuf;
-       m_len = len;
-       m_pos = 0;
-       if (sendData()) {
-         call Registers.setIeRx();
-         return SUCCESS;
-       } else {
-         m_len = 0;
-         return FAIL;
-       }
-      }
+      m_txBuf = txBuf;
+      m_rxBuf = rxBuf;
+      m_len = len;
+      m_pos = 0;
+      if (sendData())
+       call Registers.setIeRx();
+      else
+       post signalSendDone();
+      return SUCCESS;
     }
   }
 
@@ -297,7 +294,7 @@ implementation {
        return;
     }
     call Registers.clrIeRx();
-    post signalSendDone(); /* Don't signal from ISR context */
+    post signalSendDone();
   }
 
   default async event void SpiPacket.sendDone(uint8_t*, uint8_t*, uint16_t,
@@ -305,7 +302,7 @@ implementation {
 
   default async command const msp430_usci_spi_t* Configure.get()
   {
-    const static msp430_usci_spi_t def = { 
+    const static msp430_usci_spi_t def = {
       ctl0: UCSYNC | UCMODE_0 | UCMST, /* 3-pin SPI mode 0, LSB first */
       ctl1: UCSWRST | UCSSEL_3,                /* SPI clock source is SMCLK */
       brx: 10,                 /* SPI clock=SMCLK/10; ~105KHz if SMCLK=1MHz */
@@ -320,7 +317,7 @@ implementation {
   async event void Interrupts.i2cStop() {}
   async event void Interrupts.i2cCal() {}
   async event void Interrupts.brk() {}
-  async event void Interrupts.i2cNak() {}
+  async event void Interrupts.i2cNack() {}
 
   default async command bool CSn.get() { return FALSE; }
 }