ctl0: UCSYNC | UCMODE_0 | UCMST | UCMSB | UCCKPL, /* SPI mode0 master, MSB first */
ctl1: UCSWRST | UCSSEL_3, /* clock spi from SMCLK */
brx: 2, /* part says max 500KHz; this is 524288Hz */
ctl0: UCSYNC | UCMODE_0 | UCMST | UCMSB | UCCKPL, /* SPI mode0 master, MSB first */
ctl1: UCSWRST | UCSSEL_3, /* clock spi from SMCLK */
brx: 2, /* part says max 500KHz; this is 524288Hz */