]> oss.titaniummirror.com Git - tinyos-2.x.git/commit
Implement auto-set of SMCLK divider. SMCLK will be properly set to 1 binary
authorsmckown <smckown@4bc1554a-c7f2-4f65-a403-e0be01f0239c>
Tue, 9 Sep 2008 14:26:52 +0000 (14:26 +0000)
committerR. Steve McKown <rsmckown@gmail.com>
Tue, 1 Dec 2009 03:00:53 +0000 (20:00 -0700)
commit05778a038c9af4537d7ba12d932a507709fb43b7
tree4345449e40c1eb3cfd005be21308a57f3b4b6710
parent4032fd4f0aca0fbcf920c01e553bb8e7cca163fa
Implement auto-set of SMCLK divider.  SMCLK will be properly set to 1 binary
MHz if the DCOCLK is set to 1, 2, 4 or 8 binary MHz.
tos/chips/msp430/clock/Msp430ClockP.nc