Implement auto-set of SMCLK divider. SMCLK will be properly set to 1 binary

MHz if the DCOCLK is set to 1, 2, 4 or 8 binary MHz.

diff --git a/tos/chips/msp430/clock/Msp430ClockP.nc b/tos/chips/msp430/clock/Msp430ClockP.nc
index 4304345305864e121fb65e5ceffe9fec710810fe..82e776c0763387feb9e79a10027329ea41229072 100644 (file)
--- a/tos/chips/msp430/clock/Msp430ClockP.nc
+++ b/tos/chips/msp430/clock/Msp430ClockP.nc
@@ -71,6 +71,8 @@ implementation
     
   command void Msp430ClockInit.defaultInitClocks()
   {
+    const unsigned int divider = TARGET_DCO_KHZ / 1000;
+
     // BCSCTL1
     // .XT2OFF = 1; disable the external oscillator for SCLK and MCLK
     // .XTS = 0; set low frequency mode for LXFT1
@@ -82,9 +84,24 @@ implementation
     // .SELM = 0; select DCOCLK as source for MCLK
     // .DIVM = 0; set the divisor of MCLK to 1
     // .SELS = 0; select DCOCLK as source for SCLK
-    // .DIVS = 2; set the divisor of SCLK to 4
+    // .DIVS = see below
     // .DCOR = 0; select internal resistor for DCO
-    BCSCTL2 = DIVS1;
+    //
+    // TinyOS upper layers assume SMCLK runs at 1 binary MHz, or 1,048,576HZ.
+    // If DCOCLK has been set to 1, 2, 4 or 8 binary MHz, we can correctly set
+    // SMCLK to the expected value.   Platforms using different clocks should
+    // set the divider by overriding Msp430ClockInit.initClocks(), calling
+    // Msp430ClockInit.defaultInitClocks(), then massaging the DIVS bits as
+    // required.
+    if (divider >= 8)
+      BCSCTL2 = DIVS_3;
+    else if (divider >= 4)
+      BCSCTL2 = DIVS_2;
+    else if (divider >= 2)
+      BCSCTL2 = DIVS_1;
+    else
+      BCSCTL2 = DIVS_0;
+
 
     // IE1.OFIE = 0; no interrupt for oscillator fault
     CLR_FLAG( IE1, OFIE );