]> oss.titaniummirror.com Git - tinyos-2.x.git/commit
Add a BusyWait interface for controlling SHT1X timing requirements.
authorsmckown <smckown@4bc1554a-c7f2-4f65-a403-e0be01f0239c>
Tue, 16 Sep 2008 14:17:50 +0000 (14:17 +0000)
committerR. Steve McKown <rsmckown@gmail.com>
Mon, 9 Jul 2012 16:34:42 +0000 (10:34 -0600)
commit5b6c97c9ed82a7f8737639b5201954f0b7cc8a4e
tree2772660305ca48b0ef31e0cf8e392757ca8ea252
parent2e460a6c49ab59c8fefcec0bbd3659135af918b6
Add a BusyWait interface for controlling SHT1X timing requirements.

The default implementation, which does nothing, is probably suitable for all
processors running at about 10 MHz or less.  Implement a platform specific
version to enforce the 5 us timing requirements as per the data sheet.
tos/chips/sht11/SensirionBusyWaitC.nc [new file with mode: 0644]
tos/chips/sht11/SensirionSht11LogicP.nc
tos/platforms/telosa/chips/sht11/HalSensirionSht11C.nc
tos/sensorboards/im2sb/HalSensirionSht11C.nc