- +-----------------------------+
- | |
- | Cross-platform applications |
- | |
- +--------------+--------------+
-+-----------------+ | +-----------------+
-|Platform-specific| | |Platform-specific|
-| applications | | | applications |
-+--------+--------+ Platform-independent | hardware interface +--------+--------+
- | +-----------------+--------+--------+-----------------+ |
- | | | | | |
- | +-------+-------+ +-------+-------+ +-------+-------+ +-------+-------+ |
- | |.------+------.| |.------+------.| |.------+------.| |.------+------.| |
- | || || || || || || || HIL 4 || |
- | || HIL 1 || || HIL 2 || || HIL 3 || |`------+------'| |
- | || || |`------+------'| |`------+------'| | | | |
- | |`------+------'| | | | | | | | | +----+--+
- +--+----+ | | |.------+------.| | | | | | | |
- | | | | || || |.------+------.| |.------+--+---.|
- |.---+--+------.| || || || || || ||
- || || || HAL 2 || || || || ||
- || || || || || HAL 3 || || HAL 4 ||
- || HAL 1 || |`------+------'| || || || ||
- || || | | | || || || ||
- || || | | | |`------+------'| |`------+------'|
- |`------+------'| |.------+------.| | | | | | |
- | | | || || |.------+------.| | | |
- |.------+------.| || HPL 2 || || || |.------+------.|
- || HPL 1 || || || || HPL 3 || || HPL 4 ||
- |`------+------'| |`------+------'| |`------+------'| |`------+------'|
- +-------+-------+ +-------+-------+ +-------+-------+ +-------+-------+ HW/SW
- | | | | boundary
- ************************************************************************************
- +------+------+ +------+------+ +------+------+ +------+------+
- |HW Platform 1| |HW Platform 2| |HW Platform 3| |HW Platform 4|
- +-------------+ +-------------+ +-------------+ +-------------+
-
-
- Fig.1: The proposed Hardware Abstraction Architecture
+ +-----------------------------+
+ | |
+ | Cross-platform applications |
+ | |
+ +--------------+--------------+
++-----------------+ | +-----------------+
+|Platform-specific| | |Platform-specific|
+| applications | | | applications |
++--------+--------+ | +--------+--------+
+ | Platform-independent | hardware interface |
+ | +-------------+--------+----+-------------+ |
+ | | | | | |
+ | +-----+-----+ +-----+-----+ +-----+-----+ +-----+-----+ |
+ | |.----+----.| |.----+----.| |.----+----.| |.----+----.| |
+ | || || || || || || || HIL 4 || |
+ | || HIL 1 || || HIL 2 || || HIL 3 || |`----+----'| |
+ | || || |`----+----'| |`----+----'| | | | |
+ | |`----+----'| | | | | | | | | +--+--+
+ +--+--+ | | |.----+----.| | | | | | | |
+ | | | | || || |.----+----.| |.----+--+-.|
+ |.-+--+----.| || || || || || ||
+ || || || HAL 2 || || || || ||
+ || || || || || HAL 3 || || HAL 4 ||
+ || HAL 1 || |`----+----'| || || || ||
+ || || | | | || || || ||
+ || || | | | |`----+----'| |`----+----'|
+ |`----+----'| |.----+----.| | | | | | |
+ | | | || || |.----+----.| | | |
+ |.----+----.| || HPL 2 || || || |.----+----.|
+ || HPL 1 || || || || HPL 3 || || HPL 4 ||
+ |`----+----'| |`----+----'| |`----+----'| |`----+----'|
+ +-----+-----+ +-----+-----+ +-----+-----+ +-----+-----+ HW/SW
+ | | | | boundary
+ ************************************************************************
+ +------+-----+ +-----+-----+ +-----+-----+ +-----+-----+
+ |HW Plat 1 | |HW Plat 2 | |HW Plat 3 | |HW Plat 4 |
+ +------------+ +-----------+ +-----------+ +-----------+
+
+
+ Fig.1: The proposed Hardware Abstraction Architecture