cpu frequency factored out, makes it overridable.

diff --git a/tos/chips/msp430/timer/Msp430ClockP.nc b/tos/chips/msp430/timer/Msp430ClockP.nc
index 1e1a77040fad6e5512f7ed9f1de2af44ad846583..094cda714f7652a649361b9bbc1e42a5e72c6e9d 100644 (file)
--- a/tos/chips/msp430/timer/Msp430ClockP.nc
+++ b/tos/chips/msp430/timer/Msp430ClockP.nc
@@ -24,6 +24,8 @@
  * @author Cory Sharp <cssharp@eecs.berkeley.edu>
  */
 
+#include <Msp430DcoSpec.h>
+
 #include "Msp430Timer.h"
 
 module Msp430ClockP
@@ -42,9 +44,8 @@ implementation
   enum
   {
     ACLK_CALIB_PERIOD = 8,
-    ACLK_KHZ = 32,
-    TARGET_DCO_KHZ = 4096, // prescribe the cpu clock rate in kHz
-    TARGET_DCO_DELTA = (TARGET_DCO_KHZ / ACLK_KHZ) * ACLK_CALIB_PERIOD,
+    ACLK_HZ = 32768U,
+    TARGET_DCO_DELTA = (TARGET_DCO_HZ / ACLK_HZ) * ACLK_CALIB_PERIOD,
   };
 
   command void Msp430ClockInit.defaultInitClocks()

diff --git a/tos/chips/msp430/timer/Msp430DcoSpec.h b/tos/chips/msp430/timer/Msp430DcoSpec.h
new file mode 100644 (file)
index 0000000..186461a
--- /dev/null
+++ b/tos/chips/msp430/timer/Msp430DcoSpec.h
@@ -0,0 +1,49 @@
+/* -*- mode:c++; indent-tabs-mode: nil -*-
+ * Copyright (c) 2007, Technische Universitaet Berlin
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * - Redistributions of source code must retain the above copyright notice,
+ *   this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - Neither the name of the Technische Universitaet Berlin nor the names
+ *   of its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES {} LOSS OF USE, DATA,
+ * OR PROFITS {} OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * Specify the target cpu clock speed of your platform by overriding this file.
+ *
+ * Be aware that tinyos relies on binary 4Mhz, that is 4096000 Hz.  Some
+ * platforms have an external high frequency oscilator to generate the SMCLK
+ * (e.g. eyesIFX, and possibly future ZigBee compliant nodes). These
+ * oscillators provide metric frequencies, but may not run in power down
+ * modes. Here, we need to switch the SMCLK source, which is easier if
+ * the external and thd DCO source frequency are the same.
+ * 
+ * @author: Andreas Koepke (koepke@tkn.tu-berlin.de)
+ */
+
+
+#ifndef MS430DCOSPEC_H
+#define MS430DCOSPEC_H
+
+#define TARGET_DCO_HZ 4096000 // the cpu clock rate in Hz
+
+#endif