Let's let the compiler type system work for us. Instead of having a single

msp430_usci_config_t that is a union of the types for each mode, instead we
now have separate types.

diff --git a/tos/chips/msp430/usci/Msp430SpiB1C.nc b/tos/chips/msp430/usci/Msp430SpiB1C.nc
index 9464555f812fde0fc5aa1f6a2fe202d5216f733f..9cfd71db4ec0b46bd3e8e9b97b178efb4ece9a40 100644 (file)
--- a/tos/chips/msp430/usci/Msp430SpiB1C.nc
+++ b/tos/chips/msp430/usci/Msp430SpiB1C.nc
@@ -48,8 +48,7 @@ generic configuration Msp430SpiB1C() {
     interface SpiPacket;
     interface ArbiterInfo; /* ??? */
   }
-  uses interface AsyncConfigure<const msp430_usci_config_t*> as
-    Msp430UsciConfigure;
+  uses interface AsyncConfigure<const msp430_usci_spi_t*> as Configure;
 }
 implementation {
   enum {
@@ -59,7 +58,7 @@ implementation {
   components new Msp430SpiP() as SpiP;
   SpiByte = SpiP;
   SpiPacket = SpiP;
-  Msp430UsciConfigure = SpiP;
+  Configure = SpiP;
 
   components Msp430UsciA0C as UsciC;
   Resource = UsciC.Resource[CLIENT_ID];

diff --git a/tos/chips/msp430/usci/Msp430SpiP.nc b/tos/chips/msp430/usci/Msp430SpiP.nc
index fd57695a17e7905d3f5ac1fdcf4eb1f30765a3bc..2d8db430d41b9bca0375be9fd86533a0b5d03e2c 100644 (file)
--- a/tos/chips/msp430/usci/Msp430SpiP.nc
+++ b/tos/chips/msp430/usci/Msp430SpiP.nc
@@ -46,8 +46,7 @@ generic module Msp430SpiP() {
     interface HplMsp430GeneralIO as SIMO;
     interface HplMsp430GeneralIO as SOMI;
     interface HplMsp430GeneralIO as SCL;
-    interface AsyncConfigure<const msp430_usci_config_t*> as
-      Msp430UsciConfigure;
+    interface AsyncConfigure<const msp430_usci_spi_t*> as Configure;
     interface Counter<T32khz,uint16_6>
     interface ArbiterInfo;
   }
@@ -93,19 +92,19 @@ implementation {
   async command void ResourceConfigure.configure()
   {
     atomic {
-      const msp430_usci_config_t* config = call Msp430UsciConfigure.get();
+      const msp430_usci_spi_t* config = call Configure.get();
 
       call Registers.setCtl1(UCSWRST);
 
       /* Configure USCI registers */
-      call Registers.assignCtl0(config->spi.ctl0);
-      call Registers.assignCtl1(config->spi.ctl1|UCSWRST);
-      call Registers.assignBr0(config->spi.brx & 0xff);
-      call Registers.assignBr1(config->spi.brx >> 8);
-      call Registers.assignMctl(config->spi.mctl);
-      call Registers.assignIrtctl(config->spi.irtctl);
-      call Registers.assignIrrctl(config->spi.irrctl);
-      call Registers.assignAbctl(config->spi.abctl);
+      call Registers.assignCtl0(config->ctl0);
+      call Registers.assignCtl1(config->ctl1|UCSWRST);
+      call Registers.assignBr0(config->brx & 0xff);
+      call Registers.assignBr1(config->brx >> 8);
+      call Registers.assignMctl(config->mctl);
+      call Registers.assignIrtctl(config->irtctl);
+      call Registers.assignIrrctl(config->irrctl);
+      call Registers.assignAbctl(config->abctl);
       call Registers.clrStat(UCLISTEN);
 
       /* Save pin IO states */
@@ -115,8 +114,8 @@ implementation {
 
       /* Configure RX pin for UART use */
       call RXD.makeInput();
-      if (config->spi.ren & USCI_REN_RX) {
-       if (config->spi.ren & USCI_REN_RX_PULLUP)
+      if (config->ren & USCI_REN_RX) {
+       if (config->ren & USCI_REN_RX_PULLUP)
          call RXD.set();
        else
          call RXD.clr();
@@ -129,8 +128,8 @@ implementation {
        */
 
       /* Configure TX pin for UART use */
-      if (config->spi.ren & USCI_REN_TX) {
-       if (config->spi.ren & USCI_REN_TX_PULLUP)
+      if (config->ren & USCI_REN_TX) {
+       if (config->ren & USCI_REN_TX_PULLUP)
          call TXD.set();
        else
          call TXD.clr();
@@ -283,19 +282,14 @@ implementation {
       signal UartStream.receivedByte(byte);
   }
 
-  default async command const msp430_usci_config_t* Msp430UsciConfigure.get()
+  default async command const msp430_usci_spi_t* Configure.get()
   {
-    const static msp430_usci_config_t def = { 
-      spi: {
-       ctl0: UCMODE_0,         /* async, lsb first, 8N1 */
-       ctl1: UCSWRST|UCSSEL_1, /* clock spi from SMCLK */
-       brx: UBRX_32768HZ_9600,
-       mctl: UMCTL_32768HZ_9600,
-       irtctl: 0,
-       irrctl: 0,
-       abctl: 0,
-       ren: USCI_REN_NONE
-      }
+    const static msp430_usci_spi_t def = { 
+      ctl0: UCMODE_0,          /* async, lsb first, 8N1 */
+      ctl1: UCSWRST|UCSSEL_1,  /* clock spi from SMCLK */
+      brx: UBRX_32768HZ_9600,
+      mctl: UMCTL_32768HZ_9600, /* ??? */
+      ren: USCI_REN_NONE
     };
 
     return &def;

diff --git a/tos/chips/msp430/usci/Msp430UartA0C.nc b/tos/chips/msp430/usci/Msp430UartA0C.nc
index dd310326a84a85c8de3b2eedea432e1d211bd10c..1ffc4404c9ed93e5ad8fb3078d59c04ad449558d 100644 (file)
--- a/tos/chips/msp430/usci/Msp430UartA0C.nc
+++ b/tos/chips/msp430/usci/Msp430UartA0C.nc
@@ -48,8 +48,7 @@ generic configuration Msp430UartA0C() {
     interface UartByte;
     interface ArbiterInfo; /* ??? */
   }
-  uses interface AsyncConfigure<const msp430_usci_config_t*> as
-    Msp430UsciConfigure;
+  uses interface AsyncConfigure<const msp430_usci_uart_t*> as Configure;
 }
 implementation {
   enum {
@@ -59,7 +58,7 @@ implementation {
   components new Msp430UartP() as UartP;
   UartStream = UartP;
   UartByte = UartP;
-  Msp430UsciConfigure = UartP;
+  Configure = UartP;
 
   components Msp430UsciA0C as UsciC;
   Resource = UsciC.Resource[CLIENT_ID];

diff --git a/tos/chips/msp430/usci/Msp430UartA1C.nc b/tos/chips/msp430/usci/Msp430UartA1C.nc
index a5f8a89c4e1d6619eeaf27973fb3a0f9358f6463..2db1c92a03773b11e15374b2bde271df9529dd7a 100644 (file)
--- a/tos/chips/msp430/usci/Msp430UartA1C.nc
+++ b/tos/chips/msp430/usci/Msp430UartA1C.nc
@@ -48,8 +48,7 @@ generic configuration Msp430UartA1C() {
     interface UartByte;
     interface ArbiterInfo; /* ??? */
   }
-  uses interface AsyncConfigure<const msp430_usci_config_t*> as
-    Msp430UsciConfigure;
+  uses interface AsyncConfigure<const msp430_usci_uart_t*> as Configure;
 }
 implementation {
   enum {
@@ -59,7 +58,7 @@ implementation {
   components new Msp430UartP() as UartP;
   UartStream = UartP;
   UartByte = UartP;
-  Msp430UsciConfigure = UartP;
+  Configure = UartP;
 
   components Msp430UsciA1C as UsciC;
   Resource = UsciC.Resource[CLIENT_ID];

diff --git a/tos/chips/msp430/usci/Msp430UartP.nc b/tos/chips/msp430/usci/Msp430UartP.nc
index 8fe6bee02377f6fbbb0dd571a441893e1f8440ce..49dc1f1bac92445a9579b14ba43c63fa796e8c91 100644 (file)
--- a/tos/chips/msp430/usci/Msp430UartP.nc
+++ b/tos/chips/msp430/usci/Msp430UartP.nc
@@ -44,8 +44,7 @@ generic module Msp430UartP() {
     interface HplMsp430UsciInt as Interrupts;
     interface HplMsp430GeneralIO as RXD;
     interface HplMsp430GeneralIO as TXD;
-    interface AsyncConfigure<const msp430_usci_config_t*> as
-      Msp430UsciConfigure;
+    interface AsyncConfigure<const msp430_usci_uart_t*> as Configure;
     interface Counter<T32khz,uint16_t>;
     interface ArbiterInfo;
   }
@@ -91,19 +90,19 @@ implementation {
   async command void ResourceConfigure.configure()
   {
     atomic {
-      const msp430_usci_config_t* config = call Msp430UsciConfigure.get();
+      const msp430_usci_uart_t* config = call Configure.get();
 
       call Registers.setCtl1(UCSWRST);
 
       /* Configure USCI registers */
-      call Registers.assignCtl0(config->uart.ctl0);
-      call Registers.assignCtl1(config->uart.ctl1|UCSWRST);
-      call Registers.assignBr0(config->uart.brx & 0xff);
-      call Registers.assignBr1(config->uart.brx >> 8);
-      call Registers.assignMctl(config->uart.mctl);
-      call Registers.assignIrtctl(config->uart.irtctl);
-      call Registers.assignIrrctl(config->uart.irrctl);
-      call Registers.assignAbctl(config->uart.abctl);
+      call Registers.assignCtl0(config->ctl0);
+      call Registers.assignCtl1(config->ctl1|UCSWRST);
+      call Registers.assignBr0(config->brx & 0xff);
+      call Registers.assignBr1(config->brx >> 8);
+      call Registers.assignMctl(config->mctl);
+      call Registers.assignIrtctl(config->irtctl);
+      call Registers.assignIrrctl(config->irrctl);
+      call Registers.assignAbctl(config->abctl);
       call Registers.clrStat(UCLISTEN);
 
       /* Save pin IO states */
@@ -113,8 +112,8 @@ implementation {
 
       /* Configure RX pin for UART use */
       call RXD.makeInput();
-      if (config->uart.ren & USCI_REN_RX) {
-       if (config->uart.ren & USCI_REN_RX_PULLUP)
+      if (config->ren & USCI_REN_RX) {
+       if (config->ren & USCI_REN_RX_PULLUP)
          call RXD.set();
        else
          call RXD.clr();
@@ -127,8 +126,8 @@ implementation {
        */
 
       /* Configure TX pin for UART use */
-      if (config->uart.ren & USCI_REN_TX) {
-       if (config->uart.ren & USCI_REN_TX_PULLUP)
+      if (config->ren & USCI_REN_TX) {
+       if (config->ren & USCI_REN_TX_PULLUP)
          call TXD.set();
        else
          call TXD.clr();
@@ -281,19 +280,17 @@ implementation {
       signal UartStream.receivedByte(byte);
   }
 
-  default async command const msp430_usci_config_t* Msp430UsciConfigure.get()
+  default async command const msp430_usci_uart_t* Configure.get()
   {
-    const static msp430_usci_config_t def = { 
-      uart: {
-       ctl0: UCMODE_0,         /* async, lsb first, 8N1 */
-       ctl1: UCSWRST|UCSSEL_1, /* clock uart from SMCLK */
-       brx: UBRX_32768HZ_9600,
-       mctl: UMCTL_32768HZ_9600,
-       irtctl: 0,
-       irrctl: 0,
-       abctl: 0,
-       ren: USCI_REN_NONE
-      }
+    const static msp430_usci_uart_t def = { 
+      ctl0: UCMODE_0,          /* async, lsb first, 8N1 */
+      ctl1: UCSWRST|UCSSEL_1,  /* clock uart from SMCLK */
+      brx: UBRX_32768HZ_9600,
+      mctl: UMCTL_32768HZ_9600,
+      irtctl: 0,
+      irrctl: 0,
+      abctl: 0,
+      ren: USCI_REN_NONE
     };
 
     return &def;

diff --git a/tos/chips/msp430/usci/Msp430Usci.h b/tos/chips/msp430/usci/Msp430Usci.h
index 541311136479c9de31a9be20609d085bfc5966da..94ca476c05c433828c58f7ec43b76e183e0e01a5 100644 (file)
--- a/tos/chips/msp430/usci/Msp430Usci.h
+++ b/tos/chips/msp430/usci/Msp430Usci.h
@@ -69,6 +69,18 @@ typedef enum {
   USCI_REN_TX_PULLDOWN = USCI_REN_TX + 0x20
 } msp430_ren_t;
 
+/* Baud rates for UART mode.  Only 32KHz modes work right now. */
+typedef enum {
+  /* UCOS16=0.  UMCTL = UCBRFx << 4 + UCBRSx << 1 + UCOS16.
+   * 1MHZ = 1,048576HZ, 1E6MHZ = 1,000,000HZ.
+   */
+  UBRX_32768HZ_9600=3, UMCTL_32768HZ_9600=(0 << 4) + (3 << 1) + 0,
+  UBRX_1MHZ_9600=109, UMCTL_1MHZ_9600=(0 << 4) + (2 << 1) + 0,
+  UBRX_1MHZ_115200=9, UMCTL_1MHZ_115200=(0 << 4) + (1 << 1) + 0,
+  UBRX_1E6MHZ_9600=104, UMCTL_1E6MHZ_9600=(0 << 4) + (1 << 1) + 0,
+  UBRX_1E6MHZ_115200=8, UMCTL_1E6MHZ_115200=(0 << 4) + (6 << 1) + 0,
+} msp430_usci_uart_rate_t;
+
 typedef struct {
   uint8_t ctl0;
   uint8_t ctl1;
@@ -88,21 +100,14 @@ typedef struct {
   msp430_ren_t ren;
 } __attribute__ ((packed)) msp430_usci_spi_t;
 
-/* Baud rates for UART mode.  Only 32KHz modes work right now. */
-typedef enum {
-  /* UCOS16=0.  UMCTL = UCBRFx << 4 + UCBRSx << 1 + UCOS16.
-   * 1MHZ = 1,048576HZ, 1E6MHZ = 1,000,000HZ.
-   */
-  UBRX_32768HZ_9600=3, UMCTL_32768HZ_9600=(0 << 4) + (3 << 1) + 0,
-  UBRX_1MHZ_9600=109, UMCTL_1MHZ_9600=(0 << 4) + (2 << 1) + 0,
-  UBRX_1MHZ_115200=9, UMCTL_1MHZ_115200=(0 << 4) + (1 << 1) + 0,
-  UBRX_1E6MHZ_9600=104, UMCTL_1E6MHZ_9600=(0 << 4) + (1 << 1) + 0,
-  UBRX_1E6MHZ_115200=8, UMCTL_1E6MHZ_115200=(0 << 4) + (6 << 1) + 0,
-} msp430_usci_uart_rate_t;
-
-typedef union {
-  msp430_usci_uart_t uart;
-  msp430_usci_spi_t spi;
-} __attribute__ ((packed)) msp430_usci_config_t;
+typedef struct {
+  uint8_t ctl0;
+  uint8_t ctl1;
+  uint16_t brx;
+  uint8_t i2cie;
+  uint8_t i2coa;
+  uint8_t i2csa;
+  msp430_ren_t ren;
+} __attribute__ ((packed)) msp430_usci_i2c_t;
 
 #endif