-// $Id$\r
-\r
-/*\r
- * Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved.\r
- *\r
- * Permission to use, copy, modify, and distribute this software and its\r
- * documentation for any purpose, without fee, and without written agreement is\r
- * hereby granted, provided that the above copyright notice, the following\r
- * two paragraphs and the author appear in all copies of this software.\r
- * \r
- * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO \r
- * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL \r
- * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN\r
- * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH \r
- * DAMAGE. \r
- *\r
- * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,\r
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY \r
- * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS \r
- * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY \r
- * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR \r
- * MODIFICATIONS.\r
- */\r
-\r
-// @author Martin Turon <mturon@xbow.com>\r
-\r
-#ifndef _H_Atm128Power_h\r
-#define _H_Atm128Power_h\r
-\r
-//================== ATmega128 Power Management ==========================\r
-\r
-/* MCU Control Register */\r
-typedef struct\r
-{\r
- uint8_t ivce : 1; //!< Interrupt Vector Change Enable\r
- uint8_t ivsel : 1; //!< Interrupt Vector Select \r
- uint8_t stdby : 1; //!< Standby Enable (sm2) \r
- uint8_t sm : 2; //!< Sleep Mode\r
- uint8_t se : 1; //!< Sleep Enable\r
- uint8_t srw10 : 1; //!< SRAM wait state enable\r
- uint8_t srw : 1; //!< External SRAM enable\r
-} Atm128_MCUCR_t;\r
-\r
-#endif //_H_Atm128Power_h\r
+// $Id$
+
+/*
+ * Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation for any purpose, without fee, and without written agreement is
+ * hereby granted, provided that the above copyright notice, the following
+ * two paragraphs and the author appear in all copies of this software.
+ *
+ * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+ * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN
+ * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ */
+
+// @author Martin Turon <mturon@xbow.com>
+
+#ifndef _H_Atm128Power_h
+#define _H_Atm128Power_h
+
+//================== ATmega128 Power Management ==========================
+
+/* MCU Control Register */
+typedef struct
+{
+ uint8_t ivce : 1; //!< Interrupt Vector Change Enable
+ uint8_t ivsel : 1; //!< Interrupt Vector Select
+ uint8_t stdby : 1; //!< Standby Enable (sm2)
+ uint8_t sm : 2; //!< Sleep Mode
+ uint8_t se : 1; //!< Sleep Enable
+ uint8_t srw10 : 1; //!< SRAM wait state enable
+ uint8_t srw : 1; //!< External SRAM enable
+} Atm128_MCUCR_t;
+
+#endif //_H_Atm128Power_h
-// $Id$\r
-\r
-/*\r
- * Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved.\r
- *\r
- * Permission to use, copy, modify, and distribute this software and its\r
- * documentation for any purpose, without fee, and without written agreement is\r
- * hereby granted, provided that the above copyright notice, the following\r
- * two paragraphs and the author appear in all copies of this software.\r
- * \r
- * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO \r
- * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL \r
- * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN\r
- * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH \r
- * DAMAGE. \r
- *\r
- * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,\r
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY \r
- * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS \r
- * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY \r
- * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR \r
- * MODIFICATIONS.\r
- */\r
-\r
-// @author Martin Turon <mturon@xbow.com>\r
-// @author Hu Siquan <husq@xbow.com>\r
-\r
-#ifndef _H_Atm128ADC_h\r
-#define _H_Atm128ADC_h\r
-\r
-//================== 8 channel 10-bit ADC ==============================\r
-\r
-/* Voltage Reference Settings */\r
-enum {\r
- ATM128_ADC_VREF_OFF = 0, //!< VR+ = AREF and VR- = GND\r
- ATM128_ADC_VREF_AVCC = 1,//!< VR+ = AVcc and VR- = GND\r
- ATM128_ADC_VREF_RSVD,\r
- ATM128_ADC_VREF_2_56 = 3,//!< VR+ = 2.56V and VR- = GND\r
-};\r
-\r
-/* Voltage Reference Settings */\r
-enum {\r
- ATM128_ADC_RIGHT_ADJUST = 0, \r
- ATM128_ADC_LEFT_ADJUST = 1,\r
-};\r
-\r
-\r
-/* ADC Multiplexer Settings */\r
-enum {\r
- ATM128_ADC_SNGL_ADC0 = 0,\r
- ATM128_ADC_SNGL_ADC1,\r
- ATM128_ADC_SNGL_ADC2,\r
- ATM128_ADC_SNGL_ADC3,\r
- ATM128_ADC_SNGL_ADC4,\r
- ATM128_ADC_SNGL_ADC5,\r
- ATM128_ADC_SNGL_ADC6,\r
- ATM128_ADC_SNGL_ADC7,\r
- ATM128_ADC_DIFF_ADC00_10x,\r
- ATM128_ADC_DIFF_ADC10_10x,\r
- ATM128_ADC_DIFF_ADC00_200x,\r
- ATM128_ADC_DIFF_ADC10_200x,\r
- ATM128_ADC_DIFF_ADC22_10x,\r
- ATM128_ADC_DIFF_ADC32_10x,\r
- ATM128_ADC_DIFF_ADC22_200x,\r
- ATM128_ADC_DIFF_ADC32_200x,\r
- ATM128_ADC_DIFF_ADC01_1x,\r
- ATM128_ADC_DIFF_ADC11_1x,\r
- ATM128_ADC_DIFF_ADC21_1x,\r
- ATM128_ADC_DIFF_ADC31_1x,\r
- ATM128_ADC_DIFF_ADC41_1x,\r
- ATM128_ADC_DIFF_ADC51_1x,\r
- ATM128_ADC_DIFF_ADC61_1x,\r
- ATM128_ADC_DIFF_ADC71_1x,\r
- ATM128_ADC_DIFF_ADC02_1x,\r
- ATM128_ADC_DIFF_ADC12_1x,\r
- ATM128_ADC_DIFF_ADC22_1x,\r
- ATM128_ADC_DIFF_ADC32_1x,\r
- ATM128_ADC_DIFF_ADC42_1x,\r
- ATM128_ADC_DIFF_ADC52_1x,\r
- ATM128_ADC_SNGL_1_23,\r
- ATM128_ADC_SNGL_GND,\r
-};\r
-\r
-/* ADC Multiplexer Selection Register */\r
-typedef struct\r
-{\r
- uint8_t mux : 5; //!< Analog Channel and Gain Selection Bits\r
- uint8_t adlar : 1; //!< ADC Left Adjust Result\r
- uint8_t refs : 2; //!< Reference Selection Bits\r
-} Atm128Admux_t;\r
-\r
-/* ADC Prescaler Settings */\r
-/* Note: each platform must define ATM128_ADC_PRESCALE to the smallest\r
- prescaler which guarantees full A/D precision. */\r
-enum {\r
- ATM128_ADC_PRESCALE_2 = 0,\r
- ATM128_ADC_PRESCALE_2b,\r
- ATM128_ADC_PRESCALE_4,\r
- ATM128_ADC_PRESCALE_8,\r
- ATM128_ADC_PRESCALE_16,\r
- ATM128_ADC_PRESCALE_32,\r
- ATM128_ADC_PRESCALE_64,\r
- ATM128_ADC_PRESCALE_128,\r
-\r
- // This special value is used to ask the platform for the prescaler\r
- // which gives full precision.\r
- ATM128_ADC_PRESCALE\r
-};\r
-\r
-/* ADC Enable Settings */\r
-enum {\r
- ATM128_ADC_ENABLE_OFF = 0,\r
- ATM128_ADC_ENABLE_ON,\r
-};\r
-\r
-/* ADC Start Conversion Settings */\r
-enum {\r
- ATM128_ADC_START_CONVERSION_OFF = 0,\r
- ATM128_ADC_START_CONVERSION_ON,\r
-};\r
-\r
-/* ADC Free Running Select Settings */\r
-enum {\r
- ATM128_ADC_FREE_RUNNING_OFF = 0,\r
- ATM128_ADC_FREE_RUNNING_ON,\r
-};\r
-\r
-/* ADC Interrupt Flag Settings */\r
-enum {\r
- ATM128_ADC_INT_FLAG_OFF = 0,\r
- ATM128_ADC_INT_FLAG_ON,\r
-};\r
-\r
-/* ADC Interrupt Enable Settings */\r
-enum {\r
- ATM128_ADC_INT_ENABLE_OFF = 0,\r
- ATM128_ADC_INT_ENABLE_ON,\r
-};\r
-\r
-/* ADC Multiplexer Selection Register */\r
-typedef struct\r
-{\r
- uint8_t adps : 3; //!< ADC Prescaler Select Bits\r
- uint8_t adie : 1; //!< ADC Interrupt Enable\r
- uint8_t adif : 1; //!< ADC Interrupt Flag\r
- uint8_t adfr : 1; //!< ADC Free Running Select\r
- uint8_t adsc : 1; //!< ADC Start Conversion\r
- uint8_t aden : 1; //!< ADC Enable\r
-} Atm128Adcsra_t;\r
-\r
-typedef uint8_t Atm128_ADCH_t; //!< ADC data register high\r
-typedef uint8_t Atm128_ADCL_t; //!< ADC data register low\r
-\r
-// The resource identifier string for the ADC subsystem\r
-#define UQ_ATM128ADC_RESOURCE "atm128adc.resource"\r
-\r
-#endif //_H_Atm128ADC_h\r
-\r
+// $Id$
+
+/*
+ * Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation for any purpose, without fee, and without written agreement is
+ * hereby granted, provided that the above copyright notice, the following
+ * two paragraphs and the author appear in all copies of this software.
+ *
+ * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+ * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN
+ * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ */
+
+// @author Martin Turon <mturon@xbow.com>
+// @author Hu Siquan <husq@xbow.com>
+
+#ifndef _H_Atm128ADC_h
+#define _H_Atm128ADC_h
+
+//================== 8 channel 10-bit ADC ==============================
+
+/* Voltage Reference Settings */
+enum {
+ ATM128_ADC_VREF_OFF = 0, //!< VR+ = AREF and VR- = GND
+ ATM128_ADC_VREF_AVCC = 1,//!< VR+ = AVcc and VR- = GND
+ ATM128_ADC_VREF_RSVD,
+ ATM128_ADC_VREF_2_56 = 3,//!< VR+ = 2.56V and VR- = GND
+};
+
+/* Voltage Reference Settings */
+enum {
+ ATM128_ADC_RIGHT_ADJUST = 0,
+ ATM128_ADC_LEFT_ADJUST = 1,
+};
+
+
+/* ADC Multiplexer Settings */
+enum {
+ ATM128_ADC_SNGL_ADC0 = 0,
+ ATM128_ADC_SNGL_ADC1,
+ ATM128_ADC_SNGL_ADC2,
+ ATM128_ADC_SNGL_ADC3,
+ ATM128_ADC_SNGL_ADC4,
+ ATM128_ADC_SNGL_ADC5,
+ ATM128_ADC_SNGL_ADC6,
+ ATM128_ADC_SNGL_ADC7,
+ ATM128_ADC_DIFF_ADC00_10x,
+ ATM128_ADC_DIFF_ADC10_10x,
+ ATM128_ADC_DIFF_ADC00_200x,
+ ATM128_ADC_DIFF_ADC10_200x,
+ ATM128_ADC_DIFF_ADC22_10x,
+ ATM128_ADC_DIFF_ADC32_10x,
+ ATM128_ADC_DIFF_ADC22_200x,
+ ATM128_ADC_DIFF_ADC32_200x,
+ ATM128_ADC_DIFF_ADC01_1x,
+ ATM128_ADC_DIFF_ADC11_1x,
+ ATM128_ADC_DIFF_ADC21_1x,
+ ATM128_ADC_DIFF_ADC31_1x,
+ ATM128_ADC_DIFF_ADC41_1x,
+ ATM128_ADC_DIFF_ADC51_1x,
+ ATM128_ADC_DIFF_ADC61_1x,
+ ATM128_ADC_DIFF_ADC71_1x,
+ ATM128_ADC_DIFF_ADC02_1x,
+ ATM128_ADC_DIFF_ADC12_1x,
+ ATM128_ADC_DIFF_ADC22_1x,
+ ATM128_ADC_DIFF_ADC32_1x,
+ ATM128_ADC_DIFF_ADC42_1x,
+ ATM128_ADC_DIFF_ADC52_1x,
+ ATM128_ADC_SNGL_1_23,
+ ATM128_ADC_SNGL_GND,
+};
+
+/* ADC Multiplexer Selection Register */
+typedef struct
+{
+ uint8_t mux : 5; //!< Analog Channel and Gain Selection Bits
+ uint8_t adlar : 1; //!< ADC Left Adjust Result
+ uint8_t refs : 2; //!< Reference Selection Bits
+} Atm128Admux_t;
+
+/* ADC Prescaler Settings */
+/* Note: each platform must define ATM128_ADC_PRESCALE to the smallest
+ prescaler which guarantees full A/D precision. */
+enum {
+ ATM128_ADC_PRESCALE_2 = 0,
+ ATM128_ADC_PRESCALE_2b,
+ ATM128_ADC_PRESCALE_4,
+ ATM128_ADC_PRESCALE_8,
+ ATM128_ADC_PRESCALE_16,
+ ATM128_ADC_PRESCALE_32,
+ ATM128_ADC_PRESCALE_64,
+ ATM128_ADC_PRESCALE_128,
+
+ // This special value is used to ask the platform for the prescaler
+ // which gives full precision.
+ ATM128_ADC_PRESCALE
+};
+
+/* ADC Enable Settings */
+enum {
+ ATM128_ADC_ENABLE_OFF = 0,
+ ATM128_ADC_ENABLE_ON,
+};
+
+/* ADC Start Conversion Settings */
+enum {
+ ATM128_ADC_START_CONVERSION_OFF = 0,
+ ATM128_ADC_START_CONVERSION_ON,
+};
+
+/* ADC Free Running Select Settings */
+enum {
+ ATM128_ADC_FREE_RUNNING_OFF = 0,
+ ATM128_ADC_FREE_RUNNING_ON,
+};
+
+/* ADC Interrupt Flag Settings */
+enum {
+ ATM128_ADC_INT_FLAG_OFF = 0,
+ ATM128_ADC_INT_FLAG_ON,
+};
+
+/* ADC Interrupt Enable Settings */
+enum {
+ ATM128_ADC_INT_ENABLE_OFF = 0,
+ ATM128_ADC_INT_ENABLE_ON,
+};
+
+/* ADC Multiplexer Selection Register */
+typedef struct
+{
+ uint8_t adps : 3; //!< ADC Prescaler Select Bits
+ uint8_t adie : 1; //!< ADC Interrupt Enable
+ uint8_t adif : 1; //!< ADC Interrupt Flag
+ uint8_t adfr : 1; //!< ADC Free Running Select
+ uint8_t adsc : 1; //!< ADC Start Conversion
+ uint8_t aden : 1; //!< ADC Enable
+} Atm128Adcsra_t;
+
+typedef uint8_t Atm128_ADCH_t; //!< ADC data register high
+typedef uint8_t Atm128_ADCL_t; //!< ADC data register low
+
+// The resource identifier string for the ADC subsystem
+#define UQ_ATM128ADC_RESOURCE "atm128adc.resource"
+
+#endif //_H_Atm128ADC_h
+
-/// $Id$\r
-\r
-/*\r
- * Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved.\r
- *\r
- * Permission to use, copy, modify, and distribute this software and its\r
- * documentation for any purpose, without fee, and without written agreement is\r
- * hereby granted, provided that the above copyright notice, the following\r
- * two paragraphs and the author appear in all copies of this software.\r
- * \r
- * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO \r
- * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL \r
- * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN\r
- * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH \r
- * DAMAGE. \r
- *\r
- * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,\r
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY \r
- * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS \r
- * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY \r
- * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR \r
- * MODIFICATIONS.\r
- *\r
- * Copyright (c) 2002-2005 Intel Corporation\r
- * All rights reserved.\r
- *\r
- * This file is distributed under the terms in the attached INTEL-LICENSE \r
- * file. If you do not find these files, copies can be found by writing to\r
- * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, \r
- * 94704. Attention: Intel License Inquiry.\r
- */\r
-\r
-/**\r
- * Hardware Abstraction Layer interface of Atmega128 for acquiring data\r
- * from multiple channels using the ATmega128's free-running mode.\r
- * <p>\r
- * Because of the possibility that samples may be imprecise after \r
- * switching channels and/or reference voltages, and because there\r
- * is a one sample delay on swithcing channels and reference voltages,\r
- * Atm128ADCMultiple is complex. Two straightforward uses are:\r
- * <ol type="A">\r
- * <li>Acquire N samples from channel C:\r
- * <ol>\r
- * <li>call getData to start sampling on channel C at the desired rate\r
- * (note that the choice of prescalers is very limited, so you\r
- * don't have many choices for sampling rate)\r
- * <li>ignore the first dataReady event\r
- * <li>use the results of the next N dataReady() events, return FALSE\r
- * on the last one\r
- * </ol>\r
- * <li>Acquire one sample each from channels C1, ..., Cn (this pseudocode\r
- * assumes that none of these channels are differential)\r
- * <ol>\r
- * <li>call getData to start sampling on channel C1\r
- * <li>on the ith dataReady event switch to channel Ci+1 by changing\r
- * *newChannel\r
- * <li>the data passed to the ith dataReady event is for channel Ci-1\r
- * (the data from the first dataReady event is ignored)\r
- * </ol>\r
- * </ol>\r
- *\r
- * @author Hu Siquan <husq@xbow.com>\r
- * @author David Gay\r
- */ \r
-\r
-#include "Atm128Adc.h"\r
-\r
-interface Atm128AdcMultiple\r
-{\r
- /**\r
- * Initiates free-running ADC conversions, with the ability to switch \r
- * channels and reference-voltage with a one sample delay.\r
- *\r
- * @param channel Initial A/D conversion channel. The channel can \r
- * be changed in the dataReady event, though these changes happen\r
- * with a one-sample delay (this is a hardware restriction).\r
- * @param refVoltage Initial A/D reference voltage. See the\r
- * ATM128_ADC_VREF_xxx constants in Atm128ADC.h. Like the channel,\r
- * the reference voltage can be changed in the dataReady event with\r
- * a one-sample delay.\r
- * @param leftJustify TRUE to place A/D result in high-order bits \r
- * (i.e., shifted left by 6 bits), low to place it in the low-order bits\r
- * @param prescaler Prescaler value for the A/D conversion clock. If you \r
- * specify ATM128_ADC_PRESCALE, a prescaler will be chosen that guarantees\r
- * full precision. Other prescalers can be used to get faster conversions. \r
- * See the ATmega128 manual for details.\r
- * @return TRUE if the conversion will be precise, FALSE if it will be \r
- * imprecise (due to a change in reference voltage, or switching to a\r
- * differential input channel)\r
- */\r
- async command bool getData(uint8_t channel, uint8_t refVoltage,\r
- bool leftJustify, uint8_t prescaler);\r
- \r
- /**\r
- * Returns the next sample in a free-running conversion. Allow the user\r
- * to switch channels and/or reference voltages with a one sample delay.\r
- *\r
- * @param data a 2 byte unsigned data value sampled by the ADC.\r
- * @param precise if this conversion was precise, FALSE if it wasn't \r
- * (we assume that the second conversion after a change of reference\r
- * voltage or after switching to a differential channel is precise)\r
- * @param channel Channel this sample was from.\r
- * @param newChannel Change this parameter to switch to a new channel\r
- * for the second next sample.\r
- * @param newRefVoltage Change this parameter to change the reference \r
- * voltage for the second next sample.\r
- *\r
- * @return TRUE to continue sampling, FALSE to stop.\r
- */ \r
- async event bool dataReady(uint16_t data, bool precise, uint8_t channel,\r
- uint8_t *newChannel, uint8_t *newRefVoltage);\r
-\r
-\r
- /* Note: there is no cancel in free-running mode because you cannot tell\r
- from a successful (or unsuccessful) cancellation whether there will\r
- be another dataReady event. Thus you cannot tell when you can safely\r
- reuse the ADC (short of waiting one ADC conversion period, in which\r
- case you might as well use the result of dataReady to cancel).\r
- */\r
-}\r
+/// $Id$
+
+/*
+ * Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation for any purpose, without fee, and without written agreement is
+ * hereby granted, provided that the above copyright notice, the following
+ * two paragraphs and the author appear in all copies of this software.
+ *
+ * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+ * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN
+ * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ *
+ * Copyright (c) 2002-2005 Intel Corporation
+ * All rights reserved.
+ *
+ * This file is distributed under the terms in the attached INTEL-LICENSE
+ * file. If you do not find these files, copies can be found by writing to
+ * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,
+ * 94704. Attention: Intel License Inquiry.
+ */
+
+/**
+ * Hardware Abstraction Layer interface of Atmega128 for acquiring data
+ * from multiple channels using the ATmega128's free-running mode.
+ * <p>
+ * Because of the possibility that samples may be imprecise after
+ * switching channels and/or reference voltages, and because there
+ * is a one sample delay on swithcing channels and reference voltages,
+ * Atm128ADCMultiple is complex. Two straightforward uses are:
+ * <ol type="A">
+ * <li>Acquire N samples from channel C:
+ * <ol>
+ * <li>call getData to start sampling on channel C at the desired rate
+ * (note that the choice of prescalers is very limited, so you
+ * don't have many choices for sampling rate)
+ * <li>ignore the first dataReady event
+ * <li>use the results of the next N dataReady() events, return FALSE
+ * on the last one
+ * </ol>
+ * <li>Acquire one sample each from channels C1, ..., Cn (this pseudocode
+ * assumes that none of these channels are differential)
+ * <ol>
+ * <li>call getData to start sampling on channel C1
+ * <li>on the ith dataReady event switch to channel Ci+1 by changing
+ * *newChannel
+ * <li>the data passed to the ith dataReady event is for channel Ci-1
+ * (the data from the first dataReady event is ignored)
+ * </ol>
+ * </ol>
+ *
+ * @author Hu Siquan <husq@xbow.com>
+ * @author David Gay
+ */
+
+#include "Atm128Adc.h"
+
+interface Atm128AdcMultiple
+{
+ /**
+ * Initiates free-running ADC conversions, with the ability to switch
+ * channels and reference-voltage with a one sample delay.
+ *
+ * @param channel Initial A/D conversion channel. The channel can
+ * be changed in the dataReady event, though these changes happen
+ * with a one-sample delay (this is a hardware restriction).
+ * @param refVoltage Initial A/D reference voltage. See the
+ * ATM128_ADC_VREF_xxx constants in Atm128ADC.h. Like the channel,
+ * the reference voltage can be changed in the dataReady event with
+ * a one-sample delay.
+ * @param leftJustify TRUE to place A/D result in high-order bits
+ * (i.e., shifted left by 6 bits), low to place it in the low-order bits
+ * @param prescaler Prescaler value for the A/D conversion clock. If you
+ * specify ATM128_ADC_PRESCALE, a prescaler will be chosen that guarantees
+ * full precision. Other prescalers can be used to get faster conversions.
+ * See the ATmega128 manual for details.
+ * @return TRUE if the conversion will be precise, FALSE if it will be
+ * imprecise (due to a change in reference voltage, or switching to a
+ * differential input channel)
+ */
+ async command bool getData(uint8_t channel, uint8_t refVoltage,
+ bool leftJustify, uint8_t prescaler);
+
+ /**
+ * Returns the next sample in a free-running conversion. Allow the user
+ * to switch channels and/or reference voltages with a one sample delay.
+ *
+ * @param data a 2 byte unsigned data value sampled by the ADC.
+ * @param precise if this conversion was precise, FALSE if it wasn't
+ * (we assume that the second conversion after a change of reference
+ * voltage or after switching to a differential channel is precise)
+ * @param channel Channel this sample was from.
+ * @param newChannel Change this parameter to switch to a new channel
+ * for the second next sample.
+ * @param newRefVoltage Change this parameter to change the reference
+ * voltage for the second next sample.
+ *
+ * @return TRUE to continue sampling, FALSE to stop.
+ */
+ async event bool dataReady(uint16_t data, bool precise, uint8_t channel,
+ uint8_t *newChannel, uint8_t *newRefVoltage);
+
+
+ /* Note: there is no cancel in free-running mode because you cannot tell
+ from a successful (or unsuccessful) cancellation whether there will
+ be another dataReady event. Thus you cannot tell when you can safely
+ reuse the ADC (short of waiting one ADC conversion period, in which
+ case you might as well use the result of dataReady to cancel).
+ */
+}
-/* $Id$\r
- * "Copyright (c) 2000-2003 The Regents of the University of California. \r
- * All rights reserved.\r
- *\r
- * Permission to use, copy, modify, and distribute this software and its\r
- * documentation for any purpose, without fee, and without written agreement is\r
- * hereby granted, provided that the above copyright notice, the following\r
- * two paragraphs and the author appear in all copies of this software.\r
- * \r
- * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR\r
- * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT\r
- * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF\r
- * CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * \r
- * THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\r
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY\r
- * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS\r
- * ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO\r
- * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."\r
- *\r
- * Copyright (c) 2002-2005 Intel Corporation\r
- * All rights reserved.\r
- *\r
- * This file is distributed under the terms in the attached INTEL-LICENSE \r
- * file. If you do not find these files, copies can be found by writing to\r
- * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, \r
- * 94704. Attention: Intel License Inquiry.\r
- *\r
- * Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved.\r
- *\r
- * Permission to use, copy, modify, and distribute this software and its\r
- * documentation for any purpose, without fee, and without written agreement is\r
- * hereby granted, provided that the above copyright notice, the following\r
- * two paragraphs and the author appear in all copies of this software.\r
- * \r
- * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO \r
- * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL \r
- * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN\r
- * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH \r
- * DAMAGE. \r
- *\r
- * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,\r
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY \r
- * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS \r
- * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY \r
- * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR \r
- * MODIFICATIONS.\r
- */\r
-\r
-#include "Atm128Adc.h"\r
-\r
-/**\r
- * Internal component of the Atmega128 A/D HAL.\r
- *\r
- * @author Jason Hill\r
- * @author David Gay\r
- * @author Philip Levis\r
- * @author Phil Buonadonna\r
- * @author Hu Siquan <husq@xbow.com>\r
- */\r
-\r
-module Atm128AdcP \r
-{\r
- provides {\r
- interface Init;\r
- interface AsyncStdControl;\r
- interface Atm128AdcSingle;\r
- interface Atm128AdcMultiple;\r
- }\r
- uses {\r
- interface HplAtm128Adc;\r
- interface Atm128Calibrate;\r
- }\r
-}\r
-implementation\r
-{ \r
- /* State for the current and next (multiple-sampling only) conversion */\r
- struct {\r
- bool multiple : 1; /* single and multiple-sampling mode */\r
- bool precise : 1; /* is this result going to be precise? */\r
- uint8_t channel : 5; /* what channel did this sample come from? */\r
- } f, nextF;\r
- \r
- command error_t Init.init() {\r
- atomic\r
- {\r
- Atm128Adcsra_t adcsr;\r
-\r
- adcsr.aden = ATM128_ADC_ENABLE_OFF;\r
- adcsr.adsc = ATM128_ADC_START_CONVERSION_OFF; \r
- adcsr.adfr = ATM128_ADC_FREE_RUNNING_OFF; \r
- adcsr.adif = ATM128_ADC_INT_FLAG_OFF; \r
- adcsr.adie = ATM128_ADC_INT_ENABLE_OFF; \r
- adcsr.adps = ATM128_ADC_PRESCALE_2;\r
- call HplAtm128Adc.setAdcsra(adcsr);\r
- }\r
- return SUCCESS;\r
- }\r
-\r
- /* We enable the A/D when start is called, and disable it when stop is\r
- called. This drops A/D conversion latency by a factor of two (but\r
- increases idle mode power consumption a little). \r
- */\r
- async command error_t AsyncStdControl.start() {\r
- atomic call HplAtm128Adc.enableAdc();\r
- return SUCCESS;\r
- }\r
-\r
- async command error_t AsyncStdControl.stop() {\r
- atomic call HplAtm128Adc.disableAdc();\r
-\r
- return SUCCESS;\r
- }\r
-\r
- /* Return TRUE if switching to 'channel' with reference voltage 'refVoltage'\r
- will give a precise result (the first sample after changing reference\r
- voltage or switching to/between a differential channel is imprecise)\r
- */\r
- inline bool isPrecise(Atm128Admux_t admux, uint8_t channel, uint8_t refVoltage) {\r
- return refVoltage == admux.refs &&\r
- (channel <= ATM128_ADC_SNGL_ADC7 || channel >= ATM128_ADC_SNGL_1_23 || channel == admux.mux);\r
- }\r
-\r
- async event void HplAtm128Adc.dataReady(uint16_t data) {\r
- bool precise, multiple;\r
- uint8_t channel;\r
-\r
- atomic \r
- {\r
- channel = f.channel;\r
- precise = f.precise;\r
- multiple = f.multiple;\r
- }\r
-\r
- if (!multiple)\r
- {\r
- /* A single sample. Disable the ADC interrupt to avoid starting\r
- a new sample at the next "sleep" instruction. */\r
- call HplAtm128Adc.disableInterruption();\r
- signal Atm128AdcSingle.dataReady(data, precise);\r
- }\r
- else\r
- {\r
- /* Multiple sampling. The user can:\r
- - tell us to stop sampling\r
- - or, to continue sampling on a new channel, possibly with a\r
- new reference voltage; however this change applies not to\r
- the next sample (the hardware has already started working on\r
- that), but on the one after.\r
- */\r
- bool cont;\r
- uint8_t nextChannel, nextVoltage;\r
- Atm128Admux_t admux;\r
-\r
- atomic \r
- {\r
- admux = call HplAtm128Adc.getAdmux();\r
- nextVoltage = admux.refs;\r
- nextChannel = admux.mux;\r
- }\r
-\r
- cont = signal Atm128AdcMultiple.dataReady(data, precise, channel,\r
- &nextChannel, &nextVoltage);\r
- atomic\r
- if (cont)\r
- {\r
- /* Switch channels and update our internal channel+precision\r
- tracking state (f and nextF). Note that this tracking will\r
- be incorrect if we take too long to get to this point. */\r
- admux.refs = nextVoltage;\r
- admux.mux = nextChannel;\r
- call HplAtm128Adc.setAdmux(admux);\r
-\r
- f = nextF;\r
- nextF.channel = nextChannel;\r
- nextF.precise = isPrecise(admux, nextChannel, nextVoltage);\r
- }\r
- else\r
- call HplAtm128Adc.cancel();\r
- }\r
- }\r
-\r
- /* Start sampling based on request parameters */\r
- void getData(uint8_t channel, uint8_t refVoltage, bool leftJustify, uint8_t prescaler) {\r
- Atm128Admux_t admux;\r
- Atm128Adcsra_t adcsr;\r
-\r
- admux = call HplAtm128Adc.getAdmux();\r
- f.precise = isPrecise(admux, channel, refVoltage);\r
- f.channel = channel;\r
-\r
- admux.refs = refVoltage;\r
- admux.adlar = leftJustify;\r
- admux.mux = channel;\r
- call HplAtm128Adc.setAdmux(admux);\r
-\r
- adcsr.aden = ATM128_ADC_ENABLE_ON;\r
- adcsr.adsc = ATM128_ADC_START_CONVERSION_ON;\r
- adcsr.adfr = f.multiple;\r
- adcsr.adif = ATM128_ADC_INT_FLAG_ON; // clear any stale flag\r
- adcsr.adie = ATM128_ADC_INT_ENABLE_ON;\r
- if (prescaler == ATM128_ADC_PRESCALE)\r
- prescaler = call Atm128Calibrate.adcPrescaler();\r
- adcsr.adps = prescaler;\r
- call HplAtm128Adc.setAdcsra(adcsr);\r
- }\r
-\r
- async command bool Atm128AdcSingle.getData(uint8_t channel, uint8_t refVoltage,\r
- bool leftJustify, uint8_t prescaler) {\r
- atomic\r
- {\r
- f.multiple = FALSE;\r
- getData(channel, refVoltage, leftJustify, prescaler);\r
-\r
- return f.precise;\r
- }\r
- }\r
-\r
- async command bool Atm128AdcSingle.cancel() {\r
- /* There is no Atm128AdcMultiple.cancel, for reasons discussed in that\r
- interface */\r
- return call HplAtm128Adc.cancel();\r
- }\r
-\r
- async command bool Atm128AdcMultiple.getData(uint8_t channel, uint8_t refVoltage,\r
- bool leftJustify, uint8_t prescaler) {\r
- atomic\r
- {\r
- f.multiple = TRUE;\r
- getData(channel, refVoltage, leftJustify, prescaler);\r
- nextF = f;\r
- /* We assume the 2nd sample is precise */\r
- nextF.precise = TRUE;\r
-\r
- return f.precise;\r
- }\r
- }\r
-\r
- default async event void Atm128AdcSingle.dataReady(uint16_t data, bool precise) {\r
- }\r
-\r
- default async event bool Atm128AdcMultiple.dataReady(uint16_t data, bool precise, uint8_t channel,\r
- uint8_t *newChannel, uint8_t *newRefVoltage) {\r
- return FALSE; // stop conversion if we somehow end up here.\r
- }\r
-}\r
+/* $Id$
+ * "Copyright (c) 2000-2003 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation for any purpose, without fee, and without written agreement is
+ * hereby granted, provided that the above copyright notice, the following
+ * two paragraphs and the author appear in all copies of this software.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
+ * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
+ * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF
+ * CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
+ *
+ * Copyright (c) 2002-2005 Intel Corporation
+ * All rights reserved.
+ *
+ * This file is distributed under the terms in the attached INTEL-LICENSE
+ * file. If you do not find these files, copies can be found by writing to
+ * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,
+ * 94704. Attention: Intel License Inquiry.
+ *
+ * Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation for any purpose, without fee, and without written agreement is
+ * hereby granted, provided that the above copyright notice, the following
+ * two paragraphs and the author appear in all copies of this software.
+ *
+ * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+ * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN
+ * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ */
+
+#include "Atm128Adc.h"
+
+/**
+ * Internal component of the Atmega128 A/D HAL.
+ *
+ * @author Jason Hill
+ * @author David Gay
+ * @author Philip Levis
+ * @author Phil Buonadonna
+ * @author Hu Siquan <husq@xbow.com>
+ */
+
+module Atm128AdcP
+{
+ provides {
+ interface Init;
+ interface AsyncStdControl;
+ interface Atm128AdcSingle;
+ interface Atm128AdcMultiple;
+ }
+ uses {
+ interface HplAtm128Adc;
+ interface Atm128Calibrate;
+ }
+}
+implementation
+{
+ /* State for the current and next (multiple-sampling only) conversion */
+ struct {
+ bool multiple : 1; /* single and multiple-sampling mode */
+ bool precise : 1; /* is this result going to be precise? */
+ uint8_t channel : 5; /* what channel did this sample come from? */
+ } f, nextF;
+
+ command error_t Init.init() {
+ atomic
+ {
+ Atm128Adcsra_t adcsr;
+
+ adcsr.aden = ATM128_ADC_ENABLE_OFF;
+ adcsr.adsc = ATM128_ADC_START_CONVERSION_OFF;
+ adcsr.adfr = ATM128_ADC_FREE_RUNNING_OFF;
+ adcsr.adif = ATM128_ADC_INT_FLAG_OFF;
+ adcsr.adie = ATM128_ADC_INT_ENABLE_OFF;
+ adcsr.adps = ATM128_ADC_PRESCALE_2;
+ call HplAtm128Adc.setAdcsra(adcsr);
+ }
+ return SUCCESS;
+ }
+
+ /* We enable the A/D when start is called, and disable it when stop is
+ called. This drops A/D conversion latency by a factor of two (but
+ increases idle mode power consumption a little).
+ */
+ async command error_t AsyncStdControl.start() {
+ atomic call HplAtm128Adc.enableAdc();
+ return SUCCESS;
+ }
+
+ async command error_t AsyncStdControl.stop() {
+ atomic call HplAtm128Adc.disableAdc();
+
+ return SUCCESS;
+ }
+
+ /* Return TRUE if switching to 'channel' with reference voltage 'refVoltage'
+ will give a precise result (the first sample after changing reference
+ voltage or switching to/between a differential channel is imprecise)
+ */
+ inline bool isPrecise(Atm128Admux_t admux, uint8_t channel, uint8_t refVoltage) {
+ return refVoltage == admux.refs &&
+ (channel <= ATM128_ADC_SNGL_ADC7 || channel >= ATM128_ADC_SNGL_1_23 || channel == admux.mux);
+ }
+
+ async event void HplAtm128Adc.dataReady(uint16_t data) {
+ bool precise, multiple;
+ uint8_t channel;
+
+ atomic
+ {
+ channel = f.channel;
+ precise = f.precise;
+ multiple = f.multiple;
+ }
+
+ if (!multiple)
+ {
+ /* A single sample. Disable the ADC interrupt to avoid starting
+ a new sample at the next "sleep" instruction. */
+ call HplAtm128Adc.disableInterruption();
+ signal Atm128AdcSingle.dataReady(data, precise);
+ }
+ else
+ {
+ /* Multiple sampling. The user can:
+ - tell us to stop sampling
+ - or, to continue sampling on a new channel, possibly with a
+ new reference voltage; however this change applies not to
+ the next sample (the hardware has already started working on
+ that), but on the one after.
+ */
+ bool cont;
+ uint8_t nextChannel, nextVoltage;
+ Atm128Admux_t admux;
+
+ atomic
+ {
+ admux = call HplAtm128Adc.getAdmux();
+ nextVoltage = admux.refs;
+ nextChannel = admux.mux;
+ }
+
+ cont = signal Atm128AdcMultiple.dataReady(data, precise, channel,
+ &nextChannel, &nextVoltage);
+ atomic
+ if (cont)
+ {
+ /* Switch channels and update our internal channel+precision
+ tracking state (f and nextF). Note that this tracking will
+ be incorrect if we take too long to get to this point. */
+ admux.refs = nextVoltage;
+ admux.mux = nextChannel;
+ call HplAtm128Adc.setAdmux(admux);
+
+ f = nextF;
+ nextF.channel = nextChannel;
+ nextF.precise = isPrecise(admux, nextChannel, nextVoltage);
+ }
+ else
+ call HplAtm128Adc.cancel();
+ }
+ }
+
+ /* Start sampling based on request parameters */
+ void getData(uint8_t channel, uint8_t refVoltage, bool leftJustify, uint8_t prescaler) {
+ Atm128Admux_t admux;
+ Atm128Adcsra_t adcsr;
+
+ admux = call HplAtm128Adc.getAdmux();
+ f.precise = isPrecise(admux, channel, refVoltage);
+ f.channel = channel;
+
+ admux.refs = refVoltage;
+ admux.adlar = leftJustify;
+ admux.mux = channel;
+ call HplAtm128Adc.setAdmux(admux);
+
+ adcsr.aden = ATM128_ADC_ENABLE_ON;
+ adcsr.adsc = ATM128_ADC_START_CONVERSION_ON;
+ adcsr.adfr = f.multiple;
+ adcsr.adif = ATM128_ADC_INT_FLAG_ON; // clear any stale flag
+ adcsr.adie = ATM128_ADC_INT_ENABLE_ON;
+ if (prescaler == ATM128_ADC_PRESCALE)
+ prescaler = call Atm128Calibrate.adcPrescaler();
+ adcsr.adps = prescaler;
+ call HplAtm128Adc.setAdcsra(adcsr);
+ }
+
+ async command bool Atm128AdcSingle.getData(uint8_t channel, uint8_t refVoltage,
+ bool leftJustify, uint8_t prescaler) {
+ atomic
+ {
+ f.multiple = FALSE;
+ getData(channel, refVoltage, leftJustify, prescaler);
+
+ return f.precise;
+ }
+ }
+
+ async command bool Atm128AdcSingle.cancel() {
+ /* There is no Atm128AdcMultiple.cancel, for reasons discussed in that
+ interface */
+ return call HplAtm128Adc.cancel();
+ }
+
+ async command bool Atm128AdcMultiple.getData(uint8_t channel, uint8_t refVoltage,
+ bool leftJustify, uint8_t prescaler) {
+ atomic
+ {
+ f.multiple = TRUE;
+ getData(channel, refVoltage, leftJustify, prescaler);
+ nextF = f;
+ /* We assume the 2nd sample is precise */
+ nextF.precise = TRUE;
+
+ return f.precise;
+ }
+ }
+
+ default async event void Atm128AdcSingle.dataReady(uint16_t data, bool precise) {
+ }
+
+ default async event bool Atm128AdcMultiple.dataReady(uint16_t data, bool precise, uint8_t channel,
+ uint8_t *newChannel, uint8_t *newRefVoltage) {
+ return FALSE; // stop conversion if we somehow end up here.
+ }
+}
-/// $Id$\r
-\r
-/*\r
- * Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved.\r
- *\r
- * Permission to use, copy, modify, and distribute this software and its\r
- * documentation for any purpose, without fee, and without written agreement is\r
- * hereby granted, provided that the above copyright notice, the following\r
- * two paragraphs and the author appear in all copies of this software.\r
- * \r
- * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO \r
- * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL \r
- * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN\r
- * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH \r
- * DAMAGE. \r
- *\r
- * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,\r
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY \r
- * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS \r
- * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY \r
- * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR \r
- * MODIFICATIONS.\r
- *\r
- * Copyright (c) 2002-2005 Intel Corporation\r
- * All rights reserved.\r
- *\r
- * This file is distributed under the terms in the attached INTEL-LICENSE \r
- * file. If you do not find these files, copies can be found by writing to\r
- * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, \r
- * 94704. Attention: Intel License Inquiry.\r
- */\r
-\r
-/**\r
- * Hardware Abstraction Layer interface of Atmega128 for acquiring\r
- * a single sample from a channel.\r
- *\r
- * @author Hu Siquan <husq@xbow.com>\r
- * @author David Gay\r
- */\r
-\r
-#include "Atm128Adc.h"\r
-\r
-interface Atm128AdcSingle\r
-{\r
- /**\r
- * Initiates an ADC conversion on a given channel.\r
- *\r
- * @param channel A/D conversion channel.\r
- * @param refVoltage Select reference voltage for A/D conversion. See\r
- * the ATM128_ADC_VREF_xxx constants in Atm128ADC.h\r
- * @param leftJustify TRUE to place A/D result in high-order bits \r
- * (i.e., shifted left by 6 bits), low to place it in the low-order bits\r
- * @param prescaler Prescaler value for the A/D conversion clock. If you \r
- * specify ATM128_ADC_PRESCALE, a prescaler will be chosen that guarantees\r
- * full precision. Other prescalers can be used to get faster conversions. \r
- * See the ATmega128 manual for details.\r
- * @return TRUE if the conversion will be precise, FALSE if it will be \r
- * imprecise (due to a change in refernce voltage, or switching to a\r
- * differential input channel)\r
- */\r
- async command bool getData(uint8_t channel, uint8_t refVoltage,\r
- bool leftJustify, uint8_t prescaler);\r
- \r
- /**\r
- * Indicates a sample has been recorded by the ADC as the result\r
- * of a <code>getData()</code> command.\r
- *\r
- * @param data a 2 byte unsigned data value sampled by the ADC.\r
- * @param precise if the conversion precise, FALSE if it wasn't. This\r
- * values matches the result from the <code>getData</code> call.\r
- */ \r
- async event void dataReady(uint16_t data, bool precise);\r
-\r
- /**\r
- * Cancel an outstanding getData operation. Use with care, to\r
- * avoid problems with races between the dataReady event and cancel.\r
- * @return TRUE if a conversion was in-progress or an interrupt\r
- * was pending. dataReady will not be signaled. FALSE if the\r
- * conversion was already complete. dataReady will be (or has\r
- * already been) signaled.\r
- */\r
- async command bool cancel();\r
-}\r
+/// $Id$
+
+/*
+ * Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation for any purpose, without fee, and without written agreement is
+ * hereby granted, provided that the above copyright notice, the following
+ * two paragraphs and the author appear in all copies of this software.
+ *
+ * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+ * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN
+ * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ *
+ * Copyright (c) 2002-2005 Intel Corporation
+ * All rights reserved.
+ *
+ * This file is distributed under the terms in the attached INTEL-LICENSE
+ * file. If you do not find these files, copies can be found by writing to
+ * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,
+ * 94704. Attention: Intel License Inquiry.
+ */
+
+/**
+ * Hardware Abstraction Layer interface of Atmega128 for acquiring
+ * a single sample from a channel.
+ *
+ * @author Hu Siquan <husq@xbow.com>
+ * @author David Gay
+ */
+
+#include "Atm128Adc.h"
+
+interface Atm128AdcSingle
+{
+ /**
+ * Initiates an ADC conversion on a given channel.
+ *
+ * @param channel A/D conversion channel.
+ * @param refVoltage Select reference voltage for A/D conversion. See
+ * the ATM128_ADC_VREF_xxx constants in Atm128ADC.h
+ * @param leftJustify TRUE to place A/D result in high-order bits
+ * (i.e., shifted left by 6 bits), low to place it in the low-order bits
+ * @param prescaler Prescaler value for the A/D conversion clock. If you
+ * specify ATM128_ADC_PRESCALE, a prescaler will be chosen that guarantees
+ * full precision. Other prescalers can be used to get faster conversions.
+ * See the ATmega128 manual for details.
+ * @return TRUE if the conversion will be precise, FALSE if it will be
+ * imprecise (due to a change in refernce voltage, or switching to a
+ * differential input channel)
+ */
+ async command bool getData(uint8_t channel, uint8_t refVoltage,
+ bool leftJustify, uint8_t prescaler);
+
+ /**
+ * Indicates a sample has been recorded by the ADC as the result
+ * of a <code>getData()</code> command.
+ *
+ * @param data a 2 byte unsigned data value sampled by the ADC.
+ * @param precise if the conversion precise, FALSE if it wasn't. This
+ * values matches the result from the <code>getData</code> call.
+ */
+ async event void dataReady(uint16_t data, bool precise);
+
+ /**
+ * Cancel an outstanding getData operation. Use with care, to
+ * avoid problems with races between the dataReady event and cancel.
+ * @return TRUE if a conversion was in-progress or an interrupt
+ * was pending. dataReady will not be signaled. FALSE if the
+ * conversion was already complete. dataReady will be (or has
+ * already been) signaled.
+ */
+ async command bool cancel();
+}
-/// $Id$\r
+/// $Id$
/*
* Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved.
-/// $Id$\r
+/// $Id$
/*
* Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved.
-/// $Id$\r
+/// $Id$
/*
* Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved.
*
-/* \r
- * Copyright (c) 2006, Technische Universitaet Berlin\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions\r
- * are met:\r
- * - Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * - Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * - Neither the name of the Technische Universitaet Berlin nor the names\r
- * of its contributors may be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED\r
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY\r
- * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- * - Revision -------------------------------------------------------------\r
- * $Revision$\r
- * $Date$\r
- * @author: Jan Hauer <hauer@tkn.tu-berlin.de>\r
- * ========================================================================\r
- */\r
-\r
-/** \r
- * This component virtualizes access to the HAL of the MSP430 ADC12. ADC\r
- * conversion results are copied using DMA.\r
- * \r
- * @author Jan Hauer \r
- *\r
- * @see Please refer to the README.txt and TEP 101 for more information about\r
- * this component and its intended use.\r
- */\r
-#include <Msp430Adc12.h>\r
-generic configuration Msp430Adc12ClientAutoDMAC()\r
-{\r
- provides {\r
- interface Resource;\r
- interface Msp430Adc12SingleChannel;\r
- interface Msp430Adc12Overflow;\r
- }\r
-} implementation {\r
- components Msp430DmaC, Msp430Adc12DMAP, Msp430Adc12P, Msp430Adc12DMAWireC;\r
- \r
- enum {\r
- ID = unique(MSP430ADC12_RESOURCE),\r
- };\r
- Resource = Msp430Adc12P.Resource[ID];\r
- Msp430Adc12SingleChannel = Msp430Adc12DMAP.SingleChannel[ID];\r
- Msp430Adc12Overflow = Msp430Adc12P.Overflow[ID];\r
- \r
- Msp430Adc12DMAP.SubSingleChannel[ID] -> Msp430Adc12P.SingleChannel[ID];\r
- Msp430Adc12DMAP.AsyncAdcControl[ID] -> Msp430Adc12P.DMAExtension[ID];\r
-\r
-}\r
+/*
+ * Copyright (c) 2006, Technische Universitaet Berlin
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of the Technische Universitaet Berlin nor the names
+ * of its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * - Revision -------------------------------------------------------------
+ * $Revision$
+ * $Date$
+ * @author: Jan Hauer <hauer@tkn.tu-berlin.de>
+ * ========================================================================
+ */
+
+/**
+ * This component virtualizes access to the HAL of the MSP430 ADC12. ADC
+ * conversion results are copied using DMA.
+ *
+ * @author Jan Hauer
+ *
+ * @see Please refer to the README.txt and TEP 101 for more information about
+ * this component and its intended use.
+ */
+#include <Msp430Adc12.h>
+generic configuration Msp430Adc12ClientAutoDMAC()
+{
+ provides {
+ interface Resource;
+ interface Msp430Adc12SingleChannel;
+ interface Msp430Adc12Overflow;
+ }
+} implementation {
+ components Msp430DmaC, Msp430Adc12DMAP, Msp430Adc12P, Msp430Adc12DMAWireC;
+
+ enum {
+ ID = unique(MSP430ADC12_RESOURCE),
+ };
+ Resource = Msp430Adc12P.Resource[ID];
+ Msp430Adc12SingleChannel = Msp430Adc12DMAP.SingleChannel[ID];
+ Msp430Adc12Overflow = Msp430Adc12P.Overflow[ID];
+
+ Msp430Adc12DMAP.SubSingleChannel[ID] -> Msp430Adc12P.SingleChannel[ID];
+ Msp430Adc12DMAP.AsyncAdcControl[ID] -> Msp430Adc12P.DMAExtension[ID];
+
+}
-/* \r
- * Copyright (c) 2006, Technische Universitaet Berlin All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are met:\r
- * - Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer. - Redistributions in\r
- * binary form must reproduce the above copyright notice, this list of\r
- * conditions and the following disclaimer in the documentation and/or other\r
- * materials provided with the distribution. - Neither the name of the\r
- * Technische Universitaet Berlin nor the names of its contributors may be used\r
- * to endorse or promote products derived from this software without specific\r
- * prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\r
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- * POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- * - Revision -------------------------------------------------------------\r
- * $Revision$ $Date$ @author: Jan Hauer\r
- * <hauer@tkn.tu-berlin.de>\r
- * ========================================================================\r
- */\r
- \r
-\r
-/** \r
- * This component virtualizes access to the HAL of the MSP430 ADC12. ADC\r
- * conversion results are copied using DMA and reference voltage is enabled as\r
- * required by the configuration.\r
- * \r
- * @author Jan Hauer \r
- *\r
- * @see Please refer to the README.txt and TEP 101 for more information about\r
- * this component and its intended use.\r
- */\r
-#include <Msp430Adc12.h>\r
-generic configuration Msp430Adc12ClientAutoDMA_RVGC()\r
-{\r
- provides {\r
- interface Resource;\r
- interface Msp430Adc12SingleChannel;\r
- interface Msp430Adc12Overflow;\r
- }\r
- uses interface AdcConfigure<const msp430adc12_channel_config_t*>;\r
-} implementation {\r
- components Msp430Adc12P, Msp430RefVoltArbiterP, Msp430Adc12DMAWireC;\r
-\r
- enum {\r
- ID = unique(MSP430ADC12_RESOURCE),\r
- };\r
- Resource = Msp430RefVoltArbiterP.ClientResource[ID];\r
- Msp430Adc12Overflow = Msp430Adc12P.Overflow[ID];\r
- \r
- Msp430RefVoltArbiterP.AdcResource[ID] -> Msp430Adc12P.Resource[ID];\r
-\r
- components new Msp430Adc12ConfAlertC();\r
- AdcConfigure = Msp430Adc12ConfAlertC.ConfUp;\r
- Msp430RefVoltArbiterP.Config[ID] -> Msp430Adc12ConfAlertC.ConfSub; \r
-\r
- components Msp430DmaC, Msp430Adc12DMAP;\r
- \r
- Msp430Adc12SingleChannel = Msp430Adc12DMAP.SingleChannel[ID];\r
- \r
- Msp430Adc12DMAP.SubSingleChannel[ID] -> Msp430Adc12P.SingleChannel[ID];\r
- Msp430Adc12DMAP.AsyncAdcControl[ID] -> Msp430Adc12P.DMAExtension[ID];\r
-}\r
+/*
+ * Copyright (c) 2006, Technische Universitaet Berlin All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. - Redistributions in
+ * binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or other
+ * materials provided with the distribution. - Neither the name of the
+ * Technische Universitaet Berlin nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * - Revision -------------------------------------------------------------
+ * $Revision$ $Date$ @author: Jan Hauer
+ * <hauer@tkn.tu-berlin.de>
+ * ========================================================================
+ */
+
+
+/**
+ * This component virtualizes access to the HAL of the MSP430 ADC12. ADC
+ * conversion results are copied using DMA and reference voltage is enabled as
+ * required by the configuration.
+ *
+ * @author Jan Hauer
+ *
+ * @see Please refer to the README.txt and TEP 101 for more information about
+ * this component and its intended use.
+ */
+#include <Msp430Adc12.h>
+generic configuration Msp430Adc12ClientAutoDMA_RVGC()
+{
+ provides {
+ interface Resource;
+ interface Msp430Adc12SingleChannel;
+ interface Msp430Adc12Overflow;
+ }
+ uses interface AdcConfigure<const msp430adc12_channel_config_t*>;
+} implementation {
+ components Msp430Adc12P, Msp430RefVoltArbiterP, Msp430Adc12DMAWireC;
+
+ enum {
+ ID = unique(MSP430ADC12_RESOURCE),
+ };
+ Resource = Msp430RefVoltArbiterP.ClientResource[ID];
+ Msp430Adc12Overflow = Msp430Adc12P.Overflow[ID];
+
+ Msp430RefVoltArbiterP.AdcResource[ID] -> Msp430Adc12P.Resource[ID];
+
+ components new Msp430Adc12ConfAlertC();
+ AdcConfigure = Msp430Adc12ConfAlertC.ConfUp;
+ Msp430RefVoltArbiterP.Config[ID] -> Msp430Adc12ConfAlertC.ConfSub;
+
+ components Msp430DmaC, Msp430Adc12DMAP;
+
+ Msp430Adc12SingleChannel = Msp430Adc12DMAP.SingleChannel[ID];
+
+ Msp430Adc12DMAP.SubSingleChannel[ID] -> Msp430Adc12P.SingleChannel[ID];
+ Msp430Adc12DMAP.AsyncAdcControl[ID] -> Msp430Adc12P.DMAExtension[ID];
+}
-/* \r
- * Copyright (c) 2006, Technische Universitaet Berlin All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are met:\r
- * - Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer. - Redistributions in\r
- * binary form must reproduce the above copyright notice, this list of\r
- * conditions and the following disclaimer in the documentation and/or other\r
- * materials provided with the distribution. - Neither the name of the\r
- * Technische Universitaet Berlin nor the names of its contributors may be used\r
- * to endorse or promote products derived from this software without specific\r
- * prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\r
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- * POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- * - Revision -------------------------------------------------------------\r
- * $Revision$ $Date$ @author: Jan Hauer\r
- * <hauer@tkn.tu-berlin.de>\r
- * ========================================================================\r
- */\r
- \r
-/** \r
- * This component virtualizes access to the HAL of the MSP430 ADC12.\r
- * Reference voltage is enabled automatically as required by the configuration.\r
- * \r
- * @author Jan Hauer \r
- *\r
- * @see Please refer to the README.txt and TEP 101 for more information about\r
- * this component and its intended use.\r
- */\r
-#include <Msp430Adc12.h> \r
-generic configuration Msp430Adc12ClientAutoRVGC()\r
-{\r
- provides {\r
- interface Resource;\r
- interface Msp430Adc12SingleChannel;\r
- interface Msp430Adc12MultiChannel;\r
- interface Msp430Adc12Overflow;\r
- }\r
- uses interface AdcConfigure<const msp430adc12_channel_config_t*>;\r
-} implementation {\r
- components Msp430Adc12P, Msp430RefVoltArbiterP;\r
-\r
- enum {\r
- ID = unique(MSP430ADC12_RESOURCE),\r
- };\r
- Resource = Msp430RefVoltArbiterP.ClientResource[ID];\r
- Msp430Adc12SingleChannel = Msp430Adc12P.SingleChannel[ID];\r
- Msp430Adc12MultiChannel = Msp430Adc12P.MultiChannel[ID];\r
- Msp430Adc12Overflow = Msp430Adc12P.Overflow[ID];\r
- \r
- Msp430RefVoltArbiterP.AdcResource[ID] -> Msp430Adc12P.Resource[ID];\r
-\r
- components new Msp430Adc12ConfAlertC();\r
- AdcConfigure = Msp430Adc12ConfAlertC.ConfUp;\r
- Msp430RefVoltArbiterP.Config[ID] -> Msp430Adc12ConfAlertC.ConfSub; \r
-}\r
+/*
+ * Copyright (c) 2006, Technische Universitaet Berlin All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. - Redistributions in
+ * binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or other
+ * materials provided with the distribution. - Neither the name of the
+ * Technische Universitaet Berlin nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * - Revision -------------------------------------------------------------
+ * $Revision$ $Date$ @author: Jan Hauer
+ * <hauer@tkn.tu-berlin.de>
+ * ========================================================================
+ */
+
+/**
+ * This component virtualizes access to the HAL of the MSP430 ADC12.
+ * Reference voltage is enabled automatically as required by the configuration.
+ *
+ * @author Jan Hauer
+ *
+ * @see Please refer to the README.txt and TEP 101 for more information about
+ * this component and its intended use.
+ */
+#include <Msp430Adc12.h>
+generic configuration Msp430Adc12ClientAutoRVGC()
+{
+ provides {
+ interface Resource;
+ interface Msp430Adc12SingleChannel;
+ interface Msp430Adc12MultiChannel;
+ interface Msp430Adc12Overflow;
+ }
+ uses interface AdcConfigure<const msp430adc12_channel_config_t*>;
+} implementation {
+ components Msp430Adc12P, Msp430RefVoltArbiterP;
+
+ enum {
+ ID = unique(MSP430ADC12_RESOURCE),
+ };
+ Resource = Msp430RefVoltArbiterP.ClientResource[ID];
+ Msp430Adc12SingleChannel = Msp430Adc12P.SingleChannel[ID];
+ Msp430Adc12MultiChannel = Msp430Adc12P.MultiChannel[ID];
+ Msp430Adc12Overflow = Msp430Adc12P.Overflow[ID];
+
+ Msp430RefVoltArbiterP.AdcResource[ID] -> Msp430Adc12P.Resource[ID];
+
+ components new Msp430Adc12ConfAlertC();
+ AdcConfigure = Msp430Adc12ConfAlertC.ConfUp;
+ Msp430RefVoltArbiterP.Config[ID] -> Msp430Adc12ConfAlertC.ConfSub;
+}
-/* \r
- * Copyright (c) 2006, Technische Universitaet Berlin\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions\r
- * are met:\r
- * - Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * - Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * - Neither the name of the Technische Universitaet Berlin nor the names\r
- * of its contributors may be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED\r
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY\r
- * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- * - Revision -------------------------------------------------------------\r
- * $Revision$\r
- * $Date$\r
- * @author: Jan Hauer <hauer@tkn.tu-berlin.de>\r
- * ========================================================================\r
- */\r
-\r
-/** \r
- * This component virtualizes access to the HAL of the MSP430 ADC12. \r
- * \r
- * @author Jan Hauer \r
- *\r
- * @see Please refer to the README.txt and TEP 101 for more information about\r
- * this component and its intended use.\r
- */\r
-#include <Msp430Adc12.h>\r
-generic configuration Msp430Adc12ClientC()\r
-{\r
- provides {\r
- interface Resource;\r
- interface Msp430Adc12SingleChannel;\r
- interface Msp430Adc12MultiChannel;\r
- interface Msp430Adc12Overflow;\r
- }\r
-} implementation {\r
- components Msp430Adc12P;\r
- \r
- enum {\r
- ID = unique(MSP430ADC12_RESOURCE),\r
- };\r
- Resource = Msp430Adc12P.Resource[ID];\r
- Msp430Adc12SingleChannel = Msp430Adc12P.SingleChannel[ID];\r
- Msp430Adc12MultiChannel = Msp430Adc12P.MultiChannel[ID];\r
- Msp430Adc12Overflow = Msp430Adc12P.Overflow[ID];\r
-}\r
+/*
+ * Copyright (c) 2006, Technische Universitaet Berlin
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of the Technische Universitaet Berlin nor the names
+ * of its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * - Revision -------------------------------------------------------------
+ * $Revision$
+ * $Date$
+ * @author: Jan Hauer <hauer@tkn.tu-berlin.de>
+ * ========================================================================
+ */
+
+/**
+ * This component virtualizes access to the HAL of the MSP430 ADC12.
+ *
+ * @author Jan Hauer
+ *
+ * @see Please refer to the README.txt and TEP 101 for more information about
+ * this component and its intended use.
+ */
+#include <Msp430Adc12.h>
+generic configuration Msp430Adc12ClientC()
+{
+ provides {
+ interface Resource;
+ interface Msp430Adc12SingleChannel;
+ interface Msp430Adc12MultiChannel;
+ interface Msp430Adc12Overflow;
+ }
+} implementation {
+ components Msp430Adc12P;
+
+ enum {
+ ID = unique(MSP430ADC12_RESOURCE),
+ };
+ Resource = Msp430Adc12P.Resource[ID];
+ Msp430Adc12SingleChannel = Msp430Adc12P.SingleChannel[ID];
+ Msp430Adc12MultiChannel = Msp430Adc12P.MultiChannel[ID];
+ Msp430Adc12Overflow = Msp430Adc12P.Overflow[ID];
+}
-/* \r
- * Copyright (c) 2006, Technische Universitaet Berlin All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are met:\r
- * - Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer. - Redistributions in\r
- * binary form must reproduce the above copyright notice, this list of\r
- * conditions and the following disclaimer in the documentation and/or other\r
- * materials provided with the distribution. - Neither the name of the\r
- * Technische Universitaet Berlin nor the names of its contributors may be used\r
- * to endorse or promote products derived from this software without specific\r
- * prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\r
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- * POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- * - Revision -------------------------------------------------------------\r
- * $Revision$ $Date$ @author: Jan Hauer\r
- * <hauer@tkn.tu-berlin.de>\r
- * ========================================================================\r
- */\r
- \r
-/** \r
- * The only purpose of this component is to generate a nesC warning\r
- * if someone has wired to Msp430Adc12ClientAutoRVGC or \r
- * Msp430Adc12ClientAutoDMA_RVGC and forgotten to wire to AdcConfigure.\r
- * (nesC optimizes all of its code away).\r
- *\r
- * @author: Jan Hauer\r
- */\r
-#include <Msp430Adc12.h> \r
-generic module Msp430Adc12ConfAlertC()\r
-{\r
- provides interface AdcConfigure<const msp430adc12_channel_config_t*> as ConfSub;\r
- uses interface AdcConfigure<const msp430adc12_channel_config_t*> as ConfUp;\r
-} implementation {\r
- async command const msp430adc12_channel_config_t* ConfSub.getConfiguration()\r
- {\r
- return call ConfUp.getConfiguration();\r
- }\r
-}\r
+/*
+ * Copyright (c) 2006, Technische Universitaet Berlin All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. - Redistributions in
+ * binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or other
+ * materials provided with the distribution. - Neither the name of the
+ * Technische Universitaet Berlin nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * - Revision -------------------------------------------------------------
+ * $Revision$ $Date$ @author: Jan Hauer
+ * <hauer@tkn.tu-berlin.de>
+ * ========================================================================
+ */
+
+/**
+ * The only purpose of this component is to generate a nesC warning
+ * if someone has wired to Msp430Adc12ClientAutoRVGC or
+ * Msp430Adc12ClientAutoDMA_RVGC and forgotten to wire to AdcConfigure.
+ * (nesC optimizes all of its code away).
+ *
+ * @author: Jan Hauer
+ */
+#include <Msp430Adc12.h>
+generic module Msp430Adc12ConfAlertC()
+{
+ provides interface AdcConfigure<const msp430adc12_channel_config_t*> as ConfSub;
+ uses interface AdcConfigure<const msp430adc12_channel_config_t*> as ConfUp;
+} implementation {
+ async command const msp430adc12_channel_config_t* ConfSub.getConfiguration()
+ {
+ return call ConfUp.getConfiguration();
+ }
+}
-// $Id$\r
-/* tab:4\r
- * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By\r
- * downloading, copying, installing or using the software you agree to\r
- * this license. If you do not agree to this license, do not download,\r
- * install, copy or use the software.\r
- *\r
- * Intel Open Source License \r
- *\r
- * Copyright (c) 2002 Intel Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * \r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * Neither the name of the Intel Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- * \r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * \r
- * \r
- */\r
-/**\r
- * This interface supports the core peripheral interrupts of the PXA27X \r
- * processor. \r
- * It is usually parameterized based on the Peripheral ID (PPID) of the \r
- * interrupt signal.\r
- * ARM interrupt levels (IRQ/FIQ) are established by wiring.\r
- * Priorities are established by a static table (TOSH_IRP_TABLE)\r
- *\r
- * Components implementing this interface are expected to provide reentrant\r
- * (i.e. atomic) semantics.\r
- *\r
- * @author: Philip Buonadonna\r
- */\r
-\r
-interface HplPXA27xInterrupt\r
-{\r
- /** \r
- * Allocates a given peripheral interrupt with the PXA27X interrupt manager.\r
- * Specifically, it establishes the interrupt level (IRQ or FIQ) and the \r
- * priority. \r
- */\r
- async command error_t allocate();\r
-\r
- /**\r
- * Enables a periperhal interrupt.\r
- */\r
- async command void enable();\r
-\r
- /**\r
- * Disables a peripheral interrupt.\r
- */\r
- async command void disable();\r
-\r
- /**\r
- * The peripheral interrupt event.\r
- */\r
- async event void fired();\r
-}\r
+// $Id$
+/* tab:4
+ * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
+ * downloading, copying, installing or using the software you agree to
+ * this license. If you do not agree to this license, do not download,
+ * install, copy or use the software.
+ *
+ * Intel Open Source License
+ *
+ * Copyright (c) 2002 Intel Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ */
+/**
+ * This interface supports the core peripheral interrupts of the PXA27X
+ * processor.
+ * It is usually parameterized based on the Peripheral ID (PPID) of the
+ * interrupt signal.
+ * ARM interrupt levels (IRQ/FIQ) are established by wiring.
+ * Priorities are established by a static table (TOSH_IRP_TABLE)
+ *
+ * Components implementing this interface are expected to provide reentrant
+ * (i.e. atomic) semantics.
+ *
+ * @author: Philip Buonadonna
+ */
+
+interface HplPXA27xInterrupt
+{
+ /**
+ * Allocates a given peripheral interrupt with the PXA27X interrupt manager.
+ * Specifically, it establishes the interrupt level (IRQ or FIQ) and the
+ * priority.
+ */
+ async command error_t allocate();
+
+ /**
+ * Enables a periperhal interrupt.
+ */
+ async command void enable();
+
+ /**
+ * Disables a peripheral interrupt.
+ */
+ async command void disable();
+
+ /**
+ * The peripheral interrupt event.
+ */
+ async event void fired();
+}
-// $Id$\r
-/*\r
- * Copyright (c) 2005 Arch Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arch Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * This interface provides access to the ICCR functionality of\r
- * the PXA27x interrupt controller. \r
- * \r
- * Refer to the PXA27x Developers Guide for more information.\r
- *\r
- * @author: Philip Buonadonna\r
- */\r
-\r
-interface HplPXA27xInterruptCntl\r
-{\r
- /**\r
- * Sets the ICCR DIM bit of the PXA27x interrupt controller\r
- * \r
- * @param flag TRUE to set the DIM bit, FALSE to clear\r
- *\r
- */\r
- async command void setICCR_DIM(bool flag);\r
-\r
- /**\r
- * Gets the value of the ICCR DIM bit.\r
- * \r
- * @return value TRUE if set, FALSE if clear.\r
- */\r
- async command bool getICCR_DIM();\r
-\r
-}\r
-\r
+// $Id$
+/*
+ * Copyright (c) 2005 Arch Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arch Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * This interface provides access to the ICCR functionality of
+ * the PXA27x interrupt controller.
+ *
+ * Refer to the PXA27x Developers Guide for more information.
+ *
+ * @author: Philip Buonadonna
+ */
+
+interface HplPXA27xInterruptCntl
+{
+ /**
+ * Sets the ICCR DIM bit of the PXA27x interrupt controller
+ *
+ * @param flag TRUE to set the DIM bit, FALSE to clear
+ *
+ */
+ async command void setICCR_DIM(bool flag);
+
+ /**
+ * Gets the value of the ICCR DIM bit.
+ *
+ * @return value TRUE if set, FALSE if clear.
+ */
+ async command bool getICCR_DIM();
+
+}
+
-// $Id$ \r
-\r
-/* tab:4\r
- * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By\r
- * downloading, copying, installing or using the software you agree to\r
- * this license. If you do not agree to this license, do not download,\r
- * install, copy or use the software.\r
- *\r
- * Intel Open Source License \r
- *\r
- * Copyright (c) 2002 Intel Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * \r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * Neither the name of the Intel Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- * \r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * \r
- * \r
- */\r
-/*\r
- *\r
- * Authors: Phil Buonadonna\r
- *\r
- * Edits: Josh Herbach\r
- * Revised: 09/02/2005\r
- */\r
-\r
-module HplPXA27xInterruptM\r
-{\r
- provides {\r
- interface HplPXA27xInterrupt as PXA27xIrq[uint8_t id];\r
- interface HplPXA27xInterruptCntl;\r
- }\r
-}\r
-\r
-implementation \r
-{\r
-\r
- uint32_t getICHP() {\r
- uint32_t val;\r
-\r
- asm volatile ("mrc p6,0,%0,c5,c0,0\n\t":"=r" (val));\r
- return val;\r
- }\r
-\r
- /* Core PXA27X interrupt dispatch vectors */\r
- /* DO NOT change the name of these functions */\r
- void hplarmv_irq() __attribute__ ((interrupt ("IRQ"))) @C() @atomic_hwevent() {\r
-\r
- uint32_t IRQPending;\r
-\r
- IRQPending = getICHP(); // Determine which interrupt to service\r
- IRQPending >>= 16; // Right justify to the IRQ portion\r
-\r
- while (IRQPending & (1 << 15)) {\r
- uint8_t PeripheralID = (IRQPending & 0x3f); // Get rid of the Valid bit\r
- signal PXA27xIrq.fired[PeripheralID](); // Handler is responsible for clearing interrupt\r
- IRQPending = getICHP(); // Determine which interrupt to service\r
- IRQPending >>= 16; // Right justify to the IRQ portion\r
- }\r
-\r
- return;\r
- }\r
-\r
- void hplarmv_fiq() __attribute__ ((interrupt ("FIQ"))) @C() @atomic_hwevent() {\r
-\r
- } \r
-\r
- static uint8_t usedPriorities = 0;\r
-\r
- /* Helper functions */\r
- /* NOTE: Read-back of all register writes is necessary to ensure the data latches */\r
-\r
- error_t allocate(uint8_t id, bool level, uint8_t priority)\r
- {\r
- uint32_t tmp;\r
- error_t error = FAIL;\r
-\r
- atomic{\r
- uint8_t i;\r
- if(usedPriorities == 0){//assumed that the table will have some entries\r
- uint8_t PriorityTable[40], DuplicateTable[40];\r
- for(i = 0; i < 40; i++){\r
- DuplicateTable[i] = PriorityTable[i] = 0xFF;\r
- }\r
- \r
- for(i = 0; i < 40; i++)\r
- if(TOSH_IRP_TABLE[i] != 0xff){\r
- if(PriorityTable[TOSH_IRP_TABLE[i]] != 0xFF)/*duplicate priorities\r
- in the table, mark \r
- for later fixing*/\r
- DuplicateTable[i] = PriorityTable[TOSH_IRP_TABLE[i]];\r
- else\r
- PriorityTable[TOSH_IRP_TABLE[i]] = i;\r
- }\r
- \r
- //compress table\r
- for(i = 0; i < 40; i++){\r
- if(PriorityTable[i] != 0xff){\r
- PriorityTable[usedPriorities] = PriorityTable[i];\r
- if(i != usedPriorities)\r
- PriorityTable[i] = 0xFF;\r
- usedPriorities++;\r
- }\r
- }\r
-\r
- for(i = 0; i < 40; i++)\r
- if(DuplicateTable[i] != 0xFF){\r
- uint8_t j, ExtraTable[40];\r
- for(j = 0; DuplicateTable[i] != PriorityTable[j]; j++);\r
- memcpy(ExtraTable + j + 1, PriorityTable + j, usedPriorities - j);\r
- memcpy(PriorityTable + j + 1, ExtraTable + j + 1, \r
- usedPriorities - j);\r
- PriorityTable[j] = i;\r
- usedPriorities++;\r
- }\r
-\r
- for(i = 0; i < usedPriorities; i++){\r
- IPR(i) = (IPR_VALID | PriorityTable[i]);\r
- tmp = IPR(i);\r
- }\r
- }\r
-\r
- if (id < 34){\r
- if(priority == 0xff){\r
- priority = usedPriorities;\r
- usedPriorities++;\r
- IPR(priority) = (IPR_VALID | (id));\r
- tmp = IPR(priority);\r
- }\r
- if (level) {\r
- _ICLR(id) |= _PPID_Bit(id);\r
- tmp = _ICLR(id);\r
- } \r
- \r
- error = SUCCESS;\r
- }\r
- }\r
- return error;\r
- }\r
- \r
- void enable(uint8_t id)\r
- {\r
- uint32_t tmp;\r
- atomic {\r
- if (id < 34) {\r
- _ICMR(id) |= _PPID_Bit(id);\r
- tmp = _ICMR(id);\r
- }\r
- }\r
- return;\r
- }\r
-\r
- void disable(uint8_t id)\r
- {\r
- uint32_t tmp;\r
- atomic {\r
- if (id < 34) {\r
- _ICMR(id) &= ~(_PPID_Bit(id));\r
- tmp = _ICMR(id);\r
- }\r
- }\r
- return;\r
- }\r
-\r
- /* Interface implementation */\r
-\r
- async command error_t PXA27xIrq.allocate[uint8_t id]()\r
- {\r
- return allocate(id, FALSE, TOSH_IRP_TABLE[id]);\r
- }\r
-\r
- async command void PXA27xIrq.enable[uint8_t id]()\r
- {\r
- enable(id);\r
- return;\r
- }\r
-\r
- async command void PXA27xIrq.disable[uint8_t id]()\r
- {\r
- disable(id);\r
- return;\r
- }\r
-\r
- async command void HplPXA27xInterruptCntl.setICCR_DIM(bool flag) {\r
-\r
- if (flag) {\r
- ICCR |= ICCR_DIM;\r
- }\r
- else {\r
- ICCR = 0;\r
- }\r
- return;\r
-\r
- }\r
-\r
- async command bool HplPXA27xInterruptCntl.getICCR_DIM() {\r
- bool result = FALSE;\r
-\r
- if (ICCR & ICCR_DIM) {\r
- result = TRUE;\r
- }\r
-\r
- return result;\r
- }\r
-\r
- default async event void PXA27xIrq.fired[uint8_t id]() \r
- {\r
- return;\r
- }\r
-\r
-}\r
+// $Id$
+
+/* tab:4
+ * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
+ * downloading, copying, installing or using the software you agree to
+ * this license. If you do not agree to this license, do not download,
+ * install, copy or use the software.
+ *
+ * Intel Open Source License
+ *
+ * Copyright (c) 2002 Intel Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ */
+/*
+ *
+ * Authors: Phil Buonadonna
+ *
+ * Edits: Josh Herbach
+ * Revised: 09/02/2005
+ */
+
+module HplPXA27xInterruptM
+{
+ provides {
+ interface HplPXA27xInterrupt as PXA27xIrq[uint8_t id];
+ interface HplPXA27xInterruptCntl;
+ }
+}
+
+implementation
+{
+
+ uint32_t getICHP() {
+ uint32_t val;
+
+ asm volatile ("mrc p6,0,%0,c5,c0,0\n\t":"=r" (val));
+ return val;
+ }
+
+ /* Core PXA27X interrupt dispatch vectors */
+ /* DO NOT change the name of these functions */
+ void hplarmv_irq() __attribute__ ((interrupt ("IRQ"))) @C() @atomic_hwevent() {
+
+ uint32_t IRQPending;
+
+ IRQPending = getICHP(); // Determine which interrupt to service
+ IRQPending >>= 16; // Right justify to the IRQ portion
+
+ while (IRQPending & (1 << 15)) {
+ uint8_t PeripheralID = (IRQPending & 0x3f); // Get rid of the Valid bit
+ signal PXA27xIrq.fired[PeripheralID](); // Handler is responsible for clearing interrupt
+ IRQPending = getICHP(); // Determine which interrupt to service
+ IRQPending >>= 16; // Right justify to the IRQ portion
+ }
+
+ return;
+ }
+
+ void hplarmv_fiq() __attribute__ ((interrupt ("FIQ"))) @C() @atomic_hwevent() {
+
+ }
+
+ static uint8_t usedPriorities = 0;
+
+ /* Helper functions */
+ /* NOTE: Read-back of all register writes is necessary to ensure the data latches */
+
+ error_t allocate(uint8_t id, bool level, uint8_t priority)
+ {
+ uint32_t tmp;
+ error_t error = FAIL;
+
+ atomic{
+ uint8_t i;
+ if(usedPriorities == 0){//assumed that the table will have some entries
+ uint8_t PriorityTable[40], DuplicateTable[40];
+ for(i = 0; i < 40; i++){
+ DuplicateTable[i] = PriorityTable[i] = 0xFF;
+ }
+
+ for(i = 0; i < 40; i++)
+ if(TOSH_IRP_TABLE[i] != 0xff){
+ if(PriorityTable[TOSH_IRP_TABLE[i]] != 0xFF)/*duplicate priorities
+ in the table, mark
+ for later fixing*/
+ DuplicateTable[i] = PriorityTable[TOSH_IRP_TABLE[i]];
+ else
+ PriorityTable[TOSH_IRP_TABLE[i]] = i;
+ }
+
+ //compress table
+ for(i = 0; i < 40; i++){
+ if(PriorityTable[i] != 0xff){
+ PriorityTable[usedPriorities] = PriorityTable[i];
+ if(i != usedPriorities)
+ PriorityTable[i] = 0xFF;
+ usedPriorities++;
+ }
+ }
+
+ for(i = 0; i < 40; i++)
+ if(DuplicateTable[i] != 0xFF){
+ uint8_t j, ExtraTable[40];
+ for(j = 0; DuplicateTable[i] != PriorityTable[j]; j++);
+ memcpy(ExtraTable + j + 1, PriorityTable + j, usedPriorities - j);
+ memcpy(PriorityTable + j + 1, ExtraTable + j + 1,
+ usedPriorities - j);
+ PriorityTable[j] = i;
+ usedPriorities++;
+ }
+
+ for(i = 0; i < usedPriorities; i++){
+ IPR(i) = (IPR_VALID | PriorityTable[i]);
+ tmp = IPR(i);
+ }
+ }
+
+ if (id < 34){
+ if(priority == 0xff){
+ priority = usedPriorities;
+ usedPriorities++;
+ IPR(priority) = (IPR_VALID | (id));
+ tmp = IPR(priority);
+ }
+ if (level) {
+ _ICLR(id) |= _PPID_Bit(id);
+ tmp = _ICLR(id);
+ }
+
+ error = SUCCESS;
+ }
+ }
+ return error;
+ }
+
+ void enable(uint8_t id)
+ {
+ uint32_t tmp;
+ atomic {
+ if (id < 34) {
+ _ICMR(id) |= _PPID_Bit(id);
+ tmp = _ICMR(id);
+ }
+ }
+ return;
+ }
+
+ void disable(uint8_t id)
+ {
+ uint32_t tmp;
+ atomic {
+ if (id < 34) {
+ _ICMR(id) &= ~(_PPID_Bit(id));
+ tmp = _ICMR(id);
+ }
+ }
+ return;
+ }
+
+ /* Interface implementation */
+
+ async command error_t PXA27xIrq.allocate[uint8_t id]()
+ {
+ return allocate(id, FALSE, TOSH_IRP_TABLE[id]);
+ }
+
+ async command void PXA27xIrq.enable[uint8_t id]()
+ {
+ enable(id);
+ return;
+ }
+
+ async command void PXA27xIrq.disable[uint8_t id]()
+ {
+ disable(id);
+ return;
+ }
+
+ async command void HplPXA27xInterruptCntl.setICCR_DIM(bool flag) {
+
+ if (flag) {
+ ICCR |= ICCR_DIM;
+ }
+ else {
+ ICCR = 0;
+ }
+ return;
+
+ }
+
+ async command bool HplPXA27xInterruptCntl.getICCR_DIM() {
+ bool result = FALSE;
+
+ if (ICCR & ICCR_DIM) {
+ result = TRUE;
+ }
+
+ return result;
+ }
+
+ default async event void PXA27xIrq.fired[uint8_t id]()
+ {
+ return;
+ }
+
+}
-/* tab:4\r
- * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By\r
- * downloading, copying, installing or using the software you agree to\r
- * this license. If you do not agree to this license, do not download,\r
- * install, copy or use the software.\r
- *\r
- * Intel Open Source License \r
- *\r
- * Copyright (c) 2002 Intel Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * \r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * Neither the name of the Intel Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- * \r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * \r
- * \r
- */\r
-/*\r
- *\r
- * Authors: Philip Buonadonna\r
- *\r
- *\r
- */\r
-\r
-#ifndef _ARM_DEFS_H\r
-#define _ARM_DEFS_H\r
-\r
-#define ARM_CPSR_MODE_MASK (0x0000001F)\r
-#define ARM_CPSR_INT_MASK (0x000000C0)\r
-#define ARM_CPSR_COND_MASK (0xF8000000)\r
-\r
-#define ARM_CPSR_MODE_USR (0x10)\r
-#define ARM_CPSR_MODE_FIQ (0x11)\r
-#define ARM_CPSR_MODE_IRQ (0x12)\r
-#define ARM_CPSR_MODE_SVC (0x13)\r
-#define ARM_CPSR_MODE_ABT (0x17)\r
-#define ARM_CPSR_MODE_UND (0x1B)\r
-#define ARM_CPSR_MODE_SYS (0x1F)\r
-\r
-#define ARM_CPSR_BIT_N (1 << 31)\r
-#define ARM_CPSR_BIT_Z (1 << 30)\r
-#define ARM_CPSR_BIT_C (1 << 29)\r
-#define ARM_CPSR_BIT_V (1 << 28)\r
-#define ARM_CPSR_BIT_Q (1 << 27)\r
-\r
-#define ARM_CPSR_BIT_I (1 << 7)\r
-#define ARM_CPSR_BIT_F (1 << 6)\r
-#define ARM_CPRS_BIT_T (1 << 5)\r
-\r
-#endif /*_ARM_DEFS_H */\r
+/* tab:4
+ * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
+ * downloading, copying, installing or using the software you agree to
+ * this license. If you do not agree to this license, do not download,
+ * install, copy or use the software.
+ *
+ * Intel Open Source License
+ *
+ * Copyright (c) 2002 Intel Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ */
+/*
+ *
+ * Authors: Philip Buonadonna
+ *
+ *
+ */
+
+#ifndef _ARM_DEFS_H
+#define _ARM_DEFS_H
+
+#define ARM_CPSR_MODE_MASK (0x0000001F)
+#define ARM_CPSR_INT_MASK (0x000000C0)
+#define ARM_CPSR_COND_MASK (0xF8000000)
+
+#define ARM_CPSR_MODE_USR (0x10)
+#define ARM_CPSR_MODE_FIQ (0x11)
+#define ARM_CPSR_MODE_IRQ (0x12)
+#define ARM_CPSR_MODE_SVC (0x13)
+#define ARM_CPSR_MODE_ABT (0x17)
+#define ARM_CPSR_MODE_UND (0x1B)
+#define ARM_CPSR_MODE_SYS (0x1F)
+
+#define ARM_CPSR_BIT_N (1 << 31)
+#define ARM_CPSR_BIT_Z (1 << 30)
+#define ARM_CPSR_BIT_C (1 << 29)
+#define ARM_CPSR_BIT_V (1 << 28)
+#define ARM_CPSR_BIT_Q (1 << 27)
+
+#define ARM_CPSR_BIT_I (1 << 7)
+#define ARM_CPSR_BIT_F (1 << 6)
+#define ARM_CPRS_BIT_T (1 << 5)
+
+#endif /*_ARM_DEFS_H */
-/*\r
- * Copyright (c) 2005 Yale University.\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions\r
- * are met:\r
- * 1. Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials provided\r
- * with the distribution.\r
- * 3. All advertising materials mentioning features or use of this\r
- * software must display the following acknowledgement:\r
- * This product includes software developed by the Embedded Networks\r
- * and Applications Lab (ENALAB) at Yale University.\r
- * 4. Neither the name of the University nor that of the Laboratory\r
- * may be used to endorse or promote products derived from this\r
- * software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY YALE UNIVERSITY AND CONTRIBUTORS ``AS IS''\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\r
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS\r
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF\r
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\r
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
- * SUCH DAMAGE.\r
- *\r
- */ \r
- /**\r
- * @brief dma array operations\r
- * @author Andrew Barton-Sweeney (abs@cs.yale.edu)\r
- * @author Thiago Teixeira\r
- */\r
- /** \r
- * Modified and ported to tinyos-2.x.\r
- * \r
- * @author Brano Kusy (branislav.kusy@gmail.com)\r
- * @version October 25, 2007\r
- */\r
-#include "DMA.h"\r
-\r
-interface dmaArray{\r
- async command uint32_t array_getBaseIndex(DescArray *DAPtr);\r
- async command DMADescriptor_t* array_get(DescArray *DAPtr, uint8_t descIndex);\r
- command void init(DescArray *DAPtr, uint32_t num_bytes, uint32_t sourceAddr, void *buf);\r
- command void setSourceAddr(DMADescriptor_t* descPtr, uint32_t val);\r
- command void setTargetAddr(DMADescriptor_t* descPtr, uint32_t val);\r
- command void enableSourceAddrIncrement(DMADescriptor_t* descPtr, bool enable);\r
- command void enableTargetAddrIncrement(DMADescriptor_t* descPtr, bool enable);\r
- command void enableSourceFlowControl(DMADescriptor_t* descPtr, bool enable);\r
- command void enableTargetFlowControl(DMADescriptor_t* descPtr, bool enable);\r
- command void setMaxBurstSize(DMADescriptor_t* descPtr, DMAMaxBurstSize_t size);\r
- command void setTransferLength(DMADescriptor_t* descPtr, uint16_t length);\r
- command void setTransferWidth(DMADescriptor_t* descPtr, DMATransferWidth_t width);\r
-}\r
+/*
+ * Copyright (c) 2005 Yale University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * 3. All advertising materials mentioning features or use of this
+ * software must display the following acknowledgement:
+ * This product includes software developed by the Embedded Networks
+ * and Applications Lab (ENALAB) at Yale University.
+ * 4. Neither the name of the University nor that of the Laboratory
+ * may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY YALE UNIVERSITY AND CONTRIBUTORS ``AS IS''
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+ /**
+ * @brief dma array operations
+ * @author Andrew Barton-Sweeney (abs@cs.yale.edu)
+ * @author Thiago Teixeira
+ */
+ /**
+ * Modified and ported to tinyos-2.x.
+ *
+ * @author Brano Kusy (branislav.kusy@gmail.com)
+ * @version October 25, 2007
+ */
+#include "DMA.h"
+
+interface dmaArray{
+ async command uint32_t array_getBaseIndex(DescArray *DAPtr);
+ async command DMADescriptor_t* array_get(DescArray *DAPtr, uint8_t descIndex);
+ command void init(DescArray *DAPtr, uint32_t num_bytes, uint32_t sourceAddr, void *buf);
+ command void setSourceAddr(DMADescriptor_t* descPtr, uint32_t val);
+ command void setTargetAddr(DMADescriptor_t* descPtr, uint32_t val);
+ command void enableSourceAddrIncrement(DMADescriptor_t* descPtr, bool enable);
+ command void enableTargetAddrIncrement(DMADescriptor_t* descPtr, bool enable);
+ command void enableSourceFlowControl(DMADescriptor_t* descPtr, bool enable);
+ command void enableTargetFlowControl(DMADescriptor_t* descPtr, bool enable);
+ command void setMaxBurstSize(DMADescriptor_t* descPtr, DMAMaxBurstSize_t size);
+ command void setTransferLength(DMADescriptor_t* descPtr, uint16_t length);
+ command void setTransferWidth(DMADescriptor_t* descPtr, DMATransferWidth_t width);
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * \r
- * @author Phil Buonadonna\r
- */\r
-configuration HplPXA27xDMAC\r
-{\r
- provides {\r
- interface HplPXA27xDMACntl;\r
- interface HplPXA27xDMAChnl[uint8_t chnl];\r
- }\r
-}\r
-implementation\r
-{\r
- components HplPXA27xDMAM;\r
- components HplPXA27xInterruptM;\r
- components PlatformP;\r
- \r
- HplPXA27xDMACntl = HplPXA27xDMAM;\r
-\r
- HplPXA27xDMAChnl[0] = HplPXA27xDMAM.HplPXA27xDMAChnl[0];\r
- HplPXA27xDMAChnl[1] = HplPXA27xDMAM.HplPXA27xDMAChnl[1];\r
- HplPXA27xDMAChnl[2] = HplPXA27xDMAM.HplPXA27xDMAChnl[2];\r
- HplPXA27xDMAChnl[3] = HplPXA27xDMAM.HplPXA27xDMAChnl[3];\r
- HplPXA27xDMAChnl[4] = HplPXA27xDMAM.HplPXA27xDMAChnl[4];\r
- HplPXA27xDMAChnl[5] = HplPXA27xDMAM.HplPXA27xDMAChnl[5];\r
- HplPXA27xDMAChnl[6] = HplPXA27xDMAM.HplPXA27xDMAChnl[6];\r
- HplPXA27xDMAChnl[7] = HplPXA27xDMAM.HplPXA27xDMAChnl[7];\r
- HplPXA27xDMAChnl[8] = HplPXA27xDMAM.HplPXA27xDMAChnl[8];\r
- HplPXA27xDMAChnl[9] = HplPXA27xDMAM.HplPXA27xDMAChnl[9];\r
- HplPXA27xDMAChnl[10] = HplPXA27xDMAM.HplPXA27xDMAChnl[10];\r
- HplPXA27xDMAChnl[11] = HplPXA27xDMAM.HplPXA27xDMAChnl[11];\r
- HplPXA27xDMAChnl[12] = HplPXA27xDMAM.HplPXA27xDMAChnl[12];\r
- HplPXA27xDMAChnl[13] = HplPXA27xDMAM.HplPXA27xDMAChnl[13];\r
- HplPXA27xDMAChnl[14] = HplPXA27xDMAM.HplPXA27xDMAChnl[14];\r
- HplPXA27xDMAChnl[15] = HplPXA27xDMAM.HplPXA27xDMAChnl[15];\r
- HplPXA27xDMAChnl[16] = HplPXA27xDMAM.HplPXA27xDMAChnl[16];\r
- HplPXA27xDMAChnl[17] = HplPXA27xDMAM.HplPXA27xDMAChnl[17];\r
- HplPXA27xDMAChnl[18] = HplPXA27xDMAM.HplPXA27xDMAChnl[18];\r
- HplPXA27xDMAChnl[19] = HplPXA27xDMAM.HplPXA27xDMAChnl[19];\r
- HplPXA27xDMAChnl[20] = HplPXA27xDMAM.HplPXA27xDMAChnl[20];\r
- HplPXA27xDMAChnl[21] = HplPXA27xDMAM.HplPXA27xDMAChnl[21];\r
- HplPXA27xDMAChnl[22] = HplPXA27xDMAM.HplPXA27xDMAChnl[22];\r
- HplPXA27xDMAChnl[23] = HplPXA27xDMAM.HplPXA27xDMAChnl[23];\r
- HplPXA27xDMAChnl[24] = HplPXA27xDMAM.HplPXA27xDMAChnl[24];\r
- HplPXA27xDMAChnl[25] = HplPXA27xDMAM.HplPXA27xDMAChnl[25];\r
- HplPXA27xDMAChnl[26] = HplPXA27xDMAM.HplPXA27xDMAChnl[26];\r
- HplPXA27xDMAChnl[27] = HplPXA27xDMAM.HplPXA27xDMAChnl[27];\r
- HplPXA27xDMAChnl[28] = HplPXA27xDMAM.HplPXA27xDMAChnl[28];\r
- HplPXA27xDMAChnl[29] = HplPXA27xDMAM.HplPXA27xDMAChnl[29];\r
- HplPXA27xDMAChnl[30] = HplPXA27xDMAM.HplPXA27xDMAChnl[30];\r
- HplPXA27xDMAChnl[31] = HplPXA27xDMAM.HplPXA27xDMAChnl[31];\r
-\r
- HplPXA27xDMAM.Init <- PlatformP.InitL1;\r
-\r
- HplPXA27xDMAM.DMAIrq -> HplPXA27xInterruptM.PXA27xIrq[PPID_DMAC];\r
- \r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ *
+ * @author Phil Buonadonna
+ */
+configuration HplPXA27xDMAC
+{
+ provides {
+ interface HplPXA27xDMACntl;
+ interface HplPXA27xDMAChnl[uint8_t chnl];
+ }
+}
+implementation
+{
+ components HplPXA27xDMAM;
+ components HplPXA27xInterruptM;
+ components PlatformP;
+
+ HplPXA27xDMACntl = HplPXA27xDMAM;
+
+ HplPXA27xDMAChnl[0] = HplPXA27xDMAM.HplPXA27xDMAChnl[0];
+ HplPXA27xDMAChnl[1] = HplPXA27xDMAM.HplPXA27xDMAChnl[1];
+ HplPXA27xDMAChnl[2] = HplPXA27xDMAM.HplPXA27xDMAChnl[2];
+ HplPXA27xDMAChnl[3] = HplPXA27xDMAM.HplPXA27xDMAChnl[3];
+ HplPXA27xDMAChnl[4] = HplPXA27xDMAM.HplPXA27xDMAChnl[4];
+ HplPXA27xDMAChnl[5] = HplPXA27xDMAM.HplPXA27xDMAChnl[5];
+ HplPXA27xDMAChnl[6] = HplPXA27xDMAM.HplPXA27xDMAChnl[6];
+ HplPXA27xDMAChnl[7] = HplPXA27xDMAM.HplPXA27xDMAChnl[7];
+ HplPXA27xDMAChnl[8] = HplPXA27xDMAM.HplPXA27xDMAChnl[8];
+ HplPXA27xDMAChnl[9] = HplPXA27xDMAM.HplPXA27xDMAChnl[9];
+ HplPXA27xDMAChnl[10] = HplPXA27xDMAM.HplPXA27xDMAChnl[10];
+ HplPXA27xDMAChnl[11] = HplPXA27xDMAM.HplPXA27xDMAChnl[11];
+ HplPXA27xDMAChnl[12] = HplPXA27xDMAM.HplPXA27xDMAChnl[12];
+ HplPXA27xDMAChnl[13] = HplPXA27xDMAM.HplPXA27xDMAChnl[13];
+ HplPXA27xDMAChnl[14] = HplPXA27xDMAM.HplPXA27xDMAChnl[14];
+ HplPXA27xDMAChnl[15] = HplPXA27xDMAM.HplPXA27xDMAChnl[15];
+ HplPXA27xDMAChnl[16] = HplPXA27xDMAM.HplPXA27xDMAChnl[16];
+ HplPXA27xDMAChnl[17] = HplPXA27xDMAM.HplPXA27xDMAChnl[17];
+ HplPXA27xDMAChnl[18] = HplPXA27xDMAM.HplPXA27xDMAChnl[18];
+ HplPXA27xDMAChnl[19] = HplPXA27xDMAM.HplPXA27xDMAChnl[19];
+ HplPXA27xDMAChnl[20] = HplPXA27xDMAM.HplPXA27xDMAChnl[20];
+ HplPXA27xDMAChnl[21] = HplPXA27xDMAM.HplPXA27xDMAChnl[21];
+ HplPXA27xDMAChnl[22] = HplPXA27xDMAM.HplPXA27xDMAChnl[22];
+ HplPXA27xDMAChnl[23] = HplPXA27xDMAM.HplPXA27xDMAChnl[23];
+ HplPXA27xDMAChnl[24] = HplPXA27xDMAM.HplPXA27xDMAChnl[24];
+ HplPXA27xDMAChnl[25] = HplPXA27xDMAM.HplPXA27xDMAChnl[25];
+ HplPXA27xDMAChnl[26] = HplPXA27xDMAM.HplPXA27xDMAChnl[26];
+ HplPXA27xDMAChnl[27] = HplPXA27xDMAM.HplPXA27xDMAChnl[27];
+ HplPXA27xDMAChnl[28] = HplPXA27xDMAM.HplPXA27xDMAChnl[28];
+ HplPXA27xDMAChnl[29] = HplPXA27xDMAM.HplPXA27xDMAChnl[29];
+ HplPXA27xDMAChnl[30] = HplPXA27xDMAM.HplPXA27xDMAChnl[30];
+ HplPXA27xDMAChnl[31] = HplPXA27xDMAM.HplPXA27xDMAChnl[31];
+
+ HplPXA27xDMAM.Init <- PlatformP.InitL1;
+
+ HplPXA27xDMAM.DMAIrq -> HplPXA27xInterruptM.PXA27xIrq[PPID_DMAC];
+
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/* tab:4\r
- * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By\r
- * downloading, copying, installing or using the software you agree to\r
- * this license. If you do not agree to this license, do not download,\r
- * install, copy or use the software.\r
- *\r
- * Intel Open Source License \r
- *\r
- * Copyright (c) 2002 Intel Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * \r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * Neither the name of the Intel Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- * \r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * \r
- * \r
- */\r
-/*\r
- *\r
- * Authors: Phil Buonadonna\r
- * Authors: Robbie Adler\r
- */\r
-\r
-\r
-interface HplPXA27xDMAChnl\r
-{\r
- async command error_t setMap(uint8_t dev);\r
- async command void setDALGNbit(bool flag);\r
- async command bool getDALGNbit();\r
- async command bool getDINTbit();\r
- async command void setDCSR(uint32_t val);\r
- async command uint32_t getDCSR();\r
- async command void setDCMD(uint32_t val);\r
- async command uint32_t getDCMD();\r
- async command void setDDADR(uint32_t val);\r
- async command uint32_t getDDADR();\r
- async command void setDSADR(uint32_t val);\r
- async command uint32_t getDSADR();\r
- async command void setDTADR(uint32_t val);\r
- async command uint32_t getDTADR();\r
- async event void interruptDMA();\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/* tab:4
+ * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
+ * downloading, copying, installing or using the software you agree to
+ * this license. If you do not agree to this license, do not download,
+ * install, copy or use the software.
+ *
+ * Intel Open Source License
+ *
+ * Copyright (c) 2002 Intel Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ */
+/*
+ *
+ * Authors: Phil Buonadonna
+ * Authors: Robbie Adler
+ */
+
+
+interface HplPXA27xDMAChnl
+{
+ async command error_t setMap(uint8_t dev);
+ async command void setDALGNbit(bool flag);
+ async command bool getDALGNbit();
+ async command bool getDINTbit();
+ async command void setDCSR(uint32_t val);
+ async command uint32_t getDCSR();
+ async command void setDCMD(uint32_t val);
+ async command uint32_t getDCMD();
+ async command void setDDADR(uint32_t val);
+ async command uint32_t getDDADR();
+ async command void setDSADR(uint32_t val);
+ async command uint32_t getDSADR();
+ async command void setDTADR(uint32_t val);
+ async command uint32_t getDTADR();
+ async event void interruptDMA();
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/*\r
- *\r
- * Authors: Phil Buonadonna\r
- *\r
- */\r
-\r
-\r
-interface HplPXA27xDMACntl\r
-{\r
- async command void setDRCMR(uint8_t peripheral, uint8_t chnl);\r
- async command uint8_t getDRCMR(uint8_t peripheral);\r
- async command void setDALGN(uint32_t val);\r
- async command uint32_t getDALGN(uint32_t val);\r
- async command void setDPCSR(uint32_t val);\r
- async command uint32_t getDPSCR();\r
- async command void setDRQSR0(uint32_t val);\r
- async command uint32_t getDRQSR0();\r
- async command void setDRQSR1(uint32_t val);\r
- async command uint32_t getDRQSR1();\r
- async command void setDRQSR2(uint32_t val);\r
- async command uint32_t getDRQSR2();\r
- async command uint32_t getDINT();\r
- async command void setFLYCNFG(uint32_t val);\r
- async command uint32_t getFLYCNFG();\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/*
+ *
+ * Authors: Phil Buonadonna
+ *
+ */
+
+
+interface HplPXA27xDMACntl
+{
+ async command void setDRCMR(uint8_t peripheral, uint8_t chnl);
+ async command uint8_t getDRCMR(uint8_t peripheral);
+ async command void setDALGN(uint32_t val);
+ async command uint32_t getDALGN(uint32_t val);
+ async command void setDPCSR(uint32_t val);
+ async command uint32_t getDPSCR();
+ async command void setDRQSR0(uint32_t val);
+ async command uint32_t getDRQSR0();
+ async command void setDRQSR1(uint32_t val);
+ async command uint32_t getDRQSR1();
+ async command void setDRQSR2(uint32_t val);
+ async command uint32_t getDRQSR2();
+ async command uint32_t getDINT();
+ async command void setFLYCNFG(uint32_t val);
+ async command uint32_t getFLYCNFG();
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/*\r
- * This interface is to be PROVIDED by peripheral HPL components that\r
- * are DMA-able. It is used to provide information to higher level \r
- * components (e.g. HalX) that may implement higher level peripheral\r
- * functions using DMA. \r
- *\r
- * Instantiate the interface multiple times according to how many\r
- * I/O addresses a peripheral has that may be assigned to a DMA\r
- * src/tgt address register.\r
- *\r
- * Authors: Phil Buonadonna\r
- *\r
- */\r
-\r
-\r
-interface HplPXA27xDMAInfo\r
-{\r
- /**\r
- * Returns a single DMAable address for a peripheral. \r
- *\r
- * @return addr The 32 bit address of the peripheral register\r
- * of interest.\r
- */\r
- async command uint32_t getAddr();\r
-\r
- /**\r
- * Returns the DMA map index that is associated with the getAddr()\r
- * function. \r
- *\r
- * @return index The DMA map register index that is associated with\r
- * the getAddr function.\r
- */\r
- async command uint8_t getMapIndex();\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/*
+ * This interface is to be PROVIDED by peripheral HPL components that
+ * are DMA-able. It is used to provide information to higher level
+ * components (e.g. HalX) that may implement higher level peripheral
+ * functions using DMA.
+ *
+ * Instantiate the interface multiple times according to how many
+ * I/O addresses a peripheral has that may be assigned to a DMA
+ * src/tgt address register.
+ *
+ * Authors: Phil Buonadonna
+ *
+ */
+
+
+interface HplPXA27xDMAInfo
+{
+ /**
+ * Returns a single DMAable address for a peripheral.
+ *
+ * @return addr The 32 bit address of the peripheral register
+ * of interest.
+ */
+ async command uint32_t getAddr();
+
+ /**
+ * Returns the DMA map index that is associated with the getAddr()
+ * function.
+ *
+ * @return index The DMA map register index that is associated with
+ * the getAddr function.
+ */
+ async command uint8_t getMapIndex();
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * \r
- * @author Phil Buonadonna\r
- */\r
-module HplPXA27xDMAM\r
-{\r
- provides {\r
- interface Init;\r
- interface HplPXA27xDMACntl;\r
- interface HplPXA27xDMAChnl[uint8_t chnl];\r
- }\r
- uses {\r
- interface HplPXA27xInterrupt as DMAIrq;\r
- }\r
-}\r
-\r
-implementation\r
-{\r
- \r
- command error_t Init.init() {\r
- call DMAIrq.allocate();\r
- call DMAIrq.enable();\r
- return SUCCESS;\r
- }\r
- \r
- async command void HplPXA27xDMACntl.setDRCMR(uint8_t peripheral, uint8_t val) {\r
- DRCMR(peripheral) = val;\r
- }\r
- async command uint8_t HplPXA27xDMACntl.getDRCMR(uint8_t peripheral) { return DRCMR(peripheral);}\r
- async command void HplPXA27xDMACntl.setDALGN(uint32_t val) {DALGN = val;}\r
- async command uint32_t HplPXA27xDMACntl.getDALGN(uint32_t val) {return DALGN; }\r
- async command void HplPXA27xDMACntl.setDPCSR(uint32_t val) {DPCSR = val; }\r
- async command uint32_t HplPXA27xDMACntl.getDPSCR() {return DPCSR; }\r
- async command void HplPXA27xDMACntl.setDRQSR0(uint32_t val) {DRQSR0 = val; }\r
- async command uint32_t HplPXA27xDMACntl.getDRQSR0() {return DRQSR0; }\r
- async command void HplPXA27xDMACntl.setDRQSR1(uint32_t val) {DRQSR1 = val; }\r
- async command uint32_t HplPXA27xDMACntl.getDRQSR1() {return DRQSR1; }\r
- async command void HplPXA27xDMACntl.setDRQSR2(uint32_t val) {DRQSR2 = val; }\r
- async command uint32_t HplPXA27xDMACntl.getDRQSR2() {return DRQSR2; }\r
- async command uint32_t HplPXA27xDMACntl.getDINT() {return DINT; }\r
- async command void HplPXA27xDMACntl.setFLYCNFG(uint32_t val) {FLYCNFG = val; }\r
- async command uint32_t HplPXA27xDMACntl.getFLYCNFG() {return FLYCNFG; }\r
-\r
- \r
- async command error_t HplPXA27xDMAChnl.setMap[uint8_t chnl](uint8_t dev) {\r
- call HplPXA27xDMACntl.setDRCMR(dev,(DRCMR_MAPVLD | DRCMR_CHLNUM(chnl)));\r
- return SUCCESS;\r
- }\r
- async command void HplPXA27xDMAChnl.setDALGNbit[uint8_t chnl](bool flag) {\r
- if (flag) {\r
- DALGN |= (1 << chnl);\r
- }\r
- else {\r
- DALGN &= ~(1 << chnl);\r
- }\r
- return;\r
- }\r
- async command bool HplPXA27xDMAChnl.getDALGNbit[uint8_t chnl]() {\r
- return ((DALGN & (1 << chnl)) != 0);\r
- }\r
- async command bool HplPXA27xDMAChnl.getDINTbit[uint8_t chnl]() {\r
- return ((DINT & (1 << chnl)) != 0);\r
- }\r
- async command void HplPXA27xDMAChnl.setDCSR[uint8_t chnl](uint32_t val) {\r
- // uint32_t cycles;\r
- //_pxa27x_perf_clear();\r
- DCSR(chnl) = val;\r
- //_pxa27x_perf_get(cycles);\r
- }\r
- async command uint32_t HplPXA27xDMAChnl.getDCSR[uint8_t chnl]() {return DCSR(chnl); }\r
- async command void HplPXA27xDMAChnl.setDCMD[uint8_t chnl](uint32_t val) {DCMD(chnl) = val; }\r
- async command uint32_t HplPXA27xDMAChnl.getDCMD[uint8_t chnl]() {return DCMD(chnl); }\r
- async command void HplPXA27xDMAChnl.setDDADR[uint8_t chnl](uint32_t val) {DDADR(chnl) = val; }\r
- async command uint32_t HplPXA27xDMAChnl.getDDADR[uint8_t chnl]() {return DDADR(chnl); }\r
- async command void HplPXA27xDMAChnl.setDSADR[uint8_t chnl](uint32_t val) {DSADR(chnl) = val; }\r
- async command uint32_t HplPXA27xDMAChnl.getDSADR[uint8_t chnl]() {return DSADR(chnl); }\r
- async command void HplPXA27xDMAChnl.setDTADR[uint8_t chnl](uint32_t val) {DTADR(chnl) = val; }\r
- async command uint32_t HplPXA27xDMAChnl.getDTADR[uint8_t chnl]() {return DTADR(chnl); }\r
-\r
- async event void DMAIrq.fired() {\r
- uint32_t IntReg;\r
- uint8_t chnl;\r
- IntReg = call HplPXA27xDMACntl.getDINT();\r
-\r
- while (IntReg) {\r
- chnl = 31 - _pxa27x_clzui(IntReg);\r
- signal HplPXA27xDMAChnl.interruptDMA[chnl]();\r
- IntReg &= ~(1 << chnl);\r
- }\r
- return;\r
- }\r
-\r
- default async event void HplPXA27xDMAChnl.interruptDMA[uint8_t chnl]() {\r
- call HplPXA27xDMAChnl.setDCMD[chnl](0);\r
- call HplPXA27xDMAChnl.setDCSR[chnl](DCSR_EORINT | DCSR_ENDINTR\r
- | DCSR_STARTINTR | DCSR_BUSERRINTR);\r
- }\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ *
+ * @author Phil Buonadonna
+ */
+module HplPXA27xDMAM
+{
+ provides {
+ interface Init;
+ interface HplPXA27xDMACntl;
+ interface HplPXA27xDMAChnl[uint8_t chnl];
+ }
+ uses {
+ interface HplPXA27xInterrupt as DMAIrq;
+ }
+}
+
+implementation
+{
+
+ command error_t Init.init() {
+ call DMAIrq.allocate();
+ call DMAIrq.enable();
+ return SUCCESS;
+ }
+
+ async command void HplPXA27xDMACntl.setDRCMR(uint8_t peripheral, uint8_t val) {
+ DRCMR(peripheral) = val;
+ }
+ async command uint8_t HplPXA27xDMACntl.getDRCMR(uint8_t peripheral) { return DRCMR(peripheral);}
+ async command void HplPXA27xDMACntl.setDALGN(uint32_t val) {DALGN = val;}
+ async command uint32_t HplPXA27xDMACntl.getDALGN(uint32_t val) {return DALGN; }
+ async command void HplPXA27xDMACntl.setDPCSR(uint32_t val) {DPCSR = val; }
+ async command uint32_t HplPXA27xDMACntl.getDPSCR() {return DPCSR; }
+ async command void HplPXA27xDMACntl.setDRQSR0(uint32_t val) {DRQSR0 = val; }
+ async command uint32_t HplPXA27xDMACntl.getDRQSR0() {return DRQSR0; }
+ async command void HplPXA27xDMACntl.setDRQSR1(uint32_t val) {DRQSR1 = val; }
+ async command uint32_t HplPXA27xDMACntl.getDRQSR1() {return DRQSR1; }
+ async command void HplPXA27xDMACntl.setDRQSR2(uint32_t val) {DRQSR2 = val; }
+ async command uint32_t HplPXA27xDMACntl.getDRQSR2() {return DRQSR2; }
+ async command uint32_t HplPXA27xDMACntl.getDINT() {return DINT; }
+ async command void HplPXA27xDMACntl.setFLYCNFG(uint32_t val) {FLYCNFG = val; }
+ async command uint32_t HplPXA27xDMACntl.getFLYCNFG() {return FLYCNFG; }
+
+
+ async command error_t HplPXA27xDMAChnl.setMap[uint8_t chnl](uint8_t dev) {
+ call HplPXA27xDMACntl.setDRCMR(dev,(DRCMR_MAPVLD | DRCMR_CHLNUM(chnl)));
+ return SUCCESS;
+ }
+ async command void HplPXA27xDMAChnl.setDALGNbit[uint8_t chnl](bool flag) {
+ if (flag) {
+ DALGN |= (1 << chnl);
+ }
+ else {
+ DALGN &= ~(1 << chnl);
+ }
+ return;
+ }
+ async command bool HplPXA27xDMAChnl.getDALGNbit[uint8_t chnl]() {
+ return ((DALGN & (1 << chnl)) != 0);
+ }
+ async command bool HplPXA27xDMAChnl.getDINTbit[uint8_t chnl]() {
+ return ((DINT & (1 << chnl)) != 0);
+ }
+ async command void HplPXA27xDMAChnl.setDCSR[uint8_t chnl](uint32_t val) {
+ // uint32_t cycles;
+ //_pxa27x_perf_clear();
+ DCSR(chnl) = val;
+ //_pxa27x_perf_get(cycles);
+ }
+ async command uint32_t HplPXA27xDMAChnl.getDCSR[uint8_t chnl]() {return DCSR(chnl); }
+ async command void HplPXA27xDMAChnl.setDCMD[uint8_t chnl](uint32_t val) {DCMD(chnl) = val; }
+ async command uint32_t HplPXA27xDMAChnl.getDCMD[uint8_t chnl]() {return DCMD(chnl); }
+ async command void HplPXA27xDMAChnl.setDDADR[uint8_t chnl](uint32_t val) {DDADR(chnl) = val; }
+ async command uint32_t HplPXA27xDMAChnl.getDDADR[uint8_t chnl]() {return DDADR(chnl); }
+ async command void HplPXA27xDMAChnl.setDSADR[uint8_t chnl](uint32_t val) {DSADR(chnl) = val; }
+ async command uint32_t HplPXA27xDMAChnl.getDSADR[uint8_t chnl]() {return DSADR(chnl); }
+ async command void HplPXA27xDMAChnl.setDTADR[uint8_t chnl](uint32_t val) {DTADR(chnl) = val; }
+ async command uint32_t HplPXA27xDMAChnl.getDTADR[uint8_t chnl]() {return DTADR(chnl); }
+
+ async event void DMAIrq.fired() {
+ uint32_t IntReg;
+ uint8_t chnl;
+ IntReg = call HplPXA27xDMACntl.getDINT();
+
+ while (IntReg) {
+ chnl = 31 - _pxa27x_clzui(IntReg);
+ signal HplPXA27xDMAChnl.interruptDMA[chnl]();
+ IntReg &= ~(1 << chnl);
+ }
+ return;
+ }
+
+ default async event void HplPXA27xDMAChnl.interruptDMA[uint8_t chnl]() {
+ call HplPXA27xDMAChnl.setDCMD[chnl](0);
+ call HplPXA27xDMAChnl.setDCSR[chnl](DCSR_EORINT | DCSR_ENDINTR
+ | DCSR_STARTINTR | DCSR_BUSERRINTR);
+ }
+}
-// $Id$\r
-\r
-/* tab:4\r
- * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By\r
- * downloading, copying, installing or using the software you agree to\r
- * this license. If you do not agree to this license, do not download,\r
- * install, copy or use the software.\r
- *\r
- * Intel Open Source License \r
- *\r
- * Copyright (c) 2002 Intel Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * \r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * Neither the name of the Intel Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- * \r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * \r
- * \r
- */\r
-\r
-//@author Phil Buonadonna\r
-\r
-configuration GeneralIOC \r
-{\r
- provides {\r
- interface GeneralIO[uint8_t pin];\r
- interface HalPXA27xGpioInterrupt[uint8_t pin];\r
- interface GpioInterrupt[uint8_t pin];\r
- }\r
-}\r
-\r
-implementation \r
-{\r
- components HalPXA27xGeneralIOM;\r
- components HplPXA27xGPIOC;\r
-\r
- GeneralIO = HalPXA27xGeneralIOM;\r
- HalPXA27xGpioInterrupt = HalPXA27xGeneralIOM;\r
- GpioInterrupt = HalPXA27xGeneralIOM;\r
-\r
- HalPXA27xGeneralIOM.HplPXA27xGPIOPin -> HplPXA27xGPIOC;\r
-\r
-}\r
+// $Id$
+
+/* tab:4
+ * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
+ * downloading, copying, installing or using the software you agree to
+ * this license. If you do not agree to this license, do not download,
+ * install, copy or use the software.
+ *
+ * Intel Open Source License
+ *
+ * Copyright (c) 2002 Intel Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ */
+
+//@author Phil Buonadonna
+
+configuration GeneralIOC
+{
+ provides {
+ interface GeneralIO[uint8_t pin];
+ interface HalPXA27xGpioInterrupt[uint8_t pin];
+ interface GpioInterrupt[uint8_t pin];
+ }
+}
+
+implementation
+{
+ components HalPXA27xGeneralIOM;
+ components HplPXA27xGPIOC;
+
+ GeneralIO = HalPXA27xGeneralIOM;
+ HalPXA27xGpioInterrupt = HalPXA27xGeneralIOM;
+ GpioInterrupt = HalPXA27xGeneralIOM;
+
+ HalPXA27xGeneralIOM.HplPXA27xGPIOPin -> HplPXA27xGPIOC;
+
+}
-// $Id$\r
-\r
-/* tab:4\r
- * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By\r
- * downloading, copying, installing or using the software you agree to\r
- * this license. If you do not agree to this license, do not download,\r
- * install, copy or use the software.\r
- *\r
- * Intel Open Source License \r
- *\r
- * Copyright (c) 2002 Intel Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * \r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * Neither the name of the Intel Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- * \r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * \r
- * \r
- */\r
-\r
-//@author Phil Buonadonna\r
-module HalPXA27xGeneralIOM {\r
- provides {\r
- interface GeneralIO[uint8_t pin];\r
- interface HalPXA27xGpioInterrupt[uint8_t pin];\r
- interface GpioInterrupt[uint8_t pin];\r
- }\r
- uses {\r
- interface HplPXA27xGPIOPin[uint8_t pin];\r
- }\r
-}\r
-\r
-implementation {\r
- async command void GeneralIO.set[uint8_t pin]() {\r
- \r
- atomic call HplPXA27xGPIOPin.setGPSRbit[pin]();\r
- return;\r
- }\r
-\r
- async command void GeneralIO.clr[uint8_t pin]() {\r
- atomic call HplPXA27xGPIOPin.setGPCRbit[pin]();\r
- return;\r
- }\r
-\r
- async command void GeneralIO.toggle[uint8_t pin]() {\r
- atomic {\r
- if (call HplPXA27xGPIOPin.getGPLRbit[pin]()) {\r
- call HplPXA27xGPIOPin.setGPCRbit[pin]();\r
- }\r
- else {\r
- call HplPXA27xGPIOPin.setGPSRbit[pin]();\r
- }\r
- }\r
- return;\r
- }\r
-\r
- async command bool GeneralIO.get[uint8_t pin]() {\r
- bool result;\r
- result = call HplPXA27xGPIOPin.getGPLRbit[pin]();\r
- return result;\r
- }\r
-\r
- async command void GeneralIO.makeInput[uint8_t pin]() {\r
- atomic call HplPXA27xGPIOPin.setGPDRbit[pin](FALSE);\r
- return;\r
- }\r
- \r
- async command bool GeneralIO.isInput[uint8_t pin]() {\r
- bool result;\r
- result = !call HplPXA27xGPIOPin.getGPLRbit[pin]();\r
- return result;\r
- }\r
- \r
- async command void GeneralIO.makeOutput[uint8_t pin]() {\r
- atomic call HplPXA27xGPIOPin.setGPDRbit[pin](TRUE);\r
- return;\r
- }\r
-\r
- async command bool GeneralIO.isOutput[uint8_t pin]() {\r
- bool result;\r
- result = call HplPXA27xGPIOPin.getGPDRbit[pin]();\r
- return result;\r
- }\r
- \r
- async command error_t HalPXA27xGpioInterrupt.enableRisingEdge[uint8_t pin]() {\r
- atomic {\r
- call HplPXA27xGPIOPin.setGRERbit[pin](TRUE);\r
- call HplPXA27xGPIOPin.setGFERbit[pin](FALSE);\r
- }\r
- return SUCCESS;\r
- }\r
-\r
- async command error_t HalPXA27xGpioInterrupt.enableFallingEdge[uint8_t pin]() {\r
- atomic {\r
- call HplPXA27xGPIOPin.setGRERbit[pin](FALSE);\r
- call HplPXA27xGPIOPin.setGFERbit[pin](TRUE);\r
- }\r
- return SUCCESS;\r
- }\r
-\r
- async command error_t HalPXA27xGpioInterrupt.enableBothEdge[uint8_t pin]() {\r
- atomic {\r
- call HplPXA27xGPIOPin.setGRERbit[pin](TRUE);\r
- call HplPXA27xGPIOPin.setGFERbit[pin](TRUE);\r
- }\r
- return SUCCESS;\r
- }\r
-\r
- async command error_t HalPXA27xGpioInterrupt.disable[uint8_t pin]() {\r
- atomic {\r
- call HplPXA27xGPIOPin.setGRERbit[pin](FALSE);\r
- call HplPXA27xGPIOPin.setGFERbit[pin](FALSE);\r
- call HplPXA27xGPIOPin.clearGEDRbit[pin]();\r
- }\r
- return SUCCESS;\r
- }\r
-\r
- async command error_t GpioInterrupt.enableRisingEdge[uint8_t pin]() {\r
- return call HalPXA27xGpioInterrupt.enableRisingEdge[pin]();\r
- }\r
-\r
- async command error_t GpioInterrupt.enableFallingEdge[uint8_t pin]() {\r
- return call HalPXA27xGpioInterrupt.enableFallingEdge[pin]();\r
- }\r
-\r
- async command error_t GpioInterrupt.disable[uint8_t pin]() {\r
- return call HalPXA27xGpioInterrupt.disable[pin]();\r
- }\r
-\r
- async event void HplPXA27xGPIOPin.interruptGPIOPin[uint8_t pin]() {\r
- call HplPXA27xGPIOPin.clearGEDRbit[pin]();\r
- signal HalPXA27xGpioInterrupt.fired[pin]();\r
- signal GpioInterrupt.fired[pin]();\r
- return;\r
- }\r
- \r
-\r
- default async event void HalPXA27xGpioInterrupt.fired[uint8_t pin]() {\r
- return;\r
- }\r
-\r
- default async event void GpioInterrupt.fired[uint8_t pin]() {\r
- return;\r
- }\r
-\r
-}\r
+// $Id$
+
+/* tab:4
+ * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
+ * downloading, copying, installing or using the software you agree to
+ * this license. If you do not agree to this license, do not download,
+ * install, copy or use the software.
+ *
+ * Intel Open Source License
+ *
+ * Copyright (c) 2002 Intel Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ */
+
+//@author Phil Buonadonna
+module HalPXA27xGeneralIOM {
+ provides {
+ interface GeneralIO[uint8_t pin];
+ interface HalPXA27xGpioInterrupt[uint8_t pin];
+ interface GpioInterrupt[uint8_t pin];
+ }
+ uses {
+ interface HplPXA27xGPIOPin[uint8_t pin];
+ }
+}
+
+implementation {
+ async command void GeneralIO.set[uint8_t pin]() {
+
+ atomic call HplPXA27xGPIOPin.setGPSRbit[pin]();
+ return;
+ }
+
+ async command void GeneralIO.clr[uint8_t pin]() {
+ atomic call HplPXA27xGPIOPin.setGPCRbit[pin]();
+ return;
+ }
+
+ async command void GeneralIO.toggle[uint8_t pin]() {
+ atomic {
+ if (call HplPXA27xGPIOPin.getGPLRbit[pin]()) {
+ call HplPXA27xGPIOPin.setGPCRbit[pin]();
+ }
+ else {
+ call HplPXA27xGPIOPin.setGPSRbit[pin]();
+ }
+ }
+ return;
+ }
+
+ async command bool GeneralIO.get[uint8_t pin]() {
+ bool result;
+ result = call HplPXA27xGPIOPin.getGPLRbit[pin]();
+ return result;
+ }
+
+ async command void GeneralIO.makeInput[uint8_t pin]() {
+ atomic call HplPXA27xGPIOPin.setGPDRbit[pin](FALSE);
+ return;
+ }
+
+ async command bool GeneralIO.isInput[uint8_t pin]() {
+ bool result;
+ result = !call HplPXA27xGPIOPin.getGPLRbit[pin]();
+ return result;
+ }
+
+ async command void GeneralIO.makeOutput[uint8_t pin]() {
+ atomic call HplPXA27xGPIOPin.setGPDRbit[pin](TRUE);
+ return;
+ }
+
+ async command bool GeneralIO.isOutput[uint8_t pin]() {
+ bool result;
+ result = call HplPXA27xGPIOPin.getGPDRbit[pin]();
+ return result;
+ }
+
+ async command error_t HalPXA27xGpioInterrupt.enableRisingEdge[uint8_t pin]() {
+ atomic {
+ call HplPXA27xGPIOPin.setGRERbit[pin](TRUE);
+ call HplPXA27xGPIOPin.setGFERbit[pin](FALSE);
+ }
+ return SUCCESS;
+ }
+
+ async command error_t HalPXA27xGpioInterrupt.enableFallingEdge[uint8_t pin]() {
+ atomic {
+ call HplPXA27xGPIOPin.setGRERbit[pin](FALSE);
+ call HplPXA27xGPIOPin.setGFERbit[pin](TRUE);
+ }
+ return SUCCESS;
+ }
+
+ async command error_t HalPXA27xGpioInterrupt.enableBothEdge[uint8_t pin]() {
+ atomic {
+ call HplPXA27xGPIOPin.setGRERbit[pin](TRUE);
+ call HplPXA27xGPIOPin.setGFERbit[pin](TRUE);
+ }
+ return SUCCESS;
+ }
+
+ async command error_t HalPXA27xGpioInterrupt.disable[uint8_t pin]() {
+ atomic {
+ call HplPXA27xGPIOPin.setGRERbit[pin](FALSE);
+ call HplPXA27xGPIOPin.setGFERbit[pin](FALSE);
+ call HplPXA27xGPIOPin.clearGEDRbit[pin]();
+ }
+ return SUCCESS;
+ }
+
+ async command error_t GpioInterrupt.enableRisingEdge[uint8_t pin]() {
+ return call HalPXA27xGpioInterrupt.enableRisingEdge[pin]();
+ }
+
+ async command error_t GpioInterrupt.enableFallingEdge[uint8_t pin]() {
+ return call HalPXA27xGpioInterrupt.enableFallingEdge[pin]();
+ }
+
+ async command error_t GpioInterrupt.disable[uint8_t pin]() {
+ return call HalPXA27xGpioInterrupt.disable[pin]();
+ }
+
+ async event void HplPXA27xGPIOPin.interruptGPIOPin[uint8_t pin]() {
+ call HplPXA27xGPIOPin.clearGEDRbit[pin]();
+ signal HalPXA27xGpioInterrupt.fired[pin]();
+ signal GpioInterrupt.fired[pin]();
+ return;
+ }
+
+
+ default async event void HalPXA27xGpioInterrupt.fired[uint8_t pin]() {
+ return;
+ }
+
+ default async event void GpioInterrupt.fired[uint8_t pin]() {
+ return;
+ }
+
+}
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-\r
-/*\r
- * Variant of the GpioCapture interface that provides a capture\r
- * on 'BOTH'.\r
- *\r
- * @author Phil Buonadonna\r
- */\r
-\r
-interface HalPXA27xGpioCapture {\r
- \r
- /** \r
- * Enable an edge based timer capture event.\r
- *\r
- * @return Whether the timer capture has been enabled.\r
- */\r
- async command error_t captureRisingEdge();\r
- async command error_t captureFallingEdge();\r
- async command error_t captureBothEdge();\r
-\r
- /**\r
- * Fired when an edge interrupt occurs.\r
- *\r
- * @param val The value of the 32kHz timer.\r
- */\r
- async event void captured(uint16_t time);\r
-\r
- /**\r
- * Disable further captures.\r
- */ \r
- async command void disable();\r
-\r
-}\r
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+
+/*
+ * Variant of the GpioCapture interface that provides a capture
+ * on 'BOTH'.
+ *
+ * @author Phil Buonadonna
+ */
+
+interface HalPXA27xGpioCapture {
+
+ /**
+ * Enable an edge based timer capture event.
+ *
+ * @return Whether the timer capture has been enabled.
+ */
+ async command error_t captureRisingEdge();
+ async command error_t captureFallingEdge();
+ async command error_t captureBothEdge();
+
+ /**
+ * Fired when an edge interrupt occurs.
+ *
+ * @param val The value of the 32kHz timer.
+ */
+ async event void captured(uint16_t time);
+
+ /**
+ * Disable further captures.
+ */
+ async command void disable();
+
+}
-/*\r
- * Copyright (c) 2005 Arch Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arch Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-\r
-/* \r
- * Variant of the standard GpioInterrupt interface that provides a \r
- * 'BOTH' trigger.\r
- * \r
- * @author Phil Buonadonna\r
- * \r
- */\r
-\r
-interface HalPXA27xGpioInterrupt {\r
-\r
- /** \r
- * Enable an edge based interrupt. Calls to these functions are\r
- * not cumulative: only the transition type of the last called \r
- * function will be monitored for.\r
- *\r
- *\r
- * @return SUCCESS if the interrupt has been enabled\r
- */\r
- async command error_t enableRisingEdge();\r
- async command error_t enableFallingEdge();\r
- async command error_t enableBothEdge();\r
-\r
- /** \r
- * Diables an edge interrupt or capture interrupt\r
- * \r
- * @return SUCCESS if the interrupt has been disabled\r
- */ \r
- async command error_t disable();\r
-\r
- /**\r
- * Fired when an edge interrupt occurs.\r
- *\r
- * NOTE: Interrupts keep running until "disable()" is called\r
- */\r
- async event void fired();\r
-\r
-}\r
+/*
+ * Copyright (c) 2005 Arch Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arch Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+
+/*
+ * Variant of the standard GpioInterrupt interface that provides a
+ * 'BOTH' trigger.
+ *
+ * @author Phil Buonadonna
+ *
+ */
+
+interface HalPXA27xGpioInterrupt {
+
+ /**
+ * Enable an edge based interrupt. Calls to these functions are
+ * not cumulative: only the transition type of the last called
+ * function will be monitored for.
+ *
+ *
+ * @return SUCCESS if the interrupt has been enabled
+ */
+ async command error_t enableRisingEdge();
+ async command error_t enableFallingEdge();
+ async command error_t enableBothEdge();
+
+ /**
+ * Diables an edge interrupt or capture interrupt
+ *
+ * @return SUCCESS if the interrupt has been disabled
+ */
+ async command error_t disable();
+
+ /**
+ * Fired when an edge interrupt occurs.
+ *
+ * NOTE: Interrupts keep running until "disable()" is called
+ */
+ async event void fired();
+
+}
-// $Id$\r
-/*\r
- * Copyright (c) 2005 Arch Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arch Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-\r
-/**\r
- * Emulates GPIO capture functionality using HalPXA27xGpioInterrupt and the \r
- * standard 32khz counter. Provides a method to capture on BOTH edges of\r
- * a GPIO transition\r
- *\r
- * @author Phil Buonadonna\r
- */\r
-generic configuration HalPXA27xSoftCaptureC() \r
-{\r
- provides interface HalPXA27xGpioCapture;\r
- uses interface HalPXA27xGpioInterrupt;\r
-}\r
-\r
-implementation\r
-{\r
- components new HalPXa27xSoftCaptureP();\r
- components Counter32khzC;\r
- \r
- HalPXA27xGpioCapture = HalPXA27xSoftCaptureP;\r
- HalPXA27xGpioInterrupt = HalPXA27xSoftCaptureP;\r
-\r
- HalPXA27xSoftCaptureP.Counter32khz32 -> Counter32khzC.Counter32khz32;\r
-}\r
-\r
+// $Id$
+/*
+ * Copyright (c) 2005 Arch Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arch Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+
+/**
+ * Emulates GPIO capture functionality using HalPXA27xGpioInterrupt and the
+ * standard 32khz counter. Provides a method to capture on BOTH edges of
+ * a GPIO transition
+ *
+ * @author Phil Buonadonna
+ */
+generic configuration HalPXA27xSoftCaptureC()
+{
+ provides interface HalPXA27xGpioCapture;
+ uses interface HalPXA27xGpioInterrupt;
+}
+
+implementation
+{
+ components new HalPXa27xSoftCaptureP();
+ components Counter32khzC;
+
+ HalPXA27xGpioCapture = HalPXA27xSoftCaptureP;
+ HalPXA27xGpioInterrupt = HalPXA27xSoftCaptureP;
+
+ HalPXA27xSoftCaptureP.Counter32khz32 -> Counter32khzC.Counter32khz32;
+}
+
-// $Id$\r
-/*\r
- * Copyright (c) 2005 Arch Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arch Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * Emulates GPIO capture functionality using GpioInterrupt and the \r
- * standard 32khz counter. Provides a method to capture on BOTH edges of\r
- * a GPIO transition.\r
- *\r
- * @author Phil Buonadonna\r
- */\r
-generic module HalPXA27xSoftCaptureP ()\r
-{\r
- provides interface HalPXA27xGpioCapture;\r
- uses {\r
- interface HalPXA27xGpioInterrupt;\r
- interface Counter<T32khz,uint32_t> as Counter32khz32;\r
- }\r
-}\r
-\r
-implementation \r
-{\r
-\r
- async command error_t HalPXA27xGpioCapture.captureRisingEdge() {\r
- return (call HalPXA27xGpioInterrupt.enableRisingEdge());\r
- }\r
-\r
- async command error_t HalPXA27xGpioCapture.captureFallingEdge() {\r
- return (call HalPXA27xGpioInterrupt.enableFallingEdge());\r
- }\r
-\r
- async command error_t HalPXA27xGpioCapture.captureBothEdge() {\r
- return (call HalPXA27xGpioInterrupt.enableBothEdge());\r
- }\r
-\r
- async command void HalPXA27xGpioCapture.disable() {\r
- call HalPXA27xGpioInterrupt.disable();\r
- return;\r
- }\r
- \r
- async event void HalPXA27xGpioInterrupt.fired() {\r
- uint16_t captureTime;\r
-\r
- captureTime = (uint16_t) call Counter32khz32.get();\r
- signal HalPXA27xGpioCapture.captured(captureTime);\r
- return;\r
- }\r
-\r
- async event void Counter32khz32.overflow() {\r
- return;\r
- }\r
-\r
- default async event void HalPXA27xGpioCapture.captured(uint16_t time) {\r
- return;\r
- }\r
-}\r
+// $Id$
+/*
+ * Copyright (c) 2005 Arch Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arch Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * Emulates GPIO capture functionality using GpioInterrupt and the
+ * standard 32khz counter. Provides a method to capture on BOTH edges of
+ * a GPIO transition.
+ *
+ * @author Phil Buonadonna
+ */
+generic module HalPXA27xSoftCaptureP ()
+{
+ provides interface HalPXA27xGpioCapture;
+ uses {
+ interface HalPXA27xGpioInterrupt;
+ interface Counter<T32khz,uint32_t> as Counter32khz32;
+ }
+}
+
+implementation
+{
+
+ async command error_t HalPXA27xGpioCapture.captureRisingEdge() {
+ return (call HalPXA27xGpioInterrupt.enableRisingEdge());
+ }
+
+ async command error_t HalPXA27xGpioCapture.captureFallingEdge() {
+ return (call HalPXA27xGpioInterrupt.enableFallingEdge());
+ }
+
+ async command error_t HalPXA27xGpioCapture.captureBothEdge() {
+ return (call HalPXA27xGpioInterrupt.enableBothEdge());
+ }
+
+ async command void HalPXA27xGpioCapture.disable() {
+ call HalPXA27xGpioInterrupt.disable();
+ return;
+ }
+
+ async event void HalPXA27xGpioInterrupt.fired() {
+ uint16_t captureTime;
+
+ captureTime = (uint16_t) call Counter32khz32.get();
+ signal HalPXA27xGpioCapture.captured(captureTime);
+ return;
+ }
+
+ async event void Counter32khz32.overflow() {
+ return;
+ }
+
+ default async event void HalPXA27xGpioCapture.captured(uint16_t time) {
+ return;
+ }
+}
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-\r
-/**\r
- * This interface provides direct access to the PXA27x GPIO controller \r
- * registers. It is meant as an alternative to the 'per-pin' interface \r
- * where the pin abstraction may not be convienient. The event provided is\r
- * called at every signal of the underlying first-level interrupt component\r
- * and NOT on a per-pin basis.\r
- * \r
- * Commands in this interface are named according to the following scheme:\r
- * set<regname>(uint32_t val);\r
- * get<regname>();\r
- * where <regname> is the register as defined in the PXA27x Developers \r
- * Guide: General-Purpose IO Controller.\r
- *\r
- * This interface is NOT intended to be parameterized.\r
- *\r
- * @author Phil Buonadonna\r
- */\r
-\r
-interface HplPXA27xGPIO\r
-{\r
-\r
- async command void setGPLR0(uint32_t val);\r
- async command uint32_t getGPLR0();\r
- async command void setGPLR1(uint32_t val);\r
- async command uint32_t getGPLR1();\r
- async command void setGPLR2(uint32_t val);\r
- async command uint32_t getGPLR2();\r
- async command void setGPLR3(uint32_t val);\r
- async command uint32_t getGPLR3();\r
-\r
- async command void setGPDR0(uint32_t val);\r
- async command uint32_t getGPDR0();\r
- async command void setGPDR1(uint32_t val);\r
- async command uint32_t getGPDR1();\r
- async command void setGPDR2(uint32_t val);\r
- async command uint32_t getGPDR2();\r
- async command void setGPDR3(uint32_t val);\r
- async command uint32_t getGPDR3();\r
-\r
- async command void setGPSR0(uint32_t val);\r
- async command uint32_t getGPSR0();\r
- async command void setGPSR1(uint32_t val);\r
- async command uint32_t getGPSR1();\r
- async command void setGPSR2(uint32_t val);\r
- async command uint32_t getGPSR2();\r
- async command void setGPSR3(uint32_t val);\r
- async command uint32_t getGPSR3();\r
-\r
- async command void setGPCR0(uint32_t val);\r
- async command uint32_t getGPCR0();\r
- async command void setGPCR1(uint32_t val);\r
- async command uint32_t getGPCR1();\r
- async command void setGPCR2(uint32_t val);\r
- async command uint32_t getGPCR2();\r
- async command void setGPCR3(uint32_t val);\r
- async command uint32_t getGPCR3();\r
-\r
- async command void setGRER0(uint32_t val);\r
- async command uint32_t getGRER0();\r
- async command void setGRER1(uint32_t val);\r
- async command uint32_t getGRER1();\r
- async command void setGRER2(uint32_t val);\r
- async command uint32_t getGRER2();\r
- async command void setGRER3(uint32_t val);\r
- async command uint32_t getGRER3();\r
- \r
- async command void setGFER0(uint32_t val);\r
- async command uint32_t getGFER0();\r
- async command void setGFER1(uint32_t val);\r
- async command uint32_t getGFER1();\r
- async command void setGFER2(uint32_t val);\r
- async command uint32_t getGFER2();\r
- async command void setGFER3(uint32_t val);\r
- async command uint32_t getGFER3();\r
- \r
- async command void setGEDR0(uint32_t val);\r
- async command uint32_t getGEDR0();\r
- async command void setGEDR1(uint32_t val);\r
- async command uint32_t getGEDR1();\r
- async command void setGEDR2(uint32_t val);\r
- async command uint32_t getGEDR2();\r
- async command void setGEDR3(uint32_t val);\r
- async command uint32_t getGEDR3();\r
- \r
- async command void setGAFR0_L(uint32_t val);\r
- async command uint32_t getGAFR0_L();\r
- async command void setGAFR0_U(uint32_t val);\r
- async command uint32_t getGAFR0_U();\r
- async command void setGAFR1_L(uint32_t val);\r
- async command uint32_t getGAFR1_L();\r
- async command void setGAFR1_U(uint32_t val);\r
- async command uint32_t getGAFR1_U();\r
- async command void setGAFR2_L(uint32_t val);\r
- async command uint32_t getGAFR2_L();\r
- async command void setGAFR2_U(uint32_t val);\r
- async command uint32_t getGAFR2_U();\r
- async command void setGAFR3_L(uint32_t val);\r
- async command uint32_t getGAFR3_L();\r
- async command void setGAFR3_U(uint32_t val);\r
- async command uint32_t getGAFR3_U();\r
- \r
- async event void fired();\r
-}\r
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+
+/**
+ * This interface provides direct access to the PXA27x GPIO controller
+ * registers. It is meant as an alternative to the 'per-pin' interface
+ * where the pin abstraction may not be convienient. The event provided is
+ * called at every signal of the underlying first-level interrupt component
+ * and NOT on a per-pin basis.
+ *
+ * Commands in this interface are named according to the following scheme:
+ * set<regname>(uint32_t val);
+ * get<regname>();
+ * where <regname> is the register as defined in the PXA27x Developers
+ * Guide: General-Purpose IO Controller.
+ *
+ * This interface is NOT intended to be parameterized.
+ *
+ * @author Phil Buonadonna
+ */
+
+interface HplPXA27xGPIO
+{
+
+ async command void setGPLR0(uint32_t val);
+ async command uint32_t getGPLR0();
+ async command void setGPLR1(uint32_t val);
+ async command uint32_t getGPLR1();
+ async command void setGPLR2(uint32_t val);
+ async command uint32_t getGPLR2();
+ async command void setGPLR3(uint32_t val);
+ async command uint32_t getGPLR3();
+
+ async command void setGPDR0(uint32_t val);
+ async command uint32_t getGPDR0();
+ async command void setGPDR1(uint32_t val);
+ async command uint32_t getGPDR1();
+ async command void setGPDR2(uint32_t val);
+ async command uint32_t getGPDR2();
+ async command void setGPDR3(uint32_t val);
+ async command uint32_t getGPDR3();
+
+ async command void setGPSR0(uint32_t val);
+ async command uint32_t getGPSR0();
+ async command void setGPSR1(uint32_t val);
+ async command uint32_t getGPSR1();
+ async command void setGPSR2(uint32_t val);
+ async command uint32_t getGPSR2();
+ async command void setGPSR3(uint32_t val);
+ async command uint32_t getGPSR3();
+
+ async command void setGPCR0(uint32_t val);
+ async command uint32_t getGPCR0();
+ async command void setGPCR1(uint32_t val);
+ async command uint32_t getGPCR1();
+ async command void setGPCR2(uint32_t val);
+ async command uint32_t getGPCR2();
+ async command void setGPCR3(uint32_t val);
+ async command uint32_t getGPCR3();
+
+ async command void setGRER0(uint32_t val);
+ async command uint32_t getGRER0();
+ async command void setGRER1(uint32_t val);
+ async command uint32_t getGRER1();
+ async command void setGRER2(uint32_t val);
+ async command uint32_t getGRER2();
+ async command void setGRER3(uint32_t val);
+ async command uint32_t getGRER3();
+
+ async command void setGFER0(uint32_t val);
+ async command uint32_t getGFER0();
+ async command void setGFER1(uint32_t val);
+ async command uint32_t getGFER1();
+ async command void setGFER2(uint32_t val);
+ async command uint32_t getGFER2();
+ async command void setGFER3(uint32_t val);
+ async command uint32_t getGFER3();
+
+ async command void setGEDR0(uint32_t val);
+ async command uint32_t getGEDR0();
+ async command void setGEDR1(uint32_t val);
+ async command uint32_t getGEDR1();
+ async command void setGEDR2(uint32_t val);
+ async command uint32_t getGEDR2();
+ async command void setGEDR3(uint32_t val);
+ async command uint32_t getGEDR3();
+
+ async command void setGAFR0_L(uint32_t val);
+ async command uint32_t getGAFR0_L();
+ async command void setGAFR0_U(uint32_t val);
+ async command uint32_t getGAFR0_U();
+ async command void setGAFR1_L(uint32_t val);
+ async command uint32_t getGAFR1_L();
+ async command void setGAFR1_U(uint32_t val);
+ async command uint32_t getGAFR1_U();
+ async command void setGAFR2_L(uint32_t val);
+ async command uint32_t getGAFR2_L();
+ async command void setGAFR2_U(uint32_t val);
+ async command uint32_t getGAFR2_U();
+ async command void setGAFR3_L(uint32_t val);
+ async command uint32_t getGAFR3_L();
+ async command void setGAFR3_U(uint32_t val);
+ async command uint32_t getGAFR3_U();
+
+ async event void fired();
+}
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-\r
-configuration HplPXA27xGPIOC {\r
- provides {\r
- interface HplPXA27xGPIOPin[uint8_t pin];\r
- interface HplPXA27xGPIO;\r
- }\r
-}\r
-implementation \r
-{\r
- components HplPXA27xGPIOM;\r
- components HplPXA27xInterruptM;\r
- components PlatformP;\r
-\r
- HplPXA27xGPIOPin = HplPXA27xGPIOM;\r
- HplPXA27xGPIO = HplPXA27xGPIOM;\r
-\r
-\r
- HplPXA27xGPIOM.Init <- PlatformP.InitL1;\r
- \r
- HplPXA27xGPIOM.GPIOIrq0 -> HplPXA27xInterruptM.PXA27xIrq[PPID_GPIO_0];\r
- HplPXA27xGPIOM.GPIOIrq1 -> HplPXA27xInterruptM.PXA27xIrq[PPID_GPIO_1];\r
- HplPXA27xGPIOM.GPIOIrq -> HplPXA27xInterruptM.PXA27xIrq[PPID_GPIO_X];\r
-\r
-}\r
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+
+configuration HplPXA27xGPIOC {
+ provides {
+ interface HplPXA27xGPIOPin[uint8_t pin];
+ interface HplPXA27xGPIO;
+ }
+}
+implementation
+{
+ components HplPXA27xGPIOM;
+ components HplPXA27xInterruptM;
+ components PlatformP;
+
+ HplPXA27xGPIOPin = HplPXA27xGPIOM;
+ HplPXA27xGPIO = HplPXA27xGPIOM;
+
+
+ HplPXA27xGPIOM.Init <- PlatformP.InitL1;
+
+ HplPXA27xGPIOM.GPIOIrq0 -> HplPXA27xInterruptM.PXA27xIrq[PPID_GPIO_0];
+ HplPXA27xGPIOM.GPIOIrq1 -> HplPXA27xInterruptM.PXA27xIrq[PPID_GPIO_1];
+ HplPXA27xGPIOM.GPIOIrq -> HplPXA27xInterruptM.PXA27xIrq[PPID_GPIO_X];
+
+}
-// $Id$\r
-\r
-/* tab:4\r
- * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By\r
- * downloading, copying, installing or using the software you agree to\r
- * this license. If you do not agree to this license, do not download,\r
- * install, copy or use the software.\r
- *\r
- * Intel Open Source License \r
- *\r
- * Copyright (c) 2002 Intel Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * \r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * Neither the name of the Intel Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- * \r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * \r
- * \r
- */\r
-\r
-//@author Phil Buonadonna\r
-module HplPXA27xGPIOM {\r
-\r
- provides {\r
- interface Init;\r
- interface HplPXA27xGPIOPin[uint8_t pin];\r
- interface HplPXA27xGPIO;\r
- }\r
- uses {\r
- interface HplPXA27xInterrupt as GPIOIrq0;\r
- interface HplPXA27xInterrupt as GPIOIrq1;\r
- interface HplPXA27xInterrupt as GPIOIrq; // GPIO 2 - 120 only\r
- }\r
-}\r
-\r
-implementation {\r
-\r
- bool gfInitialized = FALSE;\r
-\r
- command error_t Init.init() \r
- {\r
- bool isInited;\r
-\r
- atomic {\r
- isInited = gfInitialized;\r
- gfInitialized = TRUE;\r
- }\r
-\r
- if (!isInited) {\r
- call GPIOIrq0.allocate();\r
- call GPIOIrq1.allocate();\r
- call GPIOIrq.allocate();\r
- call GPIOIrq0.enable();\r
- call GPIOIrq1.enable();\r
- call GPIOIrq.enable(); \r
- }\r
- return SUCCESS;\r
- }\r
-\r
- async command bool HplPXA27xGPIOPin.getGPLRbit[uint8_t pin]() \r
- {\r
- return ((GPLR(pin) & _GPIO_bit(pin)) != 0);\r
- }\r
-\r
- async command void HplPXA27xGPIOPin.setGPDRbit[uint8_t pin](bool dir) \r
- {\r
- if (dir) {\r
- GPDR(pin) |= _GPIO_bit(pin);\r
- }\r
- else {\r
- GPDR(pin) &= ~(_GPIO_bit(pin));\r
- }\r
- return;\r
- }\r
-\r
- async command bool HplPXA27xGPIOPin.getGPDRbit[uint8_t pin]() \r
- {\r
- return ((GPDR(pin) & _GPIO_bit(pin)) != 0);\r
- }\r
-\r
- async command void HplPXA27xGPIOPin.setGPSRbit[uint8_t pin]() \r
- {\r
- GPSR(pin) = _GPIO_bit(pin);\r
- return;\r
- }\r
-\r
- async command void HplPXA27xGPIOPin.setGPCRbit[uint8_t pin]() \r
- {\r
- GPCR(pin) = _GPIO_bit(pin);\r
- return;\r
- }\r
-\r
- async command void HplPXA27xGPIOPin.setGRERbit[uint8_t pin](bool flag) \r
- {\r
- if (flag) {\r
- GRER(pin) |= _GPIO_bit(pin);\r
- }\r
- else {\r
- GRER(pin) &= ~(_GPIO_bit(pin));\r
- }\r
- return;\r
- }\r
-\r
- async command bool HplPXA27xGPIOPin.getGRERbit[uint8_t pin]() \r
- {\r
- return ((GRER(pin) & _GPIO_bit(pin)) != 0);\r
- }\r
-\r
- async command void HplPXA27xGPIOPin.setGFERbit[uint8_t pin](bool flag) \r
- {\r
- if (flag) {\r
- GFER(pin) |= _GPIO_bit(pin);\r
- }\r
- else {\r
- GFER(pin) &= ~(_GPIO_bit(pin));\r
- }\r
- return;\r
- }\r
-\r
- async command bool HplPXA27xGPIOPin.getGFERbit[uint8_t pin]() \r
- {\r
- return ((GFER(pin) & _GPIO_bit(pin)) != 0);\r
- }\r
-\r
- async command bool HplPXA27xGPIOPin.getGEDRbit[uint8_t pin]() \r
- {\r
- return ((GEDR(pin) & _GPIO_bit(pin)) != 0);\r
- }\r
-\r
- async command bool HplPXA27xGPIOPin.clearGEDRbit[uint8_t pin]() \r
- {\r
- bool flag;\r
- flag = ((GEDR(pin) & _GPIO_bit(pin)) != 0);\r
- GEDR(pin) = _GPIO_bit(pin);\r
- return flag;\r
- }\r
-\r
- async command void HplPXA27xGPIOPin.setGAFRpin[uint8_t pin](uint8_t func) \r
- {\r
- func &= 0x3;\r
- _GPIO_setaltfn(pin,func);\r
- return;\r
- }\r
-\r
- async command uint8_t HplPXA27xGPIOPin.getGAFRpin[uint8_t pin]() \r
- {\r
- return (_GPIO_getaltfun(pin));\r
- }\r
-\r
- default async event void HplPXA27xGPIOPin.interruptGPIOPin[uint8_t pin]() \r
- {\r
- call HplPXA27xGPIOPin.clearGEDRbit[pin]();\r
- return;\r
- }\r
-\r
- async command void HplPXA27xGPIO.setGPLR0(uint32_t val) {GPLR0 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGPLR0() {return GPLR0;}\r
- async command void HplPXA27xGPIO.setGPLR1(uint32_t val) {GPLR1 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGPLR1() {return GPLR1;}\r
- async command void HplPXA27xGPIO.setGPLR2(uint32_t val) {GPLR2 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGPLR2() {return GPLR2;}\r
- async command void HplPXA27xGPIO.setGPLR3(uint32_t val) {GPLR3 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGPLR3() {return GPLR3;}\r
-\r
- async command void HplPXA27xGPIO.setGPDR0(uint32_t val) {GPDR0 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGPDR0() {return GPDR0;}\r
- async command void HplPXA27xGPIO.setGPDR1(uint32_t val) {GPDR1 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGPDR1() {return GPDR1;}\r
- async command void HplPXA27xGPIO.setGPDR2(uint32_t val) {GPDR2 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGPDR2() {return GPDR2;}\r
- async command void HplPXA27xGPIO.setGPDR3(uint32_t val) {GPDR3 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGPDR3() {return GPDR3;}\r
-\r
- async command void HplPXA27xGPIO.setGPSR0(uint32_t val) {GPSR0 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGPSR0() {return GPSR0;}\r
- async command void HplPXA27xGPIO.setGPSR1(uint32_t val) {GPSR1 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGPSR1() {return GPSR1;}\r
- async command void HplPXA27xGPIO.setGPSR2(uint32_t val) {GPSR2 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGPSR2() {return GPSR2;}\r
- async command void HplPXA27xGPIO.setGPSR3(uint32_t val) {GPSR3 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGPSR3() {return GPSR3;}\r
-\r
- async command void HplPXA27xGPIO.setGPCR0(uint32_t val) {GPCR0 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGPCR0() {return GPCR0;}\r
- async command void HplPXA27xGPIO.setGPCR1(uint32_t val) {GPCR1 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGPCR1() {return GPCR1;}\r
- async command void HplPXA27xGPIO.setGPCR2(uint32_t val) {GPCR2 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGPCR2() {return GPCR2;}\r
- async command void HplPXA27xGPIO.setGPCR3(uint32_t val) {GPCR3 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGPCR3() {return GPCR3;}\r
-\r
- async command void HplPXA27xGPIO.setGRER0(uint32_t val) {GRER0 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGRER0() {return GRER0;}\r
- async command void HplPXA27xGPIO.setGRER1(uint32_t val) {GRER1 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGRER1() {return GRER1;}\r
- async command void HplPXA27xGPIO.setGRER2(uint32_t val) {GRER2 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGRER2() {return GRER2;}\r
- async command void HplPXA27xGPIO.setGRER3(uint32_t val) {GRER3 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGRER3() {return GRER3;}\r
-\r
- async command void HplPXA27xGPIO.setGFER0(uint32_t val) {GFER0 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGFER0() {return GFER0;}\r
- async command void HplPXA27xGPIO.setGFER1(uint32_t val) {GFER1 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGFER1() {return GFER1;}\r
- async command void HplPXA27xGPIO.setGFER2(uint32_t val) {GFER2 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGFER2() {return GFER2;}\r
- async command void HplPXA27xGPIO.setGFER3(uint32_t val) {GFER3 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGFER3() {return GFER3;}\r
-\r
- async command void HplPXA27xGPIO.setGEDR0(uint32_t val) {GEDR0 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGEDR0() {return GEDR0;}\r
- async command void HplPXA27xGPIO.setGEDR1(uint32_t val) {GEDR1 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGEDR1() {return GEDR1;}\r
- async command void HplPXA27xGPIO.setGEDR2(uint32_t val) {GEDR2 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGEDR2() {return GEDR2;}\r
- async command void HplPXA27xGPIO.setGEDR3(uint32_t val) {GEDR3 = val;}\r
- async command uint32_t HplPXA27xGPIO.getGEDR3() {return GEDR3;}\r
- \r
- async command void HplPXA27xGPIO.setGAFR0_L(uint32_t val) {GAFR0_L = val;}\r
- async command uint32_t HplPXA27xGPIO.getGAFR0_L() {return GAFR0_L;}\r
- async command void HplPXA27xGPIO.setGAFR0_U(uint32_t val) {GAFR0_U = val;}\r
- async command uint32_t HplPXA27xGPIO.getGAFR0_U() {return GAFR0_U;}\r
-\r
- async command void HplPXA27xGPIO.setGAFR1_L(uint32_t val) {GAFR1_L = val;}\r
- async command uint32_t HplPXA27xGPIO.getGAFR1_L() {return GAFR1_L;}\r
- async command void HplPXA27xGPIO.setGAFR1_U(uint32_t val) {GAFR1_U = val;}\r
- async command uint32_t HplPXA27xGPIO.getGAFR1_U() {return GAFR1_U;}\r
-\r
- async command void HplPXA27xGPIO.setGAFR2_L(uint32_t val) {GAFR2_L = val;}\r
- async command uint32_t HplPXA27xGPIO.getGAFR2_L() {return GAFR2_L;}\r
- async command void HplPXA27xGPIO.setGAFR2_U(uint32_t val) {GAFR2_U = val;}\r
- async command uint32_t HplPXA27xGPIO.getGAFR2_U() {return GAFR2_U;}\r
-\r
- async command void HplPXA27xGPIO.setGAFR3_L(uint32_t val) {GAFR3_L = val;}\r
- async command uint32_t HplPXA27xGPIO.getGAFR3_L() {return GAFR3_L;}\r
- async command void HplPXA27xGPIO.setGAFR3_U(uint32_t val) {GAFR3_U = val;}\r
- async command uint32_t HplPXA27xGPIO.getGAFR3_U() {return GAFR3_U;}\r
- \r
- default async event void HplPXA27xGPIO.fired() {\r
- return;\r
- }\r
-\r
- async event void GPIOIrq.fired() \r
- {\r
-\r
- uint32_t DetectReg;\r
- uint8_t pin;\r
-\r
- signal HplPXA27xGPIO.fired(); \r
-\r
- // Mask off GPIO 0 and 1 (handled by direct IRQs)\r
- atomic DetectReg = (GEDR0 & ~((1<<1) | (1<<0))); \r
-\r
- while (DetectReg) {\r
- pin = 31 - _pxa27x_clzui(DetectReg);\r
- signal HplPXA27xGPIOPin.interruptGPIOPin[pin]();\r
- DetectReg &= ~(1 << pin);\r
- }\r
-\r
- atomic DetectReg = GEDR1;\r
-\r
- while (DetectReg) {\r
- pin = 31 - _pxa27x_clzui(DetectReg);\r
- signal HplPXA27xGPIOPin.interruptGPIOPin[(pin+32)]();\r
- DetectReg &= ~(1 << pin);\r
- }\r
-\r
- atomic DetectReg = GEDR2;\r
-\r
- while (DetectReg) {\r
- pin = 31 - _pxa27x_clzui(DetectReg);\r
- signal HplPXA27xGPIOPin.interruptGPIOPin[(pin+64)]();\r
- DetectReg &= ~(1 << pin);\r
- }\r
-\r
- atomic DetectReg = GEDR3;\r
-\r
- while (DetectReg) {\r
- pin = 31 - _pxa27x_clzui(DetectReg);\r
- signal HplPXA27xGPIOPin.interruptGPIOPin[(pin+96)]();\r
- DetectReg &= ~(1 << pin);\r
- }\r
-\r
- return;\r
- }\r
-\r
- async event void GPIOIrq0.fired()\r
- {\r
- signal HplPXA27xGPIOPin.interruptGPIOPin[0]();\r
- }\r
-\r
- async event void GPIOIrq1.fired() \r
- {\r
- signal HplPXA27xGPIOPin.interruptGPIOPin[1]();\r
- } \r
-\r
-}\r
+// $Id$
+
+/* tab:4
+ * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
+ * downloading, copying, installing or using the software you agree to
+ * this license. If you do not agree to this license, do not download,
+ * install, copy or use the software.
+ *
+ * Intel Open Source License
+ *
+ * Copyright (c) 2002 Intel Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ */
+
+//@author Phil Buonadonna
+module HplPXA27xGPIOM {
+
+ provides {
+ interface Init;
+ interface HplPXA27xGPIOPin[uint8_t pin];
+ interface HplPXA27xGPIO;
+ }
+ uses {
+ interface HplPXA27xInterrupt as GPIOIrq0;
+ interface HplPXA27xInterrupt as GPIOIrq1;
+ interface HplPXA27xInterrupt as GPIOIrq; // GPIO 2 - 120 only
+ }
+}
+
+implementation {
+
+ bool gfInitialized = FALSE;
+
+ command error_t Init.init()
+ {
+ bool isInited;
+
+ atomic {
+ isInited = gfInitialized;
+ gfInitialized = TRUE;
+ }
+
+ if (!isInited) {
+ call GPIOIrq0.allocate();
+ call GPIOIrq1.allocate();
+ call GPIOIrq.allocate();
+ call GPIOIrq0.enable();
+ call GPIOIrq1.enable();
+ call GPIOIrq.enable();
+ }
+ return SUCCESS;
+ }
+
+ async command bool HplPXA27xGPIOPin.getGPLRbit[uint8_t pin]()
+ {
+ return ((GPLR(pin) & _GPIO_bit(pin)) != 0);
+ }
+
+ async command void HplPXA27xGPIOPin.setGPDRbit[uint8_t pin](bool dir)
+ {
+ if (dir) {
+ GPDR(pin) |= _GPIO_bit(pin);
+ }
+ else {
+ GPDR(pin) &= ~(_GPIO_bit(pin));
+ }
+ return;
+ }
+
+ async command bool HplPXA27xGPIOPin.getGPDRbit[uint8_t pin]()
+ {
+ return ((GPDR(pin) & _GPIO_bit(pin)) != 0);
+ }
+
+ async command void HplPXA27xGPIOPin.setGPSRbit[uint8_t pin]()
+ {
+ GPSR(pin) = _GPIO_bit(pin);
+ return;
+ }
+
+ async command void HplPXA27xGPIOPin.setGPCRbit[uint8_t pin]()
+ {
+ GPCR(pin) = _GPIO_bit(pin);
+ return;
+ }
+
+ async command void HplPXA27xGPIOPin.setGRERbit[uint8_t pin](bool flag)
+ {
+ if (flag) {
+ GRER(pin) |= _GPIO_bit(pin);
+ }
+ else {
+ GRER(pin) &= ~(_GPIO_bit(pin));
+ }
+ return;
+ }
+
+ async command bool HplPXA27xGPIOPin.getGRERbit[uint8_t pin]()
+ {
+ return ((GRER(pin) & _GPIO_bit(pin)) != 0);
+ }
+
+ async command void HplPXA27xGPIOPin.setGFERbit[uint8_t pin](bool flag)
+ {
+ if (flag) {
+ GFER(pin) |= _GPIO_bit(pin);
+ }
+ else {
+ GFER(pin) &= ~(_GPIO_bit(pin));
+ }
+ return;
+ }
+
+ async command bool HplPXA27xGPIOPin.getGFERbit[uint8_t pin]()
+ {
+ return ((GFER(pin) & _GPIO_bit(pin)) != 0);
+ }
+
+ async command bool HplPXA27xGPIOPin.getGEDRbit[uint8_t pin]()
+ {
+ return ((GEDR(pin) & _GPIO_bit(pin)) != 0);
+ }
+
+ async command bool HplPXA27xGPIOPin.clearGEDRbit[uint8_t pin]()
+ {
+ bool flag;
+ flag = ((GEDR(pin) & _GPIO_bit(pin)) != 0);
+ GEDR(pin) = _GPIO_bit(pin);
+ return flag;
+ }
+
+ async command void HplPXA27xGPIOPin.setGAFRpin[uint8_t pin](uint8_t func)
+ {
+ func &= 0x3;
+ _GPIO_setaltfn(pin,func);
+ return;
+ }
+
+ async command uint8_t HplPXA27xGPIOPin.getGAFRpin[uint8_t pin]()
+ {
+ return (_GPIO_getaltfun(pin));
+ }
+
+ default async event void HplPXA27xGPIOPin.interruptGPIOPin[uint8_t pin]()
+ {
+ call HplPXA27xGPIOPin.clearGEDRbit[pin]();
+ return;
+ }
+
+ async command void HplPXA27xGPIO.setGPLR0(uint32_t val) {GPLR0 = val;}
+ async command uint32_t HplPXA27xGPIO.getGPLR0() {return GPLR0;}
+ async command void HplPXA27xGPIO.setGPLR1(uint32_t val) {GPLR1 = val;}
+ async command uint32_t HplPXA27xGPIO.getGPLR1() {return GPLR1;}
+ async command void HplPXA27xGPIO.setGPLR2(uint32_t val) {GPLR2 = val;}
+ async command uint32_t HplPXA27xGPIO.getGPLR2() {return GPLR2;}
+ async command void HplPXA27xGPIO.setGPLR3(uint32_t val) {GPLR3 = val;}
+ async command uint32_t HplPXA27xGPIO.getGPLR3() {return GPLR3;}
+
+ async command void HplPXA27xGPIO.setGPDR0(uint32_t val) {GPDR0 = val;}
+ async command uint32_t HplPXA27xGPIO.getGPDR0() {return GPDR0;}
+ async command void HplPXA27xGPIO.setGPDR1(uint32_t val) {GPDR1 = val;}
+ async command uint32_t HplPXA27xGPIO.getGPDR1() {return GPDR1;}
+ async command void HplPXA27xGPIO.setGPDR2(uint32_t val) {GPDR2 = val;}
+ async command uint32_t HplPXA27xGPIO.getGPDR2() {return GPDR2;}
+ async command void HplPXA27xGPIO.setGPDR3(uint32_t val) {GPDR3 = val;}
+ async command uint32_t HplPXA27xGPIO.getGPDR3() {return GPDR3;}
+
+ async command void HplPXA27xGPIO.setGPSR0(uint32_t val) {GPSR0 = val;}
+ async command uint32_t HplPXA27xGPIO.getGPSR0() {return GPSR0;}
+ async command void HplPXA27xGPIO.setGPSR1(uint32_t val) {GPSR1 = val;}
+ async command uint32_t HplPXA27xGPIO.getGPSR1() {return GPSR1;}
+ async command void HplPXA27xGPIO.setGPSR2(uint32_t val) {GPSR2 = val;}
+ async command uint32_t HplPXA27xGPIO.getGPSR2() {return GPSR2;}
+ async command void HplPXA27xGPIO.setGPSR3(uint32_t val) {GPSR3 = val;}
+ async command uint32_t HplPXA27xGPIO.getGPSR3() {return GPSR3;}
+
+ async command void HplPXA27xGPIO.setGPCR0(uint32_t val) {GPCR0 = val;}
+ async command uint32_t HplPXA27xGPIO.getGPCR0() {return GPCR0;}
+ async command void HplPXA27xGPIO.setGPCR1(uint32_t val) {GPCR1 = val;}
+ async command uint32_t HplPXA27xGPIO.getGPCR1() {return GPCR1;}
+ async command void HplPXA27xGPIO.setGPCR2(uint32_t val) {GPCR2 = val;}
+ async command uint32_t HplPXA27xGPIO.getGPCR2() {return GPCR2;}
+ async command void HplPXA27xGPIO.setGPCR3(uint32_t val) {GPCR3 = val;}
+ async command uint32_t HplPXA27xGPIO.getGPCR3() {return GPCR3;}
+
+ async command void HplPXA27xGPIO.setGRER0(uint32_t val) {GRER0 = val;}
+ async command uint32_t HplPXA27xGPIO.getGRER0() {return GRER0;}
+ async command void HplPXA27xGPIO.setGRER1(uint32_t val) {GRER1 = val;}
+ async command uint32_t HplPXA27xGPIO.getGRER1() {return GRER1;}
+ async command void HplPXA27xGPIO.setGRER2(uint32_t val) {GRER2 = val;}
+ async command uint32_t HplPXA27xGPIO.getGRER2() {return GRER2;}
+ async command void HplPXA27xGPIO.setGRER3(uint32_t val) {GRER3 = val;}
+ async command uint32_t HplPXA27xGPIO.getGRER3() {return GRER3;}
+
+ async command void HplPXA27xGPIO.setGFER0(uint32_t val) {GFER0 = val;}
+ async command uint32_t HplPXA27xGPIO.getGFER0() {return GFER0;}
+ async command void HplPXA27xGPIO.setGFER1(uint32_t val) {GFER1 = val;}
+ async command uint32_t HplPXA27xGPIO.getGFER1() {return GFER1;}
+ async command void HplPXA27xGPIO.setGFER2(uint32_t val) {GFER2 = val;}
+ async command uint32_t HplPXA27xGPIO.getGFER2() {return GFER2;}
+ async command void HplPXA27xGPIO.setGFER3(uint32_t val) {GFER3 = val;}
+ async command uint32_t HplPXA27xGPIO.getGFER3() {return GFER3;}
+
+ async command void HplPXA27xGPIO.setGEDR0(uint32_t val) {GEDR0 = val;}
+ async command uint32_t HplPXA27xGPIO.getGEDR0() {return GEDR0;}
+ async command void HplPXA27xGPIO.setGEDR1(uint32_t val) {GEDR1 = val;}
+ async command uint32_t HplPXA27xGPIO.getGEDR1() {return GEDR1;}
+ async command void HplPXA27xGPIO.setGEDR2(uint32_t val) {GEDR2 = val;}
+ async command uint32_t HplPXA27xGPIO.getGEDR2() {return GEDR2;}
+ async command void HplPXA27xGPIO.setGEDR3(uint32_t val) {GEDR3 = val;}
+ async command uint32_t HplPXA27xGPIO.getGEDR3() {return GEDR3;}
+
+ async command void HplPXA27xGPIO.setGAFR0_L(uint32_t val) {GAFR0_L = val;}
+ async command uint32_t HplPXA27xGPIO.getGAFR0_L() {return GAFR0_L;}
+ async command void HplPXA27xGPIO.setGAFR0_U(uint32_t val) {GAFR0_U = val;}
+ async command uint32_t HplPXA27xGPIO.getGAFR0_U() {return GAFR0_U;}
+
+ async command void HplPXA27xGPIO.setGAFR1_L(uint32_t val) {GAFR1_L = val;}
+ async command uint32_t HplPXA27xGPIO.getGAFR1_L() {return GAFR1_L;}
+ async command void HplPXA27xGPIO.setGAFR1_U(uint32_t val) {GAFR1_U = val;}
+ async command uint32_t HplPXA27xGPIO.getGAFR1_U() {return GAFR1_U;}
+
+ async command void HplPXA27xGPIO.setGAFR2_L(uint32_t val) {GAFR2_L = val;}
+ async command uint32_t HplPXA27xGPIO.getGAFR2_L() {return GAFR2_L;}
+ async command void HplPXA27xGPIO.setGAFR2_U(uint32_t val) {GAFR2_U = val;}
+ async command uint32_t HplPXA27xGPIO.getGAFR2_U() {return GAFR2_U;}
+
+ async command void HplPXA27xGPIO.setGAFR3_L(uint32_t val) {GAFR3_L = val;}
+ async command uint32_t HplPXA27xGPIO.getGAFR3_L() {return GAFR3_L;}
+ async command void HplPXA27xGPIO.setGAFR3_U(uint32_t val) {GAFR3_U = val;}
+ async command uint32_t HplPXA27xGPIO.getGAFR3_U() {return GAFR3_U;}
+
+ default async event void HplPXA27xGPIO.fired() {
+ return;
+ }
+
+ async event void GPIOIrq.fired()
+ {
+
+ uint32_t DetectReg;
+ uint8_t pin;
+
+ signal HplPXA27xGPIO.fired();
+
+ // Mask off GPIO 0 and 1 (handled by direct IRQs)
+ atomic DetectReg = (GEDR0 & ~((1<<1) | (1<<0)));
+
+ while (DetectReg) {
+ pin = 31 - _pxa27x_clzui(DetectReg);
+ signal HplPXA27xGPIOPin.interruptGPIOPin[pin]();
+ DetectReg &= ~(1 << pin);
+ }
+
+ atomic DetectReg = GEDR1;
+
+ while (DetectReg) {
+ pin = 31 - _pxa27x_clzui(DetectReg);
+ signal HplPXA27xGPIOPin.interruptGPIOPin[(pin+32)]();
+ DetectReg &= ~(1 << pin);
+ }
+
+ atomic DetectReg = GEDR2;
+
+ while (DetectReg) {
+ pin = 31 - _pxa27x_clzui(DetectReg);
+ signal HplPXA27xGPIOPin.interruptGPIOPin[(pin+64)]();
+ DetectReg &= ~(1 << pin);
+ }
+
+ atomic DetectReg = GEDR3;
+
+ while (DetectReg) {
+ pin = 31 - _pxa27x_clzui(DetectReg);
+ signal HplPXA27xGPIOPin.interruptGPIOPin[(pin+96)]();
+ DetectReg &= ~(1 << pin);
+ }
+
+ return;
+ }
+
+ async event void GPIOIrq0.fired()
+ {
+ signal HplPXA27xGPIOPin.interruptGPIOPin[0]();
+ }
+
+ async event void GPIOIrq1.fired()
+ {
+ signal HplPXA27xGPIOPin.interruptGPIOPin[1]();
+ }
+
+}
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * This interface provides a 'per-pin' abstraction for the PXA27x\r
- * GPIO system. It is parameterized by the specific GPIO Pin number\r
- * of the PXA27x. \r
- *\r
- * @author Phil Buonadonna\r
- */\r
-\r
-interface HplPXA27xGPIOPin \r
-{\r
- /** \r
- * Returns the logic state of a GPIO Pin.\r
- *\r
- * @return bool TRUE if logic '1', FALSE if logic '0'\r
- */\r
- async command bool getGPLRbit();\r
-\r
- /** \r
- * Configures the direction of a GPIO pin.\r
- *\r
- * @param dir TRUE to configure as an output, FALSE to configure as an input.\r
- */\r
- async command void setGPDRbit(bool dir);\r
-\r
- /** \r
- * Get's the current pin direction configuration.\r
- *\r
- * @return bool TRUE if configured as an output, FALSE if configured \r
- * as an input.\r
- */\r
- async command bool getGPDRbit();\r
-\r
- /** \r
- * Sets a GPIO pin configured as an output to a HIGH state.\r
- *\r
- */\r
- async command void setGPSRbit();\r
-\r
- /** \r
- * Sets a GPIO pin configured as an output to a LOW state.\r
- *\r
- */\r
- async command void setGPCRbit();\r
-\r
- /** \r
- * Enables/Disables events on the rising edge of a GPIO pin \r
- * signal. Calls to this function are independent of calls\r
- * to 'setFallingEDEnable()'\r
- *\r
- * @param flag TRUE to enable rising edge detection, FASLE to\r
- * disable.\r
- *\r
- */\r
- async command void setGRERbit(bool flag);\r
-\r
- /** \r
- * Returns the status of rising edge detection.\r
- *\r
- * @return val TRUE if rising edge detection is enable, FALSE\r
- * otherwise.\r
- */\r
- async command bool getGRERbit();\r
-\r
- /** \r
- * Enables/Disables events on the falling edge of a GPIO pin \r
- * signal. Calls to this function are independent of calls to\r
- * 'setRisingEDEnable()'\r
- *\r
- * @param flag TRUE to enable falling edge detection, FASLE to\r
- * disable.\r
- */\r
- async command void setGFERbit(bool flag);\r
-\r
- /** \r
- * Returns the status of falling edge detection.\r
- *\r
- * @return val TRUE if falling edge detection is enable, FALSE\r
- * otherwise.\r
- */\r
- async command bool getGFERbit();\r
-\r
- /** \r
- * Indicates wether an edge detection event is pending for GPIO Pin\r
- *\r
- * @return val TRUE if an event is pending.\r
- */\r
- async command bool getGEDRbit();\r
-\r
- /** \r
- * Clears the edge detection event status.\r
- *\r
- * @return val TRUE if there was a pending event prior to clearing, \r
- * FALSE otherwise.\r
- */\r
- async command bool clearGEDRbit();\r
-\r
- /** \r
- * Sets the GPIO pin to one of it's alternate peripheral functions.\r
- * Refer to the PXA27x Developers Manual for information on available\r
- * alternate functions.\r
- *\r
- * @param func An integer between 0 and 3 indicating the desired \r
- * pin alternate function. \r
- */\r
- async command void setGAFRpin(uint8_t func);\r
-\r
- /** \r
- * Returns the current alternate function selected for the GPIO pin.\r
- *\r
- * @return val An integer between 0 and 3 indicated the current\r
- * alternate function.\r
- */\r
- async command uint8_t getGAFRpin();\r
-\r
- /** \r
- * The pin edge detection event. Signalled when a rising/falling edge\r
- * occurs on the PIN and the respective edge detect enable is set.\r
- * The default event DOES NOT clear any pending requests.\r
- *\r
- */\r
- async event void interruptGPIOPin();\r
-}\r
-\r
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * This interface provides a 'per-pin' abstraction for the PXA27x
+ * GPIO system. It is parameterized by the specific GPIO Pin number
+ * of the PXA27x.
+ *
+ * @author Phil Buonadonna
+ */
+
+interface HplPXA27xGPIOPin
+{
+ /**
+ * Returns the logic state of a GPIO Pin.
+ *
+ * @return bool TRUE if logic '1', FALSE if logic '0'
+ */
+ async command bool getGPLRbit();
+
+ /**
+ * Configures the direction of a GPIO pin.
+ *
+ * @param dir TRUE to configure as an output, FALSE to configure as an input.
+ */
+ async command void setGPDRbit(bool dir);
+
+ /**
+ * Get's the current pin direction configuration.
+ *
+ * @return bool TRUE if configured as an output, FALSE if configured
+ * as an input.
+ */
+ async command bool getGPDRbit();
+
+ /**
+ * Sets a GPIO pin configured as an output to a HIGH state.
+ *
+ */
+ async command void setGPSRbit();
+
+ /**
+ * Sets a GPIO pin configured as an output to a LOW state.
+ *
+ */
+ async command void setGPCRbit();
+
+ /**
+ * Enables/Disables events on the rising edge of a GPIO pin
+ * signal. Calls to this function are independent of calls
+ * to 'setFallingEDEnable()'
+ *
+ * @param flag TRUE to enable rising edge detection, FASLE to
+ * disable.
+ *
+ */
+ async command void setGRERbit(bool flag);
+
+ /**
+ * Returns the status of rising edge detection.
+ *
+ * @return val TRUE if rising edge detection is enable, FALSE
+ * otherwise.
+ */
+ async command bool getGRERbit();
+
+ /**
+ * Enables/Disables events on the falling edge of a GPIO pin
+ * signal. Calls to this function are independent of calls to
+ * 'setRisingEDEnable()'
+ *
+ * @param flag TRUE to enable falling edge detection, FASLE to
+ * disable.
+ */
+ async command void setGFERbit(bool flag);
+
+ /**
+ * Returns the status of falling edge detection.
+ *
+ * @return val TRUE if falling edge detection is enable, FALSE
+ * otherwise.
+ */
+ async command bool getGFERbit();
+
+ /**
+ * Indicates wether an edge detection event is pending for GPIO Pin
+ *
+ * @return val TRUE if an event is pending.
+ */
+ async command bool getGEDRbit();
+
+ /**
+ * Clears the edge detection event status.
+ *
+ * @return val TRUE if there was a pending event prior to clearing,
+ * FALSE otherwise.
+ */
+ async command bool clearGEDRbit();
+
+ /**
+ * Sets the GPIO pin to one of it's alternate peripheral functions.
+ * Refer to the PXA27x Developers Manual for information on available
+ * alternate functions.
+ *
+ * @param func An integer between 0 and 3 indicating the desired
+ * pin alternate function.
+ */
+ async command void setGAFRpin(uint8_t func);
+
+ /**
+ * Returns the current alternate function selected for the GPIO pin.
+ *
+ * @return val An integer between 0 and 3 indicated the current
+ * alternate function.
+ */
+ async command uint8_t getGAFRpin();
+
+ /**
+ * The pin edge detection event. Signalled when a rising/falling edge
+ * occurs on the PIN and the respective edge detect enable is set.
+ * The default event DOES NOT clear any pending requests.
+ *
+ */
+ async event void interruptGPIOPin();
+}
+
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arch Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arch Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * This Hal module implements the TinyOS 2.0 I2CPacket interface over\r
- * the PXA27x I2C Hpl\r
- *\r
- * @author Phil Buonadonna\r
- */\r
-\r
-#include <I2C.h>\r
-\r
-generic configuration HalPXA27xI2CMasterC(bool fast_mode)\r
-{\r
- provides interface I2CPacket<TI2CBasicAddr>;\r
-\r
- uses interface HplPXA27xGPIOPin as I2CSCL;\r
- uses interface HplPXA27xGPIOPin as I2CSDA;\r
-}\r
-\r
-implementation\r
-{\r
- components new HalPXA27xI2CMasterP(fast_mode);\r
- components HplPXA27xI2CC;\r
- components PlatformP;\r
-\r
- I2CPacket = HalPXA27xI2CMasterP;\r
-\r
- HalPXA27xI2CMasterP.Init <- PlatformP.InitL2;\r
-\r
- HalPXA27xI2CMasterP.I2C -> HplPXA27xI2CC.I2C;\r
-\r
- I2CSCL = HalPXA27xI2CMasterP.I2CSCL;\r
- I2CSDA = HalPXA27xI2CMasterP.I2CSDA;\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arch Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arch Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * This Hal module implements the TinyOS 2.0 I2CPacket interface over
+ * the PXA27x I2C Hpl
+ *
+ * @author Phil Buonadonna
+ */
+
+#include <I2C.h>
+
+generic configuration HalPXA27xI2CMasterC(bool fast_mode)
+{
+ provides interface I2CPacket<TI2CBasicAddr>;
+
+ uses interface HplPXA27xGPIOPin as I2CSCL;
+ uses interface HplPXA27xGPIOPin as I2CSDA;
+}
+
+implementation
+{
+ components new HalPXA27xI2CMasterP(fast_mode);
+ components HplPXA27xI2CC;
+ components PlatformP;
+
+ I2CPacket = HalPXA27xI2CMasterP;
+
+ HalPXA27xI2CMasterP.Init <- PlatformP.InitL2;
+
+ HalPXA27xI2CMasterP.I2C -> HplPXA27xI2CC.I2C;
+
+ I2CSCL = HalPXA27xI2CMasterP.I2CSCL;
+ I2CSDA = HalPXA27xI2CMasterP.I2CSDA;
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arch Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arch Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * This Hal module implements the TinyOS 2.0 I2CPacket interface over\r
- * the PXA27x I2C Hpl\r
- *\r
- * @author Phil Buonadonna\r
- */\r
-\r
-#include <I2C.h>\r
-\r
-generic module HalPXA27xI2CMasterP(bool fast_mode)\r
-{\r
- provides interface Init;\r
- provides interface I2CPacket<TI2CBasicAddr>;\r
-\r
- uses interface HplPXA27xI2C as I2C;\r
-\r
- uses interface HplPXA27xGPIOPin as I2CSCL;\r
- uses interface HplPXA27xGPIOPin as I2CSDA;\r
-\r
-}\r
-\r
-implementation\r
-{\r
- // These states don't necessarily reflect the state of the I2C bus, rather the state of this\r
- // module WRT an operation. I.E. the module might be in STATE_IDLE, but the I2C bus still\r
- // held by the master for a continued read.\r
- enum {\r
- I2C_STATE_IDLE,\r
- I2C_STATE_READSTART,\r
- I2C_STATE_READ,\r
- I2C_STATE_READEND,\r
- I2C_STATE_WRITE,\r
- I2C_STATE_WRITEEND,\r
- I2C_STATE_ERROR\r
- };\r
-\r
- uint8_t mI2CState;\r
- uint16_t mCurTargetAddr;\r
- uint8_t *mCurBuf, mCurBufLen, mCurBufIndex;\r
- i2c_flags_t mCurFlags;\r
- uint32_t mBaseICRFlags;\r
-\r
- static void readNextByte() {\r
- if (mCurBufIndex >= (mCurBufLen - 1)) {\r
- atomic { mI2CState = I2C_STATE_READEND; }\r
- if (mCurFlags & I2C_STOP) {\r
- call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_DRFIE | ICR_ACKNAK | ICR_TB | ICR_STOP));\r
- }\r
- else if (mCurFlags & I2C_ACK_END) {\r
- call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_DRFIE | ICR_TB));\r
- }\r
- else {\r
- call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_DRFIE | ICR_ACKNAK | ICR_TB));\r
- }\r
- }\r
- else {\r
- atomic { mI2CState = I2C_STATE_READ; }\r
- call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_DRFIE | ICR_TB));\r
- }\r
- return;\r
- }\r
-\r
- static void writeNextByte() {\r
- if (mCurBufIndex >= mCurBufLen) {\r
- atomic { mI2CState = I2C_STATE_WRITEEND; }\r
- \r
- if (mCurFlags & I2C_STOP) {\r
- call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_TB | ICR_ITEIE | ICR_STOP));\r
- }\r
- \r
- else {\r
- call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_ITEIE | ICR_TB));\r
- }\r
- \r
- }\r
- else {\r
- call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_ITEIE |ICR_TB));\r
- }\r
- return;\r
- }\r
- \r
- static error_t startI2CTransact(uint8_t nextState, uint16_t addr, uint8_t length, uint8_t *data, \r
- i2c_flags_t flags, bool bRnW) {\r
- error_t error = SUCCESS;\r
- uint8_t tmpAddr;\r
-\r
- if ((data == NULL) || (length == 0)) {\r
- return EINVAL;\r
- }\r
-\r
- atomic {\r
- if (mI2CState == I2C_STATE_IDLE) {\r
- mI2CState = nextState;\r
- mCurTargetAddr = addr;\r
- mCurBuf = data;\r
- mCurBufLen = length;\r
- mCurBufIndex = 0;\r
- mCurFlags = flags;\r
- }\r
- else {\r
- error = EBUSY;\r
- }\r
- }\r
- if (error) {\r
- return error;\r
- }\r
-\r
- if (flags & I2C_START) {\r
-\r
- tmpAddr = (bRnW) ? 0x1 : 0x0;\r
- tmpAddr |= ((addr << 1) & 0xFE);\r
- call I2C.setIDBR(tmpAddr);\r
- call I2C.setICR( mBaseICRFlags | ICR_ITEIE | ICR_TB | ICR_START);\r
- }\r
- else if (bRnW) {\r
- atomic {\r
- readNextByte();\r
- }\r
- }\r
- else {\r
- atomic {\r
- writeNextByte();\r
- }\r
- }\r
- return error;\r
- }\r
-\r
-\r
- task void handleReadError() {\r
- call I2C.setISAR(0x7F0);\r
- call I2C.setICR(mBaseICRFlags | ICR_MA);\r
- call I2C.setICR(ICR_UR);\r
- call I2C.setICR(mBaseICRFlags);\r
- atomic {\r
- mI2CState = I2C_STATE_IDLE;\r
- signal I2CPacket.readDone(FAIL,mCurTargetAddr,mCurBufLen,mCurBuf);\r
- }\r
- return;\r
- }\r
- \r
- task void handleWriteError() {\r
- call I2C.setISAR(0x7F0);\r
- call I2C.setICR(mBaseICRFlags | ICR_MA);\r
- call I2C.setICR(ICR_UR);\r
- call I2C.setICR(mBaseICRFlags);\r
- atomic {\r
- mI2CState = I2C_STATE_IDLE;\r
- signal I2CPacket.writeDone(FAIL,mCurTargetAddr,mCurBufLen,mCurBuf);\r
- }\r
- return;\r
- }\r
-\r
- command error_t Init.init() {\r
- atomic {\r
- mBaseICRFlags = (fast_mode) ? (ICR_FM | ICR_BEIE | ICR_IUE | ICR_SCLE) : (ICR_BEIE | ICR_IUE | ICR_SCLE);\r
-\r
- call I2CSCL.setGAFRpin(I2C_SCL_ALTFN);\r
- call I2CSCL.setGPDRbit(TRUE);\r
- call I2CSDA.setGAFRpin(I2C_SDA_ALTFN);\r
- call I2CSDA.setGPDRbit(TRUE);\r
-\r
- mI2CState = I2C_STATE_IDLE;\r
- call I2C.setISAR(0);\r
- call I2C.setICR(mBaseICRFlags | ICR_ITEIE | ICR_DRFIE);\r
- } \r
- return SUCCESS;\r
- }\r
-\r
- async command error_t I2CPacket.read(i2c_flags_t flags, uint16_t addr, uint8_t length, uint8_t* data) {\r
- error_t error = SUCCESS;\r
-\r
- if ((flags & I2C_ACK_END) && (flags & I2C_STOP)) {\r
- error = EINVAL;\r
- return error;\r
- }\r
-\r
- if (flags & I2C_START) {\r
- error = startI2CTransact(I2C_STATE_READSTART,addr,length,data,flags,TRUE);\r
- }\r
- else {\r
- error = startI2CTransact(I2C_STATE_READ,addr,length,data,flags,TRUE);\r
- }\r
- \r
- return error;\r
- }\r
-\r
- async command error_t I2CPacket.write(i2c_flags_t flags, uint16_t addr, uint8_t length, uint8_t* data) {\r
- error_t error = SUCCESS;\r
-\r
- error = startI2CTransact(I2C_STATE_WRITE,addr,length,data,flags,FALSE);\r
-\r
- return error;\r
- }\r
-\r
- async event void I2C.interruptI2C() {\r
- uint32_t valISR;\r
-\r
- // PXA27x Devel Guide is wrong. You have to write to the ISR to clear the bits.\r
- valISR = call I2C.getISR();\r
- call I2C.setISR(ISR_ITE | ISR_IRF);\r
-\r
- // turn off DRFIE and ITEIE\r
- //call I2C.setICR((call I2C.getICR()) & ~(ICR_DRFIE | ICR_ITEIE));\r
- //call I2C.setICR(mBaseICRFlags);\r
-\r
- switch (mI2CState) {\r
- case I2C_STATE_IDLE:\r
- // Should never get here. Reset all pending interrupts.\r
- break;\r
-\r
- case I2C_STATE_READSTART:\r
- if (valISR & (ISR_BED | ISR_ALD)) {\r
- mI2CState = I2C_STATE_ERROR;\r
- post handleReadError();\r
- break;\r
- }\r
- readNextByte();\r
- break;\r
-\r
- case I2C_STATE_READ:\r
- if (valISR & (ISR_BED | ISR_ALD)) {\r
- mI2CState = I2C_STATE_ERROR;\r
- post handleReadError();\r
- break;\r
- }\r
- mCurBuf[mCurBufIndex] = call I2C.getIDBR();\r
- mCurBufIndex++;\r
- readNextByte();\r
- break;\r
-\r
- case I2C_STATE_READEND:\r
- if (valISR & (ISR_BED | ISR_ALD)) {\r
- mI2CState = I2C_STATE_ERROR;\r
- post handleReadError();\r
- break;\r
- }\r
- mCurBuf[mCurBufIndex] = call I2C.getIDBR();\r
- mI2CState = I2C_STATE_IDLE;\r
- signal I2CPacket.readDone(SUCCESS,mCurTargetAddr,mCurBufLen,mCurBuf);\r
- break;\r
-\r
- case I2C_STATE_WRITE:\r
- if (valISR & (ISR_BED | ISR_ALD)) {\r
- mI2CState = I2C_STATE_ERROR;\r
- post handleWriteError();\r
- break;\r
- }\r
- call I2C.setIDBR(mCurBuf[mCurBufIndex]);\r
- mCurBufIndex++;\r
- writeNextByte();\r
-\r
- break;\r
-\r
- case I2C_STATE_WRITEEND:\r
- if (valISR & (ISR_BED | ISR_ALD)) {\r
- mI2CState = I2C_STATE_ERROR;\r
- post handleWriteError();\r
- break;\r
- }\r
- mI2CState= I2C_STATE_IDLE;\r
- //call I2C.setICR(call I2C.getICR() & ~I2C_STOP);\r
- call I2C.setICR(mBaseICRFlags);\r
- signal I2CPacket.writeDone(SUCCESS,mCurTargetAddr,mCurBufLen,mCurBuf);\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- \r
- return;\r
- }\r
-\r
- default async event void I2CPacket.readDone(error_t error, uint16_t addr, \r
- uint8_t length, uint8_t* data) {\r
- return;\r
- }\r
-\r
- default async event void I2CPacket.writeDone(error_t error, uint16_t addr, \r
- uint8_t length, uint8_t* data) { \r
- return;\r
- }\r
-\r
- async event void I2CSDA.interruptGPIOPin() {}\r
- async event void I2CSCL.interruptGPIOPin() {}\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arch Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arch Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * This Hal module implements the TinyOS 2.0 I2CPacket interface over
+ * the PXA27x I2C Hpl
+ *
+ * @author Phil Buonadonna
+ */
+
+#include <I2C.h>
+
+generic module HalPXA27xI2CMasterP(bool fast_mode)
+{
+ provides interface Init;
+ provides interface I2CPacket<TI2CBasicAddr>;
+
+ uses interface HplPXA27xI2C as I2C;
+
+ uses interface HplPXA27xGPIOPin as I2CSCL;
+ uses interface HplPXA27xGPIOPin as I2CSDA;
+
+}
+
+implementation
+{
+ // These states don't necessarily reflect the state of the I2C bus, rather the state of this
+ // module WRT an operation. I.E. the module might be in STATE_IDLE, but the I2C bus still
+ // held by the master for a continued read.
+ enum {
+ I2C_STATE_IDLE,
+ I2C_STATE_READSTART,
+ I2C_STATE_READ,
+ I2C_STATE_READEND,
+ I2C_STATE_WRITE,
+ I2C_STATE_WRITEEND,
+ I2C_STATE_ERROR
+ };
+
+ uint8_t mI2CState;
+ uint16_t mCurTargetAddr;
+ uint8_t *mCurBuf, mCurBufLen, mCurBufIndex;
+ i2c_flags_t mCurFlags;
+ uint32_t mBaseICRFlags;
+
+ static void readNextByte() {
+ if (mCurBufIndex >= (mCurBufLen - 1)) {
+ atomic { mI2CState = I2C_STATE_READEND; }
+ if (mCurFlags & I2C_STOP) {
+ call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_DRFIE | ICR_ACKNAK | ICR_TB | ICR_STOP));
+ }
+ else if (mCurFlags & I2C_ACK_END) {
+ call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_DRFIE | ICR_TB));
+ }
+ else {
+ call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_DRFIE | ICR_ACKNAK | ICR_TB));
+ }
+ }
+ else {
+ atomic { mI2CState = I2C_STATE_READ; }
+ call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_DRFIE | ICR_TB));
+ }
+ return;
+ }
+
+ static void writeNextByte() {
+ if (mCurBufIndex >= mCurBufLen) {
+ atomic { mI2CState = I2C_STATE_WRITEEND; }
+
+ if (mCurFlags & I2C_STOP) {
+ call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_TB | ICR_ITEIE | ICR_STOP));
+ }
+
+ else {
+ call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_ITEIE | ICR_TB));
+ }
+
+ }
+ else {
+ call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_ITEIE |ICR_TB));
+ }
+ return;
+ }
+
+ static error_t startI2CTransact(uint8_t nextState, uint16_t addr, uint8_t length, uint8_t *data,
+ i2c_flags_t flags, bool bRnW) {
+ error_t error = SUCCESS;
+ uint8_t tmpAddr;
+
+ if ((data == NULL) || (length == 0)) {
+ return EINVAL;
+ }
+
+ atomic {
+ if (mI2CState == I2C_STATE_IDLE) {
+ mI2CState = nextState;
+ mCurTargetAddr = addr;
+ mCurBuf = data;
+ mCurBufLen = length;
+ mCurBufIndex = 0;
+ mCurFlags = flags;
+ }
+ else {
+ error = EBUSY;
+ }
+ }
+ if (error) {
+ return error;
+ }
+
+ if (flags & I2C_START) {
+
+ tmpAddr = (bRnW) ? 0x1 : 0x0;
+ tmpAddr |= ((addr << 1) & 0xFE);
+ call I2C.setIDBR(tmpAddr);
+ call I2C.setICR( mBaseICRFlags | ICR_ITEIE | ICR_TB | ICR_START);
+ }
+ else if (bRnW) {
+ atomic {
+ readNextByte();
+ }
+ }
+ else {
+ atomic {
+ writeNextByte();
+ }
+ }
+ return error;
+ }
+
+
+ task void handleReadError() {
+ call I2C.setISAR(0x7F0);
+ call I2C.setICR(mBaseICRFlags | ICR_MA);
+ call I2C.setICR(ICR_UR);
+ call I2C.setICR(mBaseICRFlags);
+ atomic {
+ mI2CState = I2C_STATE_IDLE;
+ signal I2CPacket.readDone(FAIL,mCurTargetAddr,mCurBufLen,mCurBuf);
+ }
+ return;
+ }
+
+ task void handleWriteError() {
+ call I2C.setISAR(0x7F0);
+ call I2C.setICR(mBaseICRFlags | ICR_MA);
+ call I2C.setICR(ICR_UR);
+ call I2C.setICR(mBaseICRFlags);
+ atomic {
+ mI2CState = I2C_STATE_IDLE;
+ signal I2CPacket.writeDone(FAIL,mCurTargetAddr,mCurBufLen,mCurBuf);
+ }
+ return;
+ }
+
+ command error_t Init.init() {
+ atomic {
+ mBaseICRFlags = (fast_mode) ? (ICR_FM | ICR_BEIE | ICR_IUE | ICR_SCLE) : (ICR_BEIE | ICR_IUE | ICR_SCLE);
+
+ call I2CSCL.setGAFRpin(I2C_SCL_ALTFN);
+ call I2CSCL.setGPDRbit(TRUE);
+ call I2CSDA.setGAFRpin(I2C_SDA_ALTFN);
+ call I2CSDA.setGPDRbit(TRUE);
+
+ mI2CState = I2C_STATE_IDLE;
+ call I2C.setISAR(0);
+ call I2C.setICR(mBaseICRFlags | ICR_ITEIE | ICR_DRFIE);
+ }
+ return SUCCESS;
+ }
+
+ async command error_t I2CPacket.read(i2c_flags_t flags, uint16_t addr, uint8_t length, uint8_t* data) {
+ error_t error = SUCCESS;
+
+ if ((flags & I2C_ACK_END) && (flags & I2C_STOP)) {
+ error = EINVAL;
+ return error;
+ }
+
+ if (flags & I2C_START) {
+ error = startI2CTransact(I2C_STATE_READSTART,addr,length,data,flags,TRUE);
+ }
+ else {
+ error = startI2CTransact(I2C_STATE_READ,addr,length,data,flags,TRUE);
+ }
+
+ return error;
+ }
+
+ async command error_t I2CPacket.write(i2c_flags_t flags, uint16_t addr, uint8_t length, uint8_t* data) {
+ error_t error = SUCCESS;
+
+ error = startI2CTransact(I2C_STATE_WRITE,addr,length,data,flags,FALSE);
+
+ return error;
+ }
+
+ async event void I2C.interruptI2C() {
+ uint32_t valISR;
+
+ // PXA27x Devel Guide is wrong. You have to write to the ISR to clear the bits.
+ valISR = call I2C.getISR();
+ call I2C.setISR(ISR_ITE | ISR_IRF);
+
+ // turn off DRFIE and ITEIE
+ //call I2C.setICR((call I2C.getICR()) & ~(ICR_DRFIE | ICR_ITEIE));
+ //call I2C.setICR(mBaseICRFlags);
+
+ switch (mI2CState) {
+ case I2C_STATE_IDLE:
+ // Should never get here. Reset all pending interrupts.
+ break;
+
+ case I2C_STATE_READSTART:
+ if (valISR & (ISR_BED | ISR_ALD)) {
+ mI2CState = I2C_STATE_ERROR;
+ post handleReadError();
+ break;
+ }
+ readNextByte();
+ break;
+
+ case I2C_STATE_READ:
+ if (valISR & (ISR_BED | ISR_ALD)) {
+ mI2CState = I2C_STATE_ERROR;
+ post handleReadError();
+ break;
+ }
+ mCurBuf[mCurBufIndex] = call I2C.getIDBR();
+ mCurBufIndex++;
+ readNextByte();
+ break;
+
+ case I2C_STATE_READEND:
+ if (valISR & (ISR_BED | ISR_ALD)) {
+ mI2CState = I2C_STATE_ERROR;
+ post handleReadError();
+ break;
+ }
+ mCurBuf[mCurBufIndex] = call I2C.getIDBR();
+ mI2CState = I2C_STATE_IDLE;
+ signal I2CPacket.readDone(SUCCESS,mCurTargetAddr,mCurBufLen,mCurBuf);
+ break;
+
+ case I2C_STATE_WRITE:
+ if (valISR & (ISR_BED | ISR_ALD)) {
+ mI2CState = I2C_STATE_ERROR;
+ post handleWriteError();
+ break;
+ }
+ call I2C.setIDBR(mCurBuf[mCurBufIndex]);
+ mCurBufIndex++;
+ writeNextByte();
+
+ break;
+
+ case I2C_STATE_WRITEEND:
+ if (valISR & (ISR_BED | ISR_ALD)) {
+ mI2CState = I2C_STATE_ERROR;
+ post handleWriteError();
+ break;
+ }
+ mI2CState= I2C_STATE_IDLE;
+ //call I2C.setICR(call I2C.getICR() & ~I2C_STOP);
+ call I2C.setICR(mBaseICRFlags);
+ signal I2CPacket.writeDone(SUCCESS,mCurTargetAddr,mCurBufLen,mCurBuf);
+ break;
+
+ default:
+ break;
+ }
+
+
+ return;
+ }
+
+ default async event void I2CPacket.readDone(error_t error, uint16_t addr,
+ uint8_t length, uint8_t* data) {
+ return;
+ }
+
+ default async event void I2CPacket.writeDone(error_t error, uint16_t addr,
+ uint8_t length, uint8_t* data) {
+ return;
+ }
+
+ async event void I2CSDA.interruptGPIOPin() {}
+ async event void I2CSCL.interruptGPIOPin() {}
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arch Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arch Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * The PXA27x I2C HPL interface. \r
- *\r
- * @author Phil Buonadonna\r
- */\r
-\r
-interface HplPXA27xI2C\r
-{\r
-\r
- async command uint32_t getIBMR();\r
-\r
- async command void setIDBR(uint32_t val);\r
- async command uint32_t getIDBR();\r
-\r
- async command void setICR(uint32_t val);\r
- async command uint32_t getICR();\r
-\r
- async command void setISR(uint32_t val);\r
- async command uint32_t getISR();\r
- \r
- async command void setISAR(uint32_t val);\r
- async command uint32_t getISAR();\r
-\r
- async event void interruptI2C();\r
-\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arch Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arch Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * The PXA27x I2C HPL interface.
+ *
+ * @author Phil Buonadonna
+ */
+
+interface HplPXA27xI2C
+{
+
+ async command uint32_t getIBMR();
+
+ async command void setIDBR(uint32_t val);
+ async command uint32_t getIDBR();
+
+ async command void setICR(uint32_t val);
+ async command uint32_t getICR();
+
+ async command void setISR(uint32_t val);
+ async command uint32_t getISR();
+
+ async command void setISAR(uint32_t val);
+ async command uint32_t getISAR();
+
+ async event void interruptI2C();
+
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arch Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arch Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- *\r
- * @author Phil Buonadona\r
- */\r
-\r
-configuration HplPXA27xI2CC\r
-{\r
- provides interface HplPXA27xI2C as I2C;\r
-}\r
-\r
-implementation\r
-{\r
- components new HplPXA27xI2CP(0);\r
- components HplPXA27xInterruptM;\r
- components PlatformP;\r
-\r
- I2C = HplPXA27xI2CP;\r
-\r
- HplPXA27xI2CP.Init <- PlatformP.InitL1;\r
- HplPXA27xI2CP.I2CIrq -> HplPXA27xInterruptM.PXA27xIrq[PPID_I2C];\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arch Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arch Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ *
+ * @author Phil Buonadona
+ */
+
+configuration HplPXA27xI2CC
+{
+ provides interface HplPXA27xI2C as I2C;
+}
+
+implementation
+{
+ components new HplPXA27xI2CP(0);
+ components HplPXA27xInterruptM;
+ components PlatformP;
+
+ I2C = HplPXA27xI2CP;
+
+ HplPXA27xI2CP.Init <- PlatformP.InitL1;
+ HplPXA27xI2CP.I2CIrq -> HplPXA27xInterruptM.PXA27xIrq[PPID_I2C];
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arch Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arch Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * The Private Hpl Interface for the I2C components. Handles enabling of the \r
- * clock for the interface. It DOES NOT affect the I2C_IUE bit of the ICR\r
- * register.\r
- * \r
- * @param dev The I2C to use. 0 = Standard I2c, 1 = Power I2C\r
- *\r
- * @author Phil Buonadonna\r
- */\r
-\r
-generic module HplPXA27xI2CP(uint8_t dev)\r
-{\r
- provides interface Init;\r
- provides interface HplPXA27xI2C as I2C; \r
-\r
- uses interface HplPXA27xInterrupt as I2CIrq;\r
-\r
-}\r
-\r
-implementation\r
-{\r
- bool m_fInit = FALSE;\r
-\r
- command error_t Init.init() {\r
- bool isInited;\r
-\r
- atomic {\r
- isInited = m_fInit;\r
- m_fInit = TRUE;\r
- }\r
-\r
- if (!isInited) {\r
- switch(dev) {\r
- case 0:\r
- CKEN |= CKEN14_I2C;\r
- ICR = 0;\r
- break;\r
- case 1:\r
- CKEN |= CKEN15_PMI2C;\r
- PICR = 0;\r
- break;\r
- default:\r
- break;\r
- }\r
- call I2CIrq.allocate();\r
- call I2CIrq.enable();\r
- }\r
-\r
- return SUCCESS;\r
- }\r
-\r
- async command uint32_t I2C.getIBMR() { \r
- switch(dev) {\r
- case 0: return IBMR; break;\r
- case 1: return PIBMR; break;\r
- default: return 0;\r
- }\r
- }\r
-\r
- async command void I2C.setIDBR(uint32_t val) {\r
- switch(dev) {\r
- case 0: IDBR = val; break;\r
- case 1: PIDBR = val; break;\r
- default: break;\r
- }\r
- return;\r
- }\r
-\r
- async command uint32_t I2C.getIDBR() { \r
- switch(dev) {\r
- case 0: return IDBR; break;\r
- case 1: return PIDBR; break;\r
- default: return 0;\r
- }\r
- }\r
-\r
- async command void I2C.setICR(uint32_t val) {\r
- switch(dev) {\r
- case 0: ICR = val; break;\r
- case 1: PICR = val; break;\r
- default: break;\r
- }\r
- return;\r
- }\r
-\r
- async command uint32_t I2C.getICR() { \r
- switch(dev) {\r
- case 0: return ICR; break;\r
- case 1: return PICR; break;\r
- default: return 0;\r
- }\r
- }\r
-\r
- async command void I2C.setISR(uint32_t val) { \r
- switch(dev) {\r
- case 0: ISR = val; break;\r
- case 1: PISR = val; break;\r
- default: break;\r
- }\r
- }\r
-\r
- async command uint32_t I2C.getISR() { \r
- switch(dev) {\r
- case 0: return ISR; break;\r
- case 1: return PISR; break;\r
- default: return 0;\r
- }\r
- }\r
-\r
- async command void I2C.setISAR(uint32_t val) {\r
- switch(dev) {\r
- case 0: ISAR = val; break;\r
- case 1: PISAR = val; break;\r
- default: break;\r
- }\r
- return;\r
- }\r
-\r
- async command uint32_t I2C.getISAR() { \r
- switch(dev) {\r
- case 0: return ISAR; break;\r
- case 1: return PISAR; break;\r
- default: return 0;\r
- }\r
- }\r
-\r
- async event void I2CIrq.fired() {\r
- \r
- signal I2C.interruptI2C();\r
- return;\r
- }\r
-\r
- default async event void I2C.interruptI2C() { \r
- return;\r
- }\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arch Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arch Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * The Private Hpl Interface for the I2C components. Handles enabling of the
+ * clock for the interface. It DOES NOT affect the I2C_IUE bit of the ICR
+ * register.
+ *
+ * @param dev The I2C to use. 0 = Standard I2c, 1 = Power I2C
+ *
+ * @author Phil Buonadonna
+ */
+
+generic module HplPXA27xI2CP(uint8_t dev)
+{
+ provides interface Init;
+ provides interface HplPXA27xI2C as I2C;
+
+ uses interface HplPXA27xInterrupt as I2CIrq;
+
+}
+
+implementation
+{
+ bool m_fInit = FALSE;
+
+ command error_t Init.init() {
+ bool isInited;
+
+ atomic {
+ isInited = m_fInit;
+ m_fInit = TRUE;
+ }
+
+ if (!isInited) {
+ switch(dev) {
+ case 0:
+ CKEN |= CKEN14_I2C;
+ ICR = 0;
+ break;
+ case 1:
+ CKEN |= CKEN15_PMI2C;
+ PICR = 0;
+ break;
+ default:
+ break;
+ }
+ call I2CIrq.allocate();
+ call I2CIrq.enable();
+ }
+
+ return SUCCESS;
+ }
+
+ async command uint32_t I2C.getIBMR() {
+ switch(dev) {
+ case 0: return IBMR; break;
+ case 1: return PIBMR; break;
+ default: return 0;
+ }
+ }
+
+ async command void I2C.setIDBR(uint32_t val) {
+ switch(dev) {
+ case 0: IDBR = val; break;
+ case 1: PIDBR = val; break;
+ default: break;
+ }
+ return;
+ }
+
+ async command uint32_t I2C.getIDBR() {
+ switch(dev) {
+ case 0: return IDBR; break;
+ case 1: return PIDBR; break;
+ default: return 0;
+ }
+ }
+
+ async command void I2C.setICR(uint32_t val) {
+ switch(dev) {
+ case 0: ICR = val; break;
+ case 1: PICR = val; break;
+ default: break;
+ }
+ return;
+ }
+
+ async command uint32_t I2C.getICR() {
+ switch(dev) {
+ case 0: return ICR; break;
+ case 1: return PICR; break;
+ default: return 0;
+ }
+ }
+
+ async command void I2C.setISR(uint32_t val) {
+ switch(dev) {
+ case 0: ISR = val; break;
+ case 1: PISR = val; break;
+ default: break;
+ }
+ }
+
+ async command uint32_t I2C.getISR() {
+ switch(dev) {
+ case 0: return ISR; break;
+ case 1: return PISR; break;
+ default: return 0;
+ }
+ }
+
+ async command void I2C.setISAR(uint32_t val) {
+ switch(dev) {
+ case 0: ISAR = val; break;
+ case 1: PISAR = val; break;
+ default: break;
+ }
+ return;
+ }
+
+ async command uint32_t I2C.getISAR() {
+ switch(dev) {
+ case 0: return ISAR; break;
+ case 1: return PISAR; break;
+ default: return 0;
+ }
+ }
+
+ async event void I2CIrq.fired() {
+
+ signal I2C.interruptI2C();
+ return;
+ }
+
+ default async event void I2C.interruptI2C() {
+ return;
+ }
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arch Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arch Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-configuration HplPXA27xPI2CC\r
-{\r
- provides interface HplPXA27xI2C as I2C;\r
-}\r
-\r
-implementation\r
-{\r
- components new HplPXA27xI2CP(1);\r
- components HplPXA27xInterruptM;\r
- components PlatformP;\r
-\r
- I2C = HplPXA27xI2CP;\r
-\r
- HplPXA27xI2CP.Init <- PlatformP.InitL1;\r
- HplPXA27xI2CP.I2CIrq -> HplPXA27xInterruptM.PXA27xIrq[PPID_PWR_I2C];\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arch Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arch Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+configuration HplPXA27xPI2CC
+{
+ provides interface HplPXA27xI2C as I2C;
+}
+
+implementation
+{
+ components new HplPXA27xI2CP(1);
+ components HplPXA27xInterruptM;
+ components PlatformP;
+
+ I2C = HplPXA27xI2CP;
+
+ HplPXA27xI2CP.Init <- PlatformP.InitL1;
+ HplPXA27xI2CP.I2CIrq -> HplPXA27xInterruptM.PXA27xIrq[PPID_PWR_I2C];
+}
-#ifndef __INTTYPES_H_\r
-#define __INTTYPES_H_\r
-\r
-typedef signed char int8_t;\r
-typedef unsigned char uint8_t;\r
-\r
-typedef short int16_t;\r
-typedef unsigned short uint16_t;\r
-\r
-typedef int int32_t;\r
-typedef unsigned int uint32_t;\r
-\r
-typedef long long int64_t;\r
-typedef unsigned long long uint64_t;\r
-\r
-typedef int32_t intptr_t;\r
-typedef uint32_t uintptr_t;\r
-\r
-#endif\r
+#ifndef __INTTYPES_H_
+#define __INTTYPES_H_
+
+typedef signed char int8_t;
+typedef unsigned char uint8_t;
+
+typedef short int16_t;
+typedef unsigned short uint16_t;
+
+typedef int int32_t;
+typedef unsigned int uint32_t;
+
+typedef long long int64_t;
+typedef unsigned long long uint64_t;
+
+typedef int32_t intptr_t;
+typedef uint32_t uintptr_t;
+
+#endif
-\r
-.macro CPWAIT Rd\r
- MRC P15, 0, \Rd, C2, C0, 0 @ arbitrary read of CP15 into register Rd\r
- MOV \Rd, \Rd @ wait for it (foward dependency)\r
- SUB PC, PC, #4 @ branch to next instruction\r
-.endm\r
-\r
- \r
-.macro ALLOCATE Rd\r
- MCR P15, 0, \Rd, C7, C2, 5 @ perform line allocation based on Rd\r
-.endm\r
-@@@@@@@@@@@@@@@@@@@@@@@@@\r
-@ to create an assembly function that confirms to AAPCS (or so I think ;o)\r
-@ .func function name\r
-@ STMFD R13!, {R4 - R12, LR}..alternatively STMFD R13!, {registers used, LR}\r
-@ {function body}\r
-@ LDMFD R13!, {R4 - R12, PC}...must match above with LR replaced by PC\r
-@ .endfunc\r
-@@@@@@@@@@@@@@@@@@@@@@@@@@\r
-\r
-@whether WT or WB is used is determined in mmu_table.s \r
- .extern MMUTable \r
- \r
- .equ MEMORY_CONFIG_BASE,(0x48000000) \r
- .equ FLASH_SYNC_value, (0x25C3<<1) @ Value to set flash into burst 16 sync mode\r
- @.equ FLASH_SYNC_value, (0x25C2<<1) @ Value to set flash into burst 8 sync mode\r
- .equ FLASH_WRITE,(0x0060) @ Code for writing to flash\r
- .equ FLASH_READSTATUS,(0x0070) @ Code for reading status\r
- .equ FLASH_WCONF,(0x0003) @ Code to confirm write to flash \r
- .equ FLASH_READ,(0x00FF) @ Code to place flash in read mode \r
- .equ SXCNFG_sync_value,(0x7011) @ SXCNFG value for burst16 sync flash operation\r
- @ .equ SXCNFG_sync_value,(0x6011) @ SXCNFG value for burst8 sync flash operation \r
- .equ SXCNFG_offset,(0x1c) \r
-\r
- .global initMMU\r
- .global initSyncFlash\r
- .global enableICache \r
- .global enableDCache\r
- .global disableDCache \r
- .global invalidateDCache\r
- .global cleanDCache\r
- .global globalCleanAndInvalidateDCache\r
- \r
-initSyncFlash:\r
- @this function MUST be called after the ICACHE is initialized to work correctly!!!\r
- @also, the DCache being on in WB mode will possibly cause this to randomly FAIL!\r
-.func initSyncFlash\r
- STMFD R13!, {R4 - R7, LR}\r
- ldr r1, =MEMORY_CONFIG_BASE @ Memory config register base\r
- ldr r2, =FLASH_SYNC_value @ Value to set into flash RCR register\r
- ldr r3, =FLASH_WRITE @ Write to flash instruction\r
- ldr r4, =FLASH_WCONF @ Write to flash confirm instruction\r
- ldr r5, =FLASH_READ @ Load "read array" mode command\r
- ldr r6, =0x0 @ Boot ROM Flash Base address\r
- ldr r7, =SXCNFG_sync_value @ SXCNFG Magic number for now\r
- b goSyncFlash\r
-\r
-@align on cache line so that we fetch the next 8 instructions... \r
-.align 5\r
-goSyncFlash: \r
- @ Now program everything into the Flash and SXCNFG registers\r
- str r7, [r1, #SXCNFG_offset] @ Update PXA27x SXCNFG register\r
- strh r3, [r2] @ Yes, the data is on the address bus!\r
- strh r4, [r2] @ Confirm the write to the RCR\r
- strh r5, [r6] @ Place flash back in read mode\r
- ldrh r5, [r6] @ Create a data dependency stall to guarantee write\r
- nop @ go to the end of the cache line\r
- nop\r
- nop\r
- LDMFD R13!, {R4 - R7, PC}\r
-.endfunc\r
-\r
- @assembly routine to init our MMU\r
-initMMU:\r
-.func initMMU\r
- MRC P15,0,R0,C3,C0,0 @read the domain register into R0\r
- ORR R0, R0, #0xFF @make sure that we completely enable domain 0\r
- MCR P15,0,R0,C3,C0,0 @write the domain register\r
- CPWAIT R0 @be anal and make sure it completes\r
-\r
- @time to setup the page table base register\r
- @LDR R0, =MMUTable @move the table we want into R0\r
- MCR P15, 0, R0, C2, C0 @save it \r
- CPWAIT R0 @wait it\r
-\r
- @time to enable the MMU!\r
- MRC P15,0,R0,C1,C0,0 @get CP15 register 1\r
- ORR R0, R0, #0x1 @set the MMU enable bit\r
- MCR P15,0,R0,C1,C0,0 @save it\r
- CPWAIT R0 @wait it\r
- MOV PC, LR\r
-.endfunc\r
-\r
-enableICache: \r
-.func enableICache\r
- @icache section\r
- @globally unlock the icache\r
- MCR P15, 0, R0, C9, C1, 1\r
- CPWAIT R0\r
-\r
- @globally unlock the itlb\r
- MCR P15, 0, R0, C10, C4, 1\r
- CPWAIT R0\r
- \r
- @invalidate just the icache and BTB....write to P15 C7, C5, 0\r
- MCR P15, 0, R0, C7, C5, 0\r
- CPWAIT R0\r
- \r
- @invalidate the iTLB...write to P15 C8, C5, 0\r
- MCR P15, 0, R0, c8, c5, 0 @save it\r
- CPWAIT R0 @wait it\r
- \r
- @Enable instruction cache \r
- MRC P15, 0, R0, C1, C0, 0 @get CP15 register 1\r
- ORR R0, R0, #0x1000 @set the icache bit\r
- MCR P15, 0, R0, C1, C0, 0 @wait it\r
- CPWAIT R0\r
- \r
- @enable the BTB\r
- MRC P15, 0, R0, C1, C0, 0 @get CP15 register 1\r
- ORR R0, R0, #0x800 @set the btb enable bit\r
- MCR P15, 0, R0, C1, C0, 0 @save it \r
- CPWAIT R0 @wait it \r
- MOV PC, LR\r
-.endfunc\r
-\r
-\r
-enableDCache:\r
-.func enableDCache\r
- @globally unlock the dtlb\r
- MCR P15, 0, R0, c10, c8, 1\r
- CPWAIT R0\r
- \r
- @globally unlock the dcache\r
- MCR P15, 0, R0, C9, c2, 1\r
- CPWAIT R0\r
- \r
- @first invalidate dcache and mini-dcache\r
- MCR P15, 0, R0, C7, C6, 0\r
- CPWAIT R0\r
-\r
- @invalidate the dTLB...write to P15 C8, C6, 0\r
- MCR P15, 0, R0, C8, C6, 0 @save it\r
- CPWAIT R0 @wait it\r
-\r
- \r
- @ now, enable data cache \r
- MCR P15, 0, R0, C7, C10, 4 @drain write buffer\r
- MRC P15, 0, R0, C1, C0, 0 @get CP15 register 1\r
- ORR R0, R0, #0x4 @set the dcache enable bit\r
- MCR P15, 0, R0, C1, C0, 0 @save it\r
- CPWAIT R0 @wait it\r
- MOV PC, LR\r
-.endfunc\r
-\r
-disableDCache:\r
-.func disableDCache\r
-@since caching might be WB or WT for a given line, need to invalidate/flush dcache to ensure coherency\r
- @globally unlock the dcache\r
- STMFD R13!, {R0, LR}\r
- MCR P15, 0, R0, C9, c2, 1\r
- CPWAIT R0\r
-\r
- @globally clean and invalidate the cache\r
- bl globalCleanAndInvalidateDCache\r
- \r
- @ now, disable data cache \r
- MCR P15, 0, R0, C7, C10, 4 @drain write buffer\r
- MRC P15, 0, R0, C1, C0, 0 @get CP15 register 1\r
- BIC R0, R0, #0x4 @clear the dcache enable bit\r
- MCR P15, 0, R0, C1, C0, 0 @save it\r
- CPWAIT R0 @wait it\r
- LDMFD R13!, {R0, LR}\r
-.endfunc\r
-\r
-@function to invalidate the DCCache for a given Buffer\r
-@funtion take 2 parameters\r
-@R0 = base virtual address to evict\r
-@R1 = number of bytes to evict...cache line is 32 bytes\r
-invalidateDCache: \r
-.func invalidateDCache\r
- CMPS R1,#0 @check that we're greater than 0\r
- MOVLE PC, LR @return if not\r
-invalidateDCacheLoop: \r
- MCR P15, 0, R0, C7, C6, 1 @invalidate this line\r
- SUBS R1, R1, #32 @subtract out 32 w/CPSR update\r
- ADD R0, R0, #32 @add 32 to the address w/o CPSR update\r
- BGT invalidateDCacheLoop @rerun if subtract is greater than\r
- MOV PC, LR\r
-.endfunc\r
-\r
-@function to clean the DCCache for a given Buffer\r
-@if a line is dirty, it will be cleaned...i.e. written back to memory in WB mode\r
-@funtion take 2 parameters\r
-@R0 = base virtual address to evict\r
-@R1 = number of bytes to evict...cache line is 32 bytes\r
-cleanDCache: \r
-.func cleanDCache\r
- CMPS R1,#0 @check that we're greater than 0\r
- MOVLE PC, LR @return if not\r
-cleanDCacheLoop: \r
- MCR P15, 0, R0, C7, C10, 1 @clean this line\r
- SUBS R1, R1, #32 @subtract out 32 w/CPSR update\r
- ADD R0, R0, #32 @add 32 to the address w/o CPSR update\r
- BGT cleanDCacheLoop @rerun if subtract is greater than\r
- MCR P15, 0, R0, C7, C10, 4 @drain write buffer\r
- CPWAIT R0 @wait it\r
- MOV PC, LR\r
-.endfunc\r
-\r
-\r
-@Global Clean/Invalidate THE DATA CACHE\r
-@R1 contains the virtual address of a region of cacheable memory reserved for\r
-@this clean operation\r
-@R0 is the loop count; Iterate 1024 times which is the number of lines in the\r
-@data cache\r
- \r
-globalCleanAndInvalidateDCache:\r
-.func globalCleanAndInvalidateDCache\r
- @note, this function assumes that we will NEVER have anything physical at\r
- @address 0x04000000 corresponds to static chip select 1\r
- STMFD R13!, {R0 - R3, LR}\r
- LDR R1, =0x04000000 \r
- MOV R0, #1024\r
-LOOP1:\r
- \r
- ALLOCATE R1 @ Allocate a line at the virtual address\r
- @ specified by R1.\r
- SUBS R0, R0, #1 @ Decrement loop count\r
- ADD R1, R1, #32 @ Increment the address in R1 to the next cache line\r
- BNE LOOP1\r
- \r
- @Clean the Mini-data Cache\r
- @ Can\92t use line-allocate command, so cycle 2KB of unused data through.\r
- @ R2 contains the virtual address of a region of cacheable memory reserved for\r
- @ cleaning the Mini-data Cache\r
- @ R0 is the loop count; Iterate 64 times which is the number of lines in the\r
- @ Mini-data Cache.\r
-\r
- @note, this function assumes that we will NEVER have anything physical at\r
- @address 0x05000000 corresponds to static chip select 1\r
- LDR R2, =0x05000000 \r
- MOV R0, #64\r
-LOOP2:\r
- SUBS R0, R0, #1 @ Decrement loop count\r
- LDR R3,[R2],#32 @ Load and increment to next cache line\r
- BNE LOOP2\r
- \r
- @ Invalidate the data cache and mini-data cache\r
- MCR P15, 0, R0, C7, C6, 0\r
- LDMFD R13!, {R0 - R3, PC}\r
-.endfunc\r
- \r
-.end\r
+
+.macro CPWAIT Rd
+ MRC P15, 0, \Rd, C2, C0, 0 @ arbitrary read of CP15 into register Rd
+ MOV \Rd, \Rd @ wait for it (foward dependency)
+ SUB PC, PC, #4 @ branch to next instruction
+.endm
+
+
+.macro ALLOCATE Rd
+ MCR P15, 0, \Rd, C7, C2, 5 @ perform line allocation based on Rd
+.endm
+@@@@@@@@@@@@@@@@@@@@@@@@@
+@ to create an assembly function that confirms to AAPCS (or so I think ;o)
+@ .func function name
+@ STMFD R13!, {R4 - R12, LR}..alternatively STMFD R13!, {registers used, LR}
+@ {function body}
+@ LDMFD R13!, {R4 - R12, PC}...must match above with LR replaced by PC
+@ .endfunc
+@@@@@@@@@@@@@@@@@@@@@@@@@@
+
+@whether WT or WB is used is determined in mmu_table.s
+ .extern MMUTable
+
+ .equ MEMORY_CONFIG_BASE,(0x48000000)
+ .equ FLASH_SYNC_value, (0x25C3<<1) @ Value to set flash into burst 16 sync mode
+ @.equ FLASH_SYNC_value, (0x25C2<<1) @ Value to set flash into burst 8 sync mode
+ .equ FLASH_WRITE,(0x0060) @ Code for writing to flash
+ .equ FLASH_READSTATUS,(0x0070) @ Code for reading status
+ .equ FLASH_WCONF,(0x0003) @ Code to confirm write to flash
+ .equ FLASH_READ,(0x00FF) @ Code to place flash in read mode
+ .equ SXCNFG_sync_value,(0x7011) @ SXCNFG value for burst16 sync flash operation
+ @ .equ SXCNFG_sync_value,(0x6011) @ SXCNFG value for burst8 sync flash operation
+ .equ SXCNFG_offset,(0x1c)
+
+ .global initMMU
+ .global initSyncFlash
+ .global enableICache
+ .global enableDCache
+ .global disableDCache
+ .global invalidateDCache
+ .global cleanDCache
+ .global globalCleanAndInvalidateDCache
+
+initSyncFlash:
+ @this function MUST be called after the ICACHE is initialized to work correctly!!!
+ @also, the DCache being on in WB mode will possibly cause this to randomly FAIL!
+.func initSyncFlash
+ STMFD R13!, {R4 - R7, LR}
+ ldr r1, =MEMORY_CONFIG_BASE @ Memory config register base
+ ldr r2, =FLASH_SYNC_value @ Value to set into flash RCR register
+ ldr r3, =FLASH_WRITE @ Write to flash instruction
+ ldr r4, =FLASH_WCONF @ Write to flash confirm instruction
+ ldr r5, =FLASH_READ @ Load "read array" mode command
+ ldr r6, =0x0 @ Boot ROM Flash Base address
+ ldr r7, =SXCNFG_sync_value @ SXCNFG Magic number for now
+ b goSyncFlash
+
+@align on cache line so that we fetch the next 8 instructions...
+.align 5
+goSyncFlash:
+ @ Now program everything into the Flash and SXCNFG registers
+ str r7, [r1, #SXCNFG_offset] @ Update PXA27x SXCNFG register
+ strh r3, [r2] @ Yes, the data is on the address bus!
+ strh r4, [r2] @ Confirm the write to the RCR
+ strh r5, [r6] @ Place flash back in read mode
+ ldrh r5, [r6] @ Create a data dependency stall to guarantee write
+ nop @ go to the end of the cache line
+ nop
+ nop
+ LDMFD R13!, {R4 - R7, PC}
+.endfunc
+
+ @assembly routine to init our MMU
+initMMU:
+.func initMMU
+ MRC P15,0,R0,C3,C0,0 @read the domain register into R0
+ ORR R0, R0, #0xFF @make sure that we completely enable domain 0
+ MCR P15,0,R0,C3,C0,0 @write the domain register
+ CPWAIT R0 @be anal and make sure it completes
+
+ @time to setup the page table base register
+ @LDR R0, =MMUTable @move the table we want into R0
+ MCR P15, 0, R0, C2, C0 @save it
+ CPWAIT R0 @wait it
+
+ @time to enable the MMU!
+ MRC P15,0,R0,C1,C0,0 @get CP15 register 1
+ ORR R0, R0, #0x1 @set the MMU enable bit
+ MCR P15,0,R0,C1,C0,0 @save it
+ CPWAIT R0 @wait it
+ MOV PC, LR
+.endfunc
+
+enableICache:
+.func enableICache
+ @icache section
+ @globally unlock the icache
+ MCR P15, 0, R0, C9, C1, 1
+ CPWAIT R0
+
+ @globally unlock the itlb
+ MCR P15, 0, R0, C10, C4, 1
+ CPWAIT R0
+
+ @invalidate just the icache and BTB....write to P15 C7, C5, 0
+ MCR P15, 0, R0, C7, C5, 0
+ CPWAIT R0
+
+ @invalidate the iTLB...write to P15 C8, C5, 0
+ MCR P15, 0, R0, c8, c5, 0 @save it
+ CPWAIT R0 @wait it
+
+ @Enable instruction cache
+ MRC P15, 0, R0, C1, C0, 0 @get CP15 register 1
+ ORR R0, R0, #0x1000 @set the icache bit
+ MCR P15, 0, R0, C1, C0, 0 @wait it
+ CPWAIT R0
+
+ @enable the BTB
+ MRC P15, 0, R0, C1, C0, 0 @get CP15 register 1
+ ORR R0, R0, #0x800 @set the btb enable bit
+ MCR P15, 0, R0, C1, C0, 0 @save it
+ CPWAIT R0 @wait it
+ MOV PC, LR
+.endfunc
+
+
+enableDCache:
+.func enableDCache
+ @globally unlock the dtlb
+ MCR P15, 0, R0, c10, c8, 1
+ CPWAIT R0
+
+ @globally unlock the dcache
+ MCR P15, 0, R0, C9, c2, 1
+ CPWAIT R0
+
+ @first invalidate dcache and mini-dcache
+ MCR P15, 0, R0, C7, C6, 0
+ CPWAIT R0
+
+ @invalidate the dTLB...write to P15 C8, C6, 0
+ MCR P15, 0, R0, C8, C6, 0 @save it
+ CPWAIT R0 @wait it
+
+
+ @ now, enable data cache
+ MCR P15, 0, R0, C7, C10, 4 @drain write buffer
+ MRC P15, 0, R0, C1, C0, 0 @get CP15 register 1
+ ORR R0, R0, #0x4 @set the dcache enable bit
+ MCR P15, 0, R0, C1, C0, 0 @save it
+ CPWAIT R0 @wait it
+ MOV PC, LR
+.endfunc
+
+disableDCache:
+.func disableDCache
+@since caching might be WB or WT for a given line, need to invalidate/flush dcache to ensure coherency
+ @globally unlock the dcache
+ STMFD R13!, {R0, LR}
+ MCR P15, 0, R0, C9, c2, 1
+ CPWAIT R0
+
+ @globally clean and invalidate the cache
+ bl globalCleanAndInvalidateDCache
+
+ @ now, disable data cache
+ MCR P15, 0, R0, C7, C10, 4 @drain write buffer
+ MRC P15, 0, R0, C1, C0, 0 @get CP15 register 1
+ BIC R0, R0, #0x4 @clear the dcache enable bit
+ MCR P15, 0, R0, C1, C0, 0 @save it
+ CPWAIT R0 @wait it
+ LDMFD R13!, {R0, LR}
+.endfunc
+
+@function to invalidate the DCCache for a given Buffer
+@funtion take 2 parameters
+@R0 = base virtual address to evict
+@R1 = number of bytes to evict...cache line is 32 bytes
+invalidateDCache:
+.func invalidateDCache
+ CMPS R1,#0 @check that we're greater than 0
+ MOVLE PC, LR @return if not
+invalidateDCacheLoop:
+ MCR P15, 0, R0, C7, C6, 1 @invalidate this line
+ SUBS R1, R1, #32 @subtract out 32 w/CPSR update
+ ADD R0, R0, #32 @add 32 to the address w/o CPSR update
+ BGT invalidateDCacheLoop @rerun if subtract is greater than
+ MOV PC, LR
+.endfunc
+
+@function to clean the DCCache for a given Buffer
+@if a line is dirty, it will be cleaned...i.e. written back to memory in WB mode
+@funtion take 2 parameters
+@R0 = base virtual address to evict
+@R1 = number of bytes to evict...cache line is 32 bytes
+cleanDCache:
+.func cleanDCache
+ CMPS R1,#0 @check that we're greater than 0
+ MOVLE PC, LR @return if not
+cleanDCacheLoop:
+ MCR P15, 0, R0, C7, C10, 1 @clean this line
+ SUBS R1, R1, #32 @subtract out 32 w/CPSR update
+ ADD R0, R0, #32 @add 32 to the address w/o CPSR update
+ BGT cleanDCacheLoop @rerun if subtract is greater than
+ MCR P15, 0, R0, C7, C10, 4 @drain write buffer
+ CPWAIT R0 @wait it
+ MOV PC, LR
+.endfunc
+
+
+@Global Clean/Invalidate THE DATA CACHE
+@R1 contains the virtual address of a region of cacheable memory reserved for
+@this clean operation
+@R0 is the loop count; Iterate 1024 times which is the number of lines in the
+@data cache
+
+globalCleanAndInvalidateDCache:
+.func globalCleanAndInvalidateDCache
+ @note, this function assumes that we will NEVER have anything physical at
+ @address 0x04000000 corresponds to static chip select 1
+ STMFD R13!, {R0 - R3, LR}
+ LDR R1, =0x04000000
+ MOV R0, #1024
+LOOP1:
+
+ ALLOCATE R1 @ Allocate a line at the virtual address
+ @ specified by R1.
+ SUBS R0, R0, #1 @ Decrement loop count
+ ADD R1, R1, #32 @ Increment the address in R1 to the next cache line
+ BNE LOOP1
+
+ @Clean the Mini-data Cache
+ @ CanÆt use line-allocate command, so cycle 2KB of unused data through.
+ @ R2 contains the virtual address of a region of cacheable memory reserved for
+ @ cleaning the Mini-data Cache
+ @ R0 is the loop count; Iterate 64 times which is the number of lines in the
+ @ Mini-data Cache.
+
+ @note, this function assumes that we will NEVER have anything physical at
+ @address 0x05000000 corresponds to static chip select 1
+ LDR R2, =0x05000000
+ MOV R0, #64
+LOOP2:
+ SUBS R0, R0, #1 @ Decrement loop count
+ LDR R3,[R2],#32 @ Load and increment to next cache line
+ BNE LOOP2
+
+ @ Invalidate the data cache and mini-data cache
+ MCR P15, 0, R0, C7, C6, 0
+ LDMFD R13!, {R0 - R3, PC}
+.endfunc
+
+.end
\ No newline at end of file
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * Implements the TOS 2.0 SpiByte and SpiPacket interfaces for the PXA27x.\r
- * It assumes the Motorola Serial Peripheral Interface format.\r
- * Uses DMA for the packet based transfers.\r
- * \r
- * @param valSCR The value for the SCR field in the SSCR0 register of the \r
- * associated SSP peripheral.\r
- *\r
- * @param valDSS The value for the DSS field in the SSCR0 register of the\r
- * associated SSP peripheral.\r
- * \r
- * @author Phil Buonadonna\r
- */\r
-\r
-generic module HalPXA27xSpiDMAM(uint8_t valFRF, uint8_t valSCR, uint8_t valDSS, bool enableRWOT) \r
-{\r
- provides {\r
- interface Init;\r
- interface SpiByte;\r
- interface SpiPacket[uint8_t instance];\r
- }\r
- uses {\r
- interface HplPXA27xSSP as SSP;\r
- interface HplPXA27xDMAChnl as RxDMA;\r
- interface HplPXA27xDMAChnl as TxDMA;\r
- interface HplPXA27xDMAInfo as SSPRxDMAInfo;\r
- interface HplPXA27xDMAInfo as SSPTxDMAInfo;\r
- }\r
-}\r
-\r
-implementation\r
-{\r
- // The BitBuckets need to be 8 bytes. \r
- norace unsigned long long txBitBucket, rxBitBucket;\r
- //norace uint8_t ucBitBucket[0x10000];\r
- //norace uint32_t txBitBucket, rxBitBucket;\r
- uint8_t *txCurrentBuf, *rxCurrentBuf;\r
- uint8_t instanceCurrent;\r
- uint32_t lenCurrent;\r
-\r
- command error_t Init.init() {\r
-\r
- //txBitBucket = (uint32_t)((uint32_t)&ullBitBucket[1] * ~0x7);\r
- //rxBitBucket = txBitBucket + 8;\r
- //rxBitBucket = txBitBucket = (uint32_t)&ucBitBucket[0];\r
- txCurrentBuf = rxCurrentBuf = NULL;\r
- lenCurrent = 0 ;\r
- instanceCurrent = 0;\r
-\r
- call SSP.setSSCR1((SSCR1_TRAIL | SSCR1_RFT(8) | SSCR1_TFT(8)));\r
- call SSP.setSSTO(3500);\r
- call SSP.setSSCR0(SSCR0_SCR(valSCR) | SSCR0_SSE | SSCR0_FRF(valFRF) | SSCR0_DSS(valDSS) );\r
-\r
- call TxDMA.setMap(call SSPTxDMAInfo.getMapIndex());\r
- call RxDMA.setMap(call SSPRxDMAInfo.getMapIndex());\r
- call TxDMA.setDALGNbit(TRUE);\r
- call RxDMA.setDALGNbit(TRUE);\r
-\r
- return SUCCESS;\r
- }\r
-\r
- async command uint8_t SpiByte.write(uint8_t tx) {\r
- volatile uint32_t tmp;\r
- volatile uint8_t val;\r
-#if 1\r
- while ((call SSP.getSSSR()) & SSSR_RNE) {\r
- tmp = call SSP.getSSDR();\r
- } \r
-#endif\r
- call SSP.setSSDR(tx); \r
-\r
- while ((call SSP.getSSSR()) & SSSR_BSY);\r
-\r
- val = call SSP.getSSDR();\r
-\r
- return val;\r
- }\r
-\r
- async command error_t SpiPacket.send[uint8_t instance](uint8_t* txBuf, uint8_t* rxBuf, uint16_t len) {\r
- uint32_t tmp;\r
- uint32_t txAddr,rxAddr;\r
- uint32_t txDMAFlags, rxDMAFlags;\r
- error_t error = FAIL;\r
-\r
-#if 1\r
- while ((call SSP.getSSSR()) & SSSR_RNE) {\r
- tmp = call SSP.getSSDR();\r
- }\r
-#endif \r
-\r
- atomic {\r
- txCurrentBuf = txBuf;\r
- rxCurrentBuf = rxBuf;\r
- lenCurrent = len;\r
- instanceCurrent = instance;\r
- }\r
-\r
- txDMAFlags = (DCMD_FLOWTRG | DCMD_BURST8 | DCMD_WIDTH1 \r
- | DCMD_LEN(len));\r
- rxDMAFlags = (DCMD_FLOWSRC | DCMD_ENDIRQEN | DCMD_BURST8 | DCMD_WIDTH1 \r
- | DCMD_LEN(len));\r
-\r
- if (rxBuf == NULL) { \r
- rxAddr = (uint32_t)&rxBitBucket; \r
- }\r
- else {\r
- rxAddr = (uint32_t)rxBuf; \r
- rxDMAFlags |= DCMD_INCTRGADDR; \r
- }\r
-\r
- if (txBuf == NULL) {\r
- txAddr = (uint32_t)&txBitBucket; \r
- }\r
- else {\r
- txAddr = (uint32_t)txBuf;\r
- txDMAFlags |= DCMD_INCSRCADDR;\r
- }\r
-\r
- call RxDMA.setDCSR(DCSR_NODESCFETCH | DCSR_EORIRQEN | DCSR_EORINT);\r
- call RxDMA.setDSADR(call SSPRxDMAInfo.getAddr());\r
- call RxDMA.setDTADR(rxAddr);\r
- call RxDMA.setDCMD(rxDMAFlags);\r
-\r
- call TxDMA.setDCSR(DCSR_NODESCFETCH);\r
- call TxDMA.setDSADR(txAddr);\r
- call TxDMA.setDTADR(call SSPTxDMAInfo.getAddr());\r
- call TxDMA.setDCMD(txDMAFlags);\r
- \r
- call SSP.setSSSR(SSSR_TINT);\r
- call SSP.setSSCR1((call SSP.getSSCR1()) | SSCR1_RSRE | SSCR1_TSRE);\r
-\r
- call RxDMA.setDCSR(DCSR_RUN | DCSR_NODESCFETCH | DCSR_EORIRQEN);\r
- call TxDMA.setDCSR(DCSR_RUN | DCSR_NODESCFETCH);\r
- \r
- error = SUCCESS;\r
- \r
- return error;\r
- }\r
- \r
- async event void RxDMA.interruptDMA() {\r
- uint8_t *txBuf,*rxBuf;\r
- uint8_t instance;\r
- uint32_t len;\r
- \r
- atomic {\r
- instance = instanceCurrent;\r
- len = lenCurrent;\r
- txBuf = txCurrentBuf;\r
- rxBuf = rxCurrentBuf;\r
- lenCurrent = 0;\r
- }\r
- call RxDMA.setDCMD(0);\r
- call RxDMA.setDCSR(DCSR_EORINT | DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERRINTR);\r
-\r
- signal SpiPacket.sendDone[instance](txBuf,rxBuf,len,SUCCESS);\r
-\r
- return;\r
- }\r
-\r
- async event void TxDMA.interruptDMA() {\r
- // The transmit side should NOT generate an interrupt. \r
- call TxDMA.setDCMD(0);\r
- call TxDMA.setDCSR(DCSR_EORINT | DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERRINTR);\r
- return;\r
- }\r
-\r
- async event void SSP.interruptSSP() {\r
- // For this Hal, we should never get here normally\r
- // Perhaps we should signal any weird errors? For now, just clear the interrupts\r
- call SSP.setSSSR(SSSR_BCE | SSSR_TUR | SSSR_EOC | SSSR_TINT | \r
- SSSR_PINT | SSSR_ROR );\r
- return;\r
- }\r
-\r
- default async event void SpiPacket.sendDone[uint8_t instance](uint8_t* txBuf, uint8_t* rxBuf, \r
- uint16_t len, error_t error) {\r
- return;\r
- }\r
- \r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * Implements the TOS 2.0 SpiByte and SpiPacket interfaces for the PXA27x.
+ * It assumes the Motorola Serial Peripheral Interface format.
+ * Uses DMA for the packet based transfers.
+ *
+ * @param valSCR The value for the SCR field in the SSCR0 register of the
+ * associated SSP peripheral.
+ *
+ * @param valDSS The value for the DSS field in the SSCR0 register of the
+ * associated SSP peripheral.
+ *
+ * @author Phil Buonadonna
+ */
+
+generic module HalPXA27xSpiDMAM(uint8_t valFRF, uint8_t valSCR, uint8_t valDSS, bool enableRWOT)
+{
+ provides {
+ interface Init;
+ interface SpiByte;
+ interface SpiPacket[uint8_t instance];
+ }
+ uses {
+ interface HplPXA27xSSP as SSP;
+ interface HplPXA27xDMAChnl as RxDMA;
+ interface HplPXA27xDMAChnl as TxDMA;
+ interface HplPXA27xDMAInfo as SSPRxDMAInfo;
+ interface HplPXA27xDMAInfo as SSPTxDMAInfo;
+ }
+}
+
+implementation
+{
+ // The BitBuckets need to be 8 bytes.
+ norace unsigned long long txBitBucket, rxBitBucket;
+ //norace uint8_t ucBitBucket[0x10000];
+ //norace uint32_t txBitBucket, rxBitBucket;
+ uint8_t *txCurrentBuf, *rxCurrentBuf;
+ uint8_t instanceCurrent;
+ uint32_t lenCurrent;
+
+ command error_t Init.init() {
+
+ //txBitBucket = (uint32_t)((uint32_t)&ullBitBucket[1] * ~0x7);
+ //rxBitBucket = txBitBucket + 8;
+ //rxBitBucket = txBitBucket = (uint32_t)&ucBitBucket[0];
+ txCurrentBuf = rxCurrentBuf = NULL;
+ lenCurrent = 0 ;
+ instanceCurrent = 0;
+
+ call SSP.setSSCR1((SSCR1_TRAIL | SSCR1_RFT(8) | SSCR1_TFT(8)));
+ call SSP.setSSTO(3500);
+ call SSP.setSSCR0(SSCR0_SCR(valSCR) | SSCR0_SSE | SSCR0_FRF(valFRF) | SSCR0_DSS(valDSS) );
+
+ call TxDMA.setMap(call SSPTxDMAInfo.getMapIndex());
+ call RxDMA.setMap(call SSPRxDMAInfo.getMapIndex());
+ call TxDMA.setDALGNbit(TRUE);
+ call RxDMA.setDALGNbit(TRUE);
+
+ return SUCCESS;
+ }
+
+ async command uint8_t SpiByte.write(uint8_t tx) {
+ volatile uint32_t tmp;
+ volatile uint8_t val;
+#if 1
+ while ((call SSP.getSSSR()) & SSSR_RNE) {
+ tmp = call SSP.getSSDR();
+ }
+#endif
+ call SSP.setSSDR(tx);
+
+ while ((call SSP.getSSSR()) & SSSR_BSY);
+
+ val = call SSP.getSSDR();
+
+ return val;
+ }
+
+ async command error_t SpiPacket.send[uint8_t instance](uint8_t* txBuf, uint8_t* rxBuf, uint16_t len) {
+ uint32_t tmp;
+ uint32_t txAddr,rxAddr;
+ uint32_t txDMAFlags, rxDMAFlags;
+ error_t error = FAIL;
+
+#if 1
+ while ((call SSP.getSSSR()) & SSSR_RNE) {
+ tmp = call SSP.getSSDR();
+ }
+#endif
+
+ atomic {
+ txCurrentBuf = txBuf;
+ rxCurrentBuf = rxBuf;
+ lenCurrent = len;
+ instanceCurrent = instance;
+ }
+
+ txDMAFlags = (DCMD_FLOWTRG | DCMD_BURST8 | DCMD_WIDTH1
+ | DCMD_LEN(len));
+ rxDMAFlags = (DCMD_FLOWSRC | DCMD_ENDIRQEN | DCMD_BURST8 | DCMD_WIDTH1
+ | DCMD_LEN(len));
+
+ if (rxBuf == NULL) {
+ rxAddr = (uint32_t)&rxBitBucket;
+ }
+ else {
+ rxAddr = (uint32_t)rxBuf;
+ rxDMAFlags |= DCMD_INCTRGADDR;
+ }
+
+ if (txBuf == NULL) {
+ txAddr = (uint32_t)&txBitBucket;
+ }
+ else {
+ txAddr = (uint32_t)txBuf;
+ txDMAFlags |= DCMD_INCSRCADDR;
+ }
+
+ call RxDMA.setDCSR(DCSR_NODESCFETCH | DCSR_EORIRQEN | DCSR_EORINT);
+ call RxDMA.setDSADR(call SSPRxDMAInfo.getAddr());
+ call RxDMA.setDTADR(rxAddr);
+ call RxDMA.setDCMD(rxDMAFlags);
+
+ call TxDMA.setDCSR(DCSR_NODESCFETCH);
+ call TxDMA.setDSADR(txAddr);
+ call TxDMA.setDTADR(call SSPTxDMAInfo.getAddr());
+ call TxDMA.setDCMD(txDMAFlags);
+
+ call SSP.setSSSR(SSSR_TINT);
+ call SSP.setSSCR1((call SSP.getSSCR1()) | SSCR1_RSRE | SSCR1_TSRE);
+
+ call RxDMA.setDCSR(DCSR_RUN | DCSR_NODESCFETCH | DCSR_EORIRQEN);
+ call TxDMA.setDCSR(DCSR_RUN | DCSR_NODESCFETCH);
+
+ error = SUCCESS;
+
+ return error;
+ }
+
+ async event void RxDMA.interruptDMA() {
+ uint8_t *txBuf,*rxBuf;
+ uint8_t instance;
+ uint32_t len;
+
+ atomic {
+ instance = instanceCurrent;
+ len = lenCurrent;
+ txBuf = txCurrentBuf;
+ rxBuf = rxCurrentBuf;
+ lenCurrent = 0;
+ }
+ call RxDMA.setDCMD(0);
+ call RxDMA.setDCSR(DCSR_EORINT | DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERRINTR);
+
+ signal SpiPacket.sendDone[instance](txBuf,rxBuf,len,SUCCESS);
+
+ return;
+ }
+
+ async event void TxDMA.interruptDMA() {
+ // The transmit side should NOT generate an interrupt.
+ call TxDMA.setDCMD(0);
+ call TxDMA.setDCSR(DCSR_EORINT | DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERRINTR);
+ return;
+ }
+
+ async event void SSP.interruptSSP() {
+ // For this Hal, we should never get here normally
+ // Perhaps we should signal any weird errors? For now, just clear the interrupts
+ call SSP.setSSSR(SSSR_BCE | SSSR_TUR | SSSR_EOC | SSSR_TINT |
+ SSSR_PINT | SSSR_ROR );
+ return;
+ }
+
+ default async event void SpiPacket.sendDone[uint8_t instance](uint8_t* txBuf, uint8_t* rxBuf,
+ uint16_t len, error_t error) {
+ return;
+ }
+
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * Implements the TOS 2.0 SpiByte and SpiPacket interfaces for the PXA27x.\r
- * Provides master mode communication for a variety of frame formats, speeds\r
- * and data sizes.\r
- * \r
- * @param valFRF The frame format to use. \r
- * \r
- * @param valSCR The value for the SSP clock rate.\r
- *\r
- * @param valDSS The value for the DSS field in the SSCR0 register of the\r
- * associated SSP peripheral.\r
- * \r
- * @param enableRWOT Enables Receive without transmit mode. Used only for \r
- * the SpiPacket interface. If the txBuf parameter of SpiPacket.send is null\r
- * the implementation will continuously clock in data without regard to the \r
- * contents of the TX FIFO. This is different from the spec for the interface\r
- * which requires that the transmitter send zeros (0) for this case.\r
- * \r
- * @author Phil Buonadonna\r
- * @author Miklos Maroti, Brano Kusy\r
- */\r
-\r
-generic module HalPXA27xSpiPioM(uint8_t valFRF, uint8_t valSCR, uint8_t valDSS, bool enableRWOT) \r
-{\r
- provides {\r
- interface Init;\r
- interface SpiByte;\r
- interface SpiPacket[uint8_t instance];\r
- }\r
- uses {\r
- interface HplPXA27xSSP as SSP;\r
- }\r
-}\r
-\r
-implementation\r
-{\r
- enum{\r
- FLAGS_SSCR0 = SSCR0_SCR(valSCR) | SSCR0_FRF(/*0*/valFRF) | SSCR0_DSS(valDSS),\r
- FLAGS_SSCR1 = 0\r
- };\r
-\r
- // The BitBuckets need to be 8 bytes.\r
- norace unsigned long long txBitBucket, rxBitBucket;\r
- norace uint8_t *txCurrentBuf, *rxCurrentBuf, *txPtr, *rxPtr;\r
- norace uint8_t txInc, rxInc;\r
- norace uint8_t instanceCurrent;\r
- uint32_t lenCurrent, lenRemain;\r
-\r
- command error_t Init.init() {\r
-\r
- txBitBucket = 0, rxBitBucket = 0;\r
- txCurrentBuf = rxCurrentBuf = NULL;\r
- lenCurrent = 0 ;\r
- instanceCurrent = 0;\r
- atomic lenRemain = 0;\r
-\r
- call SSP.setSSCR1(FLAGS_SSCR1);\r
- call SSP.setSSTO(3500 /*96*8*/);\r
- call SSP.setSSCR0(FLAGS_SSCR0);\r
- call SSP.setSSCR0(FLAGS_SSCR0 | SSCR0_SSE);\r
-\r
- return SUCCESS;\r
- }\r
-\r
- async command uint8_t SpiByte.write(uint8_t tx) {\r
- volatile uint8_t val;\r
-#if 1\r
- while ((call SSP.getSSSR()) & SSSR_RNE) {\r
- call SSP.getSSDR();\r
- } \r
-#endif\r
- call SSP.setSSDR(tx); \r
-\r
- while ((call SSP.getSSSR()) & SSSR_BSY);\r
-\r
- val = call SSP.getSSDR();\r
- \r
- return val;\r
- }\r
-\r
- async command error_t SpiPacket.send[uint8_t instance](uint8_t* txBuf, uint8_t* rxBuf, uint16_t len) {\r
- uint32_t i;\r
-\r
-#if 1\r
- while ((call SSP.getSSSR()) & SSSR_RNE) {\r
- call SSP.getSSDR();\r
- }\r
-#endif \r
-\r
- txCurrentBuf = txBuf;\r
- rxCurrentBuf = rxBuf;\r
- atomic lenCurrent = lenRemain = len;\r
- instanceCurrent = instance;\r
- \r
- if (rxBuf == NULL) { \r
- rxPtr = (uint8_t *)&rxBitBucket;\r
- rxInc = 0;\r
- }\r
- else {\r
- rxPtr = rxBuf;\r
- rxInc = 1;\r
- }\r
- \r
- if (txBuf == NULL) {\r
- txPtr = (uint8_t *)&txBitBucket;\r
- txInc = 0;\r
- }\r
- else {\r
- txPtr = txBuf;\r
- txInc = 1;\r
- }\r
-\r
- if ((txBuf == NULL) && (enableRWOT == TRUE)) {\r
- call SSP.setSSCR0(FLAGS_SSCR0);\r
- call SSP.setSSCR1(FLAGS_SSCR1 | SSCR1_RWOT);\r
- call SSP.setSSCR0(FLAGS_SSCR0 | SSCR0_SSE);\r
- while (len > 0) {\r
- while (!(call SSP.getSSSR() & SSSR_RNE));\r
- *rxPtr = call SSP.getSSDR();\r
- rxPtr += rxInc;\r
- len--;\r
- }\r
- call SSP.setSSCR0(FLAGS_SSCR0);\r
- call SSP.setSSCR1(FLAGS_SSCR1);\r
- call SSP.setSSCR0(FLAGS_SSCR0 | SSCR0_SSE);\r
- }\r
- else {\r
- uint8_t burst = (len < 16) ? len : 16;\r
- for (i = 0;i < burst; i++) {\r
- call SSP.setSSDR(*txPtr);\r
- txPtr += txInc;\r
- }\r
- call SSP.setSSCR1(FLAGS_SSCR1 | SSCR1_TINTE | SSCR1_RIE);\r
- }\r
- \r
- return SUCCESS;\r
- }\r
- \r
- async event void SSP.interruptSSP() {\r
- uint32_t i, uiStatus, uiFifoLevel;\r
- uint32_t burst;\r
-\r
- uiStatus = call SSP.getSSSR();\r
- call SSP.setSSSR(SSSR_TINT);\r
-\r
- uiFifoLevel = (((uiStatus & SSSR_RFL) >> 12) | 0xF) + 1;\r
- uiFifoLevel = (uiFifoLevel > lenRemain) ? lenRemain : uiFifoLevel;\r
-\r
- if( !(uiStatus & SSSR_RNE))\r
- return;\r
-\r
- for (i = 0; i < uiFifoLevel; i++) {\r
- *rxPtr = call SSP.getSSDR();\r
- rxPtr += rxInc;\r
- }\r
-\r
- atomic {\r
- lenRemain -= uiFifoLevel;\r
- burst = (lenRemain < 16) ? lenRemain : 16;\r
- }\r
-\r
- if (burst > 0) {\r
- for (i = 0;i < burst;i++) {\r
- call SSP.setSSDR(*txPtr);\r
- txPtr += txInc;\r
- }\r
- }\r
- else {\r
- uint32_t len = lenCurrent;\r
- call SSP.setSSCR1(FLAGS_SSCR1);\r
- lenCurrent = 0;\r
- signal SpiPacket.sendDone[instanceCurrent](txCurrentBuf, rxCurrentBuf,len,SUCCESS);\r
- }\r
-\r
- return;\r
- }\r
-\r
- default async event void SpiPacket.sendDone[uint8_t instance](uint8_t* txBuf, uint8_t* rxBuf, \r
- uint16_t len, error_t error) {\r
- return;\r
- }\r
- \r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * Implements the TOS 2.0 SpiByte and SpiPacket interfaces for the PXA27x.
+ * Provides master mode communication for a variety of frame formats, speeds
+ * and data sizes.
+ *
+ * @param valFRF The frame format to use.
+ *
+ * @param valSCR The value for the SSP clock rate.
+ *
+ * @param valDSS The value for the DSS field in the SSCR0 register of the
+ * associated SSP peripheral.
+ *
+ * @param enableRWOT Enables Receive without transmit mode. Used only for
+ * the SpiPacket interface. If the txBuf parameter of SpiPacket.send is null
+ * the implementation will continuously clock in data without regard to the
+ * contents of the TX FIFO. This is different from the spec for the interface
+ * which requires that the transmitter send zeros (0) for this case.
+ *
+ * @author Phil Buonadonna
+ * @author Miklos Maroti, Brano Kusy
+ */
+
+generic module HalPXA27xSpiPioM(uint8_t valFRF, uint8_t valSCR, uint8_t valDSS, bool enableRWOT)
+{
+ provides {
+ interface Init;
+ interface SpiByte;
+ interface SpiPacket[uint8_t instance];
+ }
+ uses {
+ interface HplPXA27xSSP as SSP;
+ }
+}
+
+implementation
+{
+ enum{
+ FLAGS_SSCR0 = SSCR0_SCR(valSCR) | SSCR0_FRF(/*0*/valFRF) | SSCR0_DSS(valDSS),
+ FLAGS_SSCR1 = 0
+ };
+
+ // The BitBuckets need to be 8 bytes.
+ norace unsigned long long txBitBucket, rxBitBucket;
+ norace uint8_t *txCurrentBuf, *rxCurrentBuf, *txPtr, *rxPtr;
+ norace uint8_t txInc, rxInc;
+ norace uint8_t instanceCurrent;
+ uint32_t lenCurrent, lenRemain;
+
+ command error_t Init.init() {
+
+ txBitBucket = 0, rxBitBucket = 0;
+ txCurrentBuf = rxCurrentBuf = NULL;
+ lenCurrent = 0 ;
+ instanceCurrent = 0;
+ atomic lenRemain = 0;
+
+ call SSP.setSSCR1(FLAGS_SSCR1);
+ call SSP.setSSTO(3500 /*96*8*/);
+ call SSP.setSSCR0(FLAGS_SSCR0);
+ call SSP.setSSCR0(FLAGS_SSCR0 | SSCR0_SSE);
+
+ return SUCCESS;
+ }
+
+ async command uint8_t SpiByte.write(uint8_t tx) {
+ volatile uint8_t val;
+#if 1
+ while ((call SSP.getSSSR()) & SSSR_RNE) {
+ call SSP.getSSDR();
+ }
+#endif
+ call SSP.setSSDR(tx);
+
+ while ((call SSP.getSSSR()) & SSSR_BSY);
+
+ val = call SSP.getSSDR();
+
+ return val;
+ }
+
+ async command error_t SpiPacket.send[uint8_t instance](uint8_t* txBuf, uint8_t* rxBuf, uint16_t len) {
+ uint32_t i;
+
+#if 1
+ while ((call SSP.getSSSR()) & SSSR_RNE) {
+ call SSP.getSSDR();
+ }
+#endif
+
+ txCurrentBuf = txBuf;
+ rxCurrentBuf = rxBuf;
+ atomic lenCurrent = lenRemain = len;
+ instanceCurrent = instance;
+
+ if (rxBuf == NULL) {
+ rxPtr = (uint8_t *)&rxBitBucket;
+ rxInc = 0;
+ }
+ else {
+ rxPtr = rxBuf;
+ rxInc = 1;
+ }
+
+ if (txBuf == NULL) {
+ txPtr = (uint8_t *)&txBitBucket;
+ txInc = 0;
+ }
+ else {
+ txPtr = txBuf;
+ txInc = 1;
+ }
+
+ if ((txBuf == NULL) && (enableRWOT == TRUE)) {
+ call SSP.setSSCR0(FLAGS_SSCR0);
+ call SSP.setSSCR1(FLAGS_SSCR1 | SSCR1_RWOT);
+ call SSP.setSSCR0(FLAGS_SSCR0 | SSCR0_SSE);
+ while (len > 0) {
+ while (!(call SSP.getSSSR() & SSSR_RNE));
+ *rxPtr = call SSP.getSSDR();
+ rxPtr += rxInc;
+ len--;
+ }
+ call SSP.setSSCR0(FLAGS_SSCR0);
+ call SSP.setSSCR1(FLAGS_SSCR1);
+ call SSP.setSSCR0(FLAGS_SSCR0 | SSCR0_SSE);
+ }
+ else {
+ uint8_t burst = (len < 16) ? len : 16;
+ for (i = 0;i < burst; i++) {
+ call SSP.setSSDR(*txPtr);
+ txPtr += txInc;
+ }
+ call SSP.setSSCR1(FLAGS_SSCR1 | SSCR1_TINTE | SSCR1_RIE);
+ }
+
+ return SUCCESS;
+ }
+
+ async event void SSP.interruptSSP() {
+ uint32_t i, uiStatus, uiFifoLevel;
+ uint32_t burst;
+
+ uiStatus = call SSP.getSSSR();
+ call SSP.setSSSR(SSSR_TINT);
+
+ uiFifoLevel = (((uiStatus & SSSR_RFL) >> 12) | 0xF) + 1;
+ uiFifoLevel = (uiFifoLevel > lenRemain) ? lenRemain : uiFifoLevel;
+
+ if( !(uiStatus & SSSR_RNE))
+ return;
+
+ for (i = 0; i < uiFifoLevel; i++) {
+ *rxPtr = call SSP.getSSDR();
+ rxPtr += rxInc;
+ }
+
+ atomic {
+ lenRemain -= uiFifoLevel;
+ burst = (lenRemain < 16) ? lenRemain : 16;
+ }
+
+ if (burst > 0) {
+ for (i = 0;i < burst;i++) {
+ call SSP.setSSDR(*txPtr);
+ txPtr += txInc;
+ }
+ }
+ else {
+ uint32_t len = lenCurrent;
+ call SSP.setSSCR1(FLAGS_SSCR1);
+ lenCurrent = 0;
+ signal SpiPacket.sendDone[instanceCurrent](txCurrentBuf, rxCurrentBuf,len,SUCCESS);
+ }
+
+ return;
+ }
+
+ default async event void SpiPacket.sendDone[uint8_t instance](uint8_t* txBuf, uint8_t* rxBuf,
+ uint16_t len, error_t error) {
+ return;
+ }
+
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * \r
- * @author Phil Buonadonna\r
- */\r
-interface HplPXA27xSSP \r
-{\r
- async command void setSSCR0(uint32_t val);\r
- async command uint32_t getSSCR0();\r
-\r
- async command void setSSCR1(uint32_t val);\r
- async command uint32_t getSSCR1();\r
-\r
- async command void setSSSR(uint32_t val);\r
- async command uint32_t getSSSR();\r
-\r
- async command void setSSITR(uint32_t val);\r
- async command uint32_t getSSITR();\r
-\r
- async command void setSSDR(uint32_t val);\r
- async command uint32_t getSSDR();\r
-\r
- async command void setSSTO(uint32_t val);\r
- async command uint32_t getSSTO();\r
-\r
- async command void setSSPSP(uint32_t val);\r
- async command uint32_t getSSPSP();\r
-\r
- async command void setSSTSA(uint32_t val);\r
- async command uint32_t getSSTSA();\r
-\r
- async command void setSSRSA(uint32_t val);\r
- async command uint32_t getSSRSA();\r
-\r
- async command void setSSTSS(uint32_t val);\r
- async command uint32_t getSSTSS();\r
-\r
- async command void setSSACD(uint32_t val);\r
- async command uint32_t getSSACD();\r
-\r
- async event void interruptSSP();\r
-\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ *
+ * @author Phil Buonadonna
+ */
+interface HplPXA27xSSP
+{
+ async command void setSSCR0(uint32_t val);
+ async command uint32_t getSSCR0();
+
+ async command void setSSCR1(uint32_t val);
+ async command uint32_t getSSCR1();
+
+ async command void setSSSR(uint32_t val);
+ async command uint32_t getSSSR();
+
+ async command void setSSITR(uint32_t val);
+ async command uint32_t getSSITR();
+
+ async command void setSSDR(uint32_t val);
+ async command uint32_t getSSDR();
+
+ async command void setSSTO(uint32_t val);
+ async command uint32_t getSSTO();
+
+ async command void setSSPSP(uint32_t val);
+ async command uint32_t getSSPSP();
+
+ async command void setSSTSA(uint32_t val);
+ async command uint32_t getSSTSA();
+
+ async command void setSSRSA(uint32_t val);
+ async command uint32_t getSSRSA();
+
+ async command void setSSTSS(uint32_t val);
+ async command uint32_t getSSTSS();
+
+ async command void setSSACD(uint32_t val);
+ async command uint32_t getSSACD();
+
+ async event void interruptSSP();
+
+}
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * \r
- * @author Phil Buonadonna\r
- */\r
-\r
-configuration HplPXA27xSSP1C \r
-{\r
- provides {\r
- interface HplPXA27xSSP;\r
- interface HplPXA27xDMAInfo as SSPRxDMAReg;\r
- interface HplPXA27xDMAInfo as SSPTxDMAReg;\r
- }\r
-}\r
-\r
-implementation\r
-{\r
- components HplPXA27xSSPP;\r
- components HplPXA27xInterruptM;\r
- components PlatformP;\r
-\r
- HplPXA27xSSP = HplPXA27xSSPP.HplPXA27xSSP[1];\r
- components new HplPXA27xDMAInfoC(13, (uint32_t)&SSDR_1) as SSPRxDMA;\r
- components new HplPXA27xDMAInfoC(14, (uint32_t)&SSDR_1) as SSPTxDMA;\r
- SSPRxDMAReg = SSPRxDMA;\r
- SSPTxDMAReg = SSPTxDMA;\r
-\r
- HplPXA27xSSPP.Init[1] <- PlatformP.InitL1;\r
-\r
- HplPXA27xSSPP.SSP1Irq -> HplPXA27xInterruptM.PXA27xIrq[PPID_SSP1];\r
-}\r
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ *
+ * @author Phil Buonadonna
+ */
+
+configuration HplPXA27xSSP1C
+{
+ provides {
+ interface HplPXA27xSSP;
+ interface HplPXA27xDMAInfo as SSPRxDMAReg;
+ interface HplPXA27xDMAInfo as SSPTxDMAReg;
+ }
+}
+
+implementation
+{
+ components HplPXA27xSSPP;
+ components HplPXA27xInterruptM;
+ components PlatformP;
+
+ HplPXA27xSSP = HplPXA27xSSPP.HplPXA27xSSP[1];
+ components new HplPXA27xDMAInfoC(13, (uint32_t)&SSDR_1) as SSPRxDMA;
+ components new HplPXA27xDMAInfoC(14, (uint32_t)&SSDR_1) as SSPTxDMA;
+ SSPRxDMAReg = SSPRxDMA;
+ SSPTxDMAReg = SSPTxDMA;
+
+ HplPXA27xSSPP.Init[1] <- PlatformP.InitL1;
+
+ HplPXA27xSSPP.SSP1Irq -> HplPXA27xInterruptM.PXA27xIrq[PPID_SSP1];
+}
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * \r
- * @author Phil Buonadonna\r
- */\r
-\r
-configuration HplPXA27xSSP2C \r
-{\r
- provides {\r
- interface HplPXA27xSSP;\r
- interface HplPXA27xDMAInfo as SSPRxDMAReg;\r
- interface HplPXA27xDMAInfo as SSPTxDMAReg;\r
- }\r
-}\r
-\r
-implementation\r
-{\r
- components HplPXA27xSSPP;\r
- components HplPXA27xInterruptM;\r
- components PlatformP;\r
-\r
- HplPXA27xSSP = HplPXA27xSSPP.HplPXA27xSSP[2];\r
- components new HplPXA27xDMAInfoC(15, (uint32_t)&SSDR_2) as SSPRxDMA;\r
- components new HplPXA27xDMAInfoC(16, (uint32_t)&SSDR_2) as SSPTxDMA;\r
- SSPRxDMAReg = SSPRxDMA;\r
- SSPTxDMAReg = SSPTxDMA;\r
-\r
- HplPXA27xSSPP.Init[2] <- PlatformP.InitL1;\r
-\r
- HplPXA27xSSPP.SSP2Irq -> HplPXA27xInterrupM.PXA27xIrq[PPID_SSP2];\r
-}\r
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ *
+ * @author Phil Buonadonna
+ */
+
+configuration HplPXA27xSSP2C
+{
+ provides {
+ interface HplPXA27xSSP;
+ interface HplPXA27xDMAInfo as SSPRxDMAReg;
+ interface HplPXA27xDMAInfo as SSPTxDMAReg;
+ }
+}
+
+implementation
+{
+ components HplPXA27xSSPP;
+ components HplPXA27xInterruptM;
+ components PlatformP;
+
+ HplPXA27xSSP = HplPXA27xSSPP.HplPXA27xSSP[2];
+ components new HplPXA27xDMAInfoC(15, (uint32_t)&SSDR_2) as SSPRxDMA;
+ components new HplPXA27xDMAInfoC(16, (uint32_t)&SSDR_2) as SSPTxDMA;
+ SSPRxDMAReg = SSPRxDMA;
+ SSPTxDMAReg = SSPTxDMA;
+
+ HplPXA27xSSPP.Init[2] <- PlatformP.InitL1;
+
+ HplPXA27xSSPP.SSP2Irq -> HplPXA27xInterrupM.PXA27xIrq[PPID_SSP2];
+}
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * \r
- * @author Phil Buonadonna\r
- */\r
-\r
-configuration HplPXA27xSSP3C \r
-{\r
- provides {\r
- interface HplPXA27xSSP;\r
- interface HplPXA27xDMAInfo as SSPRxDMAInfo;\r
- interface HplPXA27xDMAInfo as SSPTxDMAInfo;\r
- }\r
-}\r
-\r
-implementation\r
-{\r
- components HplPXA27xSSPP;\r
- components HplPXA27xInterruptM;\r
- components PlatformP;\r
- \r
- HplPXA27xSSP = HplPXA27xSSPP.HplPXA27xSSP[3];\r
- components new HplPXA27xDMAInfoC(66, (uint32_t)&SSDR_3) as SSPRxDMA;\r
- components new HplPXA27xDMAInfoC(67, (uint32_t)&SSDR_3) as SSPTxDMA;\r
- SSPRxDMAInfo = SSPRxDMA;\r
- SSPTxDMAInfo = SSPTxDMA;\r
-\r
- HplPXA27xSSPP.Init[3] <- PlatformP.InitL1;\r
-\r
- HplPXA27xSSPP.SSP3Irq -> HplPXA27xInterruptM.PXA27xIrq[PPID_SSP3];\r
-}\r
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ *
+ * @author Phil Buonadonna
+ */
+
+configuration HplPXA27xSSP3C
+{
+ provides {
+ interface HplPXA27xSSP;
+ interface HplPXA27xDMAInfo as SSPRxDMAInfo;
+ interface HplPXA27xDMAInfo as SSPTxDMAInfo;
+ }
+}
+
+implementation
+{
+ components HplPXA27xSSPP;
+ components HplPXA27xInterruptM;
+ components PlatformP;
+
+ HplPXA27xSSP = HplPXA27xSSPP.HplPXA27xSSP[3];
+ components new HplPXA27xDMAInfoC(66, (uint32_t)&SSDR_3) as SSPRxDMA;
+ components new HplPXA27xDMAInfoC(67, (uint32_t)&SSDR_3) as SSPTxDMA;
+ SSPRxDMAInfo = SSPRxDMA;
+ SSPTxDMAInfo = SSPTxDMA;
+
+ HplPXA27xSSPP.Init[3] <- PlatformP.InitL1;
+
+ HplPXA27xSSPP.SSP3Irq -> HplPXA27xInterruptM.PXA27xIrq[PPID_SSP3];
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- *\r
- * @author Phil Buonadonna\r
- */\r
-\r
-module HplPXA27xSSPP \r
-{\r
- provides {\r
- interface Init[uint8_t chnl];\r
- interface HplPXA27xSSP[uint8_t chnl];\r
- }\r
- uses {\r
- interface HplPXA27xInterrupt as SSP1Irq;\r
- interface HplPXA27xInterrupt as SSP2Irq;\r
- interface HplPXA27xInterrupt as SSP3Irq;\r
- }\r
-}\r
-\r
-implementation \r
-{\r
-\r
- command error_t Init.init[uint8_t chnl]() {\r
- error_t error = SUCCESS;\r
- \r
- switch (chnl) {\r
- case 1:\r
- CKEN |= CKEN23_SSP1;\r
- call SSP1Irq.enable(); \r
- break;\r
- case 2: \r
- CKEN |= CKEN3_SSP2;\r
- call SSP2Irq.enable(); \r
- break;\r
- case 3: \r
- CKEN |= CKEN4_SSP3;\r
- //call SSP3Irq.allocate();\r
- call SSP3Irq.enable(); \r
- break;\r
- default: \r
- error = FAIL;\r
- break;\r
- }\r
-\r
- return error;\r
- }\r
-\r
- async command void HplPXA27xSSP.setSSCR0[uint8_t chnl](uint32_t val) {\r
- switch (chnl) {\r
- case 1: SSCR0_1 = val; break;\r
- case 2: SSCR0_2 = val; break;\r
- case 3: SSCR0_3 = val; break;\r
- default: break;\r
- }\r
- return;\r
- }\r
-\r
- async command uint32_t HplPXA27xSSP.getSSCR0[uint8_t chnl]() {\r
- switch (chnl) {\r
- case 1: return SSCR0_1; break;\r
- case 2: return SSCR0_2; break;\r
- case 3: return SSCR0_3; break;\r
- default: return 0;\r
- }\r
- }\r
-\r
- async command void HplPXA27xSSP.setSSCR1[uint8_t chnl](uint32_t val) {\r
- switch (chnl) {\r
- case 1: SSCR1_1 = val; break;\r
- case 2: SSCR1_2 = val; break;\r
- case 3: SSCR1_3 = val; break;\r
- default: break;\r
- }\r
- return;\r
- }\r
- async command uint32_t HplPXA27xSSP.getSSCR1[uint8_t chnl]() {\r
- switch (chnl) {\r
- case 1: return SSCR1_1; break;\r
- case 2: return SSCR1_2; break;\r
- case 3: return SSCR1_3; break;\r
- default: return 0;\r
- }\r
- }\r
- \r
- async command void HplPXA27xSSP.setSSSR[uint8_t chnl](uint32_t val) {\r
- switch (chnl) {\r
- case 1: SSSR_1 = val; break;\r
- case 2: SSSR_2 = val; break;\r
- case 3: SSSR_3 = val; break;\r
- default: break;\r
- }\r
- return;\r
- }\r
- async command uint32_t HplPXA27xSSP.getSSSR[uint8_t chnl]() {\r
- switch (chnl) {\r
- case 1: return SSSR_1; break;\r
- case 2: return SSSR_2; break;\r
- case 3: return SSSR_3; break;\r
- default: return 0;\r
- }\r
- }\r
-\r
- async command void HplPXA27xSSP.setSSITR[uint8_t chnl](uint32_t val) {\r
- switch (chnl) {\r
- case 1: SSITR_1 = val; break;\r
- case 2: SSITR_2 = val; break;\r
- case 3: SSITR_3 = val; break;\r
- default: break;\r
- }\r
- return;\r
- }\r
- async command uint32_t HplPXA27xSSP.getSSITR[uint8_t chnl]() {\r
- switch (chnl) {\r
- case 1: return SSITR_1; break;\r
- case 2: return SSITR_2; break;\r
- case 3: return SSITR_3; break;\r
- default: return 0;\r
- }\r
- }\r
-\r
- async command void HplPXA27xSSP.setSSDR[uint8_t chnl](uint32_t val) {\r
- switch (chnl) {\r
- case 1: SSDR_1 = val; break;\r
- case 2: SSDR_2 = val; break;\r
- case 3: SSDR_3 = val; break;\r
- default: break;\r
- }\r
- return;\r
- }\r
- async command uint32_t HplPXA27xSSP.getSSDR[uint8_t chnl]() {\r
- switch (chnl) {\r
- case 1: return SSDR_1; break;\r
- case 2: return SSDR_2; break;\r
- case 3: return SSDR_3; break;\r
- default: return 0;\r
- }\r
- }\r
-\r
- async command void HplPXA27xSSP.setSSTO[uint8_t chnl](uint32_t val) {\r
- switch (chnl) {\r
- case 1: SSTO_1 = val; break;\r
- case 2: SSTO_2 = val; break;\r
- case 3: SSTO_3 = val; break;\r
- default: break;\r
- }\r
- return;\r
- }\r
- async command uint32_t HplPXA27xSSP.getSSTO[uint8_t chnl]() {\r
- switch (chnl) {\r
- case 1: return SSTO_1; break;\r
- case 2: return SSTO_2; break;\r
- case 3: return SSTO_3; break;\r
- default: return 0;\r
- }\r
- }\r
-\r
- async command void HplPXA27xSSP.setSSPSP[uint8_t chnl](uint32_t val) {\r
- switch (chnl) {\r
- case 1: SSPSP_1 = val; break;\r
- case 2: SSPSP_2 = val; break;\r
- case 3: SSPSP_3 = val; break;\r
- default: break;\r
- }\r
- return;\r
- }\r
- async command uint32_t HplPXA27xSSP.getSSPSP[uint8_t chnl]() {\r
- switch (chnl) {\r
- case 1: return SSPSP_1; break;\r
- case 2: return SSPSP_2; break;\r
- case 3: return SSPSP_3; break;\r
- default: return 0;\r
- }\r
- }\r
-\r
- async command void HplPXA27xSSP.setSSTSA[uint8_t chnl](uint32_t val) {\r
- switch (chnl) {\r
- case 1: SSTSA_1 = val; break;\r
- case 2: SSTSA_2 = val; break;\r
- case 3: SSTSA_3 = val; break;\r
- default: break;\r
- }\r
- return;\r
- }\r
- async command uint32_t HplPXA27xSSP.getSSTSA[uint8_t chnl]() {\r
- switch (chnl) {\r
- case 1: return SSTSA_1; break;\r
- case 2: return SSTSA_2; break;\r
- case 3: return SSTSA_3; break;\r
- default: return 0;\r
- }\r
- }\r
-\r
- async command void HplPXA27xSSP.setSSRSA[uint8_t chnl](uint32_t val) {\r
- switch (chnl) {\r
- case 1: SSRSA_1 = val; break;\r
- case 2: SSRSA_2 = val; break;\r
- case 3: SSRSA_3 = val; break;\r
- default: break;\r
- }\r
- return;\r
- }\r
- async command uint32_t HplPXA27xSSP.getSSRSA[uint8_t chnl]() {\r
- switch (chnl) {\r
- case 1: return SSRSA_1; break;\r
- case 2: return SSRSA_2; break;\r
- case 3: return SSRSA_3; break;\r
- default: return 0;\r
- }\r
- }\r
-\r
- async command void HplPXA27xSSP.setSSTSS[uint8_t chnl](uint32_t val) {\r
- switch (chnl) {\r
- case 1: SSTSS_1 = val; break;\r
- case 2: SSTSS_2 = val; break;\r
- case 3: SSTSS_3 = val; break;\r
- default: break;\r
- }\r
- return;\r
- }\r
- async command uint32_t HplPXA27xSSP.getSSTSS[uint8_t chnl]() {\r
- switch (chnl) {\r
- case 1: return SSTSS_1; break;\r
- case 2: return SSTSS_2; break;\r
- case 3: return SSTSS_3; break;\r
- default: return 0;\r
- }\r
- }\r
-\r
- async command void HplPXA27xSSP.setSSACD[uint8_t chnl](uint32_t val) {\r
- switch (chnl) {\r
- case 1: SSACD_1 = val; break;\r
- case 2: SSACD_2 = val; break;\r
- case 3: SSACD_3 = val; break;\r
- default: break;\r
- }\r
- return; \r
- }\r
- async command uint32_t HplPXA27xSSP.getSSACD[uint8_t chnl]() {\r
- switch (chnl) {\r
- case 1: return SSACD_1; break;\r
- case 2: return SSACD_2; break;\r
- case 3: return SSACD_3; break;\r
- default: return 0;\r
- }\r
- }\r
-\r
- default async event void HplPXA27xSSP.interruptSSP[uint8_t chnl]() {\r
- call HplPXA27xSSP.setSSSR[chnl](SSSR_BCE | SSSR_TUR | SSSR_EOC | SSSR_TINT | \r
- SSSR_PINT | SSSR_ROR );\r
- return;\r
- }\r
-\r
- async event void SSP1Irq.fired() {\r
- signal HplPXA27xSSP.interruptSSP[1]();\r
- }\r
- async event void SSP2Irq.fired() {\r
- signal HplPXA27xSSP.interruptSSP[2]();\r
- }\r
- async event void SSP3Irq.fired() {\r
- signal HplPXA27xSSP.interruptSSP[3]();\r
- }\r
-\r
- default async command void SSP1Irq.enable() {return;}\r
- default async command void SSP2Irq.enable() {return;}\r
- default async command void SSP3Irq.enable() {return;}\r
-\r
-}\r
-\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ *
+ * @author Phil Buonadonna
+ */
+
+module HplPXA27xSSPP
+{
+ provides {
+ interface Init[uint8_t chnl];
+ interface HplPXA27xSSP[uint8_t chnl];
+ }
+ uses {
+ interface HplPXA27xInterrupt as SSP1Irq;
+ interface HplPXA27xInterrupt as SSP2Irq;
+ interface HplPXA27xInterrupt as SSP3Irq;
+ }
+}
+
+implementation
+{
+
+ command error_t Init.init[uint8_t chnl]() {
+ error_t error = SUCCESS;
+
+ switch (chnl) {
+ case 1:
+ CKEN |= CKEN23_SSP1;
+ call SSP1Irq.enable();
+ break;
+ case 2:
+ CKEN |= CKEN3_SSP2;
+ call SSP2Irq.enable();
+ break;
+ case 3:
+ CKEN |= CKEN4_SSP3;
+ //call SSP3Irq.allocate();
+ call SSP3Irq.enable();
+ break;
+ default:
+ error = FAIL;
+ break;
+ }
+
+ return error;
+ }
+
+ async command void HplPXA27xSSP.setSSCR0[uint8_t chnl](uint32_t val) {
+ switch (chnl) {
+ case 1: SSCR0_1 = val; break;
+ case 2: SSCR0_2 = val; break;
+ case 3: SSCR0_3 = val; break;
+ default: break;
+ }
+ return;
+ }
+
+ async command uint32_t HplPXA27xSSP.getSSCR0[uint8_t chnl]() {
+ switch (chnl) {
+ case 1: return SSCR0_1; break;
+ case 2: return SSCR0_2; break;
+ case 3: return SSCR0_3; break;
+ default: return 0;
+ }
+ }
+
+ async command void HplPXA27xSSP.setSSCR1[uint8_t chnl](uint32_t val) {
+ switch (chnl) {
+ case 1: SSCR1_1 = val; break;
+ case 2: SSCR1_2 = val; break;
+ case 3: SSCR1_3 = val; break;
+ default: break;
+ }
+ return;
+ }
+ async command uint32_t HplPXA27xSSP.getSSCR1[uint8_t chnl]() {
+ switch (chnl) {
+ case 1: return SSCR1_1; break;
+ case 2: return SSCR1_2; break;
+ case 3: return SSCR1_3; break;
+ default: return 0;
+ }
+ }
+
+ async command void HplPXA27xSSP.setSSSR[uint8_t chnl](uint32_t val) {
+ switch (chnl) {
+ case 1: SSSR_1 = val; break;
+ case 2: SSSR_2 = val; break;
+ case 3: SSSR_3 = val; break;
+ default: break;
+ }
+ return;
+ }
+ async command uint32_t HplPXA27xSSP.getSSSR[uint8_t chnl]() {
+ switch (chnl) {
+ case 1: return SSSR_1; break;
+ case 2: return SSSR_2; break;
+ case 3: return SSSR_3; break;
+ default: return 0;
+ }
+ }
+
+ async command void HplPXA27xSSP.setSSITR[uint8_t chnl](uint32_t val) {
+ switch (chnl) {
+ case 1: SSITR_1 = val; break;
+ case 2: SSITR_2 = val; break;
+ case 3: SSITR_3 = val; break;
+ default: break;
+ }
+ return;
+ }
+ async command uint32_t HplPXA27xSSP.getSSITR[uint8_t chnl]() {
+ switch (chnl) {
+ case 1: return SSITR_1; break;
+ case 2: return SSITR_2; break;
+ case 3: return SSITR_3; break;
+ default: return 0;
+ }
+ }
+
+ async command void HplPXA27xSSP.setSSDR[uint8_t chnl](uint32_t val) {
+ switch (chnl) {
+ case 1: SSDR_1 = val; break;
+ case 2: SSDR_2 = val; break;
+ case 3: SSDR_3 = val; break;
+ default: break;
+ }
+ return;
+ }
+ async command uint32_t HplPXA27xSSP.getSSDR[uint8_t chnl]() {
+ switch (chnl) {
+ case 1: return SSDR_1; break;
+ case 2: return SSDR_2; break;
+ case 3: return SSDR_3; break;
+ default: return 0;
+ }
+ }
+
+ async command void HplPXA27xSSP.setSSTO[uint8_t chnl](uint32_t val) {
+ switch (chnl) {
+ case 1: SSTO_1 = val; break;
+ case 2: SSTO_2 = val; break;
+ case 3: SSTO_3 = val; break;
+ default: break;
+ }
+ return;
+ }
+ async command uint32_t HplPXA27xSSP.getSSTO[uint8_t chnl]() {
+ switch (chnl) {
+ case 1: return SSTO_1; break;
+ case 2: return SSTO_2; break;
+ case 3: return SSTO_3; break;
+ default: return 0;
+ }
+ }
+
+ async command void HplPXA27xSSP.setSSPSP[uint8_t chnl](uint32_t val) {
+ switch (chnl) {
+ case 1: SSPSP_1 = val; break;
+ case 2: SSPSP_2 = val; break;
+ case 3: SSPSP_3 = val; break;
+ default: break;
+ }
+ return;
+ }
+ async command uint32_t HplPXA27xSSP.getSSPSP[uint8_t chnl]() {
+ switch (chnl) {
+ case 1: return SSPSP_1; break;
+ case 2: return SSPSP_2; break;
+ case 3: return SSPSP_3; break;
+ default: return 0;
+ }
+ }
+
+ async command void HplPXA27xSSP.setSSTSA[uint8_t chnl](uint32_t val) {
+ switch (chnl) {
+ case 1: SSTSA_1 = val; break;
+ case 2: SSTSA_2 = val; break;
+ case 3: SSTSA_3 = val; break;
+ default: break;
+ }
+ return;
+ }
+ async command uint32_t HplPXA27xSSP.getSSTSA[uint8_t chnl]() {
+ switch (chnl) {
+ case 1: return SSTSA_1; break;
+ case 2: return SSTSA_2; break;
+ case 3: return SSTSA_3; break;
+ default: return 0;
+ }
+ }
+
+ async command void HplPXA27xSSP.setSSRSA[uint8_t chnl](uint32_t val) {
+ switch (chnl) {
+ case 1: SSRSA_1 = val; break;
+ case 2: SSRSA_2 = val; break;
+ case 3: SSRSA_3 = val; break;
+ default: break;
+ }
+ return;
+ }
+ async command uint32_t HplPXA27xSSP.getSSRSA[uint8_t chnl]() {
+ switch (chnl) {
+ case 1: return SSRSA_1; break;
+ case 2: return SSRSA_2; break;
+ case 3: return SSRSA_3; break;
+ default: return 0;
+ }
+ }
+
+ async command void HplPXA27xSSP.setSSTSS[uint8_t chnl](uint32_t val) {
+ switch (chnl) {
+ case 1: SSTSS_1 = val; break;
+ case 2: SSTSS_2 = val; break;
+ case 3: SSTSS_3 = val; break;
+ default: break;
+ }
+ return;
+ }
+ async command uint32_t HplPXA27xSSP.getSSTSS[uint8_t chnl]() {
+ switch (chnl) {
+ case 1: return SSTSS_1; break;
+ case 2: return SSTSS_2; break;
+ case 3: return SSTSS_3; break;
+ default: return 0;
+ }
+ }
+
+ async command void HplPXA27xSSP.setSSACD[uint8_t chnl](uint32_t val) {
+ switch (chnl) {
+ case 1: SSACD_1 = val; break;
+ case 2: SSACD_2 = val; break;
+ case 3: SSACD_3 = val; break;
+ default: break;
+ }
+ return;
+ }
+ async command uint32_t HplPXA27xSSP.getSSACD[uint8_t chnl]() {
+ switch (chnl) {
+ case 1: return SSACD_1; break;
+ case 2: return SSACD_2; break;
+ case 3: return SSACD_3; break;
+ default: return 0;
+ }
+ }
+
+ default async event void HplPXA27xSSP.interruptSSP[uint8_t chnl]() {
+ call HplPXA27xSSP.setSSSR[chnl](SSSR_BCE | SSSR_TUR | SSSR_EOC | SSSR_TINT |
+ SSSR_PINT | SSSR_ROR );
+ return;
+ }
+
+ async event void SSP1Irq.fired() {
+ signal HplPXA27xSSP.interruptSSP[1]();
+ }
+ async event void SSP2Irq.fired() {
+ signal HplPXA27xSSP.interruptSSP[2]();
+ }
+ async event void SSP3Irq.fired() {
+ signal HplPXA27xSSP.interruptSSP[3]();
+ }
+
+ default async command void SSP1Irq.enable() {return;}
+ default async command void SSP2Irq.enable() {return;}
+ default async command void SSP3Irq.enable() {return;}
+
+}
+
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/** \r
- * @author Phil Buonadonna\r
- *\r
- */\r
-\r
-generic configuration Alarm32khzC()\r
-{\r
- provides interface Init;\r
- provides interface Alarm<T32khz,uint32_t> as Alarm32khz32;\r
-}\r
-\r
-implementation\r
-{\r
- components new HalPXA27xAlarmM(T32khz,1) as PhysAlarm32khz;\r
- components HalPXA27xOSTimerMapC;\r
-\r
- enum {OST_CLIENT_ID = unique("PXA27xOSTimer.Resource")};\r
-\r
- Init = PhysAlarm32khz;\r
- Alarm32khz32 = PhysAlarm32khz;\r
-\r
- PhysAlarm32khz.OSTInit -> HalPXA27xOSTimerMapC.Init;\r
- PhysAlarm32khz.OSTChnl -> HalPXA27xOSTimerMapC.OSTChnl[OST_CLIENT_ID];\r
-\r
-}\r
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * @author Phil Buonadonna
+ *
+ */
+
+generic configuration Alarm32khzC()
+{
+ provides interface Init;
+ provides interface Alarm<T32khz,uint32_t> as Alarm32khz32;
+}
+
+implementation
+{
+ components new HalPXA27xAlarmM(T32khz,1) as PhysAlarm32khz;
+ components HalPXA27xOSTimerMapC;
+
+ enum {OST_CLIENT_ID = unique("PXA27xOSTimer.Resource")};
+
+ Init = PhysAlarm32khz;
+ Alarm32khz32 = PhysAlarm32khz;
+
+ PhysAlarm32khz.OSTInit -> HalPXA27xOSTimerMapC.Init;
+ PhysAlarm32khz.OSTChnl -> HalPXA27xOSTimerMapC.OSTChnl[OST_CLIENT_ID];
+
+}
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/** \r
- * @author Phil Buonadonna\r
- *\r
- */\r
-generic configuration AlarmMilliC()\r
-{\r
- provides interface Init;\r
- provides interface Alarm<TMilli,uint32_t> as AlarmMilli32;\r
-}\r
-\r
-implementation\r
-{\r
- components new HalPXA27xAlarmM(TMilli,2) as PhysAlarmMilli;\r
- components HalPXA27xOSTimerMapC;\r
- \r
- enum {OST_CLIENT_ID = unique("PXA27xOSTimer.Resource")};\r
-\r
- Init = PhysAlarmMilli;\r
- AlarmMilli32 = PhysAlarmMilli;\r
-\r
- PhysAlarmMilli.OSTInit -> HalPXA27xOSTimerMapC.Init;\r
- PhysAlarmMilli.OSTChnl -> HalPXA27xOSTimerMapC.OSTChnl[OST_CLIENT_ID];\r
-\r
-}\r
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * @author Phil Buonadonna
+ *
+ */
+generic configuration AlarmMilliC()
+{
+ provides interface Init;
+ provides interface Alarm<TMilli,uint32_t> as AlarmMilli32;
+}
+
+implementation
+{
+ components new HalPXA27xAlarmM(TMilli,2) as PhysAlarmMilli;
+ components HalPXA27xOSTimerMapC;
+
+ enum {OST_CLIENT_ID = unique("PXA27xOSTimer.Resource")};
+
+ Init = PhysAlarmMilli;
+ AlarmMilli32 = PhysAlarmMilli;
+
+ PhysAlarmMilli.OSTInit -> HalPXA27xOSTimerMapC.Init;
+ PhysAlarmMilli.OSTChnl -> HalPXA27xOSTimerMapC.OSTChnl[OST_CLIENT_ID];
+
+}
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * This configuration piggybacks off of the TOS 2.0 Counter32khzC component.\r
- * This component manages initialization of the underlying Timer components.\r
- *\r
- * @author Phil Buonadonna\r
- */\r
-configuration BusyWait32khzC\r
-{\r
- provides interface BusyWait<T32khz,uint16_t> as BusyWait32khz16;\r
-}\r
-\r
-implementation \r
-{\r
- components new HalPXA27xBusyWaitPM(T32khz,397) as PXA27xBusyWait32khz;\r
- components HplPXA27xOSTimerC;\r
-\r
- BusyWait32khz16 = PXA27xBusyWait32khz.BusyWait;\r
- \r
- PXA27xBusyWait32khz.OST -> HplPXA27xOSTimerC.OST0;\r
-}\r
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * This configuration piggybacks off of the TOS 2.0 Counter32khzC component.
+ * This component manages initialization of the underlying Timer components.
+ *
+ * @author Phil Buonadonna
+ */
+configuration BusyWait32khzC
+{
+ provides interface BusyWait<T32khz,uint16_t> as BusyWait32khz16;
+}
+
+implementation
+{
+ components new HalPXA27xBusyWaitPM(T32khz,397) as PXA27xBusyWait32khz;
+ components HplPXA27xOSTimerC;
+
+ BusyWait32khz16 = PXA27xBusyWait32khz.BusyWait;
+
+ PXA27xBusyWait32khz.OST -> HplPXA27xOSTimerC.OST0;
+}
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * Implements the BusyWaitMicroC timer component. This component\r
- * instantiates a new Counter with Microsecond precision and \r
- * binds it to the BusyWait interface via PXA27xBusyWaitP\r
- * \r
- * @author Phil Buonadonna\r
- */\r
-configuration BusyWaitMicroC\r
-{\r
- provides interface BusyWait<TMicro,uint16_t> as BusyWaitMicro16;\r
-}\r
-\r
-implementation\r
-{\r
- components new HalPXA27xBusyWaitM(TMicro,13) as PXA27xBusyWaitMicro;\r
- components HplPXA27xOSTimerC;\r
-\r
- BusyWaitMicro16 = PXA27xBusyWaitMicro.BusyWait;\r
-\r
- PXA27xBusyWaitMicro.OST -> HplPXA27xOSTimerC.OST0;\r
-}\r
-\r
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * Implements the BusyWaitMicroC timer component. This component
+ * instantiates a new Counter with Microsecond precision and
+ * binds it to the BusyWait interface via PXA27xBusyWaitP
+ *
+ * @author Phil Buonadonna
+ */
+configuration BusyWaitMicroC
+{
+ provides interface BusyWait<TMicro,uint16_t> as BusyWaitMicro16;
+}
+
+implementation
+{
+ components new HalPXA27xBusyWaitM(TMicro,13) as PXA27xBusyWaitMicro;
+ components HplPXA27xOSTimerC;
+
+ BusyWaitMicro16 = PXA27xBusyWaitMicro.BusyWait;
+
+ PXA27xBusyWaitMicro.OST -> HplPXA27xOSTimerC.OST0;
+}
+
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/** \r
- * @author Phil Buonadonna\r
- *\r
- */\r
-\r
-configuration Counter32khzC\r
-{\r
- provides interface Counter<T32khz,uint32_t> as Counter32khz32;\r
- provides interface LocalTime<T32khz> as LocalTime32khz;\r
-}\r
-\r
-implementation\r
-{\r
- components new HalPXA27xCounterM(T32khz,1) as PhysCounter32khz32;\r
- components HalPXA27xOSTimerMapC;\r
- components PlatformP;\r
-\r
- enum {OST_CLIENT_ID = unique("PXA27xOSTimer.Resource")};\r
-\r
- Counter32khz32 = PhysCounter32khz32.Counter;\r
- LocalTime32khz = PhysCounter32khz32.LocalTime;\r
-\r
- // Wire the initialization to the platform init routine\r
- PlatformP.InitL0 -> PhysCounter32khz32.Init;\r
-\r
- PhysCounter32khz32.OSTInit -> HalPXA27xOSTimerMapC.Init;\r
- PhysCounter32khz32.OSTChnl -> HalPXA27xOSTimerMapC.OSTChnl[OST_CLIENT_ID];\r
-}\r
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * @author Phil Buonadonna
+ *
+ */
+
+configuration Counter32khzC
+{
+ provides interface Counter<T32khz,uint32_t> as Counter32khz32;
+ provides interface LocalTime<T32khz> as LocalTime32khz;
+}
+
+implementation
+{
+ components new HalPXA27xCounterM(T32khz,1) as PhysCounter32khz32;
+ components HalPXA27xOSTimerMapC;
+ components PlatformP;
+
+ enum {OST_CLIENT_ID = unique("PXA27xOSTimer.Resource")};
+
+ Counter32khz32 = PhysCounter32khz32.Counter;
+ LocalTime32khz = PhysCounter32khz32.LocalTime;
+
+ // Wire the initialization to the platform init routine
+ PlatformP.InitL0 -> PhysCounter32khz32.Init;
+
+ PhysCounter32khz32.OSTInit -> HalPXA27xOSTimerMapC.Init;
+ PhysCounter32khz32.OSTChnl -> HalPXA27xOSTimerMapC.OSTChnl[OST_CLIENT_ID];
+}
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/** \r
- * @author Phil Buonadonna\r
- *\r
- */\r
-\r
-configuration CounterMilliC\r
-{\r
- provides interface Counter<TMilli,uint32_t> as CounterMilli32;\r
- provides interface LocalTime<TMilli> as LocalTimeMilli;\r
-}\r
-\r
-implementation\r
-{\r
- components new HalPXA27xCounterM(TMilli,2) as PhysCounterMilli32;\r
- components HalPXA27xOSTimerMapC;\r
- components PlatformP;\r
-\r
- enum {OST_CLIENT_ID = unique("PXA27xOSTimer.Resource")};\r
-\r
- CounterMilli32 = PhysCounterMilli32.Counter;\r
- LocalTimeMilli = PhysCounterMilli32.LocalTime;\r
-\r
- // Wire the initialization to the plaform init routine\r
- PlatformP.InitL0 -> PhysCounterMilli32.Init;\r
-\r
- PhysCounterMilli32.OSTInit -> HalPXA27xOSTimerMapC.Init;\r
- PhysCounterMilli32.OSTChnl -> HalPXA27xOSTimerMapC.OSTChnl[OST_CLIENT_ID];\r
-}\r
-\r
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * @author Phil Buonadonna
+ *
+ */
+
+configuration CounterMilliC
+{
+ provides interface Counter<TMilli,uint32_t> as CounterMilli32;
+ provides interface LocalTime<TMilli> as LocalTimeMilli;
+}
+
+implementation
+{
+ components new HalPXA27xCounterM(TMilli,2) as PhysCounterMilli32;
+ components HalPXA27xOSTimerMapC;
+ components PlatformP;
+
+ enum {OST_CLIENT_ID = unique("PXA27xOSTimer.Resource")};
+
+ CounterMilli32 = PhysCounterMilli32.Counter;
+ LocalTimeMilli = PhysCounterMilli32.LocalTime;
+
+ // Wire the initialization to the plaform init routine
+ PlatformP.InitL0 -> PhysCounterMilli32.Init;
+
+ PhysCounterMilli32.OSTInit -> HalPXA27xOSTimerMapC.Init;
+ PhysCounterMilli32.OSTChnl -> HalPXA27xOSTimerMapC.OSTChnl[OST_CLIENT_ID];
+}
+
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/** \r
- * @author Phil Buonadonna\r
- *\r
- */\r
-\r
-// @author Phil Buonadonna\r
-\r
-#include "Timer.h"\r
-\r
-generic module HalPXA27xAlarmM(typedef frequency_tag, uint8_t resolution) \r
-{\r
- provides {\r
- interface Init;\r
- interface Alarm<frequency_tag,uint32_t> as Alarm;\r
- }\r
- uses {\r
- interface Init as OSTInit;\r
- interface HplPXA27xOSTimer as OSTChnl;\r
- }\r
-}\r
-\r
-implementation\r
-{\r
- bool mfRunning;\r
- uint32_t mMinDeltaT;\r
-\r
- task void lateAlarm() {\r
- atomic {\r
- mfRunning = FALSE;\r
- signal Alarm.fired();\r
- }\r
- }\r
- \r
- command error_t Init.init() {\r
-\r
- call OSTInit.init(); \r
- // Continue on match, Non-periodic, w/ given resolution\r
- atomic {\r
- mfRunning = FALSE;\r
- switch (resolution) {\r
- case 1: // 1/32768 second\r
- mMinDeltaT = 10;\r
- break;\r
- case 2: // 1 ms\r
- mMinDeltaT = 1;\r
- break;\r
- case 3: // 1 s\r
- mMinDeltaT = 1;\r
- break;\r
- case 4: // 1 us\r
- mMinDeltaT = 300;\r
- break;\r
- default: // External\r
- mMinDeltaT = 0;\r
- break;\r
- }\r
- call OSTChnl.setOMCR(OMCR_C | OMCR_P | OMCR_CRES(resolution));\r
- call OSTChnl.setOSCR(0);\r
- }\r
- return SUCCESS;\r
-\r
- }\r
-\r
- async command void Alarm.start( uint32_t dt ) {\r
- uint32_t t0,t1,tf;\r
- //uint32_t cycles;\r
- bool bPending;\r
- if (dt < mMinDeltaT) dt = mMinDeltaT;\r
-\r
- atomic {\r
- //_pxa27x_perf_clear();\r
- t0 = call OSTChnl.getOSCR();\r
- tf = t0 + dt;\r
- call OSTChnl.setOIERbit(TRUE);\r
- call OSTChnl.setOSMR(tf);\r
- //_pxa27x_perf_get(cycles);\r
- mfRunning = TRUE;\r
- t1 = call OSTChnl.getOSCR();\r
- bPending = call OSTChnl.getOSSRbit();\r
- if ((dt <= (t1 - t0)) && !(bPending)) {\r
- call OSTChnl.setOIERbit(FALSE);\r
- post lateAlarm();\r
- }\r
- }\r
- return;\r
- }\r
-\r
- async command void Alarm.stop() {\r
- atomic {\r
- call OSTChnl.setOIERbit(FALSE);\r
- mfRunning = FALSE;\r
- }\r
- return;\r
- }\r
-\r
- async command bool Alarm.isRunning() {\r
- bool flag;\r
-\r
- atomic flag = mfRunning;\r
- return flag;\r
- }\r
-\r
- async command void Alarm.startAt( uint32_t t0, uint32_t dt ) {\r
- uint32_t tf,t1;\r
- bool bPending;\r
- tf = t0 + dt;\r
-\r
- atomic {\r
- call OSTChnl.setOIERbit(TRUE);\r
- call OSTChnl.setOSMR(tf);\r
- mfRunning = TRUE;\r
- t1 = call OSTChnl.getOSCR();\r
- bPending = call OSTChnl.getOSSRbit();\r
- if ((dt <= (t1 - t0)) && !(bPending)) {\r
- call OSTChnl.setOIERbit(FALSE);\r
- post lateAlarm();\r
- }\r
- }\r
-\r
- return;\r
- } \r
-\r
- async command uint32_t Alarm.getNow() {\r
- return call OSTChnl.getOSCR();\r
- }\r
-\r
- async command uint32_t Alarm.getAlarm() {\r
- return call OSTChnl.getOSMR();\r
- }\r
-\r
- async event void OSTChnl.fired() {\r
- call OSTChnl.clearOSSRbit();\r
- call OSTChnl.setOIERbit(FALSE);\r
- mfRunning = FALSE;\r
- signal Alarm.fired();\r
- return;\r
- }\r
-\r
- default async event void Alarm.fired() {\r
- return;\r
- }\r
-\r
-\r
-}\r
-\r
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * @author Phil Buonadonna
+ *
+ */
+
+// @author Phil Buonadonna
+
+#include "Timer.h"
+
+generic module HalPXA27xAlarmM(typedef frequency_tag, uint8_t resolution)
+{
+ provides {
+ interface Init;
+ interface Alarm<frequency_tag,uint32_t> as Alarm;
+ }
+ uses {
+ interface Init as OSTInit;
+ interface HplPXA27xOSTimer as OSTChnl;
+ }
+}
+
+implementation
+{
+ bool mfRunning;
+ uint32_t mMinDeltaT;
+
+ task void lateAlarm() {
+ atomic {
+ mfRunning = FALSE;
+ signal Alarm.fired();
+ }
+ }
+
+ command error_t Init.init() {
+
+ call OSTInit.init();
+ // Continue on match, Non-periodic, w/ given resolution
+ atomic {
+ mfRunning = FALSE;
+ switch (resolution) {
+ case 1: // 1/32768 second
+ mMinDeltaT = 10;
+ break;
+ case 2: // 1 ms
+ mMinDeltaT = 1;
+ break;
+ case 3: // 1 s
+ mMinDeltaT = 1;
+ break;
+ case 4: // 1 us
+ mMinDeltaT = 300;
+ break;
+ default: // External
+ mMinDeltaT = 0;
+ break;
+ }
+ call OSTChnl.setOMCR(OMCR_C | OMCR_P | OMCR_CRES(resolution));
+ call OSTChnl.setOSCR(0);
+ }
+ return SUCCESS;
+
+ }
+
+ async command void Alarm.start( uint32_t dt ) {
+ uint32_t t0,t1,tf;
+ //uint32_t cycles;
+ bool bPending;
+ if (dt < mMinDeltaT) dt = mMinDeltaT;
+
+ atomic {
+ //_pxa27x_perf_clear();
+ t0 = call OSTChnl.getOSCR();
+ tf = t0 + dt;
+ call OSTChnl.setOIERbit(TRUE);
+ call OSTChnl.setOSMR(tf);
+ //_pxa27x_perf_get(cycles);
+ mfRunning = TRUE;
+ t1 = call OSTChnl.getOSCR();
+ bPending = call OSTChnl.getOSSRbit();
+ if ((dt <= (t1 - t0)) && !(bPending)) {
+ call OSTChnl.setOIERbit(FALSE);
+ post lateAlarm();
+ }
+ }
+ return;
+ }
+
+ async command void Alarm.stop() {
+ atomic {
+ call OSTChnl.setOIERbit(FALSE);
+ mfRunning = FALSE;
+ }
+ return;
+ }
+
+ async command bool Alarm.isRunning() {
+ bool flag;
+
+ atomic flag = mfRunning;
+ return flag;
+ }
+
+ async command void Alarm.startAt( uint32_t t0, uint32_t dt ) {
+ uint32_t tf,t1;
+ bool bPending;
+ tf = t0 + dt;
+
+ atomic {
+ call OSTChnl.setOIERbit(TRUE);
+ call OSTChnl.setOSMR(tf);
+ mfRunning = TRUE;
+ t1 = call OSTChnl.getOSCR();
+ bPending = call OSTChnl.getOSSRbit();
+ if ((dt <= (t1 - t0)) && !(bPending)) {
+ call OSTChnl.setOIERbit(FALSE);
+ post lateAlarm();
+ }
+ }
+
+ return;
+ }
+
+ async command uint32_t Alarm.getNow() {
+ return call OSTChnl.getOSCR();
+ }
+
+ async command uint32_t Alarm.getAlarm() {
+ return call OSTChnl.getOSMR();
+ }
+
+ async event void OSTChnl.fired() {
+ call OSTChnl.clearOSSRbit();
+ call OSTChnl.setOIERbit(FALSE);
+ mfRunning = FALSE;
+ signal Alarm.fired();
+ return;
+ }
+
+ default async event void Alarm.fired() {
+ return;
+ }
+
+
+}
+
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/** \r
- * This private component provides a 16-bit BusyWait interface\r
- * of a given precision over OS Timer channel 0\r
- *\r
- * @param precision_tag A type tag mapped to the set precision\r
- *\r
- * @param val4xScale A value to scale the underlying counter by. \r
- * The passed in parameter is given by the equation\r
- * val4xScale = (3.25 MHz/<desired_precision_in_Hz>) * 4\r
- * and rounded to the nearest integer.\r
- * Example: Counter precision of 32.768 kHz would have \r
- * a val4xScale of 397\r
- * \r
- * @author Phil Buonadonna\r
- *\r
- */\r
-\r
-generic module HalPXA27xBusyWaitM(typedef precision_tag, uint16_t val4xScale)\r
-{\r
- provides interface BusyWait<precision_tag,uint16_t>;\r
- uses interface HplPXA27xOSTimer as OST;\r
-}\r
-\r
-implementation\r
-{\r
-\r
- async command void BusyWait.wait(uint16_t dt) {\r
- uint32_t dCounts;\r
- atomic {\r
- uint32_t t0 = call OST.getOSCR();\r
- dCounts = (dt * 4) * val4xScale;\r
- dCounts >>= 2;\r
- while (((call OST.getOSCR()) - t0) < dCounts);\r
- }\r
- }\r
-\r
- async event void OST.fired() {\r
- return;\r
- }\r
-\r
-}\r
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * This private component provides a 16-bit BusyWait interface
+ * of a given precision over OS Timer channel 0
+ *
+ * @param precision_tag A type tag mapped to the set precision
+ *
+ * @param val4xScale A value to scale the underlying counter by.
+ * The passed in parameter is given by the equation
+ * val4xScale = (3.25 MHz/<desired_precision_in_Hz>) * 4
+ * and rounded to the nearest integer.
+ * Example: Counter precision of 32.768 kHz would have
+ * a val4xScale of 397
+ *
+ * @author Phil Buonadonna
+ *
+ */
+
+generic module HalPXA27xBusyWaitM(typedef precision_tag, uint16_t val4xScale)
+{
+ provides interface BusyWait<precision_tag,uint16_t>;
+ uses interface HplPXA27xOSTimer as OST;
+}
+
+implementation
+{
+
+ async command void BusyWait.wait(uint16_t dt) {
+ uint32_t dCounts;
+ atomic {
+ uint32_t t0 = call OST.getOSCR();
+ dCounts = (dt * 4) * val4xScale;
+ dCounts >>= 2;
+ while (((call OST.getOSCR()) - t0) < dCounts);
+ }
+ }
+
+ async event void OST.fired() {
+ return;
+ }
+
+}
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-\r
-/** \r
- * Implements a TOS 2.0 Counter on the PXA27x HPL. The PXA27x does not \r
- * have an explicit overflow notification. We emulate one by using \r
- * the associated match register set to 0. This requires we initialize\r
- * the counter to 1 to avoid a false notification at startup.\r
- * \r
- * @author Phil Buonadonna\r
- */\r
-#include "Timer.h"\r
-\r
-generic module HalPXA27xCounterM(typedef frequency_tag, uint8_t resolution) \r
-{\r
- provides {\r
- interface Init;\r
- interface Counter<frequency_tag,uint32_t> as Counter;\r
- interface LocalTime<frequency_tag> as LocalTime;\r
- }\r
- uses {\r
- interface Init as OSTInit;\r
- interface HplPXA27xOSTimer as OSTChnl;\r
- }\r
-}\r
-\r
-implementation\r
-{\r
- command error_t Init.init() {\r
-\r
- call OSTInit.init(); \r
-\r
- // Continue on match, Non-periodic, w/ given resolution\r
- atomic {\r
- call OSTChnl.setOMCR(OMCR_C | OMCR_P | OMCR_CRES(resolution));\r
- call OSTChnl.setOSMR(0);\r
- call OSTChnl.setOSCR(1);\r
- call OSTChnl.clearOSSRbit();\r
- call OSTChnl.setOIERbit(TRUE);\r
- }\r
- return SUCCESS;\r
-\r
- }\r
- \r
- async command uint32_t Counter.get() {\r
- uint32_t cntr;\r
-\r
- cntr = call OSTChnl.getOSCR();\r
- return cntr;\r
- }\r
-\r
- async command bool Counter.isOverflowPending() {\r
- bool flag;\r
-\r
- atomic flag = call OSTChnl.getOSSRbit();\r
- return flag;\r
- }\r
-\r
- async command void Counter.clearOverflow() {\r
-\r
- atomic call OSTChnl.clearOSSRbit();\r
- }\r
-\r
- async event void OSTChnl.fired() {\r
- call OSTChnl.clearOSSRbit();\r
- signal Counter.overflow();\r
- return;\r
- }\r
-\r
- async command uint32_t LocalTime.get() {\r
- uint32_t cntr;\r
-\r
- cntr = call OSTChnl.getOSCR();\r
- return cntr;\r
- }\r
-\r
- default async event void Counter.overflow() {\r
- return;\r
- }\r
-\r
-}\r
-\r
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+
+/**
+ * Implements a TOS 2.0 Counter on the PXA27x HPL. The PXA27x does not
+ * have an explicit overflow notification. We emulate one by using
+ * the associated match register set to 0. This requires we initialize
+ * the counter to 1 to avoid a false notification at startup.
+ *
+ * @author Phil Buonadonna
+ */
+#include "Timer.h"
+
+generic module HalPXA27xCounterM(typedef frequency_tag, uint8_t resolution)
+{
+ provides {
+ interface Init;
+ interface Counter<frequency_tag,uint32_t> as Counter;
+ interface LocalTime<frequency_tag> as LocalTime;
+ }
+ uses {
+ interface Init as OSTInit;
+ interface HplPXA27xOSTimer as OSTChnl;
+ }
+}
+
+implementation
+{
+ command error_t Init.init() {
+
+ call OSTInit.init();
+
+ // Continue on match, Non-periodic, w/ given resolution
+ atomic {
+ call OSTChnl.setOMCR(OMCR_C | OMCR_P | OMCR_CRES(resolution));
+ call OSTChnl.setOSMR(0);
+ call OSTChnl.setOSCR(1);
+ call OSTChnl.clearOSSRbit();
+ call OSTChnl.setOIERbit(TRUE);
+ }
+ return SUCCESS;
+
+ }
+
+ async command uint32_t Counter.get() {
+ uint32_t cntr;
+
+ cntr = call OSTChnl.getOSCR();
+ return cntr;
+ }
+
+ async command bool Counter.isOverflowPending() {
+ bool flag;
+
+ atomic flag = call OSTChnl.getOSSRbit();
+ return flag;
+ }
+
+ async command void Counter.clearOverflow() {
+
+ atomic call OSTChnl.clearOSSRbit();
+ }
+
+ async event void OSTChnl.fired() {
+ call OSTChnl.clearOSSRbit();
+ signal Counter.overflow();
+ return;
+ }
+
+ async command uint32_t LocalTime.get() {
+ uint32_t cntr;
+
+ cntr = call OSTChnl.getOSCR();
+ return cntr;
+ }
+
+ default async event void Counter.overflow() {
+ return;
+ }
+
+}
+
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/** \r
- * This components maps requested timer resources connected using the\r
- * 'PXA27xOSTimer.Resource' flag to physical timer resource of the PXA27x.\r
- * \r
- * @author Phil Buonadonna\r
- *\r
- */\r
-\r
-configuration HalPXA27xOSTimerMapC {\r
-\r
- provides {\r
- interface Init;\r
- interface HplPXA27xOSTimer as OSTChnl[uint8_t id];\r
- }\r
-}\r
-\r
-implementation {\r
- components HplPXA27xOSTimerC;\r
-\r
- Init = HplPXA27xOSTimerC;\r
-\r
- OSTChnl[0] = HplPXA27xOSTimerC.OST4;\r
- OSTChnl[1] = HplPXA27xOSTimerC.OST5;\r
- OSTChnl[2] = HplPXA27xOSTimerC.OST6;\r
- OSTChnl[3] = HplPXA27xOSTimerC.OST7;\r
- OSTChnl[4] = HplPXA27xOSTimerC.OST8;\r
- OSTChnl[5] = HplPXA27xOSTimerC.OST9;\r
- OSTChnl[6] = HplPXA27xOSTimerC.OST10;\r
- OSTChnl[7] = HplPXA27xOSTimerC.OST11;\r
-\r
-}\r
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * This components maps requested timer resources connected using the
+ * 'PXA27xOSTimer.Resource' flag to physical timer resource of the PXA27x.
+ *
+ * @author Phil Buonadonna
+ *
+ */
+
+configuration HalPXA27xOSTimerMapC {
+
+ provides {
+ interface Init;
+ interface HplPXA27xOSTimer as OSTChnl[uint8_t id];
+ }
+}
+
+implementation {
+ components HplPXA27xOSTimerC;
+
+ Init = HplPXA27xOSTimerC;
+
+ OSTChnl[0] = HplPXA27xOSTimerC.OST4;
+ OSTChnl[1] = HplPXA27xOSTimerC.OST5;
+ OSTChnl[2] = HplPXA27xOSTimerC.OST6;
+ OSTChnl[3] = HplPXA27xOSTimerC.OST7;
+ OSTChnl[4] = HplPXA27xOSTimerC.OST8;
+ OSTChnl[5] = HplPXA27xOSTimerC.OST9;
+ OSTChnl[6] = HplPXA27xOSTimerC.OST10;
+ OSTChnl[7] = HplPXA27xOSTimerC.OST11;
+
+}
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * This interface exposes a single OS Timer channel \r
- * on the PXA27x processor. Each channel includes a counter register \r
- * (OSCRx), a match register (OSMRx), a match control register (OMCRx) \r
- * and support for events on each channel. \r
- *\r
- * Do not confuse this HPL interface with the generic 'Timer' interface \r
- * provided by TOS 2.x. They are completely different.\r
- *\r
- * Channels 0 thru 3 are the PXA25x compatibility timers. There are NO\r
- * match control register for these channels. \r
- * Calls to getOSCR/setOSCR for channels 1 thru 3 are remmaped to OSCR0.\r
- * \r
- * There may be additional configured inter-dependencies between the timer\r
- * channels. Refer to the PXA27x Developer's Guide for more information.\r
- *\r
- * @author Phil Buonadonna\r
- */\r
-\r
-interface HplPXA27xOSTimer\r
-{\r
- /**\r
- * Set/initialize the counter register (OSCRx) for the channel\r
- *\r
- * @param val Desired value to initialize/reset the counter register to.\r
- * \r
- */\r
- async command void setOSCR(uint32_t val);\r
-\r
- /**\r
- * Get the current counter register (OSCRx) value for the channel.\r
- *\r
- * @return value The 32-bit value of the counter register.\r
- */\r
- async command uint32_t getOSCR();\r
-\r
- /**\r
- * Set the match register (OSMRx) for the channel.\r
- *\r
- * @param val The desired 32-bit match value.\r
- */\r
- async command void setOSMR(uint32_t val);\r
-\r
- /**\r
- * Get the current match register (OSMRx) value for the channel.\r
- *\r
- * @return value The 32-bit value of the match register.\r
- */\r
- async command uint32_t getOSMR();\r
-\r
- /**\r
- * Set the timer channel match control register (OMCRx).\r
- * \r
- * @param val The desired OMCR value.\r
- */\r
- async command void setOMCR(uint32_t val);\r
-\r
- /**\r
- * Get the current channel match control register (OMCRx) setting.\r
- * \r
- * @return value The current OMCR value.\r
- */\r
- async command uint32_t getOMCR();\r
-\r
- /**\r
- * Returns the bit value of the OSSR register corresponding to the \r
- * channel. Indicates if a match event has ocurred.\r
- *\r
- * @return flag TRUE if an event is signaled (OSSR.M{n} is set). \r
- * FALSE otherwise \r
- * \r
- *\r
- */\r
- async command bool getOSSRbit();\r
-\r
- /**\r
- * Clears the bit position of the OSSR register corresponding to the\r
- * channel. Returns the value of the bit before clearing.\r
- *\r
- * @return flag TRUE if an event is signaled (OSSR.M{n} set) prior \r
- * to clearing. FALSE otherwise.\r
- */\r
- async command bool clearOSSRbit();\r
-\r
- /**\r
- * Sets the OIER bit corresponding to the timer match channel.\r
- *\r
- * @param flag TRUE to set the OIER bit, FALSE to clear.\r
- */\r
- async command void setOIERbit(bool flag);\r
-\r
- /**\r
- * Returns the setting of the OIER bit corresponding to the timer\r
- * match channel.\r
- * \r
- * @return flag TRUE if set, FALSE if not set.\r
- */\r
- async command bool getOIERbit();\r
-\r
- /** \r
- * Get the snapshot register (OSNR) value. \r
- * Any parameterization of this function is ignored.\r
- */\r
- async command uint32_t getOSNR();\r
-\r
- /**\r
- * Timer channel interrupt. Fired when the channel match register matches \r
- * configured \r
- */\r
- async event void fired();\r
-\r
-}\r
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * This interface exposes a single OS Timer channel
+ * on the PXA27x processor. Each channel includes a counter register
+ * (OSCRx), a match register (OSMRx), a match control register (OMCRx)
+ * and support for events on each channel.
+ *
+ * Do not confuse this HPL interface with the generic 'Timer' interface
+ * provided by TOS 2.x. They are completely different.
+ *
+ * Channels 0 thru 3 are the PXA25x compatibility timers. There are NO
+ * match control register for these channels.
+ * Calls to getOSCR/setOSCR for channels 1 thru 3 are remmaped to OSCR0.
+ *
+ * There may be additional configured inter-dependencies between the timer
+ * channels. Refer to the PXA27x Developer's Guide for more information.
+ *
+ * @author Phil Buonadonna
+ */
+
+interface HplPXA27xOSTimer
+{
+ /**
+ * Set/initialize the counter register (OSCRx) for the channel
+ *
+ * @param val Desired value to initialize/reset the counter register to.
+ *
+ */
+ async command void setOSCR(uint32_t val);
+
+ /**
+ * Get the current counter register (OSCRx) value for the channel.
+ *
+ * @return value The 32-bit value of the counter register.
+ */
+ async command uint32_t getOSCR();
+
+ /**
+ * Set the match register (OSMRx) for the channel.
+ *
+ * @param val The desired 32-bit match value.
+ */
+ async command void setOSMR(uint32_t val);
+
+ /**
+ * Get the current match register (OSMRx) value for the channel.
+ *
+ * @return value The 32-bit value of the match register.
+ */
+ async command uint32_t getOSMR();
+
+ /**
+ * Set the timer channel match control register (OMCRx).
+ *
+ * @param val The desired OMCR value.
+ */
+ async command void setOMCR(uint32_t val);
+
+ /**
+ * Get the current channel match control register (OMCRx) setting.
+ *
+ * @return value The current OMCR value.
+ */
+ async command uint32_t getOMCR();
+
+ /**
+ * Returns the bit value of the OSSR register corresponding to the
+ * channel. Indicates if a match event has ocurred.
+ *
+ * @return flag TRUE if an event is signaled (OSSR.M{n} is set).
+ * FALSE otherwise
+ *
+ *
+ */
+ async command bool getOSSRbit();
+
+ /**
+ * Clears the bit position of the OSSR register corresponding to the
+ * channel. Returns the value of the bit before clearing.
+ *
+ * @return flag TRUE if an event is signaled (OSSR.M{n} set) prior
+ * to clearing. FALSE otherwise.
+ */
+ async command bool clearOSSRbit();
+
+ /**
+ * Sets the OIER bit corresponding to the timer match channel.
+ *
+ * @param flag TRUE to set the OIER bit, FALSE to clear.
+ */
+ async command void setOIERbit(bool flag);
+
+ /**
+ * Returns the setting of the OIER bit corresponding to the timer
+ * match channel.
+ *
+ * @return flag TRUE if set, FALSE if not set.
+ */
+ async command bool getOIERbit();
+
+ /**
+ * Get the snapshot register (OSNR) value.
+ * Any parameterization of this function is ignored.
+ */
+ async command uint32_t getOSNR();
+
+ /**
+ * Timer channel interrupt. Fired when the channel match register matches
+ * configured
+ */
+ async event void fired();
+
+}
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/** \r
- * @author Phil Buonadonna\r
- *\r
- */\r
-\r
-configuration HplPXA27xOSTimerC {\r
-\r
- provides {\r
- interface Init;\r
- interface HplPXA27xOSTimer as OST0;\r
- interface HplPXA27xOSTimer as OST0M1;\r
- interface HplPXA27xOSTimer as OST0M2;\r
- interface HplPXA27xOSTimer as OST0M3;\r
- interface HplPXA27xOSTimer as OST4;\r
- interface HplPXA27xOSTimer as OST5;\r
- interface HplPXA27xOSTimer as OST6;\r
- interface HplPXA27xOSTimer as OST7;\r
- interface HplPXA27xOSTimer as OST8;\r
- interface HplPXA27xOSTimer as OST9;\r
- interface HplPXA27xOSTimer as OST10;\r
- interface HplPXA27xOSTimer as OST11;\r
- interface HplPXA27xOSTimerWatchdog as OSTWDCntl;\r
- }\r
-\r
-}\r
-\r
-implementation {\r
- components HplPXA27xOSTimerM, HplPXA27xInterruptM;\r
-\r
- Init = HplPXA27xOSTimerM;\r
-\r
- OST0 = HplPXA27xOSTimerM.PXA27xOST[0];\r
- OST0M1 = HplPXA27xOSTimerM.PXA27xOST[1];\r
- OST0M2 = HplPXA27xOSTimerM.PXA27xOST[2];\r
- OST0M3 = HplPXA27xOSTimerM.PXA27xOST[3];\r
- OST4 = HplPXA27xOSTimerM.PXA27xOST[4];\r
- OST5 = HplPXA27xOSTimerM.PXA27xOST[5];\r
- OST6 = HplPXA27xOSTimerM.PXA27xOST[6];\r
- OST7 = HplPXA27xOSTimerM.PXA27xOST[7];\r
- OST8 = HplPXA27xOSTimerM.PXA27xOST[8];\r
- OST9 = HplPXA27xOSTimerM.PXA27xOST[9];\r
- OST10 = HplPXA27xOSTimerM.PXA27xOST[10];\r
- OST11 = HplPXA27xOSTimerM.PXA27xOST[11];\r
- OSTWDCntl = HplPXA27xOSTimerM.PXA27xWD;\r
- \r
- HplPXA27xOSTimerM.OST0Irq -> HplPXA27xInterruptM.PXA27xIrq[PPID_OST_0];\r
- HplPXA27xOSTimerM.OST1Irq -> HplPXA27xInterruptM.PXA27xIrq[PPID_OST_1];\r
- HplPXA27xOSTimerM.OST2Irq -> HplPXA27xInterruptM.PXA27xIrq[PPID_OST_2];\r
- HplPXA27xOSTimerM.OST3Irq -> HplPXA27xInterruptM.PXA27xIrq[PPID_OST_3];\r
- HplPXA27xOSTimerM.OST4_11Irq -> HplPXA27xInterruptM.PXA27xIrq[PPID_OST_4_11];\r
-}\r
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * @author Phil Buonadonna
+ *
+ */
+
+configuration HplPXA27xOSTimerC {
+
+ provides {
+ interface Init;
+ interface HplPXA27xOSTimer as OST0;
+ interface HplPXA27xOSTimer as OST0M1;
+ interface HplPXA27xOSTimer as OST0M2;
+ interface HplPXA27xOSTimer as OST0M3;
+ interface HplPXA27xOSTimer as OST4;
+ interface HplPXA27xOSTimer as OST5;
+ interface HplPXA27xOSTimer as OST6;
+ interface HplPXA27xOSTimer as OST7;
+ interface HplPXA27xOSTimer as OST8;
+ interface HplPXA27xOSTimer as OST9;
+ interface HplPXA27xOSTimer as OST10;
+ interface HplPXA27xOSTimer as OST11;
+ interface HplPXA27xOSTimerWatchdog as OSTWDCntl;
+ }
+
+}
+
+implementation {
+ components HplPXA27xOSTimerM, HplPXA27xInterruptM;
+
+ Init = HplPXA27xOSTimerM;
+
+ OST0 = HplPXA27xOSTimerM.PXA27xOST[0];
+ OST0M1 = HplPXA27xOSTimerM.PXA27xOST[1];
+ OST0M2 = HplPXA27xOSTimerM.PXA27xOST[2];
+ OST0M3 = HplPXA27xOSTimerM.PXA27xOST[3];
+ OST4 = HplPXA27xOSTimerM.PXA27xOST[4];
+ OST5 = HplPXA27xOSTimerM.PXA27xOST[5];
+ OST6 = HplPXA27xOSTimerM.PXA27xOST[6];
+ OST7 = HplPXA27xOSTimerM.PXA27xOST[7];
+ OST8 = HplPXA27xOSTimerM.PXA27xOST[8];
+ OST9 = HplPXA27xOSTimerM.PXA27xOST[9];
+ OST10 = HplPXA27xOSTimerM.PXA27xOST[10];
+ OST11 = HplPXA27xOSTimerM.PXA27xOST[11];
+ OSTWDCntl = HplPXA27xOSTimerM.PXA27xWD;
+
+ HplPXA27xOSTimerM.OST0Irq -> HplPXA27xInterruptM.PXA27xIrq[PPID_OST_0];
+ HplPXA27xOSTimerM.OST1Irq -> HplPXA27xInterruptM.PXA27xIrq[PPID_OST_1];
+ HplPXA27xOSTimerM.OST2Irq -> HplPXA27xInterruptM.PXA27xIrq[PPID_OST_2];
+ HplPXA27xOSTimerM.OST3Irq -> HplPXA27xInterruptM.PXA27xIrq[PPID_OST_3];
+ HplPXA27xOSTimerM.OST4_11Irq -> HplPXA27xInterruptM.PXA27xIrq[PPID_OST_4_11];
+}
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/** \r
- * @author Phil Buonadonna\r
- *\r
- */\r
-\r
-\r
-module HplPXA27xOSTimerM {\r
- provides {\r
- interface Init;\r
- interface HplPXA27xOSTimer as PXA27xOST[uint8_t chnl_id];\r
- interface HplPXA27xOSTimerWatchdog as PXA27xWD;\r
- }\r
- uses {\r
- interface HplPXA27xInterrupt as OST0Irq;\r
- interface HplPXA27xInterrupt as OST1Irq;\r
- interface HplPXA27xInterrupt as OST2Irq;\r
- interface HplPXA27xInterrupt as OST3Irq;\r
- interface HplPXA27xInterrupt as OST4_11Irq;\r
- }\r
-}\r
-\r
-implementation {\r
-\r
- bool gfInitialized = FALSE;\r
-\r
- void DispatchOSTInterrupt(uint8_t id)\r
- {\r
- signal PXA27xOST.fired[id]();\r
- return;\r
- }\r
-\r
- command error_t Init.init()\r
- {\r
- bool initflag;\r
- atomic {\r
- initflag = gfInitialized;\r
- gfInitialized = TRUE;\r
- }\r
- \r
- if (!initflag) {\r
- OIER = 0x0UL;\r
- OSSR = 0xFFFFFFFF; // Clear all status bits.\r
- call OST0Irq.allocate();\r
- call OST1Irq.allocate();\r
- call OST2Irq.allocate();\r
- call OST3Irq.allocate();\r
- call OST4_11Irq.allocate();\r
- call OST0Irq.enable();\r
- call OST1Irq.enable();\r
- call OST2Irq.enable();\r
- call OST3Irq.enable();\r
- call OST4_11Irq.enable();\r
- }\r
-\r
- return SUCCESS;\r
- }\r
- \r
- async command void PXA27xOST.setOSCR[uint8_t chnl_id](uint32_t val) \r
- {\r
- uint8_t remap_id;\r
-\r
- remap_id = ((chnl_id < 4) ? (0) : (chnl_id));\r
- OSCR(remap_id) = val;\r
-\r
- return;\r
- }\r
- \r
- async command uint32_t PXA27xOST.getOSCR[uint8_t chnl_id]()\r
- {\r
- uint8_t remap_id;\r
- uint32_t val;\r
-\r
- remap_id = ((chnl_id < 4) ? (0) : (chnl_id));\r
- val = OSCR(remap_id);\r
-\r
- return val;\r
- }\r
- \r
- async command void PXA27xOST.setOSMR[uint8_t chnl_id](uint32_t val)\r
- {\r
- OSMR(chnl_id) = val;\r
- return;\r
- }\r
-\r
- async command uint32_t PXA27xOST.getOSMR[uint8_t chnl_id]()\r
- {\r
- uint32_t val;\r
- val = OSMR(chnl_id);\r
- return val;\r
- }\r
-\r
- async command void PXA27xOST.setOMCR[uint8_t chnl_id](uint32_t val)\r
- {\r
- if (chnl_id > 3) {\r
- OMCR(chnl_id) = val;\r
- }\r
- return;\r
- }\r
-\r
- async command uint32_t PXA27xOST.getOMCR[uint8_t chnl_id]()\r
- {\r
- uint32_t val = 0;\r
- if (chnl_id > 3) {\r
- val = OMCR(chnl_id);\r
- }\r
- return val;\r
- }\r
-\r
- async command bool PXA27xOST.getOSSRbit[uint8_t chnl_id]() \r
- {\r
- bool bFlag = FALSE;\r
- \r
- if (((OSSR) & (1 << chnl_id)) != 0) {\r
- bFlag = TRUE;\r
- }\r
-\r
- return bFlag;\r
- }\r
-\r
- async command bool PXA27xOST.clearOSSRbit[uint8_t chnl_id]()\r
- {\r
- bool bFlag = FALSE;\r
-\r
- if (((OSSR) & (1 << chnl_id)) != 0) {\r
- bFlag = TRUE;\r
- }\r
-\r
- // Clear the bit value\r
- OSSR = (1 << chnl_id);\r
-\r
- return bFlag;\r
- }\r
-\r
- async command void PXA27xOST.setOIERbit[uint8_t chnl_id](bool flag)\r
- {\r
- if (flag == TRUE) {\r
- OIER |= (1 << chnl_id);\r
- }\r
- else {\r
- OIER &= ~(1 << chnl_id); \r
- }\r
- return;\r
- }\r
- \r
- async command bool PXA27xOST.getOIERbit[uint8_t chnl_id]()\r
- {\r
- return ((OIER & (1 << chnl_id)) != 0);\r
- }\r
-\r
- async command uint32_t PXA27xOST.getOSNR[uint8_t chnl_id]() \r
- {\r
- uint32_t val;\r
- val = OSNR;\r
- return val;\r
- }\r
-\r
- async command void PXA27xWD.enableWatchdog() \r
- {\r
- OWER = OWER_WME;\r
- }\r
-\r
-\r
- // All interrupts are funneled through DispatchOSTInterrupt.\r
- // This should not have any impact on performance and simplifies\r
- // the software implementation.\r
-\r
- async event void OST0Irq.fired() \r
- {\r
- DispatchOSTInterrupt(0);\r
- }\r
- \r
- async event void OST1Irq.fired() \r
- {\r
- DispatchOSTInterrupt(1);\r
- }\r
- \r
- async event void OST2Irq.fired() \r
- {\r
- DispatchOSTInterrupt(2);\r
- }\r
-\r
- async event void OST3Irq.fired() \r
- {\r
- DispatchOSTInterrupt(3);\r
- }\r
-\r
- async event void OST4_11Irq.fired() \r
- {\r
- uint32_t statusReg;\r
- uint8_t chnl;\r
-\r
- statusReg = OSSR;\r
- statusReg &= ~(OSSR_M3 | OSSR_M2 | OSSR_M1 | OSSR_M0);\r
-\r
- while (statusReg) {\r
- chnl = 31 - _pxa27x_clzui(statusReg);\r
- DispatchOSTInterrupt(chnl); \r
- statusReg &= ~(1 << chnl);\r
- }\r
- \r
- return;\r
- }\r
-\r
- default async event void PXA27xOST.fired[uint8_t chnl_id]() \r
- {\r
- call PXA27xOST.setOIERbit[chnl_id](FALSE);\r
- call PXA27xOST.clearOSSRbit[chnl_id]();\r
- return;\r
- }\r
-\r
-}\r
- \r
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * @author Phil Buonadonna
+ *
+ */
+
+
+module HplPXA27xOSTimerM {
+ provides {
+ interface Init;
+ interface HplPXA27xOSTimer as PXA27xOST[uint8_t chnl_id];
+ interface HplPXA27xOSTimerWatchdog as PXA27xWD;
+ }
+ uses {
+ interface HplPXA27xInterrupt as OST0Irq;
+ interface HplPXA27xInterrupt as OST1Irq;
+ interface HplPXA27xInterrupt as OST2Irq;
+ interface HplPXA27xInterrupt as OST3Irq;
+ interface HplPXA27xInterrupt as OST4_11Irq;
+ }
+}
+
+implementation {
+
+ bool gfInitialized = FALSE;
+
+ void DispatchOSTInterrupt(uint8_t id)
+ {
+ signal PXA27xOST.fired[id]();
+ return;
+ }
+
+ command error_t Init.init()
+ {
+ bool initflag;
+ atomic {
+ initflag = gfInitialized;
+ gfInitialized = TRUE;
+ }
+
+ if (!initflag) {
+ OIER = 0x0UL;
+ OSSR = 0xFFFFFFFF; // Clear all status bits.
+ call OST0Irq.allocate();
+ call OST1Irq.allocate();
+ call OST2Irq.allocate();
+ call OST3Irq.allocate();
+ call OST4_11Irq.allocate();
+ call OST0Irq.enable();
+ call OST1Irq.enable();
+ call OST2Irq.enable();
+ call OST3Irq.enable();
+ call OST4_11Irq.enable();
+ }
+
+ return SUCCESS;
+ }
+
+ async command void PXA27xOST.setOSCR[uint8_t chnl_id](uint32_t val)
+ {
+ uint8_t remap_id;
+
+ remap_id = ((chnl_id < 4) ? (0) : (chnl_id));
+ OSCR(remap_id) = val;
+
+ return;
+ }
+
+ async command uint32_t PXA27xOST.getOSCR[uint8_t chnl_id]()
+ {
+ uint8_t remap_id;
+ uint32_t val;
+
+ remap_id = ((chnl_id < 4) ? (0) : (chnl_id));
+ val = OSCR(remap_id);
+
+ return val;
+ }
+
+ async command void PXA27xOST.setOSMR[uint8_t chnl_id](uint32_t val)
+ {
+ OSMR(chnl_id) = val;
+ return;
+ }
+
+ async command uint32_t PXA27xOST.getOSMR[uint8_t chnl_id]()
+ {
+ uint32_t val;
+ val = OSMR(chnl_id);
+ return val;
+ }
+
+ async command void PXA27xOST.setOMCR[uint8_t chnl_id](uint32_t val)
+ {
+ if (chnl_id > 3) {
+ OMCR(chnl_id) = val;
+ }
+ return;
+ }
+
+ async command uint32_t PXA27xOST.getOMCR[uint8_t chnl_id]()
+ {
+ uint32_t val = 0;
+ if (chnl_id > 3) {
+ val = OMCR(chnl_id);
+ }
+ return val;
+ }
+
+ async command bool PXA27xOST.getOSSRbit[uint8_t chnl_id]()
+ {
+ bool bFlag = FALSE;
+
+ if (((OSSR) & (1 << chnl_id)) != 0) {
+ bFlag = TRUE;
+ }
+
+ return bFlag;
+ }
+
+ async command bool PXA27xOST.clearOSSRbit[uint8_t chnl_id]()
+ {
+ bool bFlag = FALSE;
+
+ if (((OSSR) & (1 << chnl_id)) != 0) {
+ bFlag = TRUE;
+ }
+
+ // Clear the bit value
+ OSSR = (1 << chnl_id);
+
+ return bFlag;
+ }
+
+ async command void PXA27xOST.setOIERbit[uint8_t chnl_id](bool flag)
+ {
+ if (flag == TRUE) {
+ OIER |= (1 << chnl_id);
+ }
+ else {
+ OIER &= ~(1 << chnl_id);
+ }
+ return;
+ }
+
+ async command bool PXA27xOST.getOIERbit[uint8_t chnl_id]()
+ {
+ return ((OIER & (1 << chnl_id)) != 0);
+ }
+
+ async command uint32_t PXA27xOST.getOSNR[uint8_t chnl_id]()
+ {
+ uint32_t val;
+ val = OSNR;
+ return val;
+ }
+
+ async command void PXA27xWD.enableWatchdog()
+ {
+ OWER = OWER_WME;
+ }
+
+
+ // All interrupts are funneled through DispatchOSTInterrupt.
+ // This should not have any impact on performance and simplifies
+ // the software implementation.
+
+ async event void OST0Irq.fired()
+ {
+ DispatchOSTInterrupt(0);
+ }
+
+ async event void OST1Irq.fired()
+ {
+ DispatchOSTInterrupt(1);
+ }
+
+ async event void OST2Irq.fired()
+ {
+ DispatchOSTInterrupt(2);
+ }
+
+ async event void OST3Irq.fired()
+ {
+ DispatchOSTInterrupt(3);
+ }
+
+ async event void OST4_11Irq.fired()
+ {
+ uint32_t statusReg;
+ uint8_t chnl;
+
+ statusReg = OSSR;
+ statusReg &= ~(OSSR_M3 | OSSR_M2 | OSSR_M1 | OSSR_M0);
+
+ while (statusReg) {
+ chnl = 31 - _pxa27x_clzui(statusReg);
+ DispatchOSTInterrupt(chnl);
+ statusReg &= ~(1 << chnl);
+ }
+
+ return;
+ }
+
+ default async event void PXA27xOST.fired[uint8_t chnl_id]()
+ {
+ call PXA27xOST.setOIERbit[chnl_id](FALSE);
+ call PXA27xOST.clearOSSRbit[chnl_id]();
+ return;
+ }
+
+}
+
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-\r
-/**\r
- * This interface exposes the watchdog control of the PXA27x OS Timer\r
- *\r
- * Refer to the PXA27x Developer's Guide for more information.\r
- *\r
- * @author Phil Buonadonna\r
- */\r
-\r
-interface HplPXA27xOSTimerWatchdog\r
-{\r
- /** \r
- * Enable the timer-based watchdog reset feature.\r
- * Once enabled, this feature may only be disabled by a reset.\r
- */\r
- async command void enableWatchdog();\r
-}\r
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+
+/**
+ * This interface exposes the watchdog control of the PXA27x OS Timer
+ *
+ * Refer to the PXA27x Developer's Guide for more information.
+ *
+ * @author Phil Buonadonna
+ */
+
+interface HplPXA27xOSTimerWatchdog
+{
+ /**
+ * Enable the timer-based watchdog reset feature.
+ * Once enabled, this feature may only be disabled by a reset.
+ */
+ async command void enableWatchdog();
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arch Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arch Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-\r
-/**\r
- * @author Phil Buonadonna\r
- */\r
-\r
-#include "pxa27x_serial.h"\r
-\r
-interface HalPXA27xSerialCntl\r
-{\r
- /** \r
- * Modify runtime port parameters\r
- *\r
- * @param baudrate The integer value of baudrate\r
- * @param databits The Number of data bits\r
- * @param partiy Values of EVEN,ODD or NONE\r
- * @param stopbits Values of 1 or 2\r
- * @param flow_cntl TRUE to enable hardware flow control\r
- *\r
- * @return SUCCESS if parameters successfully applied. FAIL otherwise\r
- */\r
- async command error_t configPort(uint32_t baudrate, \r
- uint8_t databits, \r
- uart_parity_t parity, \r
- uint8_t stopbits, \r
- bool flow_cntl);\r
- \r
- /**\r
- * Flush the port FIFOs\r
- *\r
- * @return SUCCESS if flushed, FAIL otherwise.\r
- */\r
- async command error_t flushPort();\r
-\r
-}\r
-\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arch Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arch Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+
+/**
+ * @author Phil Buonadonna
+ */
+
+#include "pxa27x_serial.h"
+
+interface HalPXA27xSerialCntl
+{
+ /**
+ * Modify runtime port parameters
+ *
+ * @param baudrate The integer value of baudrate
+ * @param databits The Number of data bits
+ * @param partiy Values of EVEN,ODD or NONE
+ * @param stopbits Values of 1 or 2
+ * @param flow_cntl TRUE to enable hardware flow control
+ *
+ * @return SUCCESS if parameters successfully applied. FAIL otherwise
+ */
+ async command error_t configPort(uint32_t baudrate,
+ uint8_t databits,
+ uart_parity_t parity,
+ uint8_t stopbits,
+ bool flow_cntl);
+
+ /**
+ * Flush the port FIFOs
+ *
+ * @return SUCCESS if flushed, FAIL otherwise.
+ */
+ async command error_t flushPort();
+
+}
+
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/*\r
- * Intel Open Source License\r
- *\r
- * Copyright (c) 2002 Intel Corporation\r
- * All rights reserved.\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- *\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * Neither the name of the Intel Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- *\r
- */\r
-/**\r
- * Implements the UartByte, UartStream and HalPXA27xSerialPacket interface \r
- * for a PXA27x UART. \r
- * \r
- *\r
- * @param defaultRate Default baud rate for the serial port. \r
- *\r
- *\r
- * @author Phil Buonadonna\r
- */\r
-\r
-#include "pxa27x_serial.h"\r
-\r
-generic module HalPXA27xSerialP(uint32_t defaultRate)\r
-{\r
- provides {\r
- interface Init;\r
- interface StdControl;\r
- interface UartByte;\r
- interface UartStream;\r
- interface HalPXA27xSerialPacket;\r
- interface HalPXA27xSerialCntl;\r
- }\r
- uses {\r
- interface Init as UARTInit;\r
- interface HplPXA27xUART as UART;\r
- interface HplPXA27xDMAChnl as RxDMA;\r
- interface HplPXA27xDMAChnl as TxDMA;\r
- interface HplPXA27xDMAInfo as UARTRxDMAInfo;\r
- interface HplPXA27xDMAInfo as UARTTxDMAInfo;\r
- }\r
-}\r
-\r
-implementation \r
-{\r
-\r
- uint8_t *txCurrentBuf, *rxCurrentBuf;\r
- uint32_t txCurrentLen, rxCurrentLen, rxCurrentIdx;\r
- uint32_t gulFCRShadow;\r
- bool gbUsingUartStreamSendIF = FALSE;\r
- bool gbUsingUartStreamRcvIF = FALSE;\r
- bool gbRcvByteEvtEnabled = TRUE;\r
-\r
- command error_t Init.init() {\r
- error_t error = SUCCESS;\r
-\r
- atomic {\r
- call UARTInit.init();\r
- txCurrentBuf = rxCurrentBuf = NULL;\r
- gbUsingUartStreamSendIF = FALSE;\r
- gbUsingUartStreamRcvIF = FALSE;\r
- gbRcvByteEvtEnabled = TRUE;\r
- gulFCRShadow = (FCR_TRFIFOE | FCR_ITL(0)); // FIFO Mode, 1 byte Rx threshold\r
- }\r
- call TxDMA.setMap(call UARTTxDMAInfo.getMapIndex());\r
- call RxDMA.setMap(call UARTRxDMAInfo.getMapIndex());\r
- call TxDMA.setDALGNbit(TRUE);\r
- call RxDMA.setDALGNbit(TRUE);\r
-\r
- error = call HalPXA27xSerialCntl.configPort(defaultRate,8,NONE,1,FALSE);\r
- \r
- atomic {call UART.setFCR(gulFCRShadow);}\r
- return error;\r
- }\r
-\r
- command error_t StdControl.start() {\r
- atomic {\r
- call UART.setIER(IER_UUE | IER_RAVIE);\r
- }\r
- return SUCCESS;\r
- }\r
-\r
- command error_t StdControl.stop() {\r
- atomic {\r
- call UART.setIER(0);\r
- }\r
- return SUCCESS;\r
- }\r
-\r
- async command error_t UartByte.send(uint8_t data) {\r
- atomic call UART.setTHR(data);\r
- while ((call UART.getLSR() & LSR_TEMT) == 0);\r
- return SUCCESS;\r
- }\r
-\r
- async command error_t UartByte.receive( uint8_t *data, uint8_t timeout) {\r
- error_t error = FAIL;\r
- uint8_t t;\r
- for (t = 0; t < timeout; t++) {\r
- if (call UART.getLSR() & LSR_DR) {\r
- *data = call UART.getRBR();\r
- error = SUCCESS;\r
- break;\r
- }\r
- }\r
- return error;\r
- }\r
-\r
- async command error_t UartStream.send( uint8_t* buf, uint16_t len ) {\r
- error_t error;\r
- atomic gbUsingUartStreamSendIF = TRUE;\r
- error = call HalPXA27xSerialPacket.send(buf,len);\r
- if (error) {\r
- atomic gbUsingUartStreamSendIF = FALSE;\r
- }\r
- return error;\r
- }\r
-\r
-\r
- async command error_t UartStream.enableReceiveInterrupt() {\r
- error_t error = SUCCESS;\r
- atomic {\r
- if (rxCurrentBuf == NULL) {\r
- call UART.setIER(call UART.getIER() | IER_RAVIE);\r
- }\r
- gbRcvByteEvtEnabled = TRUE;\r
- }\r
- return SUCCESS;\r
- }\r
-\r
- async command error_t UartStream.disableReceiveInterrupt() {\r
- atomic {\r
- // Check to make sure a short stream/packet call isn't in progress\r
- if ((rxCurrentBuf == NULL) || (rxCurrentLen >= 8)) {\r
- call UART.setIER(call UART.getIER() & ~IER_RAVIE);\r
- }\r
- gbRcvByteEvtEnabled = FALSE;\r
- }\r
- return SUCCESS;\r
- }\r
-\r
- async command error_t UartStream.receive( uint8_t* buf, uint16_t len ) {\r
- error_t error;\r
- atomic gbUsingUartStreamRcvIF = TRUE;\r
- error = call HalPXA27xSerialPacket.receive(buf,len,0);\r
- if (error) {\r
- atomic gbUsingUartStreamRcvIF = FALSE;\r
- }\r
- return error;\r
- }\r
- \r
- async command error_t HalPXA27xSerialPacket.send(uint8_t *buf, uint16_t len) {\r
- uint32_t txAddr;\r
- uint32_t DMAFlags;\r
- error_t error = SUCCESS;\r
-\r
- atomic {\r
- if (txCurrentBuf == NULL) {\r
- txCurrentBuf = buf;\r
- txCurrentLen = len;\r
- }\r
- else {\r
- error = FAIL;\r
- }\r
- }\r
-\r
- if (error) \r
- return error;\r
- \r
- if (len < 8) {\r
- uint16_t i;\r
- // Use PIO. Invariant: FIFO is empty\r
- atomic {\r
- gulFCRShadow |= FCR_TIL;\r
- call UART.setFCR(gulFCRShadow); \r
- }\r
- for (i = 0;i < len;i++) {\r
- call UART.setTHR(buf[i]);\r
- }\r
- atomic call UART.setIER(call UART.getIER() | IER_TIE);\r
- }\r
- else {\r
- // Use DMA\r
- DMAFlags = (DCMD_FLOWTRG | DCMD_BURST8 | DCMD_WIDTH1 | DCMD_ENDIRQEN\r
- | DCMD_LEN(len) );\r
- \r
- txAddr = (uint32_t) buf;\r
- DMAFlags |= DCMD_INCSRCADDR;\r
- \r
- call TxDMA.setDCSR(DCSR_NODESCFETCH);\r
- call TxDMA.setDSADR(txAddr);\r
- call TxDMA.setDTADR(call UARTTxDMAInfo.getAddr());\r
- call TxDMA.setDCMD(DMAFlags);\r
- \r
- atomic {\r
- call UART.setIER(call UART.getIER() | IER_DMAE);\r
- }\r
-\r
- call TxDMA.setDCSR(DCSR_RUN | DCSR_NODESCFETCH);\r
- }\r
- return error;\r
- }\r
-\r
-\r
- async command error_t HalPXA27xSerialPacket.receive(uint8_t *buf, uint16_t len, \r
- uint16_t timeout) {\r
- uint32_t rxAddr;\r
- uint32_t DMAFlags;\r
- error_t error = SUCCESS;\r
-\r
- atomic {\r
- if (rxCurrentBuf == NULL) {\r
- rxCurrentBuf = buf;\r
- rxCurrentLen = len;\r
- rxCurrentIdx = 0;\r
- }\r
- else {\r
- error = FAIL;\r
- }\r
- }\r
-\r
- if (error) \r
- return error;\r
-\r
- if (len < 8) {\r
- // Use PIO. Invariant: FIFO is empty\r
- atomic {\r
- gulFCRShadow = ((gulFCRShadow & ~(FCR_ITL(3))) | FCR_ITL(0));\r
- call UART.setFCR(gulFCRShadow); \r
- call UART.setIER(call UART.getIER() | IER_RAVIE);\r
- }\r
- }\r
- else {\r
- // Use DMA\r
- DMAFlags = (DCMD_FLOWSRC | DCMD_BURST8 | DCMD_WIDTH1 | DCMD_ENDIRQEN\r
- | DCMD_LEN(len) );\r
- \r
- rxAddr = (uint32_t) buf;\r
- DMAFlags |= DCMD_INCTRGADDR;\r
- \r
- call RxDMA.setDCSR(DCSR_NODESCFETCH);\r
- call RxDMA.setDTADR(rxAddr);\r
- call RxDMA.setDSADR(call UARTRxDMAInfo.getAddr());\r
- call RxDMA.setDCMD(DMAFlags);\r
-\r
- atomic {\r
- gulFCRShadow = ((gulFCRShadow & ~(FCR_ITL(3))) | FCR_ITL(1));\r
- call UART.setFCR(gulFCRShadow); \r
- call UART.setIER((call UART.getIER() & ~IER_RAVIE) | IER_DMAE);\r
- }\r
-\r
- call RxDMA.setDCSR(DCSR_RUN | DCSR_NODESCFETCH);\r
- }\r
- return error;\r
- }\r
- \r
- void DispatchStreamRcvSignal() {\r
- uint8_t *pBuf = rxCurrentBuf;\r
- uint16_t len = rxCurrentLen;\r
- rxCurrentBuf = NULL;\r
- if (gbUsingUartStreamRcvIF) {\r
- gbUsingUartStreamRcvIF = FALSE;\r
- signal UartStream.receiveDone(pBuf, len, SUCCESS);\r
- }\r
- else {\r
- pBuf = signal HalPXA27xSerialPacket.receiveDone(pBuf, len, SUCCESS);\r
- if (pBuf) {\r
- call HalPXA27xSerialPacket.receive(pBuf,len,0);\r
- }\r
- }\r
- return;\r
- }\r
-\r
- void DispatchStreamSendSignal() {\r
- uint8_t *pBuf = txCurrentBuf;\r
- uint16_t len = txCurrentLen;\r
- txCurrentBuf = NULL;\r
- if (gbUsingUartStreamSendIF) {\r
- gbUsingUartStreamSendIF = FALSE;\r
- signal UartStream.sendDone(pBuf, len, SUCCESS);\r
- }\r
- else {\r
- pBuf = signal HalPXA27xSerialPacket.sendDone(pBuf, len, SUCCESS);\r
- if (pBuf) {\r
- call HalPXA27xSerialPacket.send(pBuf,len);\r
- }\r
- }\r
- return;\r
- }\r
-\r
- async event void RxDMA.interruptDMA() {\r
- call RxDMA.setDCMD(0);\r
- call RxDMA.setDCSR(DCSR_EORINT | DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERRINTR);\r
- DispatchStreamRcvSignal();\r
- if (gbRcvByteEvtEnabled) \r
- call UART.setIER(call UART.getIER() | IER_RAVIE);\r
- return;\r
- }\r
-\r
- async event void TxDMA.interruptDMA() {\r
- call TxDMA.setDCMD(0);\r
- call TxDMA.setDCSR(DCSR_EORINT | DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERRINTR);\r
- DispatchStreamSendSignal();\r
- return;\r
- }\r
-\r
-\r
- async command error_t HalPXA27xSerialCntl.configPort(uint32_t baudrate, \r
- uint8_t databits, \r
- uart_parity_t parity, \r
- uint8_t stopbits, \r
- bool flow_cntl) {\r
- uint32_t uiDivisor;\r
- uint32_t valLCR = 0;\r
- uint32_t valMCR = MCR_OUT2;\r
- \r
- uiDivisor = 921600/baudrate;\r
- // Check for invalid baud rate divisor value.\r
- // XXX - Eventually could use '0' to imply auto rate detection\r
- if ((uiDivisor & 0xFFFF0000) || (uiDivisor == 0)) {\r
- return EINVAL;\r
- }\r
-\r
- if ((databits > 8 || databits < 5)) {\r
- return EINVAL;\r
- }\r
- valLCR |= LCR_WLS((databits-5));\r
-\r
- switch (parity) {\r
- case EVEN: \r
- valLCR |= LCR_EPS;\r
- // Fall through to enable\r
- case ODD:\r
- valLCR |= LCR_PEN;\r
- break;\r
- case NONE:\r
- break;\r
- default:\r
- return EINVAL;\r
- break;\r
- }\r
- \r
- if ((stopbits > 2) || (stopbits < 1)) {\r
- return EINVAL;\r
- }\r
- else if (stopbits == 2) {\r
- valLCR |= LCR_STB;\r
- }\r
-\r
- if (flow_cntl) {\r
- valMCR |= MCR_AFE;\r
- }\r
-\r
- atomic {\r
- call UART.setDLL((uiDivisor & 0xFF));\r
- call UART.setDLH(((uiDivisor >> 8) & 0xFF));\r
- call UART.setLCR(valLCR);\r
- call UART.setMCR(valMCR);\r
- }\r
- \r
- return SUCCESS;\r
- }\r
- \r
- async command error_t HalPXA27xSerialCntl.flushPort() {\r
-\r
- atomic {\r
- call UART.setFCR(gulFCRShadow | FCR_RESETTF | FCR_RESETRF);\r
- }\r
-\r
- return SUCCESS;\r
- }\r
- \r
- async event void UART.interruptUART() {\r
- uint8_t error, intSource;\r
- uint8_t ucByte;\r
-\r
- intSource = call UART.getIIR();\r
- intSource &= IIR_IID_MASK;\r
- intSource = intSource >> 1;\r
- \r
- switch (intSource) {\r
- case 0: // MODEM STATUS\r
- break;\r
- case 1: // TRANSMIT FIFO\r
- call UART.setIER(call UART.getIER() & ~IER_TIE);\r
- DispatchStreamSendSignal();\r
- break;\r
- case 2: // RECEIVE FIFO data available\r
- while (call UART.getLSR() & LSR_DR) {\r
- ucByte = call UART.getRBR();\r
-\r
- if (rxCurrentBuf != NULL) {\r
- rxCurrentBuf[rxCurrentIdx] = ucByte;\r
- rxCurrentIdx++;\r
- if (rxCurrentIdx >= rxCurrentLen) \r
- DispatchStreamRcvSignal();\r
- }\r
- else if (gbRcvByteEvtEnabled) {\r
- signal UartStream.receivedByte(ucByte);\r
- }\r
- }\r
- break;\r
- case 3: // ERROR\r
- error = call UART.getLSR();\r
- break;\r
- default:\r
- break;\r
- }\r
- return;\r
- }\r
-\r
- default async event void UartStream.sendDone( uint8_t* buf, uint16_t len, error_t error ) {\r
- return; \r
- }\r
-\r
- default async event void UartStream.receivedByte(uint8_t data) {\r
- return;\r
- }\r
-\r
- default async event void UartStream.receiveDone( uint8_t* buf, uint16_t len, error_t error ) {\r
- return;\r
- }\r
-\r
- default async event uint8_t* HalPXA27xSerialPacket.sendDone(uint8_t *buf, \r
- uint16_t len, \r
- uart_status_t status) {\r
- return NULL;\r
- }\r
-\r
- default async event uint8_t* HalPXA27xSerialPacket.receiveDone(uint8_t *buf, \r
- uint16_t len, \r
- uart_status_t status) {\r
- return NULL;\r
- }\r
-\r
-\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/*
+ * Intel Open Source License
+ *
+ * Copyright (c) 2002 Intel Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ */
+/**
+ * Implements the UartByte, UartStream and HalPXA27xSerialPacket interface
+ * for a PXA27x UART.
+ *
+ *
+ * @param defaultRate Default baud rate for the serial port.
+ *
+ *
+ * @author Phil Buonadonna
+ */
+
+#include "pxa27x_serial.h"
+
+generic module HalPXA27xSerialP(uint32_t defaultRate)
+{
+ provides {
+ interface Init;
+ interface StdControl;
+ interface UartByte;
+ interface UartStream;
+ interface HalPXA27xSerialPacket;
+ interface HalPXA27xSerialCntl;
+ }
+ uses {
+ interface Init as UARTInit;
+ interface HplPXA27xUART as UART;
+ interface HplPXA27xDMAChnl as RxDMA;
+ interface HplPXA27xDMAChnl as TxDMA;
+ interface HplPXA27xDMAInfo as UARTRxDMAInfo;
+ interface HplPXA27xDMAInfo as UARTTxDMAInfo;
+ }
+}
+
+implementation
+{
+
+ uint8_t *txCurrentBuf, *rxCurrentBuf;
+ uint32_t txCurrentLen, rxCurrentLen, rxCurrentIdx;
+ uint32_t gulFCRShadow;
+ bool gbUsingUartStreamSendIF = FALSE;
+ bool gbUsingUartStreamRcvIF = FALSE;
+ bool gbRcvByteEvtEnabled = TRUE;
+
+ command error_t Init.init() {
+ error_t error = SUCCESS;
+
+ atomic {
+ call UARTInit.init();
+ txCurrentBuf = rxCurrentBuf = NULL;
+ gbUsingUartStreamSendIF = FALSE;
+ gbUsingUartStreamRcvIF = FALSE;
+ gbRcvByteEvtEnabled = TRUE;
+ gulFCRShadow = (FCR_TRFIFOE | FCR_ITL(0)); // FIFO Mode, 1 byte Rx threshold
+ }
+ call TxDMA.setMap(call UARTTxDMAInfo.getMapIndex());
+ call RxDMA.setMap(call UARTRxDMAInfo.getMapIndex());
+ call TxDMA.setDALGNbit(TRUE);
+ call RxDMA.setDALGNbit(TRUE);
+
+ error = call HalPXA27xSerialCntl.configPort(defaultRate,8,NONE,1,FALSE);
+
+ atomic {call UART.setFCR(gulFCRShadow);}
+ return error;
+ }
+
+ command error_t StdControl.start() {
+ atomic {
+ call UART.setIER(IER_UUE | IER_RAVIE);
+ }
+ return SUCCESS;
+ }
+
+ command error_t StdControl.stop() {
+ atomic {
+ call UART.setIER(0);
+ }
+ return SUCCESS;
+ }
+
+ async command error_t UartByte.send(uint8_t data) {
+ atomic call UART.setTHR(data);
+ while ((call UART.getLSR() & LSR_TEMT) == 0);
+ return SUCCESS;
+ }
+
+ async command error_t UartByte.receive( uint8_t *data, uint8_t timeout) {
+ error_t error = FAIL;
+ uint8_t t;
+ for (t = 0; t < timeout; t++) {
+ if (call UART.getLSR() & LSR_DR) {
+ *data = call UART.getRBR();
+ error = SUCCESS;
+ break;
+ }
+ }
+ return error;
+ }
+
+ async command error_t UartStream.send( uint8_t* buf, uint16_t len ) {
+ error_t error;
+ atomic gbUsingUartStreamSendIF = TRUE;
+ error = call HalPXA27xSerialPacket.send(buf,len);
+ if (error) {
+ atomic gbUsingUartStreamSendIF = FALSE;
+ }
+ return error;
+ }
+
+
+ async command error_t UartStream.enableReceiveInterrupt() {
+ error_t error = SUCCESS;
+ atomic {
+ if (rxCurrentBuf == NULL) {
+ call UART.setIER(call UART.getIER() | IER_RAVIE);
+ }
+ gbRcvByteEvtEnabled = TRUE;
+ }
+ return SUCCESS;
+ }
+
+ async command error_t UartStream.disableReceiveInterrupt() {
+ atomic {
+ // Check to make sure a short stream/packet call isn't in progress
+ if ((rxCurrentBuf == NULL) || (rxCurrentLen >= 8)) {
+ call UART.setIER(call UART.getIER() & ~IER_RAVIE);
+ }
+ gbRcvByteEvtEnabled = FALSE;
+ }
+ return SUCCESS;
+ }
+
+ async command error_t UartStream.receive( uint8_t* buf, uint16_t len ) {
+ error_t error;
+ atomic gbUsingUartStreamRcvIF = TRUE;
+ error = call HalPXA27xSerialPacket.receive(buf,len,0);
+ if (error) {
+ atomic gbUsingUartStreamRcvIF = FALSE;
+ }
+ return error;
+ }
+
+ async command error_t HalPXA27xSerialPacket.send(uint8_t *buf, uint16_t len) {
+ uint32_t txAddr;
+ uint32_t DMAFlags;
+ error_t error = SUCCESS;
+
+ atomic {
+ if (txCurrentBuf == NULL) {
+ txCurrentBuf = buf;
+ txCurrentLen = len;
+ }
+ else {
+ error = FAIL;
+ }
+ }
+
+ if (error)
+ return error;
+
+ if (len < 8) {
+ uint16_t i;
+ // Use PIO. Invariant: FIFO is empty
+ atomic {
+ gulFCRShadow |= FCR_TIL;
+ call UART.setFCR(gulFCRShadow);
+ }
+ for (i = 0;i < len;i++) {
+ call UART.setTHR(buf[i]);
+ }
+ atomic call UART.setIER(call UART.getIER() | IER_TIE);
+ }
+ else {
+ // Use DMA
+ DMAFlags = (DCMD_FLOWTRG | DCMD_BURST8 | DCMD_WIDTH1 | DCMD_ENDIRQEN
+ | DCMD_LEN(len) );
+
+ txAddr = (uint32_t) buf;
+ DMAFlags |= DCMD_INCSRCADDR;
+
+ call TxDMA.setDCSR(DCSR_NODESCFETCH);
+ call TxDMA.setDSADR(txAddr);
+ call TxDMA.setDTADR(call UARTTxDMAInfo.getAddr());
+ call TxDMA.setDCMD(DMAFlags);
+
+ atomic {
+ call UART.setIER(call UART.getIER() | IER_DMAE);
+ }
+
+ call TxDMA.setDCSR(DCSR_RUN | DCSR_NODESCFETCH);
+ }
+ return error;
+ }
+
+
+ async command error_t HalPXA27xSerialPacket.receive(uint8_t *buf, uint16_t len,
+ uint16_t timeout) {
+ uint32_t rxAddr;
+ uint32_t DMAFlags;
+ error_t error = SUCCESS;
+
+ atomic {
+ if (rxCurrentBuf == NULL) {
+ rxCurrentBuf = buf;
+ rxCurrentLen = len;
+ rxCurrentIdx = 0;
+ }
+ else {
+ error = FAIL;
+ }
+ }
+
+ if (error)
+ return error;
+
+ if (len < 8) {
+ // Use PIO. Invariant: FIFO is empty
+ atomic {
+ gulFCRShadow = ((gulFCRShadow & ~(FCR_ITL(3))) | FCR_ITL(0));
+ call UART.setFCR(gulFCRShadow);
+ call UART.setIER(call UART.getIER() | IER_RAVIE);
+ }
+ }
+ else {
+ // Use DMA
+ DMAFlags = (DCMD_FLOWSRC | DCMD_BURST8 | DCMD_WIDTH1 | DCMD_ENDIRQEN
+ | DCMD_LEN(len) );
+
+ rxAddr = (uint32_t) buf;
+ DMAFlags |= DCMD_INCTRGADDR;
+
+ call RxDMA.setDCSR(DCSR_NODESCFETCH);
+ call RxDMA.setDTADR(rxAddr);
+ call RxDMA.setDSADR(call UARTRxDMAInfo.getAddr());
+ call RxDMA.setDCMD(DMAFlags);
+
+ atomic {
+ gulFCRShadow = ((gulFCRShadow & ~(FCR_ITL(3))) | FCR_ITL(1));
+ call UART.setFCR(gulFCRShadow);
+ call UART.setIER((call UART.getIER() & ~IER_RAVIE) | IER_DMAE);
+ }
+
+ call RxDMA.setDCSR(DCSR_RUN | DCSR_NODESCFETCH);
+ }
+ return error;
+ }
+
+ void DispatchStreamRcvSignal() {
+ uint8_t *pBuf = rxCurrentBuf;
+ uint16_t len = rxCurrentLen;
+ rxCurrentBuf = NULL;
+ if (gbUsingUartStreamRcvIF) {
+ gbUsingUartStreamRcvIF = FALSE;
+ signal UartStream.receiveDone(pBuf, len, SUCCESS);
+ }
+ else {
+ pBuf = signal HalPXA27xSerialPacket.receiveDone(pBuf, len, SUCCESS);
+ if (pBuf) {
+ call HalPXA27xSerialPacket.receive(pBuf,len,0);
+ }
+ }
+ return;
+ }
+
+ void DispatchStreamSendSignal() {
+ uint8_t *pBuf = txCurrentBuf;
+ uint16_t len = txCurrentLen;
+ txCurrentBuf = NULL;
+ if (gbUsingUartStreamSendIF) {
+ gbUsingUartStreamSendIF = FALSE;
+ signal UartStream.sendDone(pBuf, len, SUCCESS);
+ }
+ else {
+ pBuf = signal HalPXA27xSerialPacket.sendDone(pBuf, len, SUCCESS);
+ if (pBuf) {
+ call HalPXA27xSerialPacket.send(pBuf,len);
+ }
+ }
+ return;
+ }
+
+ async event void RxDMA.interruptDMA() {
+ call RxDMA.setDCMD(0);
+ call RxDMA.setDCSR(DCSR_EORINT | DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERRINTR);
+ DispatchStreamRcvSignal();
+ if (gbRcvByteEvtEnabled)
+ call UART.setIER(call UART.getIER() | IER_RAVIE);
+ return;
+ }
+
+ async event void TxDMA.interruptDMA() {
+ call TxDMA.setDCMD(0);
+ call TxDMA.setDCSR(DCSR_EORINT | DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERRINTR);
+ DispatchStreamSendSignal();
+ return;
+ }
+
+
+ async command error_t HalPXA27xSerialCntl.configPort(uint32_t baudrate,
+ uint8_t databits,
+ uart_parity_t parity,
+ uint8_t stopbits,
+ bool flow_cntl) {
+ uint32_t uiDivisor;
+ uint32_t valLCR = 0;
+ uint32_t valMCR = MCR_OUT2;
+
+ uiDivisor = 921600/baudrate;
+ // Check for invalid baud rate divisor value.
+ // XXX - Eventually could use '0' to imply auto rate detection
+ if ((uiDivisor & 0xFFFF0000) || (uiDivisor == 0)) {
+ return EINVAL;
+ }
+
+ if ((databits > 8 || databits < 5)) {
+ return EINVAL;
+ }
+ valLCR |= LCR_WLS((databits-5));
+
+ switch (parity) {
+ case EVEN:
+ valLCR |= LCR_EPS;
+ // Fall through to enable
+ case ODD:
+ valLCR |= LCR_PEN;
+ break;
+ case NONE:
+ break;
+ default:
+ return EINVAL;
+ break;
+ }
+
+ if ((stopbits > 2) || (stopbits < 1)) {
+ return EINVAL;
+ }
+ else if (stopbits == 2) {
+ valLCR |= LCR_STB;
+ }
+
+ if (flow_cntl) {
+ valMCR |= MCR_AFE;
+ }
+
+ atomic {
+ call UART.setDLL((uiDivisor & 0xFF));
+ call UART.setDLH(((uiDivisor >> 8) & 0xFF));
+ call UART.setLCR(valLCR);
+ call UART.setMCR(valMCR);
+ }
+
+ return SUCCESS;
+ }
+
+ async command error_t HalPXA27xSerialCntl.flushPort() {
+
+ atomic {
+ call UART.setFCR(gulFCRShadow | FCR_RESETTF | FCR_RESETRF);
+ }
+
+ return SUCCESS;
+ }
+
+ async event void UART.interruptUART() {
+ uint8_t error, intSource;
+ uint8_t ucByte;
+
+ intSource = call UART.getIIR();
+ intSource &= IIR_IID_MASK;
+ intSource = intSource >> 1;
+
+ switch (intSource) {
+ case 0: // MODEM STATUS
+ break;
+ case 1: // TRANSMIT FIFO
+ call UART.setIER(call UART.getIER() & ~IER_TIE);
+ DispatchStreamSendSignal();
+ break;
+ case 2: // RECEIVE FIFO data available
+ while (call UART.getLSR() & LSR_DR) {
+ ucByte = call UART.getRBR();
+
+ if (rxCurrentBuf != NULL) {
+ rxCurrentBuf[rxCurrentIdx] = ucByte;
+ rxCurrentIdx++;
+ if (rxCurrentIdx >= rxCurrentLen)
+ DispatchStreamRcvSignal();
+ }
+ else if (gbRcvByteEvtEnabled) {
+ signal UartStream.receivedByte(ucByte);
+ }
+ }
+ break;
+ case 3: // ERROR
+ error = call UART.getLSR();
+ break;
+ default:
+ break;
+ }
+ return;
+ }
+
+ default async event void UartStream.sendDone( uint8_t* buf, uint16_t len, error_t error ) {
+ return;
+ }
+
+ default async event void UartStream.receivedByte(uint8_t data) {
+ return;
+ }
+
+ default async event void UartStream.receiveDone( uint8_t* buf, uint16_t len, error_t error ) {
+ return;
+ }
+
+ default async event uint8_t* HalPXA27xSerialPacket.sendDone(uint8_t *buf,
+ uint16_t len,
+ uart_status_t status) {
+ return NULL;
+ }
+
+ default async event uint8_t* HalPXA27xSerialPacket.receiveDone(uint8_t *buf,
+ uint16_t len,
+ uart_status_t status) {
+ return NULL;
+ }
+
+
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arch Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arch Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-\r
-/**\r
- * @author Phil Buonadonna\r
- */\r
-\r
-#include "pxa27x_serial.h"\r
-\r
-interface HalPXA27xSerialPacket\r
-{\r
- /**\r
- * Begin transmission of a UART stream. If SUCCESS is returned,\r
- * <code>sendDone</code> will be signalled when transmission is\r
- * complete.\r
- *\r
- * @param buf Buffer for bytes to send.\r
- * @param len Number of bytes to send.\r
- * @return SUCCESS if request was accepted, FAIL otherwise.\r
- */\r
- async command error_t send(uint8_t *buf, uint16_t len);\r
- \r
- /**\r
- * Signal completion of sending a stream.\r
- *\r
- * @param buf Bytes sent.\r
- * @param len Number of bytes sent.\r
- * @param status UART error status.\r
- *\r
- * @return buf A pointer to a new buffer of equal length\r
- * as in the original <code>send</code> call that is to be transmitted (chained\r
- * send). Set to NULL to end further transmissions.\r
- */\r
- async event uint8_t *sendDone(uint8_t *buf, uint16_t len, uart_status_t status);\r
-\r
- /**\r
- * Begin reception of a UART stream. If SUCCESS is returned,\r
- * <code>receiveDone</code> will be signalled when reception is\r
- * complete.\r
- *\r
- * @param buf Buffer for received bytes.\r
- * @param len Number of bytes to receive.\r
- * @param timeout Timeout, in milliseconds, for receive operation\r
- *\r
- * @return SUCCESS if request was accepted, FAIL otherwise.\r
- */\r
- async command error_t receive(uint8_t *buf, uint16_t len, uint16_t timeout);\r
-\r
- /**\r
- * Signal completion of receiving a stream.\r
- *\r
- * @param buf Buffer for bytes received.\r
- * @param len Number of bytes received.\r
- * @param status UART error status\r
- *\r
- * @return buf A pointer to a new buffer of equal or greater length \r
- * as in the original <code>receive</code> call in which it intiate a\r
- * new packet reception (chained receive). Set to NULL to terminate further\r
- * reception. \r
- */\r
- async event uint8_t *receiveDone(uint8_t *buf, uint16_t len, uart_status_t status);\r
- \r
-}\r
-\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arch Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arch Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+
+/**
+ * @author Phil Buonadonna
+ */
+
+#include "pxa27x_serial.h"
+
+interface HalPXA27xSerialPacket
+{
+ /**
+ * Begin transmission of a UART stream. If SUCCESS is returned,
+ * <code>sendDone</code> will be signalled when transmission is
+ * complete.
+ *
+ * @param buf Buffer for bytes to send.
+ * @param len Number of bytes to send.
+ * @return SUCCESS if request was accepted, FAIL otherwise.
+ */
+ async command error_t send(uint8_t *buf, uint16_t len);
+
+ /**
+ * Signal completion of sending a stream.
+ *
+ * @param buf Bytes sent.
+ * @param len Number of bytes sent.
+ * @param status UART error status.
+ *
+ * @return buf A pointer to a new buffer of equal length
+ * as in the original <code>send</code> call that is to be transmitted (chained
+ * send). Set to NULL to end further transmissions.
+ */
+ async event uint8_t *sendDone(uint8_t *buf, uint16_t len, uart_status_t status);
+
+ /**
+ * Begin reception of a UART stream. If SUCCESS is returned,
+ * <code>receiveDone</code> will be signalled when reception is
+ * complete.
+ *
+ * @param buf Buffer for received bytes.
+ * @param len Number of bytes to receive.
+ * @param timeout Timeout, in milliseconds, for receive operation
+ *
+ * @return SUCCESS if request was accepted, FAIL otherwise.
+ */
+ async command error_t receive(uint8_t *buf, uint16_t len, uint16_t timeout);
+
+ /**
+ * Signal completion of receiving a stream.
+ *
+ * @param buf Buffer for bytes received.
+ * @param len Number of bytes received.
+ * @param status UART error status
+ *
+ * @return buf A pointer to a new buffer of equal or greater length
+ * as in the original <code>receive</code> call in which it intiate a
+ * new packet reception (chained receive). Set to NULL to terminate further
+ * reception.
+ */
+ async event uint8_t *receiveDone(uint8_t *buf, uint16_t len, uart_status_t status);
+
+}
+
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arch Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arch Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- *\r
- * @author Phil Buonadonna\r
- */\r
-\r
-configuration HplPXA27xBTUARTC \r
-{\r
- provides interface Init;\r
- provides interface HplPXA27xUART as BTUART;\r
-}\r
-\r
-implementation \r
-{\r
- components new HplPXA27xUARTP((uint32_t)&BTRBR);\r
- components HplPXA27xInterruptM;\r
-\r
- Init = HplPXA27xUARTP;\r
- BTUART = HplPXA27xUARTP.UART;\r
-\r
- HplPXA27xUARTP.UARTIrq -> HplPXA27xInterruptM.PXA27xIrq[PPID_BTUART];\r
-\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arch Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arch Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ *
+ * @author Phil Buonadonna
+ */
+
+configuration HplPXA27xBTUARTC
+{
+ provides interface Init;
+ provides interface HplPXA27xUART as BTUART;
+}
+
+implementation
+{
+ components new HplPXA27xUARTP((uint32_t)&BTRBR);
+ components HplPXA27xInterruptM;
+
+ Init = HplPXA27xUARTP;
+ BTUART = HplPXA27xUARTP.UART;
+
+ HplPXA27xUARTP.UARTIrq -> HplPXA27xInterruptM.PXA27xIrq[PPID_BTUART];
+
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arch Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arch Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- *\r
- * @author Phil Buonadonna\r
- */\r
-\r
-configuration HplPXA27xFFUARTC \r
-{\r
- provides interface Init;\r
- provides interface HplPXA27xUART as FFUART;\r
-}\r
-\r
-implementation \r
-{\r
- components new HplPXA27xUARTP((uint32_t)&FFRBR);\r
- components HplPXA27xInterruptM;\r
-\r
- Init = HplPXA27xUARTP;\r
- FFUART = HplPXA27xUARTP.UART;\r
-\r
- HplPXA27xUARTP.UARTIrq -> HplPXA27xInterruptM.PXA27xIrq[PPID_FFUART];\r
-\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arch Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arch Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ *
+ * @author Phil Buonadonna
+ */
+
+configuration HplPXA27xFFUARTC
+{
+ provides interface Init;
+ provides interface HplPXA27xUART as FFUART;
+}
+
+implementation
+{
+ components new HplPXA27xUARTP((uint32_t)&FFRBR);
+ components HplPXA27xInterruptM;
+
+ Init = HplPXA27xUARTP;
+ FFUART = HplPXA27xUARTP.UART;
+
+ HplPXA27xUARTP.UARTIrq -> HplPXA27xInterruptM.PXA27xIrq[PPID_FFUART];
+
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arch Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arch Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- *\r
- * @author Phil Buonadonna\r
- */\r
-\r
-configuration HplPXA27xSTUARTC \r
-{\r
- provides interface Init;\r
- provides interface HplPXA27xUART as STUART;\r
-}\r
-\r
-implementation \r
-{\r
- components new HplPXA27xUARTP((uint32_t)&STRBR);\r
- components HplPXA27xInterruptM;\r
-\r
- Init = HplPXA27xUARTP;\r
- STUART = HplPXA27xUARTP.UART;\r
-\r
- HplPXA27xUARTP.UARTIrq -> HplPXA27xInterruptM.PXA27xIrq[PPID_STUART];\r
-\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arch Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arch Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ *
+ * @author Phil Buonadonna
+ */
+
+configuration HplPXA27xSTUARTC
+{
+ provides interface Init;
+ provides interface HplPXA27xUART as STUART;
+}
+
+implementation
+{
+ components new HplPXA27xUARTP((uint32_t)&STRBR);
+ components HplPXA27xInterruptM;
+
+ Init = HplPXA27xUARTP;
+ STUART = HplPXA27xUARTP.UART;
+
+ HplPXA27xUARTP.UARTIrq -> HplPXA27xInterruptM.PXA27xIrq[PPID_STUART];
+
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * Interface to access UART peripheral register on the PXA27x. Function \r
- * names are based on the common portion of the names outlined in\r
- * the PXA27x Developers Guide.\r
- * \r
- * @author Phil Buonadonna\r
- */\r
-\r
-interface HplPXA27xUART\r
-{\r
- async command uint32_t getRBR();\r
- async command void setTHR(uint32_t val);\r
-\r
- async command void setDLL(uint32_t val);\r
- async command uint32_t getDLL();\r
-\r
- async command void setDLH(uint32_t val);\r
- async command uint32_t getDLH();\r
-\r
- async command void setIER(uint32_t val);\r
- async command uint32_t getIER();\r
-\r
- async command uint32_t getIIR();\r
-\r
- async command void setFCR(uint32_t val);\r
-\r
- async command void setLCR(uint32_t val);\r
- async command uint32_t getLCR();\r
-\r
- async command void setMCR(uint32_t val);\r
- async command uint32_t getMCR();\r
-\r
- async command uint32_t getLSR();\r
-\r
- async command uint32_t getMSR();\r
-\r
- async command void setSPR(uint32_t val);\r
- async command uint32_t getSPR();\r
-\r
- async command void setISR(uint32_t val);\r
- async command uint32_t getISR();\r
-\r
- async command void setFOR(uint32_t val);\r
- async command uint32_t getFOR();\r
-\r
- async command void setABR(uint32_t val);\r
- async command uint32_t getABR();\r
-\r
- async command uint32_t getACR();\r
-\r
- async event void interruptUART();\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * Interface to access UART peripheral register on the PXA27x. Function
+ * names are based on the common portion of the names outlined in
+ * the PXA27x Developers Guide.
+ *
+ * @author Phil Buonadonna
+ */
+
+interface HplPXA27xUART
+{
+ async command uint32_t getRBR();
+ async command void setTHR(uint32_t val);
+
+ async command void setDLL(uint32_t val);
+ async command uint32_t getDLL();
+
+ async command void setDLH(uint32_t val);
+ async command uint32_t getDLH();
+
+ async command void setIER(uint32_t val);
+ async command uint32_t getIER();
+
+ async command uint32_t getIIR();
+
+ async command void setFCR(uint32_t val);
+
+ async command void setLCR(uint32_t val);
+ async command uint32_t getLCR();
+
+ async command void setMCR(uint32_t val);
+ async command uint32_t getMCR();
+
+ async command uint32_t getLSR();
+
+ async command uint32_t getMSR();
+
+ async command void setSPR(uint32_t val);
+ async command uint32_t getSPR();
+
+ async command void setISR(uint32_t val);
+ async command uint32_t getISR();
+
+ async command void setFOR(uint32_t val);
+ async command uint32_t getFOR();
+
+ async command void setABR(uint32_t val);
+ async command uint32_t getABR();
+
+ async command uint32_t getACR();
+
+ async event void interruptUART();
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * Provides low-level initialization, 1st level interrupt dispatch and register\r
- * access for the different uarts. It is a generic that's bound to \r
- * the particular UART upon creation.\r
- *\r
- * @param baseaddr. The base address of the associated uart. One of \r
- * &FFRBR, &BTRBR or &STRBR.\r
- * This component automatically handles setting of the DLAB bit for\r
- * divisor register access (DLL and DLH) \r
- *\r
- * @author Phil Buonadonna\r
- */\r
-\r
-#include "PXA27X_UARTREG.h"\r
-\r
-generic module HplPXA27xUARTP(uint32_t base_addr)\r
-{\r
- provides interface Init;\r
- provides interface HplPXA27xUART as UART;\r
- uses interface HplPXA27xInterrupt as UARTIrq;\r
-}\r
-\r
-implementation\r
-{\r
- bool m_fInit = FALSE;\r
-\r
- command error_t Init.init() {\r
- bool isInited;\r
-\r
- atomic {\r
- isInited = m_fInit;\r
- m_fInit = TRUE;\r
- }\r
-\r
- if (!isInited) {\r
- switch (base_addr) {\r
- case (0x40100000):\r
- CKEN |= CKEN6_FFUART;\r
- break;\r
- case (0x40200000):\r
- CKEN |= CKEN7_BTUART;\r
- break;\r
- case (0x40700000):\r
- CKEN |= CKEN5_STUART;\r
- break;\r
- default:\r
- break;\r
- }\r
- call UARTIrq.allocate();\r
- call UARTIrq.enable();\r
- UARTLCR(base_addr) |= LCR_DLAB;\r
- UARTDLL(base_addr) = 0x04;\r
- UARTDLH(base_addr) = 0x00;\r
- UARTLCR(base_addr) &= ~LCR_DLAB;\r
- }\r
-\r
- return SUCCESS;\r
- }\r
-\r
- async command uint32_t UART.getRBR() { return UARTRBR(base_addr); }\r
- async command void UART.setTHR(uint32_t val) { UARTTHR(base_addr) = val; }\r
- async command void UART.setDLL(uint32_t val) { \r
- UARTLCR(base_addr) |= LCR_DLAB;\r
- UARTDLL(base_addr) = val; \r
- UARTLCR(base_addr) &= ~LCR_DLAB;\r
- }\r
- async command uint32_t UART.getDLL() { \r
- uint32_t val;\r
- UARTLCR(base_addr) |= LCR_DLAB;\r
- val = UARTDLL(base_addr); \r
- UARTLCR(base_addr) &= ~LCR_DLAB;\r
- return val;\r
- }\r
- async command void UART.setDLH(uint32_t val) { \r
- UARTLCR(base_addr) |= LCR_DLAB;\r
- UARTDLH(base_addr) = val; \r
- UARTLCR(base_addr) &= ~LCR_DLAB;\r
- }\r
- async command uint32_t UART.getDLH() { \r
- uint32_t val;\r
- UARTLCR(base_addr) |= LCR_DLAB;\r
- val = UARTDLH(base_addr);\r
- UARTLCR(base_addr) &= ~LCR_DLAB;\r
- return val;\r
- }\r
- async command void UART.setIER(uint32_t val) { UARTIER(base_addr) = val; }\r
- async command uint32_t UART.getIER() { return UARTIER(base_addr); }\r
- async command uint32_t UART.getIIR() { return UARTIIR(base_addr); }\r
- async command void UART.setFCR(uint32_t val) { UARTFCR(base_addr) = val; }\r
- async command void UART.setLCR(uint32_t val) { UARTLCR(base_addr) = val; }\r
- async command uint32_t UART.getLCR() { return UARTLCR(base_addr); }\r
- async command void UART.setMCR(uint32_t val) { UARTMCR(base_addr) = val; }\r
- async command uint32_t UART.getMCR() { return UARTMCR(base_addr); }\r
- async command uint32_t UART.getLSR() { return UARTLSR(base_addr); }\r
- async command uint32_t UART.getMSR() { return UARTMSR(base_addr); }\r
- async command void UART.setSPR(uint32_t val) { UARTSPR(base_addr) = val; }\r
- async command uint32_t UART.getSPR() { return UARTSPR(base_addr); }\r
- async command void UART.setISR(uint32_t val) { UARTISR(base_addr) = val; }\r
- async command uint32_t UART.getISR() { return UARTISR(base_addr); }\r
- async command void UART.setFOR(uint32_t val) { UARTFOR(base_addr) = val; }\r
- async command uint32_t UART.getFOR() { return UARTFOR(base_addr); }\r
- async command void UART.setABR(uint32_t val) { UARTABR(base_addr) = val; }\r
- async command uint32_t UART.getABR() { return UARTABR(base_addr); }\r
- async command uint32_t UART.getACR() { return UARTACR(base_addr); }\r
-\r
- async event void UARTIrq.fired () {\r
-\r
- signal UART.interruptUART();\r
- }\r
-\r
- default async event void UART.interruptUART() { return; }\r
- \r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * Provides low-level initialization, 1st level interrupt dispatch and register
+ * access for the different uarts. It is a generic that's bound to
+ * the particular UART upon creation.
+ *
+ * @param baseaddr. The base address of the associated uart. One of
+ * &FFRBR, &BTRBR or &STRBR.
+ * This component automatically handles setting of the DLAB bit for
+ * divisor register access (DLL and DLH)
+ *
+ * @author Phil Buonadonna
+ */
+
+#include "PXA27X_UARTREG.h"
+
+generic module HplPXA27xUARTP(uint32_t base_addr)
+{
+ provides interface Init;
+ provides interface HplPXA27xUART as UART;
+ uses interface HplPXA27xInterrupt as UARTIrq;
+}
+
+implementation
+{
+ bool m_fInit = FALSE;
+
+ command error_t Init.init() {
+ bool isInited;
+
+ atomic {
+ isInited = m_fInit;
+ m_fInit = TRUE;
+ }
+
+ if (!isInited) {
+ switch (base_addr) {
+ case (0x40100000):
+ CKEN |= CKEN6_FFUART;
+ break;
+ case (0x40200000):
+ CKEN |= CKEN7_BTUART;
+ break;
+ case (0x40700000):
+ CKEN |= CKEN5_STUART;
+ break;
+ default:
+ break;
+ }
+ call UARTIrq.allocate();
+ call UARTIrq.enable();
+ UARTLCR(base_addr) |= LCR_DLAB;
+ UARTDLL(base_addr) = 0x04;
+ UARTDLH(base_addr) = 0x00;
+ UARTLCR(base_addr) &= ~LCR_DLAB;
+ }
+
+ return SUCCESS;
+ }
+
+ async command uint32_t UART.getRBR() { return UARTRBR(base_addr); }
+ async command void UART.setTHR(uint32_t val) { UARTTHR(base_addr) = val; }
+ async command void UART.setDLL(uint32_t val) {
+ UARTLCR(base_addr) |= LCR_DLAB;
+ UARTDLL(base_addr) = val;
+ UARTLCR(base_addr) &= ~LCR_DLAB;
+ }
+ async command uint32_t UART.getDLL() {
+ uint32_t val;
+ UARTLCR(base_addr) |= LCR_DLAB;
+ val = UARTDLL(base_addr);
+ UARTLCR(base_addr) &= ~LCR_DLAB;
+ return val;
+ }
+ async command void UART.setDLH(uint32_t val) {
+ UARTLCR(base_addr) |= LCR_DLAB;
+ UARTDLH(base_addr) = val;
+ UARTLCR(base_addr) &= ~LCR_DLAB;
+ }
+ async command uint32_t UART.getDLH() {
+ uint32_t val;
+ UARTLCR(base_addr) |= LCR_DLAB;
+ val = UARTDLH(base_addr);
+ UARTLCR(base_addr) &= ~LCR_DLAB;
+ return val;
+ }
+ async command void UART.setIER(uint32_t val) { UARTIER(base_addr) = val; }
+ async command uint32_t UART.getIER() { return UARTIER(base_addr); }
+ async command uint32_t UART.getIIR() { return UARTIIR(base_addr); }
+ async command void UART.setFCR(uint32_t val) { UARTFCR(base_addr) = val; }
+ async command void UART.setLCR(uint32_t val) { UARTLCR(base_addr) = val; }
+ async command uint32_t UART.getLCR() { return UARTLCR(base_addr); }
+ async command void UART.setMCR(uint32_t val) { UARTMCR(base_addr) = val; }
+ async command uint32_t UART.getMCR() { return UARTMCR(base_addr); }
+ async command uint32_t UART.getLSR() { return UARTLSR(base_addr); }
+ async command uint32_t UART.getMSR() { return UARTMSR(base_addr); }
+ async command void UART.setSPR(uint32_t val) { UARTSPR(base_addr) = val; }
+ async command uint32_t UART.getSPR() { return UARTSPR(base_addr); }
+ async command void UART.setISR(uint32_t val) { UARTISR(base_addr) = val; }
+ async command uint32_t UART.getISR() { return UARTISR(base_addr); }
+ async command void UART.setFOR(uint32_t val) { UARTFOR(base_addr) = val; }
+ async command uint32_t UART.getFOR() { return UARTFOR(base_addr); }
+ async command void UART.setABR(uint32_t val) { UARTABR(base_addr) = val; }
+ async command uint32_t UART.getABR() { return UARTABR(base_addr); }
+ async command uint32_t UART.getACR() { return UARTACR(base_addr); }
+
+ async event void UARTIrq.fired () {
+
+ signal UART.interruptUART();
+ }
+
+ default async event void UART.interruptUART() { return; }
+
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arch Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-\r
-/* \r
- * Helper macros to make programming the HplPXA27xUARTP component easier\r
- */\r
-\r
-#ifndef _PXA27X_UARTREG_H\r
-#define _PXA27X_UARTREG_H\r
-\r
-#define UARTRBR(_base) _PXAREG_OFFSET(_base,0)\r
-#define UARTTHR(_base) _PXAREG_OFFSET(_base,0)\r
-#define UARTIER(_base) _PXAREG_OFFSET(_base,0x04)\r
-#define UARTIIR(_base) _PXAREG_OFFSET(_base,0x08)\r
-#define UARTFCR(_base) _PXAREG_OFFSET(_base,0x08)\r
-#define UARTLCR(_base) _PXAREG_OFFSET(_base,0x0C)\r
-#define UARTMCR(_base) _PXAREG_OFFSET(_base,0x10)\r
-#define UARTLSR(_base) _PXAREG_OFFSET(_base,0x14)\r
-#define UARTMSR(_base) _PXAREG_OFFSET(_base,0x18)\r
-#define UARTSPR(_base) _PXAREG_OFFSET(_base,0x1C)\r
-#define UARTISR(_base) _PXAREG_OFFSET(_base,0x20)\r
-#define UARTFOR(_base) _PXAREG_OFFSET(_base,0x24)\r
-#define UARTABR(_base) _PXAREG_OFFSET(_base,0x28)\r
-#define UARTACR(_base) _PXAREG_OFFSET(_base,0x2C)\r
-\r
-#define UARTDLL(_base) _PXAREG_OFFSET(_base,0)\r
-#define UARTDLH(_base) _PXAREG_OFFSET(_base,0x04)\r
-\r
-#endif /* _PXA27X_UARTREG_H */\r
-\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arch Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+
+/*
+ * Helper macros to make programming the HplPXA27xUARTP component easier
+ */
+
+#ifndef _PXA27X_UARTREG_H
+#define _PXA27X_UARTREG_H
+
+#define UARTRBR(_base) _PXAREG_OFFSET(_base,0)
+#define UARTTHR(_base) _PXAREG_OFFSET(_base,0)
+#define UARTIER(_base) _PXAREG_OFFSET(_base,0x04)
+#define UARTIIR(_base) _PXAREG_OFFSET(_base,0x08)
+#define UARTFCR(_base) _PXAREG_OFFSET(_base,0x08)
+#define UARTLCR(_base) _PXAREG_OFFSET(_base,0x0C)
+#define UARTMCR(_base) _PXAREG_OFFSET(_base,0x10)
+#define UARTLSR(_base) _PXAREG_OFFSET(_base,0x14)
+#define UARTMSR(_base) _PXAREG_OFFSET(_base,0x18)
+#define UARTSPR(_base) _PXAREG_OFFSET(_base,0x1C)
+#define UARTISR(_base) _PXAREG_OFFSET(_base,0x20)
+#define UARTFOR(_base) _PXAREG_OFFSET(_base,0x24)
+#define UARTABR(_base) _PXAREG_OFFSET(_base,0x28)
+#define UARTACR(_base) _PXAREG_OFFSET(_base,0x2C)
+
+#define UARTDLL(_base) _PXAREG_OFFSET(_base,0)
+#define UARTDLH(_base) _PXAREG_OFFSET(_base,0x04)
+
+#endif /* _PXA27X_UARTREG_H */
+
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-\r
-\r
-#ifndef _pxa27x_serial_h\r
-#define _pxa27x_serial_h\r
-\r
-typedef uint8_t uart_status_t; // ??? if this is supposed to be a uint8_t\r
-\r
-typedef enum {\r
- EVEN,\r
- ODD,\r
- NONE\r
-} uart_parity_t;\r
-\r
-#endif /* _pxa27x_serial_h */\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+
+
+#ifndef _pxa27x_serial_h
+#define _pxa27x_serial_h
+
+typedef uint8_t uart_status_t; // ??? if this is supposed to be a uint8_t
+
+typedef enum {
+ EVEN,
+ ODD,
+ NONE
+} uart_parity_t;
+
+#endif /* _pxa27x_serial_h */
-/*\r
- * Copyright (c) 2005-2006 Rincon Research Corporation\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions\r
- * are met:\r
- * - Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * - Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the\r
- * distribution.\r
- * - Neither the name of the Arch Rock Corporation nor the names of\r
- * its contributors may be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\r
- * ARCHED ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\r
- * OF THE POSSIBILITY OF SUCH DAMAGE\r
- */\r
- \r
-/**\r
- * Low Power Listening interface\r
- *\r
- * @author David Moss\r
- * @author Jonathan Hui\r
- */\r
- \r
-interface LowPowerListening {\r
-\r
- /**\r
- * Set this this node's radio sleep interval, in milliseconds.\r
- * Once every interval, the node will sleep and perform an Rx check \r
- * on the radio. Setting the sleep interval to 0 will keep the radio\r
- * always on.\r
- *\r
- * This is the equivalent of setting the local duty cycle rate.\r
- *\r
- * @param sleepIntervalMs the length of this node's Rx check interval, in [ms]\r
- */\r
- command void setLocalSleepInterval(uint16_t sleepIntervalMs);\r
- \r
- /**\r
- * @return the local node's sleep interval, in [ms]\r
- */\r
- command uint16_t getLocalSleepInterval();\r
- \r
- /**\r
- * Set this node's radio duty cycle rate, in units of [percentage*100].\r
- * For example, to get a 0.05% duty cycle,\r
- * <code>\r
- * call LowPowerListening.setDutyCycle(5); // or equivalently...\r
- * call LowPowerListening.setDutyCycle(00005); // for better readability?\r
- * </code>\r
- *\r
- * For a 100% duty cycle (always on),\r
- * <code>\r
- * call LowPowerListening.setDutyCycle(10000);\r
- * </code>\r
- *\r
- * This is the equivalent of setting the local sleep interval explicitly.\r
- * \r
- * @param dutyCycle The duty cycle percentage, in units of [percentage*100]\r
- */\r
- command void setLocalDutyCycle(uint16_t dutyCycle);\r
- \r
- /**\r
- * @return this node's radio duty cycle rate, in units of [percentage*100]\r
- */\r
- command uint16_t getLocalDutyCycle();\r
- \r
- \r
- /**\r
- * Configure this outgoing message so it can be transmitted to a neighbor mote\r
- * with the specified Rx sleep interval.\r
- * @param msg Pointer to the message that will be sent\r
- * @param sleepInterval The receiving node's sleep interval, in [ms]\r
- */\r
- command void setRxSleepInterval(message_t *msg, uint16_t sleepIntervalMs);\r
- \r
- /**\r
- * @return the destination node's sleep interval configured in this message\r
- */\r
- command uint16_t getRxSleepInterval(message_t *msg);\r
- \r
- /**\r
- * Configure this outgoing message so it can be transmitted to a neighbor mote\r
- * with the specified Rx duty cycle rate.\r
- * Duty cycle is in units of [percentage*100], i.e. 0.25% duty cycle = 25.\r
- * \r
- * @param msg Pointer to the message that will be sent\r
- * @param dutyCycle The duty cycle of the receiving mote, in units of \r
- * [percentage*100]\r
- */\r
- command void setRxDutyCycle(message_t *msg, uint16_t dutyCycle);\r
- \r
- /**\r
- * @return the destination node's duty cycle configured in this message\r
- * in units of [percentage*100]\r
- */\r
- command uint16_t getRxDutyCycle(message_t *msg);\r
- \r
- /**\r
- * Convert a duty cycle, in units of [percentage*100], to\r
- * the sleep interval of the mote in milliseconds\r
- * @param dutyCycle The duty cycle in units of [percentage*100]\r
- * @return The equivalent sleep interval, in units of [ms]\r
- */\r
- command uint16_t dutyCycleToSleepInterval(uint16_t dutyCycle);\r
- \r
- /**\r
- * Convert a sleep interval, in units of [ms], to a duty cycle\r
- * in units of [percentage*100]\r
- * @param sleepInterval The sleep interval in units of [ms]\r
- * @return The duty cycle in units of [percentage*100]\r
- */\r
- command uint16_t sleepIntervalToDutyCycle(uint16_t sleepInterval);\r
- \r
-}\r
+/*
+ * Copyright (c) 2005-2006 Rincon Research Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of the Arch Rock Corporation nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * ARCHED ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE
+ */
+
+/**
+ * Low Power Listening interface
+ *
+ * @author David Moss
+ * @author Jonathan Hui
+ */
+
+interface LowPowerListening {
+
+ /**
+ * Set this this node's radio sleep interval, in milliseconds.
+ * Once every interval, the node will sleep and perform an Rx check
+ * on the radio. Setting the sleep interval to 0 will keep the radio
+ * always on.
+ *
+ * This is the equivalent of setting the local duty cycle rate.
+ *
+ * @param sleepIntervalMs the length of this node's Rx check interval, in [ms]
+ */
+ command void setLocalSleepInterval(uint16_t sleepIntervalMs);
+
+ /**
+ * @return the local node's sleep interval, in [ms]
+ */
+ command uint16_t getLocalSleepInterval();
+
+ /**
+ * Set this node's radio duty cycle rate, in units of [percentage*100].
+ * For example, to get a 0.05% duty cycle,
+ * <code>
+ * call LowPowerListening.setDutyCycle(5); // or equivalently...
+ * call LowPowerListening.setDutyCycle(00005); // for better readability?
+ * </code>
+ *
+ * For a 100% duty cycle (always on),
+ * <code>
+ * call LowPowerListening.setDutyCycle(10000);
+ * </code>
+ *
+ * This is the equivalent of setting the local sleep interval explicitly.
+ *
+ * @param dutyCycle The duty cycle percentage, in units of [percentage*100]
+ */
+ command void setLocalDutyCycle(uint16_t dutyCycle);
+
+ /**
+ * @return this node's radio duty cycle rate, in units of [percentage*100]
+ */
+ command uint16_t getLocalDutyCycle();
+
+
+ /**
+ * Configure this outgoing message so it can be transmitted to a neighbor mote
+ * with the specified Rx sleep interval.
+ * @param msg Pointer to the message that will be sent
+ * @param sleepInterval The receiving node's sleep interval, in [ms]
+ */
+ command void setRxSleepInterval(message_t *msg, uint16_t sleepIntervalMs);
+
+ /**
+ * @return the destination node's sleep interval configured in this message
+ */
+ command uint16_t getRxSleepInterval(message_t *msg);
+
+ /**
+ * Configure this outgoing message so it can be transmitted to a neighbor mote
+ * with the specified Rx duty cycle rate.
+ * Duty cycle is in units of [percentage*100], i.e. 0.25% duty cycle = 25.
+ *
+ * @param msg Pointer to the message that will be sent
+ * @param dutyCycle The duty cycle of the receiving mote, in units of
+ * [percentage*100]
+ */
+ command void setRxDutyCycle(message_t *msg, uint16_t dutyCycle);
+
+ /**
+ * @return the destination node's duty cycle configured in this message
+ * in units of [percentage*100]
+ */
+ command uint16_t getRxDutyCycle(message_t *msg);
+
+ /**
+ * Convert a duty cycle, in units of [percentage*100], to
+ * the sleep interval of the mote in milliseconds
+ * @param dutyCycle The duty cycle in units of [percentage*100]
+ * @return The equivalent sleep interval, in units of [ms]
+ */
+ command uint16_t dutyCycleToSleepInterval(uint16_t dutyCycle);
+
+ /**
+ * Convert a sleep interval, in units of [ms], to a duty cycle
+ * in units of [percentage*100]
+ * @param sleepInterval The sleep interval in units of [ms]
+ * @return The duty cycle in units of [percentage*100]
+ */
+ command uint16_t sleepIntervalToDutyCycle(uint16_t sleepInterval);
+
+}
-// $Id$\r
-\r
-/* tab:4\r
- * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By\r
- * downloading, copying, installing or using the software you agree to\r
- * this license. If you do not agree to this license, do not download,\r
- * install, copy or use the software.\r
- *\r
- * Intel Open Source License \r
- *\r
- * Copyright (c) 2002 Intel Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * \r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * Neither the name of the Intel Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- * \r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * \r
- * \r
- */\r
-\r
-/**\r
- * Emulates GPIO capture functionality using GpioInterrupt and the \r
- * standard 32khz counter\r
- *\r
- * @author Phil Buonadonna\r
- */\r
-generic configuration SoftCaptureC() \r
-{\r
- provides interface GpioCapture;\r
- uses interface GpioInterrupt;\r
-}\r
-\r
-implementation\r
-{\r
- components new SoftCaptureP();\r
- components Counter32khzC;\r
- \r
- GpioCapture = SoftCaptureP;\r
- GpioInterrupt = SoftCaptureP;\r
-\r
- SoftCaptureP.Counter32khz32 -> Counter32khzC.Counter32khz32;\r
-}\r
-\r
+// $Id$
+
+/* tab:4
+ * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
+ * downloading, copying, installing or using the software you agree to
+ * this license. If you do not agree to this license, do not download,
+ * install, copy or use the software.
+ *
+ * Intel Open Source License
+ *
+ * Copyright (c) 2002 Intel Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ */
+
+/**
+ * Emulates GPIO capture functionality using GpioInterrupt and the
+ * standard 32khz counter
+ *
+ * @author Phil Buonadonna
+ */
+generic configuration SoftCaptureC()
+{
+ provides interface GpioCapture;
+ uses interface GpioInterrupt;
+}
+
+implementation
+{
+ components new SoftCaptureP();
+ components Counter32khzC;
+
+ GpioCapture = SoftCaptureP;
+ GpioInterrupt = SoftCaptureP;
+
+ SoftCaptureP.Counter32khz32 -> Counter32khzC.Counter32khz32;
+}
+
-// $Id$\r
-\r
-/* tab:4\r
- * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By\r
- * downloading, copying, installing or using the software you agree to\r
- * this license. If you do not agree to this license, do not download,\r
- * install, copy or use the software.\r
- *\r
- * Intel Open Source License \r
- *\r
- * Copyright (c) 2002 Intel Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * \r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * Neither the name of the Intel Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- * \r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * \r
- * \r
- */\r
-\r
-/**\r
- * Emulates GPIO capture functionality using GpioInterrupt and the \r
- * standard 32khz counter\r
- *\r
- * @author Phil Buonadonna\r
- */\r
-generic module SoftCaptureP ()\r
-{\r
- provides interface GpioCapture;\r
- uses {\r
- interface GpioInterrupt;\r
- interface Counter<T32khz,uint32_t> as Counter32khz32;\r
- }\r
-}\r
-\r
-implementation \r
-{\r
-\r
- async command error_t GpioCapture.captureRisingEdge() {\r
- return (call GpioInterrupt.enableRisingEdge());\r
- }\r
-\r
- async command error_t GpioCapture.captureFallingEdge() {\r
- return (call GpioInterrupt.enableFallingEdge());\r
- }\r
-\r
- async command void GpioCapture.disable() {\r
- call GpioInterrupt.disable();\r
- return;\r
- }\r
- \r
- async event void GpioInterrupt.fired() {\r
- uint16_t captureTime;\r
-\r
- captureTime = (uint16_t) call Counter32khz32.get();\r
- signal GpioCapture.captured(captureTime);\r
- return;\r
- }\r
-\r
- async event void Counter32khz32.overflow() {\r
- return;\r
- }\r
-\r
- default async event void GpioCapture.captured(uint16_t time) {\r
- return;\r
- }\r
-}\r
+// $Id$
+
+/* tab:4
+ * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
+ * downloading, copying, installing or using the software you agree to
+ * this license. If you do not agree to this license, do not download,
+ * install, copy or use the software.
+ *
+ * Intel Open Source License
+ *
+ * Copyright (c) 2002 Intel Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ */
+
+/**
+ * Emulates GPIO capture functionality using GpioInterrupt and the
+ * standard 32khz counter
+ *
+ * @author Phil Buonadonna
+ */
+generic module SoftCaptureP ()
+{
+ provides interface GpioCapture;
+ uses {
+ interface GpioInterrupt;
+ interface Counter<T32khz,uint32_t> as Counter32khz32;
+ }
+}
+
+implementation
+{
+
+ async command error_t GpioCapture.captureRisingEdge() {
+ return (call GpioInterrupt.enableRisingEdge());
+ }
+
+ async command error_t GpioCapture.captureFallingEdge() {
+ return (call GpioInterrupt.enableFallingEdge());
+ }
+
+ async command void GpioCapture.disable() {
+ call GpioInterrupt.disable();
+ return;
+ }
+
+ async event void GpioInterrupt.fired() {
+ uint16_t captureTime;
+
+ captureTime = (uint16_t) call Counter32khz32.get();
+ signal GpioCapture.captured(captureTime);
+ return;
+ }
+
+ async event void Counter32khz32.overflow() {
+ return;
+ }
+
+ default async event void GpioCapture.captured(uint16_t time) {
+ return;
+ }
+}
-/* \r
- * "Copyright (c) 2000-2004 The Regents of the University of California. \r
- * All rights reserved.\r
- *\r
- * Permission to use, copy, modify, and distribute this software and its\r
- * documentation for any purpose, without fee, and without written agreement is\r
- * hereby granted, provided that the above copyright notice, the following\r
- * two paragraphs and the author appear in all copies of this software.\r
- * \r
- * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR\r
- * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT\r
- * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF\r
- * CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * \r
- * THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\r
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY\r
- * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS\r
- * ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO\r
- * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."\r
- */\r
-\r
-/**\r
- * @author Jonathan Hui <jwhui@cs.berkeley.edu>\r
- */\r
-\r
-interface Crc\r
-{\r
- command uint16_t crc16(void* COUNT(len) buf, uint8_t len);\r
-}\r
+/*
+ * "Copyright (c) 2000-2004 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation for any purpose, without fee, and without written agreement is
+ * hereby granted, provided that the above copyright notice, the following
+ * two paragraphs and the author appear in all copies of this software.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
+ * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
+ * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF
+ * CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
+ */
+
+/**
+ * @author Jonathan Hui <jwhui@cs.berkeley.edu>
+ */
+
+interface Crc
+{
+ command uint16_t crc16(void* COUNT(len) buf, uint8_t len);
+}
-/* \r
- * "Copyright (c) 2000-2004 The Regents of the University of California. \r
- * All rights reserved.\r
- *\r
- * Permission to use, copy, modify, and distribute this software and its\r
- * documentation for any purpose, without fee, and without written agreement is\r
- * hereby granted, provided that the above copyright notice, the following\r
- * two paragraphs and the author appear in all copies of this software.\r
- * \r
- * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR\r
- * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT\r
- * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF\r
- * CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * \r
- * THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\r
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY\r
- * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS\r
- * ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO\r
- * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."\r
- */\r
-\r
-/**\r
- * @author Jonathan Hui <jwhui@cs.berkeley.edu>\r
- */\r
-\r
-#include "crc.h"\r
-\r
-module CrcP\r
-{\r
- provides interface Crc;\r
-}\r
-\r
-implementation\r
-{\r
- // From T1 "tos/system/CrcC.nc"\r
- command uint16_t Crc.crc16(void* buf, uint8_t len)\r
- {\r
- uint8_t* tmpBuf = (uint8_t*)buf;\r
- uint16_t crc;\r
- \r
- for (crc = 0; len > 0; len--) {\r
- crc = crcByte(crc, *tmpBuf); // Calculates running CRC\r
- tmpBuf++;\r
- }\r
- \r
- return crc;\r
- }\r
-}\r
+/*
+ * "Copyright (c) 2000-2004 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation for any purpose, without fee, and without written agreement is
+ * hereby granted, provided that the above copyright notice, the following
+ * two paragraphs and the author appear in all copies of this software.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
+ * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
+ * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF
+ * CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
+ */
+
+/**
+ * @author Jonathan Hui <jwhui@cs.berkeley.edu>
+ */
+
+#include "crc.h"
+
+module CrcP
+{
+ provides interface Crc;
+}
+
+implementation
+{
+ // From T1 "tos/system/CrcC.nc"
+ command uint16_t Crc.crc16(void* buf, uint8_t len)
+ {
+ uint8_t* tmpBuf = (uint8_t*)buf;
+ uint16_t crc;
+
+ for (crc = 0; len > 0; len--) {
+ crc = crcByte(crc, *tmpBuf); // Calculates running CRC
+ tmpBuf++;
+ }
+
+ return crc;
+ }
+}
-// $Id$\r
-\r
-/* tab:2\r
- *\r
- *\r
- * "Copyright (c) 2000-2005 The Regents of the University of California. \r
- * All rights reserved.\r
- *\r
- * Permission to use, copy, modify, and distribute this software and its\r
- * documentation for any purpose, without fee, and without written agreement is\r
- * hereby granted, provided that the above copyright notice, the following\r
- * two paragraphs and the author appear in all copies of this software.\r
- * \r
- * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR\r
- * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT\r
- * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF\r
- * CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * \r
- * THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\r
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY\r
- * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS\r
- * ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO\r
- * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."\r
- *\r
- */\r
-\r
-/**\r
- * @author Jonathan Hui <jwhui@cs.berkeley.edu>\r
- */\r
-\r
-#ifndef __NETPROG_PLATFORM_H__\r
-#define __NETPROG_PLATFORM_H__\r
-\r
-void netprog_reboot() {\r
- wdt_enable(1);\r
- while(1);\r
-}\r
-\r
-#endif\r
+// $Id$
+
+/* tab:2
+ *
+ *
+ * "Copyright (c) 2000-2005 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation for any purpose, without fee, and without written agreement is
+ * hereby granted, provided that the above copyright notice, the following
+ * two paragraphs and the author appear in all copies of this software.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
+ * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
+ * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF
+ * CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
+ *
+ */
+
+/**
+ * @author Jonathan Hui <jwhui@cs.berkeley.edu>
+ */
+
+#ifndef __NETPROG_PLATFORM_H__
+#define __NETPROG_PLATFORM_H__
+
+void netprog_reboot() {
+ wdt_enable(1);
+ while(1);
+}
+
+#endif
-% This is the sample topology file (chain topology), the node id should start with 0\r
-% The format is \r
-% nodeid x y\r
-\r
-0 0 0\r
-1 1 0\r
-2 2 0\r
-3 3 0\r
-4 4 0\r
-5 5 0\r
-6 6 0\r
-7 7 0\r
-8 8 0\r
-9 9 0\r
-10 10 0\r
-11 11 0\r
-12 12 0\r
-13 13 0\r
-14 14 0\r
-15 15 0\r
-16 16 0\r
-17 17 0\r
-18 18 0\r
-19 19 0\r
-20 20 0\r
-21 21 0\r
-22 22 0\r
-23 23 0\r
-24 24 0\r
-25 25 0\r
-26 26 0\r
-27 27 0\r
-28 28 0\r
-29 29 0\r
-30 30 0\r
-31 31 0\r
-32 32 0\r
-33 33 0\r
-34 34 0\r
-35 35 0\r
-36 36 0\r
-37 37 0\r
-38 38 0\r
-39 39 0\r
-40 40 0\r
-41 41 0\r
-42 42 0\r
-43 43 0\r
-44 44 0\r
-45 45 0\r
-46 46 0\r
-47 47 0\r
-48 48 0\r
-49 49 0\r
-50 50 0\r
-51 51 0\r
-52 52 0\r
-53 53 0\r
-54 54 0\r
-55 55 0\r
-56 56 0\r
-57 57 0\r
-58 58 0\r
-59 59 0\r
-60 60 0\r
-61 61 0\r
-62 62 0\r
-63 63 0\r
-64 64 0\r
-65 65 0\r
-66 66 0\r
-67 67 0\r
-68 68 0\r
-69 69 0\r
-70 70 0\r
+% This is the sample topology file (chain topology), the node id should start with 0
+% The format is
+% nodeid x y
+
+0 0 0
+1 1 0
+2 2 0
+3 3 0
+4 4 0
+5 5 0
+6 6 0
+7 7 0
+8 8 0
+9 9 0
+10 10 0
+11 11 0
+12 12 0
+13 13 0
+14 14 0
+15 15 0
+16 16 0
+17 17 0
+18 18 0
+19 19 0
+20 20 0
+21 21 0
+22 22 0
+23 23 0
+24 24 0
+25 25 0
+26 26 0
+27 27 0
+28 28 0
+29 29 0
+30 30 0
+31 31 0
+32 32 0
+33 33 0
+34 34 0
+35 35 0
+36 36 0
+37 37 0
+38 38 0
+39 39 0
+40 40 0
+41 41 0
+42 42 0
+43 43 0
+44 44 0
+45 45 0
+46 46 0
+47 47 0
+48 48 0
+49 49 0
+50 50 0
+51 51 0
+52 52 0
+53 53 0
+54 54 0
+55 55 0
+56 56 0
+57 57 0
+58 58 0
+59 59 0
+60 60 0
+61 61 0
+62 62 0
+63 63 0
+64 64 0
+65 65 0
+66 66 0
+67 67 0
+68 68 0
+69 69 0
+70 70 0
-/*\r
- * Copyright (c) 2005 Arch Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arch Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/** \r
- * @author Phil Buonadonna\r
- *\r
- */\r
-\r
-#include "Timer.h"\r
-\r
-configuration HilTimerMilliC\r
-{\r
- provides interface Init;\r
- provides interface Timer<TMilli> as TimerMilli[ uint8_t num ];\r
-}\r
-\r
-implementation\r
-{\r
- components new VirtualizeTimerC(TMilli,uniqueCount(UQ_TIMER_MILLI)) as VirtTimersMilli32;\r
- components new AlarmToTimerC(TMilli) as AlarmToTimerMilli32;\r
- components new HalPXA27xAlarmM(TMilli,2) as PhysAlarmMilli32;\r
- components HalPXA27xOSTimerMapC;\r
-\r
- enum {OST_CLIENT_ID = unique("PXA27xOSTimer.Resource")};\r
-\r
- Init = PhysAlarmMilli32;\r
-\r
- TimerMilli = VirtTimersMilli32.Timer;\r
-\r
- VirtTimersMilli32.TimerFrom -> AlarmToTimerMilli32.Timer;\r
-\r
- AlarmToTimerMilli32.Alarm -> PhysAlarmMilli32.Alarm;\r
-\r
- PhysAlarmMilli32.OSTInit -> HalPXA27xOSTimerMapC.Init;\r
- PhysAlarmMilli32.OSTChnl -> HalPXA27xOSTimerMapC.OSTChnl[OST_CLIENT_ID];\r
-\r
-}\r
+/*
+ * Copyright (c) 2005 Arch Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arch Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * @author Phil Buonadonna
+ *
+ */
+
+#include "Timer.h"
+
+configuration HilTimerMilliC
+{
+ provides interface Init;
+ provides interface Timer<TMilli> as TimerMilli[ uint8_t num ];
+}
+
+implementation
+{
+ components new VirtualizeTimerC(TMilli,uniqueCount(UQ_TIMER_MILLI)) as VirtTimersMilli32;
+ components new AlarmToTimerC(TMilli) as AlarmToTimerMilli32;
+ components new HalPXA27xAlarmM(TMilli,2) as PhysAlarmMilli32;
+ components HalPXA27xOSTimerMapC;
+
+ enum {OST_CLIENT_ID = unique("PXA27xOSTimer.Resource")};
+
+ Init = PhysAlarmMilli32;
+
+ TimerMilli = VirtTimersMilli32.Timer;
+
+ VirtTimersMilli32.TimerFrom -> AlarmToTimerMilli32.Timer;
+
+ AlarmToTimerMilli32.Alarm -> PhysAlarmMilli32.Alarm;
+
+ PhysAlarmMilli32.OSTInit -> HalPXA27xOSTimerMapC.Init;
+ PhysAlarmMilli32.OSTChnl -> HalPXA27xOSTimerMapC.OSTChnl[OST_CLIENT_ID];
+
+}
-/*\r
- * Copyright (c) 2005 Arch Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arch Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * @author Philip Buonadonna\r
- */\r
-configuration PlatformResetC {\r
- provides interface PlatformReset;\r
-}\r
-\r
-implementation {\r
- components PlatformC;\r
-\r
- PlatformReset = PlatformC;\r
-\r
-}\r
+/*
+ * Copyright (c) 2005 Arch Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arch Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * @author Philip Buonadonna
+ */
+configuration PlatformResetC {
+ provides interface PlatformReset;
+}
+
+implementation {
+ components PlatformC;
+
+ PlatformReset = PlatformC;
+
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-\r
-/**\r
- * \r
- * @author Phil Buonadonna\r
- */\r
-\r
-generic configuration HplCC2420AlarmC() \r
-{\r
-\r
- provides interface Init;\r
- //provides interface Alarm<T32khz,uint16_t> as Alarm32khz16;\r
- provides interface Alarm<T32khz,uint32_t> as Alarm32khz32;\r
-\r
-}\r
-\r
-implementation \r
-{\r
-\r
- components new Alarm32khzC();\r
-\r
- Init = Alarm32khzC;\r
- //Alarm32khz16 = Alarm32khzC.Alarm32khz16;\r
- Alarm32khz32 = Alarm32khzC.Alarm32khz32;\r
- \r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+
+/**
+ *
+ * @author Phil Buonadonna
+ */
+
+generic configuration HplCC2420AlarmC()
+{
+
+ provides interface Init;
+ //provides interface Alarm<T32khz,uint16_t> as Alarm32khz16;
+ provides interface Alarm<T32khz,uint32_t> as Alarm32khz32;
+
+}
+
+implementation
+{
+
+ components new Alarm32khzC();
+
+ Init = Alarm32khzC;
+ //Alarm32khz16 = Alarm32khzC.Alarm32khz16;
+ Alarm32khz32 = Alarm32khzC.Alarm32khz32;
+
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-configuration HplCC2420InterruptsC \r
-{\r
-\r
- provides interface GpioCapture as CaptureSFD;\r
- provides interface GpioInterrupt as InterruptCCA;\r
- provides interface GpioInterrupt as InterruptFIFOP;\r
-\r
-}\r
-\r
-implementation \r
-{\r
- components GeneralIOC;\r
- components new SoftCaptureC();\r
-\r
- CaptureSFD = SoftCaptureC.GpioCapture;\r
- InterruptCCA = GeneralIOC.GpioInterrupt[CC2420_CCA_PIN];\r
- InterruptFIFOP = GeneralIOC.GpioInterrupt[CC2420_FIFOP_PIN];\r
-\r
- SoftCaptureC.GpioInterrupt -> GeneralIOC.GpioInterrupt[CC2420_SFD_PIN]; \r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+configuration HplCC2420InterruptsC
+{
+
+ provides interface GpioCapture as CaptureSFD;
+ provides interface GpioInterrupt as InterruptCCA;
+ provides interface GpioInterrupt as InterruptFIFOP;
+
+}
+
+implementation
+{
+ components GeneralIOC;
+ components new SoftCaptureC();
+
+ CaptureSFD = SoftCaptureC.GpioCapture;
+ InterruptCCA = GeneralIOC.GpioInterrupt[CC2420_CCA_PIN];
+ InterruptFIFOP = GeneralIOC.GpioInterrupt[CC2420_FIFOP_PIN];
+
+ SoftCaptureC.GpioInterrupt -> GeneralIOC.GpioInterrupt[CC2420_SFD_PIN];
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * \r
- * @author Phil Buonadonna\r
- */\r
-configuration HplCC2420PinsC \r
-{\r
-\r
- provides interface GeneralIO as CCA;\r
- provides interface GeneralIO as CSN;\r
- provides interface GeneralIO as FIFO;\r
- provides interface GeneralIO as FIFOP;\r
- provides interface GeneralIO as RSTN;\r
- provides interface GeneralIO as SFD;\r
- provides interface GeneralIO as VREN;\r
-\r
-}\r
-\r
-implementation \r
-{\r
- components GeneralIOC;\r
- \r
- CCA = GeneralIOC.GeneralIO[CC2420_CCA_PIN];\r
- CSN = GeneralIOC.GeneralIO[CC2420_CSN_PIN];\r
- FIFO = GeneralIOC.GeneralIO[CC2420_FIFO_PIN];\r
- FIFOP = GeneralIOC.GeneralIO[CC2420_FIFOP_PIN];\r
- RSTN = GeneralIOC.GeneralIO[CC2420_RSTN_PIN];\r
- SFD = GeneralIOC.GeneralIO[CC2420_SFD_PIN];\r
- VREN = GeneralIOC.GeneralIO[CC2420_VREN_PIN];\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ *
+ * @author Phil Buonadonna
+ */
+configuration HplCC2420PinsC
+{
+
+ provides interface GeneralIO as CCA;
+ provides interface GeneralIO as CSN;
+ provides interface GeneralIO as FIFO;
+ provides interface GeneralIO as FIFOP;
+ provides interface GeneralIO as RSTN;
+ provides interface GeneralIO as SFD;
+ provides interface GeneralIO as VREN;
+
+}
+
+implementation
+{
+ components GeneralIOC;
+
+ CCA = GeneralIOC.GeneralIO[CC2420_CCA_PIN];
+ CSN = GeneralIOC.GeneralIO[CC2420_CSN_PIN];
+ FIFO = GeneralIOC.GeneralIO[CC2420_FIFO_PIN];
+ FIFOP = GeneralIOC.GeneralIO[CC2420_FIFOP_PIN];
+ RSTN = GeneralIOC.GeneralIO[CC2420_RSTN_PIN];
+ SFD = GeneralIOC.GeneralIO[CC2420_SFD_PIN];
+ VREN = GeneralIOC.GeneralIO[CC2420_VREN_PIN];
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- *\r
- * @author Phil Buonadonna\r
- */\r
-generic configuration HplCC2420SpiC() \r
-{\r
-\r
- provides interface Resource;\r
- provides interface SpiByte;\r
- provides interface SpiPacket;\r
- \r
-}\r
-\r
-implementation \r
-{\r
-\r
- enum {\r
- SPI_CLIENT_ID = unique("CC2420SpiClient")\r
- };\r
-\r
- components IM2CC2420SpiP;\r
- \r
- Resource = IM2CC2420SpiP.Resource[SPI_CLIENT_ID];\r
- SpiByte = IM2CC2420SpiP.SpiByte;\r
- SpiPacket = IM2CC2420SpiP.SpiPacket[SPI_CLIENT_ID];\r
-\r
- components PlatformP;\r
- IM2CC2420SpiP.Init <- PlatformP.InitL3;\r
-\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ *
+ * @author Phil Buonadonna
+ */
+generic configuration HplCC2420SpiC()
+{
+
+ provides interface Resource;
+ provides interface SpiByte;
+ provides interface SpiPacket;
+
+}
+
+implementation
+{
+
+ enum {
+ SPI_CLIENT_ID = unique("CC2420SpiClient")
+ };
+
+ components IM2CC2420SpiP;
+
+ Resource = IM2CC2420SpiP.Resource[SPI_CLIENT_ID];
+ SpiByte = IM2CC2420SpiP.SpiByte;
+ SpiPacket = IM2CC2420SpiP.SpiPacket[SPI_CLIENT_ID];
+
+ components PlatformP;
+ IM2CC2420SpiP.Init <- PlatformP.InitL3;
+
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- *\r
- * @author Phil Buonadonna\r
- */\r
-module IM2CC2420InitSpiP \r
-{\r
- \r
- provides interface Init;\r
- uses {\r
- interface HplPXA27xGPIOPin as SCLK;\r
- interface HplPXA27xGPIOPin as TXD;\r
- interface HplPXA27xGPIOPin as RXD;\r
- }\r
-}\r
-\r
-implementation \r
-{\r
- command error_t Init.init() {\r
- call SCLK.setGAFRpin(SSP3_SCLK_ALTFN);\r
- call SCLK.setGPDRbit(TRUE);\r
- call TXD.setGAFRpin(SSP3_TXD_ALTFN);\r
- call TXD.setGPDRbit(TRUE);\r
- call RXD.setGAFRpin(SSP3_RXD_ALTFN);\r
- call RXD.setGPDRbit(FALSE);\r
-\r
- return SUCCESS;\r
- }\r
- async event void SCLK.interruptGPIOPin() { return;} \r
- async event void TXD.interruptGPIOPin() { return;} \r
- async event void RXD.interruptGPIOPin() { return;} \r
-\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ *
+ * @author Phil Buonadonna
+ */
+module IM2CC2420InitSpiP
+{
+
+ provides interface Init;
+ uses {
+ interface HplPXA27xGPIOPin as SCLK;
+ interface HplPXA27xGPIOPin as TXD;
+ interface HplPXA27xGPIOPin as RXD;
+ }
+}
+
+implementation
+{
+ command error_t Init.init() {
+ call SCLK.setGAFRpin(SSP3_SCLK_ALTFN);
+ call SCLK.setGPDRbit(TRUE);
+ call TXD.setGAFRpin(SSP3_TXD_ALTFN);
+ call TXD.setGPDRbit(TRUE);
+ call RXD.setGAFRpin(SSP3_RXD_ALTFN);
+ call RXD.setGPDRbit(FALSE);
+
+ return SUCCESS;
+ }
+ async event void SCLK.interruptGPIOPin() { return;}
+ async event void TXD.interruptGPIOPin() { return;}
+ async event void RXD.interruptGPIOPin() { return;}
+
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- *\r
- * @author Phil Buonadonna\r
- */\r
-configuration IM2CC2420SpiP \r
-{\r
- \r
- provides interface Init;\r
- provides interface Resource[uint8_t id];\r
- provides interface SpiByte;\r
- provides interface SpiPacket[uint8_t instance];\r
-\r
-}\r
-\r
-implementation \r
-{\r
-\r
- components new SimpleFcfsArbiterC("CC2420SpiClient") as FcfsArbiterC;\r
- //components new HalPXA27xSpiDMAC(1,0x7,FALSE) as HalPXA27xSpiM; // 6.5 Mbps, 8bit width\r
- components new HalPXA27xSpiPioC(1,0x7,FALSE) as HalPXA27xSpiM; // 6.5 Mbps, 8bit width\r
- components IM2CC2420InitSpiP;\r
- components HplPXA27xSSP3C;\r
- components HplPXA27xDMAC;\r
- components HplPXA27xGPIOC;\r
- components PlatformP;\r
-\r
- Init = IM2CC2420InitSpiP;\r
- Init = HalPXA27xSpiM.Init;\r
-\r
- SpiByte = HalPXA27xSpiM;\r
- SpiPacket = HalPXA27xSpiM;\r
- Resource = FcfsArbiterC;\r
-\r
- IM2CC2420InitSpiP.SCLK -> HplPXA27xGPIOC.HplPXA27xGPIOPin[SSP3_SCLK];\r
- IM2CC2420InitSpiP.TXD -> HplPXA27xGPIOC.HplPXA27xGPIOPin[SSP3_TXD];\r
- IM2CC2420InitSpiP.RXD -> HplPXA27xGPIOC.HplPXA27xGPIOPin[SSP3_RXD];\r
-\r
- //HalPXA27xSpiM.RxDMA -> HplPXA27xDMAC.HplPXA27xDMAChnl[0];\r
- //HalPXA27xSpiM.TxDMA -> HplPXA27xDMAC.HplPXA27xDMAChnl[1];\r
- //HalPXA27xSpiM.SSPRxDMAInfo -> HplPXA27xSSP3C.SSPRxDMAInfo;\r
- //HalPXA27xSpiM.SSPTxDMAInfo -> HplPXA27xSSP3C.SSPTxDMAInfo;\r
-\r
- HalPXA27xSpiM.SSP -> HplPXA27xSSP3C.HplPXA27xSSP;\r
- \r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ *
+ * @author Phil Buonadonna
+ */
+configuration IM2CC2420SpiP
+{
+
+ provides interface Init;
+ provides interface Resource[uint8_t id];
+ provides interface SpiByte;
+ provides interface SpiPacket[uint8_t instance];
+
+}
+
+implementation
+{
+
+ components new SimpleFcfsArbiterC("CC2420SpiClient") as FcfsArbiterC;
+ //components new HalPXA27xSpiDMAC(1,0x7,FALSE) as HalPXA27xSpiM; // 6.5 Mbps, 8bit width
+ components new HalPXA27xSpiPioC(1,0x7,FALSE) as HalPXA27xSpiM; // 6.5 Mbps, 8bit width
+ components IM2CC2420InitSpiP;
+ components HplPXA27xSSP3C;
+ components HplPXA27xDMAC;
+ components HplPXA27xGPIOC;
+ components PlatformP;
+
+ Init = IM2CC2420InitSpiP;
+ Init = HalPXA27xSpiM.Init;
+
+ SpiByte = HalPXA27xSpiM;
+ SpiPacket = HalPXA27xSpiM;
+ Resource = FcfsArbiterC;
+
+ IM2CC2420InitSpiP.SCLK -> HplPXA27xGPIOC.HplPXA27xGPIOPin[SSP3_SCLK];
+ IM2CC2420InitSpiP.TXD -> HplPXA27xGPIOC.HplPXA27xGPIOPin[SSP3_TXD];
+ IM2CC2420InitSpiP.RXD -> HplPXA27xGPIOC.HplPXA27xGPIOPin[SSP3_RXD];
+
+ //HalPXA27xSpiM.RxDMA -> HplPXA27xDMAC.HplPXA27xDMAChnl[0];
+ //HalPXA27xSpiM.TxDMA -> HplPXA27xDMAC.HplPXA27xDMAChnl[1];
+ //HalPXA27xSpiM.SSPRxDMAInfo -> HplPXA27xSSP3C.SSPRxDMAInfo;
+ //HalPXA27xSpiM.SSPTxDMAInfo -> HplPXA27xSSP3C.SSPTxDMAInfo;
+
+ HalPXA27xSpiM.SSP -> HplPXA27xSSP3C.HplPXA27xSSP;
+
+}
-/* tab:4\r
- * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By\r
- * downloading, copying, installing or using the software you agree to\r
- * this license. If you do not agree to this license, do not download,\r
- * install, copy or use the software.\r
- *\r
- * Intel Open Source License \r
- *\r
- * Copyright (c) 2002 Intel Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * \r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * Neither the name of the Intel Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- * \r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * \r
- */\r
-\r
-/*\r
- *\r
- * Authors: Lama Nachman, Robert Adler\r
- */\r
-\r
-interface PMIC {\r
- /*\r
- * Set the voltage of the regulator controling the core\r
- *\r
- * @param core voltage specified in one of the supported trim values\r
- *\r
- * @return none\r
- */\r
- command error_t setCoreVoltage(uint8_t trimValue);\r
- command error_t shutDownLDOs();\r
- \r
- command error_t getBatteryVoltage(uint8_t *val);\r
- command error_t enableAutoCharging(bool enable);\r
- command error_t enableManualCharging(bool enable); \r
- command error_t chargingStatus(uint8_t *vBat, uint8_t *vChg, uint8_t *iChg); \r
-}\r
+/* tab:4
+ * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
+ * downloading, copying, installing or using the software you agree to
+ * this license. If you do not agree to this license, do not download,
+ * install, copy or use the software.
+ *
+ * Intel Open Source License
+ *
+ * Copyright (c) 2002 Intel Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ *
+ * Authors: Lama Nachman, Robert Adler
+ */
+
+interface PMIC {
+ /*
+ * Set the voltage of the regulator controling the core
+ *
+ * @param core voltage specified in one of the supported trim values
+ *
+ * @return none
+ */
+ command error_t setCoreVoltage(uint8_t trimValue);
+ command error_t shutDownLDOs();
+
+ command error_t getBatteryVoltage(uint8_t *val);
+ command error_t enableAutoCharging(bool enable);
+ command error_t enableManualCharging(bool enable);
+ command error_t chargingStatus(uint8_t *vBat, uint8_t *vChg, uint8_t *iChg);
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/* tab:4\r
- * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By\r
- * downloading, copying, installing or using the software you agree to\r
- * this license. If you do not agree to this license, do not download,\r
- * install, copy or use the software.\r
- *\r
- * Intel Open Source License \r
- *\r
- * Copyright (c) 2002 Intel Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * \r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * Neither the name of the Intel Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- * \r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * \r
- * \r
- */\r
-/*\r
- *\r
- * Authors: Lama Nachman, Robert Adler\r
- */\r
-configuration PMICC{\r
- provides{\r
- interface Init;\r
- interface PMIC;\r
- }\r
-}\r
-\r
-implementation{\r
- components PMICM;\r
- components new TimerMilliC();\r
- components HplPXA27xPI2CC, HplPXA27xGPIOC;\r
- components PlatformP;\r
-\r
- Init = PMICM;\r
- PMIC = PMICM;\r
-\r
- PMICM.Init <- PlatformP.InitL2;\r
-\r
- PMICM.chargeMonitorTimer -> TimerMilliC;\r
- PMICM.PMICGPIO -> HplPXA27xGPIOC.HplPXA27xGPIOPin[1];\r
- PMICM.PI2C -> HplPXA27xPI2CC.I2C;\r
- PMICM.PlatformReset -> PlatformP.PlatformReset;\r
-\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/* tab:4
+ * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
+ * downloading, copying, installing or using the software you agree to
+ * this license. If you do not agree to this license, do not download,
+ * install, copy or use the software.
+ *
+ * Intel Open Source License
+ *
+ * Copyright (c) 2002 Intel Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ */
+/*
+ *
+ * Authors: Lama Nachman, Robert Adler
+ */
+configuration PMICC{
+ provides{
+ interface Init;
+ interface PMIC;
+ }
+}
+
+implementation{
+ components PMICM;
+ components new TimerMilliC();
+ components HplPXA27xPI2CC, HplPXA27xGPIOC;
+ components PlatformP;
+
+ Init = PMICM;
+ PMIC = PMICM;
+
+ PMICM.Init <- PlatformP.InitL2;
+
+ PMICM.chargeMonitorTimer -> TimerMilliC;
+ PMICM.PMICGPIO -> HplPXA27xGPIOC.HplPXA27xGPIOPin[1];
+ PMICM.PI2C -> HplPXA27xPI2CC.I2C;
+ PMICM.PlatformReset -> PlatformP.PlatformReset;
+
+}
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arched Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arched Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/* tab:4\r
- * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By\r
- * downloading, copying, installing or using the software you agree to\r
- * this license. If you do not agree to this license, do not download,\r
- * install, copy or use the software.\r
- *\r
- * Intel Open Source License \r
- *\r
- * Copyright (c) 2002 Intel Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * \r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * Neither the name of the Intel Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- * \r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * \r
- * \r
- */\r
-\r
-/*\r
- *\r
- * Authors: Lama Nachman, Robert Adler\r
- */\r
-\r
-#define START_RADIO_LDO 1\r
-#define START_SENSOR_BOARD_LDO 1\r
-/*\r
- * VCC_MEM is connected to BUCK2 by default, make sure you have a board\r
- * that has the right resistor settings before disabling BUCK2\r
- */\r
-#define DISABLE_BUCK2 0 \r
-\r
-//#include "trace.h"\r
-#include "Timer.h"\r
-#include "pmic.h"\r
-\r
-module PMICM {\r
- provides{\r
- interface Init;\r
- interface PMIC;\r
- }\r
-\r
- uses interface Timer<TMilli> as chargeMonitorTimer;\r
- uses interface HplPXA27xGPIOPin as PMICGPIO;\r
- uses interface HplPXA27xI2C as PI2C;\r
- uses interface PlatformReset;\r
-}\r
-\r
-implementation {\r
-#include "pmic.h"\r
- \r
- bool gotReset;\r
- \r
- \r
- error_t readPMIC(uint8_t address, uint8_t *value, uint8_t numBytes){\r
- //send the PMIC the address that we want to read\r
- if(numBytes > 0){\r
- call PI2C.setIDBR(PMIC_SLAVE_ADDR<<1); \r
- call PI2C.setICR(call PI2C.getICR() | ICR_START);\r
- call PI2C.setICR(call PI2C.getICR() | ICR_TB); \r
- while(call PI2C.getICR() & ICR_TB);\r
- \r
- //actually send the address terminated with a STOP\r
- call PI2C.setIDBR(address);\r
- call PI2C.setICR(call PI2C.getICR() & ~ICR_START);\r
- call PI2C.setICR(call PI2C.getICR() | ICR_STOP);\r
- call PI2C.setICR(call PI2C.getICR() | ICR_TB); \r
- while(call PI2C.getICR() & ICR_TB);\r
- call PI2C.setICR(call PI2C.getICR() & ~ICR_STOP);\r
- \r
- //actually request the read of the data\r
- call PI2C.setIDBR(PMIC_SLAVE_ADDR<<1 | 1);\r
- call PI2C.setICR(call PI2C.getICR() | ICR_START); \r
- call PI2C.setICR(call PI2C.getICR() | ICR_TB);\r
- while(call PI2C.getICR() & ICR_TB);\r
- call PI2C.setICR(call PI2C.getICR() & ~ICR_START);\r
- \r
- //using Page Read Mode\r
- while (numBytes > 1){\r
- call PI2C.setICR(call PI2C.getICR() | ICR_TB); \r
- while(call PI2C.getICR() & ICR_TB);\r
- *value = call PI2C.getIDBR(); \r
- value++;\r
- numBytes--;\r
- }\r
- \r
- call PI2C.setICR(call PI2C.getICR() | ICR_STOP);\r
- call PI2C.setICR(call PI2C.getICR() | ICR_ACKNAK);\r
- call PI2C.setICR(call PI2C.getICR() | ICR_TB); \r
- while(call PI2C.getICR() & ICR_TB);\r
- *value = call PI2C.getIDBR(); \r
- call PI2C.setICR(call PI2C.getICR() & ~ICR_STOP); \r
- call PI2C.setICR(call PI2C.getICR() & ~ICR_ACKNAK);\r
- \r
- return SUCCESS;\r
- }\r
- else{\r
- return FAIL;\r
- }\r
- }\r
-\r
- error_t writePMIC(uint8_t address, uint8_t value){\r
- call PI2C.setIDBR(PMIC_SLAVE_ADDR<<1); \r
- call PI2C.setICR(call PI2C.getICR() | ICR_START); \r
- call PI2C.setICR(call PI2C.getICR() | ICR_TB); \r
- while(call PI2C.getICR() & ICR_TB);\r
- \r
- PIDBR = address;\r
- call PI2C.setICR(call PI2C.getICR() & ~ICR_START); \r
- call PI2C.setICR(call PI2C.getICR() | ICR_TB); \r
- while(call PI2C.getICR() & ICR_TB);\r
-\r
- PIDBR = value;\r
- call PI2C.setICR(call PI2C.getICR() | ICR_STOP); \r
- call PI2C.setICR(call PI2C.getICR() | ICR_TB); \r
- while(call PI2C.getICR() & ICR_TB);\r
- call PI2C.setICR(call PI2C.getICR() & ~ICR_STOP); PICR &= ~ICR_STOP;\r
-\r
- return SUCCESS;\r
- }\r
- \r
- void startLDOs() {\r
- //uint8_t temp;\r
- uint8_t oldVal, newVal;\r
-\r
-#if START_SENSOR_BOARD_LDO \r
- // TODO : Need to move out of here to sensor board functions\r
- readPMIC(PMIC_A_REG_CONTROL_1, &oldVal, 1);\r
- newVal = oldVal | ARC1_LDO10_EN | ARC1_LDO11_EN; // sensor board\r
- writePMIC(PMIC_A_REG_CONTROL_1, newVal);\r
-\r
- readPMIC(PMIC_B_REG_CONTROL_2, &oldVal, 1);\r
- newVal = oldVal | BRC2_LDO10_EN | BRC2_LDO11_EN;\r
- writePMIC(PMIC_B_REG_CONTROL_2, newVal);\r
-#endif\r
-\r
-#if START_RADIO_LDO\r
- // TODO : Move to radio start\r
- readPMIC(PMIC_B_REG_CONTROL_1, &oldVal, 1);\r
- newVal = oldVal | BRC1_LDO5_EN; \r
- writePMIC(PMIC_B_REG_CONTROL_1, newVal);\r
-#endif\r
-\r
-#if DISABLE_BUCK2 // Disable BUCK2 if VCC_MEM is not configured to use BUCK2\r
- readPMIC(PMIC_B_REG_CONTROL_1, &oldVal, 1);\r
- newVal = oldVal & ~BRC1_BUCK_EN;\r
- writePMIC(PMIC_B_REG_CONTROL_1, newVal);\r
-#endif\r
-\r
-#if 0\r
- // Configure above LDOs, Radio and sensor board LDOs to turn off in sleep\r
- // TODO : Sleep setting doesn't work\r
- temp = BSC1_LDO1(1) | BSC1_LDO2(1) | BSC1_LDO3(1) | BSC1_LDO4(1);\r
- writePMIC(PMIC_B_SLEEP_CONTROL_1, temp);\r
- temp = BSC2_LDO5(1) | BSC2_LDO7(1) | BSC2_LDO8(1) | BSC2_LDO9(1);\r
- writePMIC(PMIC_B_SLEEP_CONTROL_2, temp);\r
- temp = BSC3_LDO12(1); \r
- writePMIC(PMIC_B_SLEEP_CONTROL_3, temp);\r
-#endif\r
- }\r
-\r
- error_t startPMICstuff() {\r
- //command result_t StdControl.start(){ XXX-pb\r
- //init unit\r
- uint8_t val[3];\r
- //call PI2CInterrupt.enable(); XXX-pb\r
-\r
- }\r
-\r
- command error_t Init.init(){\r
- uint8_t val[3];\r
- PCFR |= PCFR_PI2C_EN; // Overrides GPIO settings on pins\r
- call PI2C.setICR(call PI2C.getICR() | (ICR_IUE | ICR_SCLE));\r
- atomic{\r
- gotReset=FALSE;\r
- } \r
-\r
- call PMICGPIO.setGAFRpin(0);\r
- call PMICGPIO.setGPDRbit(FALSE);\r
- call PMICGPIO.setGFERbit(TRUE);\r
- /*\r
- * Reset the watchdog, switch it to an interrupt, so we can disable it\r
- * Ignore SLEEP_N pin, enable H/W reset via button \r
- */\r
- writePMIC(PMIC_SYS_CONTROL_A, \r
- SCA_RESET_WDOG | SCA_WDOG_ACTION | SCA_HWRES_EN);\r
-\r
- // Disable all interrupts from PMIC except for ONKEY button\r
- writePMIC(PMIC_IRQ_MASK_A, ~IMA_ONKEY_N);\r
- writePMIC(PMIC_IRQ_MASK_B, 0xFF);\r
- writePMIC(PMIC_IRQ_MASK_C, 0xFF);\r
- \r
- //read out the EVENT registers so that we can receive interrupts\r
- readPMIC(PMIC_EVENTS, val, 3);\r
-\r
- // Set default core voltage to 0.85 V\r
-#ifdef PXA27X_13M\r
- //P85 is not reliable, using P95\r
- call PMIC.setCoreVoltage(B2R1_TRIM_P95_V);\r
-#else\r
- call PMIC.setCoreVoltage(B2R1_TRIM_1_25_V);\r
-#endif\r
- startLDOs();\r
- return SUCCESS;\r
- }\r
-\r
- async event void PI2C.interruptI2C() { //PI2CInterrupt.fired(){\r
- uint32_t status, update=0;\r
- status = call PI2C.getISR(); //PISR;\r
- if(status & ISR_ITE){\r
- update |= ISR_ITE;\r
- //trace(DBG_USR1,"sent data");\r
- }\r
-\r
- if(status & ISR_BED){\r
- update |= ISR_BED;\r
- //trace(DBG_USR1,"bus error");\r
- }\r
- call PI2C.setISAR(update); //PISR = update;\r
- }\r
- \r
- async event void PMICGPIO.interruptGPIOPin(){\r
- uint8_t events[3];\r
- bool localGotReset;\r
- \r
- //call PMICGPIO.call PMICInterrupt.clear(); XXX autocleard by GPIO module\r
- \r
- readPMIC(PMIC_EVENTS, events, 3);\r
- \r
- if(events[EVENTS_A_OFFSET] & EA_ONKEY_N){\r
- atomic{\r
- localGotReset = gotReset;\r
- }\r
- if(localGotReset==TRUE){\r
- call PlatformReset.reset();\r
- }\r
- else{\r
- atomic{\r
- gotReset=TRUE;\r
- }\r
- }\r
- }\r
- else{\r
- //trace(DBG_USR1,"PMIC EVENTs =%#x %#x %#x\r\n",events[0], events[1], events[2]);\r
- }\r
- }\r
-\r
- /*\r
- * The Buck2 controls the core voltage, set to appropriate trim value\r
- */\r
- command error_t PMIC.setCoreVoltage(uint8_t trimValue) {\r
- writePMIC(PMIC_BUCK2_REG1, (trimValue & B2R1_TRIM_MASK) | B2R1_GO);\r
- return SUCCESS;\r
- }\r
- \r
- command error_t PMIC.shutDownLDOs() {\r
- uint8_t temp;\r
- uint8_t oldVal, newVal;\r
- /* \r
- * Shut down all LDOs that are not controlled by the sleep mode\r
- * Note, we assume here the LDO10 & LDO11 (sensor board) will be off\r
- * Should be moved to sensor board control\r
- */\r
-\r
- // LDO1, LDO4, LDO6, LDO7, LDO8, LDO9, LDO10, LDO 11, LDO13, LDO14\r
-\r
- readPMIC(PMIC_A_REG_CONTROL_1, &oldVal, 1);\r
- newVal = oldVal & ~ARC1_LDO13_EN & ~ARC1_LDO14_EN;\r
- newVal = newVal & ~ARC1_LDO10_EN & ~ARC1_LDO11_EN; // sensor board\r
- writePMIC(PMIC_A_REG_CONTROL_1, newVal);\r
-\r
- readPMIC(PMIC_B_REG_CONTROL_1, &oldVal, 1);\r
- newVal = oldVal & ~BRC1_LDO1_EN & ~BRC1_LDO4_EN & ~BRC1_LDO5_EN &\r
- ~BRC1_LDO6_EN & ~BRC1_LDO7_EN;\r
- writePMIC(PMIC_B_REG_CONTROL_1, newVal);\r
-\r
- readPMIC(PMIC_B_REG_CONTROL_2, &oldVal, 1);\r
- newVal = oldVal & ~BRC2_LDO8_EN & ~BRC2_LDO9_EN & ~BRC2_LDO10_EN &\r
- ~BRC2_LDO11_EN & ~BRC2_LDO14_EN & ~BRC2_SIMCP_EN;\r
- writePMIC(PMIC_B_REG_CONTROL_2, newVal);\r
- \r
- return SUCCESS;\r
- }\r
-\r
- error_t getPMICADCVal(uint8_t channel, uint8_t *val){\r
- uint8_t oldval;\r
- error_t rval;\r
- \r
- //read out the old value so that we can reset at the end\r
- rval = readPMIC(PMIC_ADC_MAN_CONTROL, &oldval,1);\r
- if (rval == SUCCESS) {\r
- rval = writePMIC(PMIC_ADC_MAN_CONTROL, PMIC_AMC_ADCMUX(channel) | \r
- PMIC_AMC_MAN_CONV | PMIC_AMC_LDO_INT_Enable);\r
- }\r
- if (rval == SUCCESS) {\r
- rval = readPMIC(PMIC_MAN_RES,val,1);\r
- }\r
- if (rval == SUCCESS) {\r
- //reset to old state\r
- rval = writePMIC(PMIC_ADC_MAN_CONTROL, oldval);\r
- }\r
-\r
- return rval;\r
- }\r
-\r
- command error_t PMIC.getBatteryVoltage(uint8_t *val){\r
- //for now, let's use the manual conversion mode\r
- return getPMICADCVal(0, val);\r
- }\r
- \r
- command error_t PMIC.chargingStatus(uint8_t *vBat, uint8_t *vChg, \r
- uint8_t *iChg){\r
- getPMICADCVal(0, vBat);\r
- getPMICADCVal(2, vChg);\r
- getPMICADCVal(1, iChg);\r
- return SUCCESS;\r
- } \r
- \r
- command error_t PMIC.enableAutoCharging(bool enable){\r
- return SUCCESS;\r
- }\r
- \r
- command error_t PMIC.enableManualCharging(bool enable){\r
- //just turn on or off the LED for now!!\r
- uint8_t val;\r
- \r
- if(enable){\r
- //want to turn on the charger\r
- getPMICADCVal(2, &val);\r
- //if charger is present due some stuff...75 should be 4.65V or so \r
- if(val > 75 ) {\r
- //trace(DBG_USR1,"Charger Voltage is %.3fV...enabling charger...\r\n", ((val*6) * .01035));\r
- //write the total timeout to be 8 hours\r
- writePMIC(PMIC_TCTR_CONTROL,8);\r
- //enable the charger at 100mA and 4.35V\r
- writePMIC(PMIC_CHARGE_CONTROL,PMIC_CC_CHARGE_ENABLE | PMIC_CC_ISET(1) | PMIC_CC_VSET(7));\r
- //turn on the LED\r
- writePMIC(PMIC_LED1_CONTROL,0x80);\r
- //start a timer to monitor our progress every 5 minutes!\r
- call chargeMonitorTimer.startPeriodic(300000);\r
- }\r
- else{\r
- //trace(DBG_USR1,"Charger Voltage is %.3fV...charger not enabled\r\n", ((val*6) * .01035));\r
- }\r
- }\r
- else{\r
- //turn off the charger and the LED\r
- call PMIC.getBatteryVoltage(&val);\r
- //trace(DBG_USR1,"Disabling Charger...Battery Voltage is %.3fV\r\n", (val * .01035) + 2.65);\r
- //disable everything that we enabled\r
- writePMIC(PMIC_TCTR_CONTROL,0);\r
- writePMIC(PMIC_CHARGE_CONTROL,0);\r
- writePMIC(PMIC_LED1_CONTROL,0x00);\r
- }\r
- return SUCCESS; \r
- } \r
- \r
- event void chargeMonitorTimer.fired(){\r
- uint8_t val;\r
- call PMIC.getBatteryVoltage(&val);\r
- //stop when vBat>4V\r
- if(val>130){\r
- call PMIC.enableManualCharging(FALSE);\r
- call chargeMonitorTimer.stop();\r
- }\r
- return;\r
- }\r
-\r
-\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arched Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arched Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/* tab:4
+ * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
+ * downloading, copying, installing or using the software you agree to
+ * this license. If you do not agree to this license, do not download,
+ * install, copy or use the software.
+ *
+ * Intel Open Source License
+ *
+ * Copyright (c) 2002 Intel Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ */
+
+/*
+ *
+ * Authors: Lama Nachman, Robert Adler
+ */
+
+#define START_RADIO_LDO 1
+#define START_SENSOR_BOARD_LDO 1
+/*
+ * VCC_MEM is connected to BUCK2 by default, make sure you have a board
+ * that has the right resistor settings before disabling BUCK2
+ */
+#define DISABLE_BUCK2 0
+
+//#include "trace.h"
+#include "Timer.h"
+#include "pmic.h"
+
+module PMICM {
+ provides{
+ interface Init;
+ interface PMIC;
+ }
+
+ uses interface Timer<TMilli> as chargeMonitorTimer;
+ uses interface HplPXA27xGPIOPin as PMICGPIO;
+ uses interface HplPXA27xI2C as PI2C;
+ uses interface PlatformReset;
+}
+
+implementation {
+#include "pmic.h"
+
+ bool gotReset;
+
+
+ error_t readPMIC(uint8_t address, uint8_t *value, uint8_t numBytes){
+ //send the PMIC the address that we want to read
+ if(numBytes > 0){
+ call PI2C.setIDBR(PMIC_SLAVE_ADDR<<1);
+ call PI2C.setICR(call PI2C.getICR() | ICR_START);
+ call PI2C.setICR(call PI2C.getICR() | ICR_TB);
+ while(call PI2C.getICR() & ICR_TB);
+
+ //actually send the address terminated with a STOP
+ call PI2C.setIDBR(address);
+ call PI2C.setICR(call PI2C.getICR() & ~ICR_START);
+ call PI2C.setICR(call PI2C.getICR() | ICR_STOP);
+ call PI2C.setICR(call PI2C.getICR() | ICR_TB);
+ while(call PI2C.getICR() & ICR_TB);
+ call PI2C.setICR(call PI2C.getICR() & ~ICR_STOP);
+
+ //actually request the read of the data
+ call PI2C.setIDBR(PMIC_SLAVE_ADDR<<1 | 1);
+ call PI2C.setICR(call PI2C.getICR() | ICR_START);
+ call PI2C.setICR(call PI2C.getICR() | ICR_TB);
+ while(call PI2C.getICR() & ICR_TB);
+ call PI2C.setICR(call PI2C.getICR() & ~ICR_START);
+
+ //using Page Read Mode
+ while (numBytes > 1){
+ call PI2C.setICR(call PI2C.getICR() | ICR_TB);
+ while(call PI2C.getICR() & ICR_TB);
+ *value = call PI2C.getIDBR();
+ value++;
+ numBytes--;
+ }
+
+ call PI2C.setICR(call PI2C.getICR() | ICR_STOP);
+ call PI2C.setICR(call PI2C.getICR() | ICR_ACKNAK);
+ call PI2C.setICR(call PI2C.getICR() | ICR_TB);
+ while(call PI2C.getICR() & ICR_TB);
+ *value = call PI2C.getIDBR();
+ call PI2C.setICR(call PI2C.getICR() & ~ICR_STOP);
+ call PI2C.setICR(call PI2C.getICR() & ~ICR_ACKNAK);
+
+ return SUCCESS;
+ }
+ else{
+ return FAIL;
+ }
+ }
+
+ error_t writePMIC(uint8_t address, uint8_t value){
+ call PI2C.setIDBR(PMIC_SLAVE_ADDR<<1);
+ call PI2C.setICR(call PI2C.getICR() | ICR_START);
+ call PI2C.setICR(call PI2C.getICR() | ICR_TB);
+ while(call PI2C.getICR() & ICR_TB);
+
+ PIDBR = address;
+ call PI2C.setICR(call PI2C.getICR() & ~ICR_START);
+ call PI2C.setICR(call PI2C.getICR() | ICR_TB);
+ while(call PI2C.getICR() & ICR_TB);
+
+ PIDBR = value;
+ call PI2C.setICR(call PI2C.getICR() | ICR_STOP);
+ call PI2C.setICR(call PI2C.getICR() | ICR_TB);
+ while(call PI2C.getICR() & ICR_TB);
+ call PI2C.setICR(call PI2C.getICR() & ~ICR_STOP); PICR &= ~ICR_STOP;
+
+ return SUCCESS;
+ }
+
+ void startLDOs() {
+ //uint8_t temp;
+ uint8_t oldVal, newVal;
+
+#if START_SENSOR_BOARD_LDO
+ // TODO : Need to move out of here to sensor board functions
+ readPMIC(PMIC_A_REG_CONTROL_1, &oldVal, 1);
+ newVal = oldVal | ARC1_LDO10_EN | ARC1_LDO11_EN; // sensor board
+ writePMIC(PMIC_A_REG_CONTROL_1, newVal);
+
+ readPMIC(PMIC_B_REG_CONTROL_2, &oldVal, 1);
+ newVal = oldVal | BRC2_LDO10_EN | BRC2_LDO11_EN;
+ writePMIC(PMIC_B_REG_CONTROL_2, newVal);
+#endif
+
+#if START_RADIO_LDO
+ // TODO : Move to radio start
+ readPMIC(PMIC_B_REG_CONTROL_1, &oldVal, 1);
+ newVal = oldVal | BRC1_LDO5_EN;
+ writePMIC(PMIC_B_REG_CONTROL_1, newVal);
+#endif
+
+#if DISABLE_BUCK2 // Disable BUCK2 if VCC_MEM is not configured to use BUCK2
+ readPMIC(PMIC_B_REG_CONTROL_1, &oldVal, 1);
+ newVal = oldVal & ~BRC1_BUCK_EN;
+ writePMIC(PMIC_B_REG_CONTROL_1, newVal);
+#endif
+
+#if 0
+ // Configure above LDOs, Radio and sensor board LDOs to turn off in sleep
+ // TODO : Sleep setting doesn't work
+ temp = BSC1_LDO1(1) | BSC1_LDO2(1) | BSC1_LDO3(1) | BSC1_LDO4(1);
+ writePMIC(PMIC_B_SLEEP_CONTROL_1, temp);
+ temp = BSC2_LDO5(1) | BSC2_LDO7(1) | BSC2_LDO8(1) | BSC2_LDO9(1);
+ writePMIC(PMIC_B_SLEEP_CONTROL_2, temp);
+ temp = BSC3_LDO12(1);
+ writePMIC(PMIC_B_SLEEP_CONTROL_3, temp);
+#endif
+ }
+
+ error_t startPMICstuff() {
+ //command result_t StdControl.start(){ XXX-pb
+ //init unit
+ uint8_t val[3];
+ //call PI2CInterrupt.enable(); XXX-pb
+
+ }
+
+ command error_t Init.init(){
+ uint8_t val[3];
+ PCFR |= PCFR_PI2C_EN; // Overrides GPIO settings on pins
+ call PI2C.setICR(call PI2C.getICR() | (ICR_IUE | ICR_SCLE));
+ atomic{
+ gotReset=FALSE;
+ }
+
+ call PMICGPIO.setGAFRpin(0);
+ call PMICGPIO.setGPDRbit(FALSE);
+ call PMICGPIO.setGFERbit(TRUE);
+ /*
+ * Reset the watchdog, switch it to an interrupt, so we can disable it
+ * Ignore SLEEP_N pin, enable H/W reset via button
+ */
+ writePMIC(PMIC_SYS_CONTROL_A,
+ SCA_RESET_WDOG | SCA_WDOG_ACTION | SCA_HWRES_EN);
+
+ // Disable all interrupts from PMIC except for ONKEY button
+ writePMIC(PMIC_IRQ_MASK_A, ~IMA_ONKEY_N);
+ writePMIC(PMIC_IRQ_MASK_B, 0xFF);
+ writePMIC(PMIC_IRQ_MASK_C, 0xFF);
+
+ //read out the EVENT registers so that we can receive interrupts
+ readPMIC(PMIC_EVENTS, val, 3);
+
+ // Set default core voltage to 0.85 V
+#ifdef PXA27X_13M
+ //P85 is not reliable, using P95
+ call PMIC.setCoreVoltage(B2R1_TRIM_P95_V);
+#else
+ call PMIC.setCoreVoltage(B2R1_TRIM_1_25_V);
+#endif
+ startLDOs();
+ return SUCCESS;
+ }
+
+ async event void PI2C.interruptI2C() { //PI2CInterrupt.fired(){
+ uint32_t status, update=0;
+ status = call PI2C.getISR(); //PISR;
+ if(status & ISR_ITE){
+ update |= ISR_ITE;
+ //trace(DBG_USR1,"sent data");
+ }
+
+ if(status & ISR_BED){
+ update |= ISR_BED;
+ //trace(DBG_USR1,"bus error");
+ }
+ call PI2C.setISAR(update); //PISR = update;
+ }
+
+ async event void PMICGPIO.interruptGPIOPin(){
+ uint8_t events[3];
+ bool localGotReset;
+
+ //call PMICGPIO.call PMICInterrupt.clear(); XXX autocleard by GPIO module
+
+ readPMIC(PMIC_EVENTS, events, 3);
+
+ if(events[EVENTS_A_OFFSET] & EA_ONKEY_N){
+ atomic{
+ localGotReset = gotReset;
+ }
+ if(localGotReset==TRUE){
+ call PlatformReset.reset();
+ }
+ else{
+ atomic{
+ gotReset=TRUE;
+ }
+ }
+ }
+ else{
+ //trace(DBG_USR1,"PMIC EVENTs =%#x %#x %#x\r\n",events[0], events[1], events[2]);
+ }
+ }
+
+ /*
+ * The Buck2 controls the core voltage, set to appropriate trim value
+ */
+ command error_t PMIC.setCoreVoltage(uint8_t trimValue) {
+ writePMIC(PMIC_BUCK2_REG1, (trimValue & B2R1_TRIM_MASK) | B2R1_GO);
+ return SUCCESS;
+ }
+
+ command error_t PMIC.shutDownLDOs() {
+ uint8_t temp;
+ uint8_t oldVal, newVal;
+ /*
+ * Shut down all LDOs that are not controlled by the sleep mode
+ * Note, we assume here the LDO10 & LDO11 (sensor board) will be off
+ * Should be moved to sensor board control
+ */
+
+ // LDO1, LDO4, LDO6, LDO7, LDO8, LDO9, LDO10, LDO 11, LDO13, LDO14
+
+ readPMIC(PMIC_A_REG_CONTROL_1, &oldVal, 1);
+ newVal = oldVal & ~ARC1_LDO13_EN & ~ARC1_LDO14_EN;
+ newVal = newVal & ~ARC1_LDO10_EN & ~ARC1_LDO11_EN; // sensor board
+ writePMIC(PMIC_A_REG_CONTROL_1, newVal);
+
+ readPMIC(PMIC_B_REG_CONTROL_1, &oldVal, 1);
+ newVal = oldVal & ~BRC1_LDO1_EN & ~BRC1_LDO4_EN & ~BRC1_LDO5_EN &
+ ~BRC1_LDO6_EN & ~BRC1_LDO7_EN;
+ writePMIC(PMIC_B_REG_CONTROL_1, newVal);
+
+ readPMIC(PMIC_B_REG_CONTROL_2, &oldVal, 1);
+ newVal = oldVal & ~BRC2_LDO8_EN & ~BRC2_LDO9_EN & ~BRC2_LDO10_EN &
+ ~BRC2_LDO11_EN & ~BRC2_LDO14_EN & ~BRC2_SIMCP_EN;
+ writePMIC(PMIC_B_REG_CONTROL_2, newVal);
+
+ return SUCCESS;
+ }
+
+ error_t getPMICADCVal(uint8_t channel, uint8_t *val){
+ uint8_t oldval;
+ error_t rval;
+
+ //read out the old value so that we can reset at the end
+ rval = readPMIC(PMIC_ADC_MAN_CONTROL, &oldval,1);
+ if (rval == SUCCESS) {
+ rval = writePMIC(PMIC_ADC_MAN_CONTROL, PMIC_AMC_ADCMUX(channel) |
+ PMIC_AMC_MAN_CONV | PMIC_AMC_LDO_INT_Enable);
+ }
+ if (rval == SUCCESS) {
+ rval = readPMIC(PMIC_MAN_RES,val,1);
+ }
+ if (rval == SUCCESS) {
+ //reset to old state
+ rval = writePMIC(PMIC_ADC_MAN_CONTROL, oldval);
+ }
+
+ return rval;
+ }
+
+ command error_t PMIC.getBatteryVoltage(uint8_t *val){
+ //for now, let's use the manual conversion mode
+ return getPMICADCVal(0, val);
+ }
+
+ command error_t PMIC.chargingStatus(uint8_t *vBat, uint8_t *vChg,
+ uint8_t *iChg){
+ getPMICADCVal(0, vBat);
+ getPMICADCVal(2, vChg);
+ getPMICADCVal(1, iChg);
+ return SUCCESS;
+ }
+
+ command error_t PMIC.enableAutoCharging(bool enable){
+ return SUCCESS;
+ }
+
+ command error_t PMIC.enableManualCharging(bool enable){
+ //just turn on or off the LED for now!!
+ uint8_t val;
+
+ if(enable){
+ //want to turn on the charger
+ getPMICADCVal(2, &val);
+ //if charger is present due some stuff...75 should be 4.65V or so
+ if(val > 75 ) {
+ //trace(DBG_USR1,"Charger Voltage is %.3fV...enabling charger...\r\n", ((val*6) * .01035));
+ //write the total timeout to be 8 hours
+ writePMIC(PMIC_TCTR_CONTROL,8);
+ //enable the charger at 100mA and 4.35V
+ writePMIC(PMIC_CHARGE_CONTROL,PMIC_CC_CHARGE_ENABLE | PMIC_CC_ISET(1) | PMIC_CC_VSET(7));
+ //turn on the LED
+ writePMIC(PMIC_LED1_CONTROL,0x80);
+ //start a timer to monitor our progress every 5 minutes!
+ call chargeMonitorTimer.startPeriodic(300000);
+ }
+ else{
+ //trace(DBG_USR1,"Charger Voltage is %.3fV...charger not enabled\r\n", ((val*6) * .01035));
+ }
+ }
+ else{
+ //turn off the charger and the LED
+ call PMIC.getBatteryVoltage(&val);
+ //trace(DBG_USR1,"Disabling Charger...Battery Voltage is %.3fV\r\n", (val * .01035) + 2.65);
+ //disable everything that we enabled
+ writePMIC(PMIC_TCTR_CONTROL,0);
+ writePMIC(PMIC_CHARGE_CONTROL,0);
+ writePMIC(PMIC_LED1_CONTROL,0x00);
+ }
+ return SUCCESS;
+ }
+
+ event void chargeMonitorTimer.fired(){
+ uint8_t val;
+ call PMIC.getBatteryVoltage(&val);
+ //stop when vBat>4V
+ if(val>130){
+ call PMIC.enableManualCharging(FALSE);
+ call chargeMonitorTimer.stop();
+ }
+ return;
+ }
+
+
+}
-OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",\r
- "elf32-littlearm")\r
-OUTPUT_ARCH(arm)\r
-MEMORY\r
-{\r
- text (rx) : ORIGIN = 0, LENGTH = 64M\r
- data (rw!x) : ORIGIN = 0x5c000000, LENGTH = 256K\r
-}\r
-SECTIONS\r
-{\r
- .text :\r
- {\r
- *(.vectors)\r
- *(.text .stub .text.* .gnu.linkonce.t.*)\r
- *(.rodata.*)\r
- *(.rodata) \r
- /* .gnu.warning sections are handled specially by elf32.em. */\r
- *(.gnu.warning)\r
- *(.glue_7t) *(.glue_7)\r
- KEEP (*(.fini))\r
- } >text\r
- PROVIDE (__etext = .);\r
- PROVIDE (_etext = .);\r
- PROVIDE (etext = .);\r
- .data : AT (ADDR(.text) + SIZEOF(.text))\r
- {\r
- __data_start = . ;\r
- *(.data .data.* .gnu.linkonce.d.*)\r
- *(.gnu.linkonce.d*)\r
- _edata = .;\r
- PROVIDE (edata = .);\r
- } > data\r
- .bss SIZEOF(.data) + ADDR(.data) :\r
- {\r
- __bss_start = .;\r
- __bss_start__ = .;\r
- *(.dynbss)\r
- *(.bss .bss.* .gnu.linkonce.b.*)\r
- *(COMMON)\r
- _end = .;\r
- _bss_end__ = . ; __bss_end__ = . ; __end__ = . ;\r
- PROVIDE (end = .);\r
- } >data\r
- __data_load_start = LOADADDR(.data);\r
- __data_load_end = __data_load_start + SIZEOF(.data);\r
- /* Stabs debugging sections. */\r
- .stab 0 : { *(.stab) }\r
- .stabstr 0 : { *(.stabstr) }\r
- .stab.excl 0 : { *(.stab.excl) }\r
- .stab.exclstr 0 : { *(.stab.exclstr) }\r
- .stab.index 0 : { *(.stab.index) }\r
- .stab.indexstr 0 : { *(.stab.indexstr) }\r
- .comment 0 : { *(.comment) }\r
- /* DWARF debug sections.\r
- Symbols in the DWARF debugging sections are relative to the beginning\r
- of the section so we begin them at 0. */\r
- /* DWARF 1 */\r
- .debug 0 : { *(.debug) }\r
- .line 0 : { *(.line) }\r
- /* GNU DWARF 1 extensions */\r
- .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
- .debug_sfnames 0 : { *(.debug_sfnames) }\r
- /* DWARF 1.1 and DWARF 2 */\r
- .debug_aranges 0 : { *(.debug_aranges) }\r
- .debug_pubnames 0 : { *(.debug_pubnames) }\r
- /* DWARF 2 */\r
- .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
- .debug_abbrev 0 : { *(.debug_abbrev) }\r
- .debug_line 0 : { *(.debug_line) }\r
- .debug_frame 0 : { *(.debug_frame) }\r
- .debug_str 0 : { *(.debug_str) }\r
- .debug_loc 0 : { *(.debug_loc) }\r
- .debug_macinfo 0 : { *(.debug_macinfo) }\r
- /* SGI/MIPS DWARF 2 extensions */\r
- .debug_weaknames 0 : { *(.debug_weaknames) }\r
- .debug_funcnames 0 : { *(.debug_funcnames) }\r
- .debug_typenames 0 : { *(.debug_typenames) }\r
- .debug_varnames 0 : { *(.debug_varnames) }\r
- .stack 0x80000 :\r
- {\r
- _stack = .;\r
- *(.stack)\r
- }\r
- /DISCARD/ : { *(.note.GNU-stack) }\r
-}\r
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
+ "elf32-littlearm")
+OUTPUT_ARCH(arm)
+MEMORY
+{
+ text (rx) : ORIGIN = 0, LENGTH = 64M
+ data (rw!x) : ORIGIN = 0x5c000000, LENGTH = 256K
+}
+SECTIONS
+{
+ .text :
+ {
+ *(.vectors)
+ *(.text .stub .text.* .gnu.linkonce.t.*)
+ *(.rodata.*)
+ *(.rodata)
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ *(.glue_7t) *(.glue_7)
+ KEEP (*(.fini))
+ } >text
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+ .data : AT (ADDR(.text) + SIZEOF(.text))
+ {
+ __data_start = . ;
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.gnu.linkonce.d*)
+ _edata = .;
+ PROVIDE (edata = .);
+ } > data
+ .bss SIZEOF(.data) + ADDR(.data) :
+ {
+ __bss_start = .;
+ __bss_start__ = .;
+ *(.dynbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ _end = .;
+ _bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
+ PROVIDE (end = .);
+ } >data
+ __data_load_start = LOADADDR(.data);
+ __data_load_end = __data_load_start + SIZEOF(.data);
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ .stack 0x80000 :
+ {
+ _stack = .;
+ *(.stack)
+ }
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
-/* tab:4\r
- * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By\r
- * downloading, copying, installing or using the software you agree to\r
- * this license. If you do not agree to this license, do not download,\r
- * install, copy or use the software.\r
- *\r
- * Intel Open Source License \r
- *\r
- * Copyright (c) 2002 Intel Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * \r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * Neither the name of the Intel Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- * \r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * \r
- * \r
- */\r
-/*\r
- *\r
- * Authors: Phil Buonadonna,David Gay\r
- * Date last modified: $Revision$\r
- *\r
- */\r
- \r
- .equ ARM_CPSR_MODE_MASK,(0x0000001F)\r
- .equ ARM_CPSR_INT_MASK,(0x000000C0)\r
- .equ ARM_CPSR_COND_MASK,(0xF8000000)\r
- \r
- .equ ARM_CPSR_MODE_USR,(0x10)\r
- .equ ARM_CPSR_MODE_FIQ,(0x11)\r
- .equ ARM_CPSR_MODE_IRQ,(0x12)\r
- .equ ARM_CPSR_MODE_SVC,(0x13)\r
- .equ ARM_CPSR_MODE_ABT,(0x17)\r
- .equ ARM_CPSR_MODE_UND,(0x1B)\r
- .equ ARM_CPSR_MODE_SYS,(0x1F)\r
-\r
- .equ ARM_CPSR_BIT_N,(0x80000000)\r
- .equ ARM_CPSR_BIT_Z,(0x40000000)\r
- .equ ARM_CPSR_BIT_C,(0x20000000)\r
- .equ ARM_CPSR_BIT_V,(0x10000000)\r
- .equ ARM_CPSR_BIT_Q,(0x08000000)\r
- \r
- .equ ARM_CPSR_BIT_I,(0x00000080)\r
- .equ ARM_CPSR_BIT_F,(0x00000040)\r
- .equ ARM_CPRS_BIT_T,(0x00000020)\r
-\r
- .equ _TOS_STACK_SIZE,(0x400) @ TinyOS Exception stack sizes\r
- .equ _TOS_ISRAM_PHYSBASE,(0x5C000000) @ Internal SRAM on PXA27X\r
- .text\r
- \r
-.globl start\r
-start:\r
- mrs r0, CPSR\r
- bic r0, r0, #ARM_CPSR_MODE_MASK\r
- orr r0, r0, #(ARM_CPSR_MODE_SVC | ARM_CPSR_INT_MASK)\r
- msr cpsr_cf, r0\r
- \r
- /* Initialize the stack pointers for all modes */\r
- mov r0,#_TOS_ISRAM_PHYSBASE\r
- ldr r2, =(256*1024 - 4) @ and go to the last slot (256K - 4)\r
- add r2,r2,r0\r
- \r
- mov r0, #ARM_CPSR_MODE_ABT \r
- msr CPSR_c, R0\r
- mov sp, r2\r
- sub r2, r2, #_TOS_STACK_SIZE\r
-\r
- mov r0, #ARM_CPSR_MODE_UND \r
- msr CPSR_c, R0\r
- mov sp, r2\r
- sub r2, r2, #_TOS_STACK_SIZE\r
- \r
- mov r0, #ARM_CPSR_MODE_FIQ \r
- msr CPSR_c, R0\r
- mov sp, r2\r
- sub r2, r2, #_TOS_STACK_SIZE\r
-\r
- mov r0, #ARM_CPSR_MODE_IRQ \r
- msr CPSR_c, R0\r
- mov sp, r2\r
- sub r2, r2, #(_TOS_STACK_SIZE * 2)\r
- \r
- mov r0, #ARM_CPSR_MODE_SVC \r
- msr CPSR_c, R0\r
- mov sp, r2\r
- \r
- \r
- /* copy data */\r
- ldr r0, =__data_load_start\r
- ldr r1, =__data_load_end\r
- ldr r2, =__data_start\r
-.Lcopy: \r
- cmp r0, r1\r
- beq .Lcopydone\r
- ldrb r3, [r0], #1\r
- strb r3, [r2], #1\r
- b .Lcopy\r
-.Lcopydone:\r
- /* clear bss */\r
- ldr r0, =__bss_start__\r
- ldr r1, =__bss_end__\r
- mov r2, #0\r
-.Lclear: \r
- cmp r0, r1\r
- beq .Lcleardone\r
- strb r2, [r0], #1\r
- b .Lclear\r
-.Lcleardone: \r
- mov r0, #0 /* argc? */\r
- mov r1, #0 /* argv? */\r
- bl main\r
-\r
-.L1: \r
- nop\r
- b .L1\r
-\r
-@if we receive and interrupt that we don't handle, behavior will depend on whether we're in release or not\r
-.ifdef RELEASE \r
-@reboot...assumes that we started out in supervisor mode..and that we'll be returning \r
-hplarmv_undef:\r
- movs PC, #0\r
-hplarmv_swi:\r
- movs PC, #0\r
-hplarmv_pabort:\r
- movs PC, #0\r
-hplarmv_dabort:\r
- movs PC, #0\r
-hplarmv_reserved:\r
- movs PC, #0\r
-hplarmv_irq:\r
- movs PC, #0\r
-hplarmv_fiq: \r
- movs PC, #0\r
-.else\r
-@infinite loop so that we can detect what happened with a debugger\r
-@in future, we'll want to blink specific LED patter or something for the USER...or perhaps blue light of death\r
-hplarmv_undef:\r
- b hplarmv_undef \r
-hplarmv_swi:\r
- b hplarmv_swi\r
-hplarmv_pabort:\r
- b hplarmv_pabort\r
-hplarmv_dabort:\r
- b hplarmv_dabort\r
-hplarmv_reserved:\r
- b hplarmv_reserved \r
-hplarmv_irq:\r
- b hplarmv_irq \r
-hplarmv_fiq: \r
- b hplarmv_fiq\r
-.endif\r
-\r
-reset_handler_start:\r
-@ reset handler should first check whether this is a debug exception\r
-@ or a real RESET event.\r
-@ NOTE: r13 is only safe register to use.\r
-@ - For RESET, don\92t really care about which register is used\r
-@ - For debug exception, r13=DBG_r13, prevents application registers\r
-@ - from being corrupted, before debug handler can save.\r
- mrs r13, cpsr\r
- and r13, r13, #0x1f\r
- cmp r13, #0x15 @ are we in DBG mode?\r
- beq dbg_handler_stub @ if so, go to the dbg handler stub\r
- mov r13, #0x8000001c @ otherwise, enable debug, set MOE bits\r
- mcr p14, 0, r13, c10, c0, 0 @ and continue with the reset handler\r
-@ normal reset handler initialization follows code here,\r
-@ or branch to the reset handler. \r
- b start\r
-\r
-.align 5 @ align code to a cache line boundary.\r
-dbg_handler_stub:\r
-@ First save the state of the IC enable/disable bit in DBG_LR[0].\r
- mrc p15, 0, r13, c1, c0, 0\r
- and r13, r13, #0x1000\r
- orr r14, r14, r13, lsr #12\r
-@ Next, enable the IC.\r
- mrc p15, 0, r13, c1, c0, 0\r
- orr r13, r13, #0x1000\r
- mcr p15, 0, r13, c1, c0, 0\r
-@ do a sync operation to ensure all outstanding instr fetches have\r
-@ completed before continuing. The invalidate cache line function\r
-@ serves as a synchronization operation, that\92s why it is used\r
-@ here. The target line is some scratch address in memory.\r
- adr r13, line2\r
- mcr p15, 0, r13, c7, c5, 1\r
-@ invalidate BTB. make sure downloaded vector table does not hit one of\r
-@ the application\92s branches cached in the BTB, branch to the wrong place\r
- mcr p15, 0, r13, c7, c5, 6\r
-@ Now, send \91ready for download\92 message to debugger, indicating debugger\r
-@ can begin the download. \91ready for download\92 = 0x00B00000.\r
-TXloop:\r
- mrc p14, 0, r15, c14, c0, 0 @ first make sure TX reg. is available\r
- bvs TXloop\r
- mov r13, #0x00B00000\r
- mcr p14, 0, r13, c8, c0, 0 @ now write to TX\r
-@ Wait for debugger to indicate that the download is complete.\r
- RXloop:\r
- mrc p14, 0, r15, c14, c0, 0 @ spin in loop waiting for data from the\r
- bpl RXloop @ debugger in RX.\r
-@ before reading the RX register to get the address to branch to, restore\r
-@ the state of the IC (saved in DBG_r14[0]) to the value it have at the\r
-@ start of the debug handler stub. Also, note it must be restored before \r
-@ reading the RX register because of limited scratch registers (r13)\r
- mrc p15, 0, r13, c1, c0, 0\r
-@ First, check DBG_LR[0] to see if the IC was enabled or disabled\r
- tst r14, #0x1\r
-@ Then, if it was previously disabled, then disable it now, otherwise,\r
-@ there\92s no need to change the state, because its already enabled.\r
- biceq r13, r13, #0x1000\r
- mcr p15, 0, r13, c1, c0, 0\r
-@ Restore the link register value\r
- bic r14, r14, #0x1\r
-@ Now r13 can be used to read RX and get the target address to branch to.\r
- mrc p14, 0, r13, c9, c0, 0 @ Read RX and\r
- mov pc, r13 @ branch to downloaded address.\r
-@ scratch memory space used by the invalidate IC line function above.\r
-.align 5 @ make sure it starts at a cache line\r
-@ boundary, so nothing else is affected\r
-line2:\r
-.word 0\r
-.word 0\r
-.word 0\r
-.word 0\r
-.word 0\r
-.word 0\r
-.word 0\r
-.word 0 \r
- \r
- .weak hplarmv_undef, hplarmv_swi, hplarmv_pabort, hplarmv_dabort, hplarmv_reserved, hplarmv_irq, hplarmv_fiq\r
-\r
- .section .vectors\r
- b reset_handler_start\r
- b hplarmv_undef\r
- b hplarmv_swi\r
- b hplarmv_pabort\r
- b hplarmv_dabort\r
- b hplarmv_reserved\r
- b hplarmv_irq\r
- b hplarmv_fiq\r
-\r
-.end\r
- \r
-\r
+/* tab:4
+ * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
+ * downloading, copying, installing or using the software you agree to
+ * this license. If you do not agree to this license, do not download,
+ * install, copy or use the software.
+ *
+ * Intel Open Source License
+ *
+ * Copyright (c) 2002 Intel Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ */
+/*
+ *
+ * Authors: Phil Buonadonna,David Gay
+ * Date last modified: $Revision$
+ *
+ */
+
+ .equ ARM_CPSR_MODE_MASK,(0x0000001F)
+ .equ ARM_CPSR_INT_MASK,(0x000000C0)
+ .equ ARM_CPSR_COND_MASK,(0xF8000000)
+
+ .equ ARM_CPSR_MODE_USR,(0x10)
+ .equ ARM_CPSR_MODE_FIQ,(0x11)
+ .equ ARM_CPSR_MODE_IRQ,(0x12)
+ .equ ARM_CPSR_MODE_SVC,(0x13)
+ .equ ARM_CPSR_MODE_ABT,(0x17)
+ .equ ARM_CPSR_MODE_UND,(0x1B)
+ .equ ARM_CPSR_MODE_SYS,(0x1F)
+
+ .equ ARM_CPSR_BIT_N,(0x80000000)
+ .equ ARM_CPSR_BIT_Z,(0x40000000)
+ .equ ARM_CPSR_BIT_C,(0x20000000)
+ .equ ARM_CPSR_BIT_V,(0x10000000)
+ .equ ARM_CPSR_BIT_Q,(0x08000000)
+
+ .equ ARM_CPSR_BIT_I,(0x00000080)
+ .equ ARM_CPSR_BIT_F,(0x00000040)
+ .equ ARM_CPRS_BIT_T,(0x00000020)
+
+ .equ _TOS_STACK_SIZE,(0x400) @ TinyOS Exception stack sizes
+ .equ _TOS_ISRAM_PHYSBASE,(0x5C000000) @ Internal SRAM on PXA27X
+ .text
+
+.globl start
+start:
+ mrs r0, CPSR
+ bic r0, r0, #ARM_CPSR_MODE_MASK
+ orr r0, r0, #(ARM_CPSR_MODE_SVC | ARM_CPSR_INT_MASK)
+ msr cpsr_cf, r0
+
+ /* Initialize the stack pointers for all modes */
+ mov r0,#_TOS_ISRAM_PHYSBASE
+ ldr r2, =(256*1024 - 4) @ and go to the last slot (256K - 4)
+ add r2,r2,r0
+
+ mov r0, #ARM_CPSR_MODE_ABT
+ msr CPSR_c, R0
+ mov sp, r2
+ sub r2, r2, #_TOS_STACK_SIZE
+
+ mov r0, #ARM_CPSR_MODE_UND
+ msr CPSR_c, R0
+ mov sp, r2
+ sub r2, r2, #_TOS_STACK_SIZE
+
+ mov r0, #ARM_CPSR_MODE_FIQ
+ msr CPSR_c, R0
+ mov sp, r2
+ sub r2, r2, #_TOS_STACK_SIZE
+
+ mov r0, #ARM_CPSR_MODE_IRQ
+ msr CPSR_c, R0
+ mov sp, r2
+ sub r2, r2, #(_TOS_STACK_SIZE * 2)
+
+ mov r0, #ARM_CPSR_MODE_SVC
+ msr CPSR_c, R0
+ mov sp, r2
+
+
+ /* copy data */
+ ldr r0, =__data_load_start
+ ldr r1, =__data_load_end
+ ldr r2, =__data_start
+.Lcopy:
+ cmp r0, r1
+ beq .Lcopydone
+ ldrb r3, [r0], #1
+ strb r3, [r2], #1
+ b .Lcopy
+.Lcopydone:
+ /* clear bss */
+ ldr r0, =__bss_start__
+ ldr r1, =__bss_end__
+ mov r2, #0
+.Lclear:
+ cmp r0, r1
+ beq .Lcleardone
+ strb r2, [r0], #1
+ b .Lclear
+.Lcleardone:
+ mov r0, #0 /* argc? */
+ mov r1, #0 /* argv? */
+ bl main
+
+.L1:
+ nop
+ b .L1
+
+@if we receive and interrupt that we don't handle, behavior will depend on whether we're in release or not
+.ifdef RELEASE
+@reboot...assumes that we started out in supervisor mode..and that we'll be returning
+hplarmv_undef:
+ movs PC, #0
+hplarmv_swi:
+ movs PC, #0
+hplarmv_pabort:
+ movs PC, #0
+hplarmv_dabort:
+ movs PC, #0
+hplarmv_reserved:
+ movs PC, #0
+hplarmv_irq:
+ movs PC, #0
+hplarmv_fiq:
+ movs PC, #0
+.else
+@infinite loop so that we can detect what happened with a debugger
+@in future, we'll want to blink specific LED patter or something for the USER...or perhaps blue light of death
+hplarmv_undef:
+ b hplarmv_undef
+hplarmv_swi:
+ b hplarmv_swi
+hplarmv_pabort:
+ b hplarmv_pabort
+hplarmv_dabort:
+ b hplarmv_dabort
+hplarmv_reserved:
+ b hplarmv_reserved
+hplarmv_irq:
+ b hplarmv_irq
+hplarmv_fiq:
+ b hplarmv_fiq
+.endif
+
+reset_handler_start:
+@ reset handler should first check whether this is a debug exception
+@ or a real RESET event.
+@ NOTE: r13 is only safe register to use.
+@ - For RESET, donÆt really care about which register is used
+@ - For debug exception, r13=DBG_r13, prevents application registers
+@ - from being corrupted, before debug handler can save.
+ mrs r13, cpsr
+ and r13, r13, #0x1f
+ cmp r13, #0x15 @ are we in DBG mode?
+ beq dbg_handler_stub @ if so, go to the dbg handler stub
+ mov r13, #0x8000001c @ otherwise, enable debug, set MOE bits
+ mcr p14, 0, r13, c10, c0, 0 @ and continue with the reset handler
+@ normal reset handler initialization follows code here,
+@ or branch to the reset handler.
+ b start
+
+.align 5 @ align code to a cache line boundary.
+dbg_handler_stub:
+@ First save the state of the IC enable/disable bit in DBG_LR[0].
+ mrc p15, 0, r13, c1, c0, 0
+ and r13, r13, #0x1000
+ orr r14, r14, r13, lsr #12
+@ Next, enable the IC.
+ mrc p15, 0, r13, c1, c0, 0
+ orr r13, r13, #0x1000
+ mcr p15, 0, r13, c1, c0, 0
+@ do a sync operation to ensure all outstanding instr fetches have
+@ completed before continuing. The invalidate cache line function
+@ serves as a synchronization operation, thatÆs why it is used
+@ here. The target line is some scratch address in memory.
+ adr r13, line2
+ mcr p15, 0, r13, c7, c5, 1
+@ invalidate BTB. make sure downloaded vector table does not hit one of
+@ the applicationÆs branches cached in the BTB, branch to the wrong place
+ mcr p15, 0, r13, c7, c5, 6
+@ Now, send æready for downloadÆ message to debugger, indicating debugger
+@ can begin the download. æready for downloadÆ = 0x00B00000.
+TXloop:
+ mrc p14, 0, r15, c14, c0, 0 @ first make sure TX reg. is available
+ bvs TXloop
+ mov r13, #0x00B00000
+ mcr p14, 0, r13, c8, c0, 0 @ now write to TX
+@ Wait for debugger to indicate that the download is complete.
+ RXloop:
+ mrc p14, 0, r15, c14, c0, 0 @ spin in loop waiting for data from the
+ bpl RXloop @ debugger in RX.
+@ before reading the RX register to get the address to branch to, restore
+@ the state of the IC (saved in DBG_r14[0]) to the value it have at the
+@ start of the debug handler stub. Also, note it must be restored before
+@ reading the RX register because of limited scratch registers (r13)
+ mrc p15, 0, r13, c1, c0, 0
+@ First, check DBG_LR[0] to see if the IC was enabled or disabled
+ tst r14, #0x1
+@ Then, if it was previously disabled, then disable it now, otherwise,
+@ thereÆs no need to change the state, because its already enabled.
+ biceq r13, r13, #0x1000
+ mcr p15, 0, r13, c1, c0, 0
+@ Restore the link register value
+ bic r14, r14, #0x1
+@ Now r13 can be used to read RX and get the target address to branch to.
+ mrc p14, 0, r13, c9, c0, 0 @ Read RX and
+ mov pc, r13 @ branch to downloaded address.
+@ scratch memory space used by the invalidate IC line function above.
+.align 5 @ make sure it starts at a cache line
+@ boundary, so nothing else is affected
+line2:
+.word 0
+.word 0
+.word 0
+.word 0
+.word 0
+.word 0
+.word 0
+.word 0
+
+ .weak hplarmv_undef, hplarmv_swi, hplarmv_pabort, hplarmv_dabort, hplarmv_reserved, hplarmv_irq, hplarmv_fiq
+
+ .section .vectors
+ b reset_handler_start
+ b hplarmv_undef
+ b hplarmv_swi
+ b hplarmv_pabort
+ b hplarmv_dabort
+ b hplarmv_reserved
+ b hplarmv_irq
+ b hplarmv_fiq
+
+.end
+
+
\ No newline at end of file
-/* Copyright (c) 2007 Johns Hopkins University.\r
- * All rights reserved.\r
- *\r
- * Permission to use, copy, modify, and distribute this software and its\r
- * documentation for any purpose, without fee, and without written\r
- * agreement is hereby granted, provided that the above copyright\r
- * notice, the (updated) modification history and the author appear in\r
- * all copies of this source code.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS `AS IS'\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS\r
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, LOSS OF USE, DATA,\r
- * OR PROFITS) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\r
- * THE POSSIBILITY OF SUCH DAMAGE.\r
- */\r
-/**\r
- * Battery Voltage. The returned value represents the difference\r
- * between the battery voltage and V_BG (1.23V). The formula to convert\r
- * it to mV is: 1223 * 1024 / value.\r
- *\r
- * @author Razvan Musaloiu-E.\r
- */\r
-\r
-generic configuration VoltageC()\r
-{\r
- provides interface Read<uint16_t>;\r
-}\r
-\r
-implementation\r
-{\r
- components new AdcReadClientC(), VoltageP;\r
-\r
- Read = AdcReadClientC;\r
-\r
- AdcReadClientC.Atm128AdcConfig -> VoltageP;\r
-}\r
+/* Copyright (c) 2007 Johns Hopkins University.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation for any purpose, without fee, and without written
+ * agreement is hereby granted, provided that the above copyright
+ * notice, the (updated) modification history and the author appear in
+ * all copies of this source code.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS `AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, LOSS OF USE, DATA,
+ * OR PROFITS) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * Battery Voltage. The returned value represents the difference
+ * between the battery voltage and V_BG (1.23V). The formula to convert
+ * it to mV is: 1223 * 1024 / value.
+ *
+ * @author Razvan Musaloiu-E.
+ */
+
+generic configuration VoltageC()
+{
+ provides interface Read<uint16_t>;
+}
+
+implementation
+{
+ components new AdcReadClientC(), VoltageP;
+
+ Read = AdcReadClientC;
+
+ AdcReadClientC.Atm128AdcConfig -> VoltageP;
+}
-/* Copyright (c) 2007 Johns Hopkins University.\r
- * All rights reserved.\r
- *\r
- * Permission to use, copy, modify, and distribute this software and its\r
- * documentation for any purpose, without fee, and without written\r
- * agreement is hereby granted, provided that the above copyright\r
- * notice, the (updated) modification history and the author appear in\r
- * all copies of this source code.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS `AS IS'\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS\r
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, LOSS OF USE, DATA,\r
- * OR PROFITS) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\r
- * THE POSSIBILITY OF SUCH DAMAGE.\r
- */\r
-/**\r
- * Battery Voltage. The returned value represents the difference\r
- * between the battery voltage and V_BG (1.23V). The formula to convert\r
- * it to mV is: 1223 * 1024 / value.\r
- *\r
- * @author Razvan Musaloiu-E.\r
- */\r
-module VoltageP\r
-{\r
- provides interface Atm128AdcConfig;\r
-}\r
-implementation\r
-{\r
- async command uint8_t Atm128AdcConfig.getChannel()\r
- {\r
- // select the 1.23V (V_BG). Reference: Table 97, page 244 from the Atmega128\r
- return ATM128_ADC_SNGL_1_23;\r
- }\r
-\r
- async command uint8_t Atm128AdcConfig.getRefVoltage()\r
- {\r
- return ATM128_ADC_VREF_OFF;\r
- }\r
-\r
- async command uint8_t Atm128AdcConfig.getPrescaler()\r
- {\r
- return ATM128_ADC_PRESCALE;\r
- }\r
-}\r
+/* Copyright (c) 2007 Johns Hopkins University.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation for any purpose, without fee, and without written
+ * agreement is hereby granted, provided that the above copyright
+ * notice, the (updated) modification history and the author appear in
+ * all copies of this source code.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS `AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, LOSS OF USE, DATA,
+ * OR PROFITS) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * Battery Voltage. The returned value represents the difference
+ * between the battery voltage and V_BG (1.23V). The formula to convert
+ * it to mV is: 1223 * 1024 / value.
+ *
+ * @author Razvan Musaloiu-E.
+ */
+module VoltageP
+{
+ provides interface Atm128AdcConfig;
+}
+implementation
+{
+ async command uint8_t Atm128AdcConfig.getChannel()
+ {
+ // select the 1.23V (V_BG). Reference: Table 97, page 244 from the Atmega128
+ return ATM128_ADC_SNGL_1_23;
+ }
+
+ async command uint8_t Atm128AdcConfig.getRefVoltage()
+ {
+ return ATM128_ADC_VREF_OFF;
+ }
+
+ async command uint8_t Atm128AdcConfig.getPrescaler()
+ {
+ return ATM128_ADC_PRESCALE;
+ }
+}
-#ifndef TEST_SENSOR_H\r
-#define TEST_SENSOR_H\r
-\r
-typedef nx_struct TestSensorMsg {\r
- nx_uint16_t value;\r
-} TestSensorMsg;\r
-\r
-enum {\r
- AM_TESTSENSORMSG = 10,\r
-};\r
-\r
-#endif\r
+#ifndef TEST_SENSOR_H
+#define TEST_SENSOR_H
+
+typedef nx_struct TestSensorMsg {
+ nx_uint16_t value;
+} TestSensorMsg;
+
+enum {
+ AM_TESTSENSORMSG = 10,
+};
+
+#endif
-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arch Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arch Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * \r
- * @author Phil Buonadonna <pbuonadonna@archrock.com>\r
- * Revision: $Revision$\r
- *\r
- */\r
-\r
-#ifndef _IM2SB_H\r
-#define _IM2SB_H\r
-\r
-#define GPIO_SHT11_DATA (100)\r
-#define GPIO_SHT11_CLK (98)\r
-\r
-#define GPIO_TSL2561_LIGHT_INT (99)\r
-#define GPIO_MAX1363_ANALOG_INT (99)\r
-\r
-#define GPIO_LIS3L02DQ_RDY_INT (96)\r
-#define GPIO_TMP175_TEMP_ALERT (96)\r
-\r
-#define GPIO_PWR_ADC_NSHDWN (93)\r
-\r
-#define TSL2561_SLAVE_ADDR (0x49)\r
-#define TMP175_SLAVE_ADDR (0x48)\r
-#define MAX136_SLAVE_ADDR (0x34)\r
-\r
-#endif /* _IM2SB_H */\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arch Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arch Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ *
+ * @author Phil Buonadonna <pbuonadonna@archrock.com>
+ * Revision: $Revision$
+ *
+ */
+
+#ifndef _IM2SB_H
+#define _IM2SB_H
+
+#define GPIO_SHT11_DATA (100)
+#define GPIO_SHT11_CLK (98)
+
+#define GPIO_TSL2561_LIGHT_INT (99)
+#define GPIO_MAX1363_ANALOG_INT (99)
+
+#define GPIO_LIS3L02DQ_RDY_INT (96)
+#define GPIO_TMP175_TEMP_ALERT (96)
+
+#define GPIO_PWR_ADC_NSHDWN (93)
+
+#define TSL2561_SLAVE_ADDR (0x49)
+#define TMP175_SLAVE_ADDR (0x48)
+#define MAX136_SLAVE_ADDR (0x34)
+
+#endif /* _IM2SB_H */
-/*\r
- * Copyright (c) 2007 Stanford University.\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions\r
- * are met:\r
- * - Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * - Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the\r
- * distribution.\r
- * - Neither the name of the Stanford University nor the names of\r
- * its contributors may be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL STANFORD\r
- * UNIVERSITY OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\r
- * OF THE POSSIBILITY OF SUCH DAMAGE.\r
- */\r
-\r
-/**\r
- * @author Kevin Klues <klueska@cs.stanford.edu>\r
- * @date August 20th, 2007\r
- */\r
-\r
-configuration ArbitratedTempDeviceP\r
-{\r
- provides interface Read<uint16_t>[uint8_t client];\r
-}\r
-implementation\r
-{\r
- components TempImplP,\r
- new ArbitratedReadC(uint16_t) as ArbitrateRead;\r
-\r
- Read = ArbitrateRead;\r
- ArbitrateRead.Service -> TempImplP.Read;\r
- ArbitrateRead.Resource -> TempImplP.Resource;\r
-}\r
+/*
+ * Copyright (c) 2007 Stanford University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of the Stanford University nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL STANFORD
+ * UNIVERSITY OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @author Kevin Klues <klueska@cs.stanford.edu>
+ * @date August 20th, 2007
+ */
+
+configuration ArbitratedTempDeviceP
+{
+ provides interface Read<uint16_t>[uint8_t client];
+}
+implementation
+{
+ components TempImplP,
+ new ArbitratedReadC(uint16_t) as ArbitrateRead;
+
+ Read = ArbitrateRead;
+ ArbitrateRead.Service -> TempImplP.Read;
+ ArbitrateRead.Resource -> TempImplP.Resource;
+}
-/*\r
- * Copyright (c) 2007 Stanford University.\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions\r
- * are met:\r
- * - Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * - Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the\r
- * distribution.\r
- * - Neither the name of the Stanford University nor the names of\r
- * its contributors may be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL STANFORD\r
- * UNIVERSITY OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\r
- * OF THE POSSIBILITY OF SUCH DAMAGE.\r
- */\r
-\r
-/**\r
- * @author Kevin Klues <klueska@cs.stanford.edu>\r
- * @date August 20th, 2007\r
- */\r
-\r
-generic configuration SharedAnalogDeviceC(char resourceName[], uint32_t startup_delay) {\r
- provides {\r
- interface Resource[uint8_t];\r
- interface Read<uint16_t>[uint8_t];\r
- }\r
- uses {\r
- interface Atm128AdcConfig as AdcConfig;\r
- interface GeneralIO as EnablePin;\r
- } \r
-}\r
-implementation {\r
- components new RoundRobinArbiterC(resourceName) as Arbiter;\r
- components new SplitControlPowerManagerC() as PowerManager;\r
- components new SharedAnalogDeviceP(startup_delay) as AnalogDevice;\r
- components new AdcReadNowClientC() as Adc;\r
- components new TimerMilliC();\r
- Resource = Arbiter;\r
- Read = AnalogDevice;\r
-\r
- PowerManager.ArbiterInfo -> Arbiter;\r
- PowerManager.SplitControl -> AnalogDevice;\r
- PowerManager.ResourceDefaultOwner -> Arbiter;\r
- AnalogDevice.ActualRead -> Adc;\r
- AnalogDevice.Timer -> TimerMilliC;\r
- AnalogDevice.AnalogDeviceResource -> Adc;\r
-\r
- Adc.Atm128AdcConfig = AdcConfig;\r
- AnalogDevice.EnablePin = EnablePin;\r
-}\r
+/*
+ * Copyright (c) 2007 Stanford University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of the Stanford University nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL STANFORD
+ * UNIVERSITY OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @author Kevin Klues <klueska@cs.stanford.edu>
+ * @date August 20th, 2007
+ */
+
+generic configuration SharedAnalogDeviceC(char resourceName[], uint32_t startup_delay) {
+ provides {
+ interface Resource[uint8_t];
+ interface Read<uint16_t>[uint8_t];
+ }
+ uses {
+ interface Atm128AdcConfig as AdcConfig;
+ interface GeneralIO as EnablePin;
+ }
+}
+implementation {
+ components new RoundRobinArbiterC(resourceName) as Arbiter;
+ components new SplitControlPowerManagerC() as PowerManager;
+ components new SharedAnalogDeviceP(startup_delay) as AnalogDevice;
+ components new AdcReadNowClientC() as Adc;
+ components new TimerMilliC();
+ Resource = Arbiter;
+ Read = AnalogDevice;
+
+ PowerManager.ArbiterInfo -> Arbiter;
+ PowerManager.SplitControl -> AnalogDevice;
+ PowerManager.ResourceDefaultOwner -> Arbiter;
+ AnalogDevice.ActualRead -> Adc;
+ AnalogDevice.Timer -> TimerMilliC;
+ AnalogDevice.AnalogDeviceResource -> Adc;
+
+ Adc.Atm128AdcConfig = AdcConfig;
+ AnalogDevice.EnablePin = EnablePin;
+}
-/* $Id$\r
- * Copyright (c) 2006 Intel Corporation\r
- * All rights reserved.\r
- *\r
- * This file is distributed under the terms in the attached INTEL-LICENSE \r
- * file. If you do not find these files, copies can be found by writing to\r
- * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, \r
- * 94704. Attention: Intel License Inquiry.\r
- */\r
-/**\r
- * Photodiode of the mda100 sensor board.\r
- * \r
- * @author David Gay\r
- */\r
-\r
-#include "mda100.h"\r
-\r
-generic configuration TempC() {\r
- provides interface Read<uint16_t>;\r
-}\r
-implementation {\r
- components ArbitratedTempDeviceP;\r
-\r
- Read = ArbitratedTempDeviceP.Read[unique(UQ_MDA100_TEMP_RESOURCE)];\r
-}\r
+/* $Id$
+ * Copyright (c) 2006 Intel Corporation
+ * All rights reserved.
+ *
+ * This file is distributed under the terms in the attached INTEL-LICENSE
+ * file. If you do not find these files, copies can be found by writing to
+ * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,
+ * 94704. Attention: Intel License Inquiry.
+ */
+/**
+ * Photodiode of the mda100 sensor board.
+ *
+ * @author David Gay
+ */
+
+#include "mda100.h"
+
+generic configuration TempC() {
+ provides interface Read<uint16_t>;
+}
+implementation {
+ components ArbitratedTempDeviceP;
+
+ Read = ArbitratedTempDeviceP.Read[unique(UQ_MDA100_TEMP_RESOURCE)];
+}
-configuration ArbitratedTempDeviceP\r
-{\r
- provides interface Read<uint16_t>[uint8_t client];\r
-}\r
-implementation\r
-{\r
- components PhotoTempDeviceC,\r
- new ArbitratedReadC(uint16_t) as ArbitrateRead;\r
-\r
- Read = ArbitrateRead;\r
- ArbitrateRead.Service -> PhotoTempDeviceC.ReadTemp;\r
- ArbitrateRead.Resource -> PhotoTempDeviceC.TempResource;\r
-}\r
+configuration ArbitratedTempDeviceP
+{
+ provides interface Read<uint16_t>[uint8_t client];
+}
+implementation
+{
+ components PhotoTempDeviceC,
+ new ArbitratedReadC(uint16_t) as ArbitrateRead;
+
+ Read = ArbitrateRead;
+ ArbitrateRead.Service -> PhotoTempDeviceC.ReadTemp;
+ ArbitrateRead.Resource -> PhotoTempDeviceC.TempResource;
+}
-// $Id$\r
-\r
-/* tab:4\r
- * "Copyright (c) 2000-2003 The Regents of the University of California. \r
- * All rights reserved.\r
- *\r
- * Permission to use, copy, modify, and distribute this software and its\r
- * documentation for any purpose, without fee, and without written agreement is\r
- * hereby granted, provided that the above copyright notice, the following\r
- * two paragraphs and the author appear in all copies of this software.\r
- * \r
- * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR\r
- * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT\r
- * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF\r
- * CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * \r
- * THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\r
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY\r
- * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS\r
- * ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO\r
- * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."\r
- *\r
- * Copyright (c) 2002-2003 Intel Corporation\r
- * All rights reserved.\r
- *\r
- * This file is distributed under the terms in the attached INTEL-LICENSE \r
- * file. If you do not find these files, copies can be found by writing to\r
- * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, \r
- * 94704. Attention: Intel License Inquiry.\r
- */\r
-\r
-/*\r
- * Authors: Alec Woo\r
- * Date lase modified: 8/20/02\r
- *\r
- * The MagSetting inteface provides an asynchronous mechanism for\r
- * setting the gain offset for the Magnetometer on the mica sensorboard.\r
- * This is particularly useful in calibrating the offset of the Magnetometer\r
- * such that X and Y axis can stay in the center for idle signals. \r
- * If not calibrated, the data you get may rail. (railing means\r
- * the data either stays at the maximum (~785) or minimum (~240)). \r
- *\r
- * The gain adjust has 256 steps ranging from 0 to 255.\r
- *\r
- */\r
-\r
-/**\r
- * @author Alec Woo\r
- */\r
-\r
-interface Mag {\r
- /* Effects: adjust pot setting on the X axis of the magnetometer.\r
- * Returns: return SUCCESS of FAILED.\r
- */\r
- command error_t gainAdjustX(uint8_t val);\r
-\r
- /* Effects: adjust pot setting on the Y axis of the magnetometer.\r
- * Returns: return SUCCESS of FAILED.\r
- */\r
- command error_t gainAdjustY(uint8_t val);\r
-\r
- /* Pot adjustment on the X axis of the magnetometer is finished.\r
- * Returns: return SUCCESS.\r
- */\r
- event error_t gainAdjustXDone(bool result);\r
-\r
- /* Pot adjustment on the Y axis of the magnetometer is finished.\r
- * Returns: return SUCCESS.\r
- */\r
- event error_t gainAdjustYDone(bool result);\r
-}\r
+// $Id$
+
+/* tab:4
+ * "Copyright (c) 2000-2003 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation for any purpose, without fee, and without written agreement is
+ * hereby granted, provided that the above copyright notice, the following
+ * two paragraphs and the author appear in all copies of this software.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
+ * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
+ * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF
+ * CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
+ *
+ * Copyright (c) 2002-2003 Intel Corporation
+ * All rights reserved.
+ *
+ * This file is distributed under the terms in the attached INTEL-LICENSE
+ * file. If you do not find these files, copies can be found by writing to
+ * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,
+ * 94704. Attention: Intel License Inquiry.
+ */
+
+/*
+ * Authors: Alec Woo
+ * Date lase modified: 8/20/02
+ *
+ * The MagSetting inteface provides an asynchronous mechanism for
+ * setting the gain offset for the Magnetometer on the mica sensorboard.
+ * This is particularly useful in calibrating the offset of the Magnetometer
+ * such that X and Y axis can stay in the center for idle signals.
+ * If not calibrated, the data you get may rail. (railing means
+ * the data either stays at the maximum (~785) or minimum (~240)).
+ *
+ * The gain adjust has 256 steps ranging from 0 to 255.
+ *
+ */
+
+/**
+ * @author Alec Woo
+ */
+
+interface Mag {
+ /* Effects: adjust pot setting on the X axis of the magnetometer.
+ * Returns: return SUCCESS of FAILED.
+ */
+ command error_t gainAdjustX(uint8_t val);
+
+ /* Effects: adjust pot setting on the Y axis of the magnetometer.
+ * Returns: return SUCCESS of FAILED.
+ */
+ command error_t gainAdjustY(uint8_t val);
+
+ /* Pot adjustment on the X axis of the magnetometer is finished.
+ * Returns: return SUCCESS.
+ */
+ event error_t gainAdjustXDone(bool result);
+
+ /* Pot adjustment on the Y axis of the magnetometer is finished.
+ * Returns: return SUCCESS.
+ */
+ event error_t gainAdjustYDone(bool result);
+}
-/* $Id$\r
- * Copyright (c) 2006 Intel Corporation\r
- * All rights reserved.\r
- *\r
- * This file is distributed under the terms in the attached INTEL-LICENSE\r
- * file. If you do not find these files, copies can be found by writing to\r
- * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,\r
- * 94704. Attention: Intel License Inquiry.\r
- */\r
-/**\r
- * Internal component for basicsb photodiode. Arbitrates access to the photo\r
- * diode and automatically turns it on or off based on user requests.\r
- *\r
- * @author Alif Chen\r
- */\r
-\r
-#include "mts300.h"\r
-#include "I2C.h"\r
-\r
-configuration MagConfigP {\r
- provides {\r
- interface Mag;\r
- interface Resource[uint8_t client];\r
- interface Atm128AdcConfig as ConfigX;\r
- interface Atm128AdcConfig as ConfigY;\r
- }\r
-}\r
-implementation {\r
- components MagP, MicaBusC, new Atm128I2CMasterC() as I2CPot,\r
- new TimerMilliC() as WarmupTimer,\r
- new RoundRobinArbiterC(UQ_MAG_RESOURCE) as Arbiter,\r
- new SplitControlPowerManagerC() as PowerManager;\r
-\r
- Mag = MagP;\r
-\r
- Resource = Arbiter;\r
- ConfigX = MagP.ConfigX;\r
- ConfigY = MagP.ConfigY;\r
-\r
- PowerManager.ResourceDefaultOwner -> Arbiter;\r
- PowerManager.ArbiterInfo -> Arbiter;\r
- PowerManager.SplitControl -> MagP;\r
-\r
- MagP.I2CPacket -> I2CPot;\r
- MagP.I2CResource -> I2CPot;\r
-\r
- MagP.Timer -> WarmupTimer;\r
- MagP.MagPower -> MicaBusC.PW5;\r
- MagP.MagAdcX -> MicaBusC.Adc6;\r
- MagP.MagAdcY -> MicaBusC.Adc5;\r
-}\r
+/* $Id$
+ * Copyright (c) 2006 Intel Corporation
+ * All rights reserved.
+ *
+ * This file is distributed under the terms in the attached INTEL-LICENSE
+ * file. If you do not find these files, copies can be found by writing to
+ * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,
+ * 94704. Attention: Intel License Inquiry.
+ */
+/**
+ * Internal component for basicsb photodiode. Arbitrates access to the photo
+ * diode and automatically turns it on or off based on user requests.
+ *
+ * @author Alif Chen
+ */
+
+#include "mts300.h"
+#include "I2C.h"
+
+configuration MagConfigP {
+ provides {
+ interface Mag;
+ interface Resource[uint8_t client];
+ interface Atm128AdcConfig as ConfigX;
+ interface Atm128AdcConfig as ConfigY;
+ }
+}
+implementation {
+ components MagP, MicaBusC, new Atm128I2CMasterC() as I2CPot,
+ new TimerMilliC() as WarmupTimer,
+ new RoundRobinArbiterC(UQ_MAG_RESOURCE) as Arbiter,
+ new SplitControlPowerManagerC() as PowerManager;
+
+ Mag = MagP;
+
+ Resource = Arbiter;
+ ConfigX = MagP.ConfigX;
+ ConfigY = MagP.ConfigY;
+
+ PowerManager.ResourceDefaultOwner -> Arbiter;
+ PowerManager.ArbiterInfo -> Arbiter;
+ PowerManager.SplitControl -> MagP;
+
+ MagP.I2CPacket -> I2CPot;
+ MagP.I2CResource -> I2CPot;
+
+ MagP.Timer -> WarmupTimer;
+ MagP.MagPower -> MicaBusC.PW5;
+ MagP.MagAdcX -> MicaBusC.Adc6;
+ MagP.MagAdcY -> MicaBusC.Adc5;
+}
-#include "mts300.h"\r
-#include "Timer.h"\r
-#include "I2C.h"\r
-\r
-module MagP\r
-{\r
- provides interface SplitControl;\r
- provides interface Mag;\r
- provides interface Atm128AdcConfig as ConfigX;\r
- provides interface Atm128AdcConfig as ConfigY;\r
-\r
- uses interface Timer<TMilli>;\r
- uses interface GeneralIO as MagPower;\r
- uses interface MicaBusAdc as MagAdcX;\r
- uses interface MicaBusAdc as MagAdcY;\r
- uses interface I2CPacket<TI2CBasicAddr>;\r
- uses interface Resource as I2CResource;\r
-}\r
-\r
-implementation\r
-{\r
- uint8_t gainData[2];\r
-\r
- command error_t SplitControl.start()\r
- {\r
- call MagPower.makeOutput();\r
- call MagPower.set();\r
-\r
- call Timer.startOneShot(100); \r
- return SUCCESS;\r
- }\r
-\r
- event void Timer.fired() {\r
- signal SplitControl.startDone(SUCCESS);\r
- }\r
-\r
- command error_t SplitControl.stop()\r
- {\r
- call MagPower.clr();\r
- call MagPower.makeInput();\r
-\r
- signal SplitControl.stopDone(SUCCESS);\r
- return SUCCESS;\r
- }\r
-\r
- command error_t Mag.gainAdjustX(uint8_t val)\r
- {\r
- gainData[0] = 1; // pot subaddr\r
- gainData[1] = val; // value to write\r
- return call I2CResource.request();\r
- }\r
- command error_t Mag.gainAdjustY(uint8_t val)\r
- {\r
- gainData[0] = 0; // pot subaddr\r
- gainData[1] = val; // value to write\r
- return call I2CResource.request();\r
- }\r
- /**\r
- * Resource request\r
- *\r
- */\r
- event void I2CResource.granted()\r
- {\r
- if ( call I2CPacket.write(0x3,TOS_MAG_POT_ADDR, 2, gainData) == SUCCESS)\r
- {\r
- return ;\r
- }\r
- }\r
- /**\r
- * I2CPot2\r
- *\r
- */\r
- async event void I2CPacket.readDone(error_t error, uint16_t addr, uint8_t length, uint8_t* data)\r
- {\r
- return ;\r
- }\r
-\r
- async event void I2CPacket.writeDone(error_t error, uint16_t addr, uint8_t length, uint8_t* data)\r
- {\r
- call I2CResource.release();\r
- if (gainData[0] ==1)\r
- {\r
- signal Mag.gainAdjustXDone(error);\r
- }\r
- if (gainData[0] ==0)\r
- {\r
- signal Mag.gainAdjustYDone(error);\r
- }\r
- return ;\r
- }\r
-\r
- async command uint8_t ConfigX.getChannel() {\r
- return call MagAdcX.getChannel();\r
- }\r
-\r
- async command uint8_t ConfigX.getRefVoltage() {\r
- return ATM128_ADC_VREF_OFF;\r
- }\r
-\r
- async command uint8_t ConfigX.getPrescaler() {\r
- return ATM128_ADC_PRESCALE;\r
- }\r
-\r
- async command uint8_t ConfigY.getChannel() {\r
- return call MagAdcY.getChannel();\r
- }\r
-\r
- async command uint8_t ConfigY.getRefVoltage() {\r
- return ATM128_ADC_VREF_OFF;\r
- }\r
-\r
- async command uint8_t ConfigY.getPrescaler() {\r
- return ATM128_ADC_PRESCALE;\r
- }\r
-\r
- default event error_t Mag.gainAdjustXDone(bool result)\r
- {\r
- return result;\r
- }\r
- default event error_t Mag.gainAdjustYDone(bool result)\r
- {\r
- return result;\r
- }\r
+#include "mts300.h"
+#include "Timer.h"
+#include "I2C.h"
+
+module MagP
+{
+ provides interface SplitControl;
+ provides interface Mag;
+ provides interface Atm128AdcConfig as ConfigX;
+ provides interface Atm128AdcConfig as ConfigY;
+
+ uses interface Timer<TMilli>;
+ uses interface GeneralIO as MagPower;
+ uses interface MicaBusAdc as MagAdcX;
+ uses interface MicaBusAdc as MagAdcY;
+ uses interface I2CPacket<TI2CBasicAddr>;
+ uses interface Resource as I2CResource;
+}
+
+implementation
+{
+ uint8_t gainData[2];
+
+ command error_t SplitControl.start()
+ {
+ call MagPower.makeOutput();
+ call MagPower.set();
+
+ call Timer.startOneShot(100);
+ return SUCCESS;
+ }
+
+ event void Timer.fired() {
+ signal SplitControl.startDone(SUCCESS);
+ }
+
+ command error_t SplitControl.stop()
+ {
+ call MagPower.clr();
+ call MagPower.makeInput();
+
+ signal SplitControl.stopDone(SUCCESS);
+ return SUCCESS;
+ }
+
+ command error_t Mag.gainAdjustX(uint8_t val)
+ {
+ gainData[0] = 1; // pot subaddr
+ gainData[1] = val; // value to write
+ return call I2CResource.request();
+ }
+ command error_t Mag.gainAdjustY(uint8_t val)
+ {
+ gainData[0] = 0; // pot subaddr
+ gainData[1] = val; // value to write
+ return call I2CResource.request();
+ }
+ /**
+ * Resource request
+ *
+ */
+ event void I2CResource.granted()
+ {
+ if ( call I2CPacket.write(0x3,TOS_MAG_POT_ADDR, 2, gainData) == SUCCESS)
+ {
+ return ;
+ }
+ }
+ /**
+ * I2CPot2
+ *
+ */
+ async event void I2CPacket.readDone(error_t error, uint16_t addr, uint8_t length, uint8_t* data)
+ {
+ return ;
+ }
+
+ async event void I2CPacket.writeDone(error_t error, uint16_t addr, uint8_t length, uint8_t* data)
+ {
+ call I2CResource.release();
+ if (gainData[0] ==1)
+ {
+ signal Mag.gainAdjustXDone(error);
+ }
+ if (gainData[0] ==0)
+ {
+ signal Mag.gainAdjustYDone(error);
+ }
+ return ;
+ }
+
+ async command uint8_t ConfigX.getChannel() {
+ return call MagAdcX.getChannel();
+ }
+
+ async command uint8_t ConfigX.getRefVoltage() {
+ return ATM128_ADC_VREF_OFF;
+ }
+
+ async command uint8_t ConfigX.getPrescaler() {
+ return ATM128_ADC_PRESCALE;
+ }
+
+ async command uint8_t ConfigY.getChannel() {
+ return call MagAdcY.getChannel();
+ }
+
+ async command uint8_t ConfigY.getRefVoltage() {
+ return ATM128_ADC_VREF_OFF;
+ }
+
+ async command uint8_t ConfigY.getPrescaler() {
+ return ATM128_ADC_PRESCALE;
+ }
+
+ default event error_t Mag.gainAdjustXDone(bool result)
+ {
+ return result;
+ }
+ default event error_t Mag.gainAdjustYDone(bool result)
+ {
+ return result;
+ }
}
\ No newline at end of file
-// $Id$\r
-\r
-/* tab:4\r
- * "Copyright (c) 2000-2003 The Regents of the University of California.\r
- * All rights reserved.\r
- *\r
- * Permission to use, copy, modify, and distribute this software and its\r
- * documentation for any purpose, without fee, and without written agreement is\r
- * hereby granted, provided that the above copyright notice, the following\r
- * two paragraphs and the author appear in all copies of this software.\r
- *\r
- * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR\r
- * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT\r
- * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF\r
- * CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- * THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\r
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY\r
- * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS\r
- * ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO\r
- * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."\r
- *\r
- * Copyright (c) 2002-2003 Intel Corporation\r
- * All rights reserved.\r
- *\r
- * This file is distributed under the terms in the attached INTEL-LICENSE\r
- * file. If you do not find these files, copies can be found by writing to\r
- * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,\r
- * 94704. Attention: Intel License Inquiry.\r
- */\r
-#include "mts300.h"\r
-\r
-configuration MagReadP \r
-{\r
- provides \r
- {\r
- interface Mag;\r
- interface Read<uint16_t> as MagX[uint8_t client];\r
- interface Read<uint16_t> as MagY[uint8_t client];\r
- }\r
- uses\r
- {\r
- interface Read<uint16_t> as ActualX[uint8_t client];\r
- interface Read<uint16_t> as ActualY[uint8_t client];\r
- }\r
-}\r
-implementation\r
-{\r
- components MagConfigP,\r
- new ArbitratedReadC(uint16_t) as AdcX,\r
- new ArbitratedReadC(uint16_t) as AdcY;\r
-\r
- Mag = MagConfigP;\r
-\r
- MagX = AdcX;\r
- AdcX.Resource -> MagConfigP;\r
- AdcX.Service = ActualX;\r
-\r
- MagY = AdcY;\r
- AdcY.Resource -> MagConfigP;\r
- AdcY.Service = ActualY;\r
-}\r
+// $Id$
+
+/* tab:4
+ * "Copyright (c) 2000-2003 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation for any purpose, without fee, and without written agreement is
+ * hereby granted, provided that the above copyright notice, the following
+ * two paragraphs and the author appear in all copies of this software.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
+ * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
+ * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF
+ * CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
+ *
+ * Copyright (c) 2002-2003 Intel Corporation
+ * All rights reserved.
+ *
+ * This file is distributed under the terms in the attached INTEL-LICENSE
+ * file. If you do not find these files, copies can be found by writing to
+ * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,
+ * 94704. Attention: Intel License Inquiry.
+ */
+#include "mts300.h"
+
+configuration MagReadP
+{
+ provides
+ {
+ interface Mag;
+ interface Read<uint16_t> as MagX[uint8_t client];
+ interface Read<uint16_t> as MagY[uint8_t client];
+ }
+ uses
+ {
+ interface Read<uint16_t> as ActualX[uint8_t client];
+ interface Read<uint16_t> as ActualY[uint8_t client];
+ }
+}
+implementation
+{
+ components MagConfigP,
+ new ArbitratedReadC(uint16_t) as AdcX,
+ new ArbitratedReadC(uint16_t) as AdcY;
+
+ Mag = MagConfigP;
+
+ MagX = AdcX;
+ AdcX.Resource -> MagConfigP;
+ AdcX.Service = ActualX;
+
+ MagY = AdcY;
+ AdcY.Resource -> MagConfigP;
+ AdcY.Service = ActualY;
+}
-// $Id$\r
-\r
-/* tab:4\r
- * "Copyright (c) 2000-2003 The Regents of the University of California.\r
- * All rights reserved.\r
- *\r
- * Permission to use, copy, modify, and distribute this software and its\r
- * documentation for any purpose, without fee, and without written agreement is\r
- * hereby granted, provided that the above copyright notice, the following\r
- * two paragraphs and the author appear in all copies of this software.\r
- *\r
- * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR\r
- * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT\r
- * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF\r
- * CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- * THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\r
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY\r
- * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS\r
- * ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO\r
- * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."\r
- *\r
- * Copyright (c) 2002-2003 Intel Corporation\r
- * All rights reserved.\r
- *\r
- * This file is distributed under the terms in the attached INTEL-LICENSE\r
- * file. If you do not find these files, copies can be found by writing to\r
- * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,\r
- * 94704. Attention: Intel License Inquiry.\r
- */\r
-#include "mts300.h"\r
-\r
-configuration MagReadStreamP\r
-{\r
- provides {\r
- interface Mag;\r
- interface ReadStream<uint16_t> as ReadStreamX[uint8_t client];\r
- interface ReadStream<uint16_t> as ReadStreamY[uint8_t client];\r
- }\r
- uses {\r
- interface ReadStream<uint16_t> as ActualX[uint8_t client];\r
- interface ReadStream<uint16_t> as ActualY[uint8_t client];\r
- }\r
-}\r
-implementation\r
-{\r
- enum {\r
- NMAG_CLIENTS = uniqueCount(UQ_MAG_RESOURCE)\r
- };\r
- components MagConfigP,\r
- new ArbitratedReadStreamC(NMAG_CLIENTS, uint16_t) as MultiplexX,\r
- new ArbitratedReadStreamC(NMAG_CLIENTS, uint16_t) as MultiplexY;\r
-\r
- Mag = MagConfigP;\r
-\r
- ReadStreamX = MultiplexX;\r
- MultiplexX.Resource -> MagConfigP;\r
- MultiplexX.Service = ActualX;\r
-\r
- ReadStreamY = MultiplexY;\r
- MultiplexY.Resource -> MagConfigP;\r
- MultiplexY.Service = ActualY;\r
+// $Id$
+
+/* tab:4
+ * "Copyright (c) 2000-2003 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation for any purpose, without fee, and without written agreement is
+ * hereby granted, provided that the above copyright notice, the following
+ * two paragraphs and the author appear in all copies of this software.
+ *
+ * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
+ * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
+ * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF
+ * CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
+ *
+ * Copyright (c) 2002-2003 Intel Corporation
+ * All rights reserved.
+ *
+ * This file is distributed under the terms in the attached INTEL-LICENSE
+ * file. If you do not find these files, copies can be found by writing to
+ * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,
+ * 94704. Attention: Intel License Inquiry.
+ */
+#include "mts300.h"
+
+configuration MagReadStreamP
+{
+ provides {
+ interface Mag;
+ interface ReadStream<uint16_t> as ReadStreamX[uint8_t client];
+ interface ReadStream<uint16_t> as ReadStreamY[uint8_t client];
+ }
+ uses {
+ interface ReadStream<uint16_t> as ActualX[uint8_t client];
+ interface ReadStream<uint16_t> as ActualY[uint8_t client];
+ }
+}
+implementation
+{
+ enum {
+ NMAG_CLIENTS = uniqueCount(UQ_MAG_RESOURCE)
+ };
+ components MagConfigP,
+ new ArbitratedReadStreamC(NMAG_CLIENTS, uint16_t) as MultiplexX,
+ new ArbitratedReadStreamC(NMAG_CLIENTS, uint16_t) as MultiplexY;
+
+ Mag = MagConfigP;
+
+ ReadStreamX = MultiplexX;
+ MultiplexX.Resource -> MagConfigP;
+ MultiplexX.Service = ActualX;
+
+ ReadStreamY = MultiplexY;
+ MultiplexY.Resource -> MagConfigP;
+ MultiplexY.Service = ActualY;
}
\ No newline at end of file
-/* $Id$\r
- * Copyright (c) 2006 Intel Corporation\r
- * All rights reserved.\r
- *\r
- * This file is distributed under the terms in the attached INTEL-LICENSE \r
- * file. If you do not find these files, copies can be found by writing to\r
- * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, \r
- * 94704. Attention: Intel License Inquiry.\r
- */\r
-/**\r
- * @author Alif Chen\r
- */\r
-\r
-#include "mts300.h"\r
-\r
-generic configuration MagXC()\r
-{\r
- provides interface Mag;\r
- provides interface Read<uint16_t>;\r
-}\r
-implementation {\r
- enum {\r
- ID = unique(UQ_MAG_RESOURCE)\r
- };\r
- \r
- components MagReadP,MagConfigP, new AdcReadClientC() as AdcX;\r
-\r
- Mag = MagReadP;\r
-\r
- Read = MagReadP.MagX[ID];\r
- MagReadP.ActualX[ID] -> AdcX;\r
- AdcX.Atm128AdcConfig -> MagConfigP.ConfigX;\r
-}\r
-\r
+/* $Id$
+ * Copyright (c) 2006 Intel Corporation
+ * All rights reserved.
+ *
+ * This file is distributed under the terms in the attached INTEL-LICENSE
+ * file. If you do not find these files, copies can be found by writing to
+ * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,
+ * 94704. Attention: Intel License Inquiry.
+ */
+/**
+ * @author Alif Chen
+ */
+
+#include "mts300.h"
+
+generic configuration MagXC()
+{
+ provides interface Mag;
+ provides interface Read<uint16_t>;
+}
+implementation {
+ enum {
+ ID = unique(UQ_MAG_RESOURCE)
+ };
+
+ components MagReadP,MagConfigP, new AdcReadClientC() as AdcX;
+
+ Mag = MagReadP;
+
+ Read = MagReadP.MagX[ID];
+ MagReadP.ActualX[ID] -> AdcX;
+ AdcX.Atm128AdcConfig -> MagConfigP.ConfigX;
+}
+
-/* $Id$\r
- * Copyright (c) 2006 Intel Corporation\r
- * All rights reserved.\r
- *\r
- * This file is distributed under the terms in the attached INTEL-LICENSE \r
- * file. If you do not find these files, copies can be found by writing to\r
- * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, \r
- * 94704. Attention: Intel License Inquiry.\r
- */\r
-/**\r
- * \r
- * @author Alif Chen\r
- */\r
-\r
-#include "mts300.h"\r
-\r
-generic configuration MagXStreamC() {\r
- provides interface ReadStream<uint16_t>;\r
- provides interface Mag;\r
-}\r
-implementation {\r
- enum {\r
- ID = unique(UQ_ACCEL_RESOURCE)\r
- };\r
- components MagReadStreamP, MagConfigP, new AdcReadStreamClientC();\r
-\r
- Mag = MagReadStreamP;\r
-\r
- ReadStream = MagReadStreamP.ReadStreamX[ID];\r
- MagReadStreamP.ActualX[ID] -> AdcReadStreamClientC;\r
- AdcReadStreamClientC.Atm128AdcConfig -> MagConfigP.ConfigX;\r
-}\r
+/* $Id$
+ * Copyright (c) 2006 Intel Corporation
+ * All rights reserved.
+ *
+ * This file is distributed under the terms in the attached INTEL-LICENSE
+ * file. If you do not find these files, copies can be found by writing to
+ * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,
+ * 94704. Attention: Intel License Inquiry.
+ */
+/**
+ *
+ * @author Alif Chen
+ */
+
+#include "mts300.h"
+
+generic configuration MagXStreamC() {
+ provides interface ReadStream<uint16_t>;
+ provides interface Mag;
+}
+implementation {
+ enum {
+ ID = unique(UQ_ACCEL_RESOURCE)
+ };
+ components MagReadStreamP, MagConfigP, new AdcReadStreamClientC();
+
+ Mag = MagReadStreamP;
+
+ ReadStream = MagReadStreamP.ReadStreamX[ID];
+ MagReadStreamP.ActualX[ID] -> AdcReadStreamClientC;
+ AdcReadStreamClientC.Atm128AdcConfig -> MagConfigP.ConfigX;
+}
-/* $Id$\r
- * Copyright (c) 2006 Intel Corporation\r
- * All rights reserved.\r
- *\r
- * This file is distributed under the terms in the attached INTEL-LICENSE \r
- * file. If you do not find these files, copies can be found by writing to\r
- * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, \r
- * 94704. Attention: Intel License Inquiry.\r
- */\r
-/**\r
- * @author Alif Chen\r
- */\r
-\r
-#include "mts300.h"\r
-\r
-generic configuration MagYC()\r
-{\r
- provides interface Mag;\r
- provides interface Read<uint16_t>;\r
-}\r
-implementation {\r
- enum {\r
- ID = unique(UQ_MAG_RESOURCE)\r
- };\r
- \r
- components MagReadP,MagConfigP, new AdcReadClientC() as AdcY;\r
-\r
- Mag = MagReadP;\r
-\r
- Read = MagReadP.MagY[ID];\r
- MagReadP.ActualY[ID] -> AdcY;\r
- AdcY.Atm128AdcConfig -> MagConfigP.ConfigY;\r
-}\r
-\r
+/* $Id$
+ * Copyright (c) 2006 Intel Corporation
+ * All rights reserved.
+ *
+ * This file is distributed under the terms in the attached INTEL-LICENSE
+ * file. If you do not find these files, copies can be found by writing to
+ * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,
+ * 94704. Attention: Intel License Inquiry.
+ */
+/**
+ * @author Alif Chen
+ */
+
+#include "mts300.h"
+
+generic configuration MagYC()
+{
+ provides interface Mag;
+ provides interface Read<uint16_t>;
+}
+implementation {
+ enum {
+ ID = unique(UQ_MAG_RESOURCE)
+ };
+
+ components MagReadP,MagConfigP, new AdcReadClientC() as AdcY;
+
+ Mag = MagReadP;
+
+ Read = MagReadP.MagY[ID];
+ MagReadP.ActualY[ID] -> AdcY;
+ AdcY.Atm128AdcConfig -> MagConfigP.ConfigY;
+}
+
-/* $Id$\r
- * Copyright (c) 2006 Intel Corporation\r
- * All rights reserved.\r
- *\r
- * This file is distributed under the terms in the attached INTEL-LICENSE \r
- * file. If you do not find these files, copies can be found by writing to\r
- * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, \r
- * 94704. Attention: Intel License Inquiry.\r
- */\r
-/**\r
- * @author Alif Chen\r
- */\r
-\r
-#include "mts300.h"\r
-\r
-generic configuration MagYStreamC() {\r
- provides interface ReadStream<uint16_t>;\r
- provides interface Mag;\r
-}\r
-implementation {\r
- enum {\r
- ID = unique(UQ_ACCEL_RESOURCE)\r
- };\r
- components MagReadStreamP, MagConfigP, new AdcReadStreamClientC();\r
-\r
- Mag = MagReadStreamP;\r
-\r
- ReadStream = MagReadStreamP.ReadStreamY[ID];\r
- MagReadStreamP.ActualY[ID] -> AdcReadStreamClientC;\r
- AdcReadStreamClientC.Atm128AdcConfig -> MagConfigP.ConfigY;\r
-}\r
+/* $Id$
+ * Copyright (c) 2006 Intel Corporation
+ * All rights reserved.
+ *
+ * This file is distributed under the terms in the attached INTEL-LICENSE
+ * file. If you do not find these files, copies can be found by writing to
+ * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,
+ * 94704. Attention: Intel License Inquiry.
+ */
+/**
+ * @author Alif Chen
+ */
+
+#include "mts300.h"
+
+generic configuration MagYStreamC() {
+ provides interface ReadStream<uint16_t>;
+ provides interface Mag;
+}
+implementation {
+ enum {
+ ID = unique(UQ_ACCEL_RESOURCE)
+ };
+ components MagReadStreamP, MagConfigP, new AdcReadStreamClientC();
+
+ Mag = MagReadStreamP;
+
+ ReadStream = MagReadStreamP.ReadStreamY[ID];
+ MagReadStreamP.ActualY[ID] -> AdcReadStreamClientC;
+ AdcReadStreamClientC.Atm128AdcConfig -> MagConfigP.ConfigY;
+}
-configuration MicReadP\r
-{\r
- provides \r
- {\r
- interface Read<uint16_t>[uint8_t client];\r
- }\r
- uses\r
- {\r
- interface Read<uint16_t> as ActualRead[uint8_t client];\r
- }\r
-}\r
-implementation\r
-{\r
- components MicDeviceP,\r
- new ArbitratedReadC(uint16_t);\r
-\r
- Read = ArbitratedReadC;\r
- ArbitratedReadC.Resource -> MicDeviceP;\r
- ArbitratedReadC.Service = ActualRead;\r
-}\r
-\r
+configuration MicReadP
+{
+ provides
+ {
+ interface Read<uint16_t>[uint8_t client];
+ }
+ uses
+ {
+ interface Read<uint16_t> as ActualRead[uint8_t client];
+ }
+}
+implementation
+{
+ components MicDeviceP,
+ new ArbitratedReadC(uint16_t);
+
+ Read = ArbitratedReadC;
+ ArbitratedReadC.Resource -> MicDeviceP;
+ ArbitratedReadC.Service = ActualRead;
+}
+
-configuration MicReadStreamP\r
-{\r
- provides \r
- {\r
- interface MicSetting;\r
- interface ReadStream<uint16_t>[uint8_t client];\r
- }\r
- uses\r
- {\r
- interface ReadStream<uint16_t> as ActualRead[uint8_t client];\r
- }\r
-}\r
-implementation\r
-{\r
- enum {\r
- NMIC_CLIENTS = uniqueCount(UQ_MIC_RESOURCE)\r
- };\r
- components MicDeviceP,\r
- new ArbitratedReadStreamC(NMIC_CLIENTS, uint16_t);\r
-\r
- MicSetting = MicDeviceP;\r
-\r
- ReadStream = ArbitratedReadStreamC;\r
- ArbitratedReadStreamC.Resource -> MicDeviceP;\r
- ArbitratedReadStreamC.Service = ActualRead;\r
-}\r
-\r
+configuration MicReadStreamP
+{
+ provides
+ {
+ interface MicSetting;
+ interface ReadStream<uint16_t>[uint8_t client];
+ }
+ uses
+ {
+ interface ReadStream<uint16_t> as ActualRead[uint8_t client];
+ }
+}
+implementation
+{
+ enum {
+ NMIC_CLIENTS = uniqueCount(UQ_MIC_RESOURCE)
+ };
+ components MicDeviceP,
+ new ArbitratedReadStreamC(NMIC_CLIENTS, uint16_t);
+
+ MicSetting = MicDeviceP;
+
+ ReadStream = ArbitratedReadStreamC;
+ ArbitratedReadStreamC.Resource -> MicDeviceP;
+ ArbitratedReadStreamC.Service = ActualRead;
+}
+
-/**\r
- * Copyright (c) 2005-2006 Crossbow Technology, Inc.\r
- * All rights reserved.\r
- *\r
- * Permission to use, copy, modify, and distribute this software and its\r
- * documentation for any purpose, without fee, and without written\r
- * agreement is hereby granted, provided that the above copyright\r
- * notice, the (updated) modification history and the author appear in\r
- * all copies of this source code.\r
- *\r
- * Permission is also granted to distribute this software under the\r
- * standard BSD license as contained in the TinyOS distribution.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS `AS IS'\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS\r
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, LOSS OF USE, DATA,\r
- * OR PROFITS) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\r
- * THE POSSIBILITY OF SUCH DAMAGE.\r
- */\r
- /*\r
- * @author Hu Siquan <husq@xbow.com>\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "mts300.h"\r
-\r
-generic configuration MicStreamC() {\r
- provides interface ReadStream<uint16_t>;\r
- provides interface MicSetting;\r
-}\r
-implementation {\r
- enum {\r
- ID = unique(UQ_MIC_RESOURCE)\r
- };\r
- components MicReadStreamP, MicDeviceP, new AdcReadStreamClientC();\r
-\r
- ReadStream = MicReadStreamP.ReadStream[ID];\r
- MicReadStreamP.ActualRead[ID] -> AdcReadStreamClientC;\r
- AdcReadStreamClientC.Atm128AdcConfig -> MicDeviceP.Atm128AdcConfig;\r
- MicSetting = MicReadStreamP;\r
-}\r
+/**
+ * Copyright (c) 2005-2006 Crossbow Technology, Inc.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation for any purpose, without fee, and without written
+ * agreement is hereby granted, provided that the above copyright
+ * notice, the (updated) modification history and the author appear in
+ * all copies of this source code.
+ *
+ * Permission is also granted to distribute this software under the
+ * standard BSD license as contained in the TinyOS distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS `AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, LOSS OF USE, DATA,
+ * OR PROFITS) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ /*
+ * @author Hu Siquan <husq@xbow.com>
+ *
+ * $Id$
+ */
+
+#include "mts300.h"
+
+generic configuration MicStreamC() {
+ provides interface ReadStream<uint16_t>;
+ provides interface MicSetting;
+}
+implementation {
+ enum {
+ ID = unique(UQ_MIC_RESOURCE)
+ };
+ components MicReadStreamP, MicDeviceP, new AdcReadStreamClientC();
+
+ ReadStream = MicReadStreamP.ReadStream[ID];
+ MicReadStreamP.ActualRead[ID] -> AdcReadStreamClientC;
+ AdcReadStreamClientC.Atm128AdcConfig -> MicDeviceP.Atm128AdcConfig;
+ MicSetting = MicReadStreamP;
+}
-/**\r
- * Copyright (c) 2005-2006 Crossbow Technology, Inc.\r
- * All rights reserved.\r
- *\r
- * Permission to use, copy, modify, and distribute this software and its\r
- * documentation for any purpose, without fee, and without written\r
- * agreement is hereby granted, provided that the above copyright\r
- * notice, the (updated) modification history and the author appear in\r
- * all copies of this source code.\r
- *\r
- * Permission is also granted to distribute this software under the\r
- * standard BSD license as contained in the TinyOS distribution.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS `AS IS'\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS\r
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, LOSS OF USE, DATA,\r
- * OR PROFITS) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\r
- * THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- * @author Martin Turon <mturon@xbow.com>\r
- * @author Hu Siquan <husq@xbow.com>\r
- *\r
- * $Id$\r
- */\r
-\r
-//configuration SensorMts300C\r
-generic configuration SensorMts300C()\r
-{\r
- provides\r
- {\r
- interface Mts300Sounder as Sounder; //!< sounder\r
- interface Read<uint16_t> as Vref; //!< voltage\r
- interface Read<uint16_t> as Temp; //!< Thermister\r
- interface Read<uint16_t> as Light; //!< Photo sensor\r
- interface Read<uint16_t> as Microphone; //!< Mic sensor\r
- interface Read<uint16_t> as AccelX; //!< Accelerometer sensor\r
- interface Read<uint16_t> as AccelY; //!< Accelerometer sensor\r
- interface Read<uint16_t> as MagX; //!< magnetometer sensor\r
- interface Read<uint16_t> as MagY; //!< magnetometer sensor\r
- }\r
-}\r
-implementation\r
-{\r
- components SounderC,\r
- new VoltageC(),\r
- new AccelXC(),\r
- new AccelYC(),\r
- new PhotoC(),\r
- new TempC(),\r
- new MicC(),\r
- new MagXC(),\r
- new MagYC();\r
-\r
- Sounder = SounderC;\r
- Vref = VoltageC;\r
- Temp = TempC;\r
- Light = PhotoC;\r
- Microphone = MicC;\r
- AccelX = AccelXC;\r
- AccelY = AccelYC;\r
- MagX = MagXC;\r
- MagY = MagYC;\r
-}\r
+/**
+ * Copyright (c) 2005-2006 Crossbow Technology, Inc.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation for any purpose, without fee, and without written
+ * agreement is hereby granted, provided that the above copyright
+ * notice, the (updated) modification history and the author appear in
+ * all copies of this source code.
+ *
+ * Permission is also granted to distribute this software under the
+ * standard BSD license as contained in the TinyOS distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS `AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, LOSS OF USE, DATA,
+ * OR PROFITS) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * @author Martin Turon <mturon@xbow.com>
+ * @author Hu Siquan <husq@xbow.com>
+ *
+ * $Id$
+ */
+
+//configuration SensorMts300C
+generic configuration SensorMts300C()
+{
+ provides
+ {
+ interface Mts300Sounder as Sounder; //!< sounder
+ interface Read<uint16_t> as Vref; //!< voltage
+ interface Read<uint16_t> as Temp; //!< Thermister
+ interface Read<uint16_t> as Light; //!< Photo sensor
+ interface Read<uint16_t> as Microphone; //!< Mic sensor
+ interface Read<uint16_t> as AccelX; //!< Accelerometer sensor
+ interface Read<uint16_t> as AccelY; //!< Accelerometer sensor
+ interface Read<uint16_t> as MagX; //!< magnetometer sensor
+ interface Read<uint16_t> as MagY; //!< magnetometer sensor
+ }
+}
+implementation
+{
+ components SounderC,
+ new VoltageC(),
+ new AccelXC(),
+ new AccelYC(),
+ new PhotoC(),
+ new TempC(),
+ new MicC(),
+ new MagXC(),
+ new MagYC();
+
+ Sounder = SounderC;
+ Vref = VoltageC;
+ Temp = TempC;
+ Light = PhotoC;
+ Microphone = MicC;
+ AccelX = AccelXC;
+ AccelY = AccelYC;
+ MagX = MagXC;
+ MagY = MagYC;
+}
-/* $Id$\r
- * Copyright (c) 2006 Intel Corporation\r
- * All rights reserved.\r
- *\r
- * This file is distributed under the terms in the attached INTEL-LICENSE \r
- * file. If you do not find these files, copies can be found by writing to\r
- * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, \r
- * 94704. Attention: Intel License Inquiry.\r
- */\r
-/**\r
- * Photodiode of the mts300 sensor board.\r
- * \r
- * @author David Gay\r
- */\r
-\r
-#include "mts300.h"\r
-\r
-generic configuration TempC() {\r
- provides interface Read<uint16_t>;\r
-}\r
-implementation {\r
- components ArbitratedTempDeviceP;\r
-\r
- Read = ArbitratedTempDeviceP.Read[unique(UQ_TEMP_RESOURCE)];\r
-}\r
+/* $Id$
+ * Copyright (c) 2006 Intel Corporation
+ * All rights reserved.
+ *
+ * This file is distributed under the terms in the attached INTEL-LICENSE
+ * file. If you do not find these files, copies can be found by writing to
+ * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,
+ * 94704. Attention: Intel License Inquiry.
+ */
+/**
+ * Photodiode of the mts300 sensor board.
+ *
+ * @author David Gay
+ */
+
+#include "mts300.h"
+
+generic configuration TempC() {
+ provides interface Read<uint16_t>;
+}
+implementation {
+ components ArbitratedTempDeviceP;
+
+ Read = ArbitratedTempDeviceP.Read[unique(UQ_TEMP_RESOURCE)];
+}
projects / tinyos-2.x.git / commitdiff