]> oss.titaniummirror.com Git - tinyos-2.x.git/commitdiff
- Fix UartByte to properly disable interrupts before busywaiting on the TX interrupt...
authorvlahan <vlahan>
Tue, 10 Jul 2007 00:49:41 +0000 (00:49 +0000)
committervlahan <vlahan>
Tue, 10 Jul 2007 00:49:41 +0000 (00:49 +0000)
tos/chips/msp430/usart/Msp430UartP.nc

index 290fb60605a81a9435306999298bbe0f8b959d2a..9393595c0a90c3533027187d1cd4a75b93a12d9b 100644 (file)
@@ -157,10 +157,13 @@ implementation {
     }
   }
   
-  async command error_t UartByte.send( uint8_t data ) {
-    call Usart.tx( data );
-    while( !call Usart.isTxIntrPending() );
-    call Usart.clrTxIntr();
+    async command error_t UartByte.send( uint8_t data ) {
+      call Usart.clrTxIntr();
+      call Usart.disableTxIntr ();
+      call Usart.tx( data );
+      while( !call Usart.isTxIntrPending() );
+      call Usart.clrTxIntr();
+      call Usart.enableTxIntr();
     return SUCCESS;
   }