-;;{{{ Negation
-
-(define_expand "negsi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (neg:SI (match_operand:SI 1 "register_operand" "")))]
- ""
- "{
- if (REGNO (operands[0]) == REGNO (operands[1]))
- {
- if (reload_in_progress || reload_completed)
- {
- rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/);
-
- emit_insn (gen_movsi (reg, GEN_INT (0)));
- emit_insn (gen_subsi3 (reg, reg, operands[0]));
- emit_insn (gen_movsi (operands[0], reg));
- }
- else
- {
- rtx reg = gen_reg_rtx (SImode);
-
- emit_insn (gen_movsi (reg, GEN_INT (0)));
- emit_insn (gen_subsi3 (reg, reg, operands[0]));
- emit_insn (gen_movsi (operands[0], reg));
- }
- }
- else
- {
- emit_insn (gen_movsi_internal (operands[0], GEN_INT (0)));
- emit_insn (gen_subsi3 (operands[0], operands[0], operands[1]));
- }
- DONE;
- }"
-)
-
-;;}}}
-