+;; ::::::::::::::::::::
+;; ::
+;; :: Attributes
+;; ::
+;; ::::::::::::::::::::
+
+;; Processor type.
+(define_attr "cpu" "cfv1, cfv2, cfv3, cfv4, unknown"
+ (const (symbol_ref "m68k_sched_cpu")))
+
+;; MAC type.
+(define_attr "mac" "no, cf_mac, cf_emac"
+ (const (symbol_ref "m68k_sched_mac")))
+
+;; Instruction type for use in scheduling description.
+;; _l and _w suffixes indicate size of the operands of instruction.
+;; alu - usual arithmetic or logic instruction.
+;; aluq - arithmetic or logic instruction which has a quick immediate (the one
+;; that is encoded in the instruction word) for its Y operand.
+;; alux - Arithmetic instruction that uses carry bit (e.g., addx and subx).
+;; bcc - conditional branch.
+;; bitr - bit operation that only updates flags.
+;; bitrw - bit operation that updates flags and output operand.
+;; bra, bsr, clr, cmp, div, ext - corresponding instruction.
+;; falu, fbcc, fcmp, fdiv, fmove, fmul, fneg, fsqrt, ftst - corresponding
+;; instruction.
+;; ib - fake instruction to subscribe slots in ColdFire V1,V2,V3 instruction
+;; buffer.
+;; ignore - fake instruction.
+;; jmp, jsr, lea, link, mov3q, move, moveq, mul - corresponding instruction.
+;; mvsz - mvs or mvz instruction.
+;; neg, nop, pea, rts, scc - corresponding instruction.
+;; shift - arithmetic or logical shift instruction.
+;; trap, tst, unlk - corresponding instruction.
+(define_attr "type"
+ "alu_l,aluq_l,alux_l,bcc,bitr,bitrw,bra,bsr,clr,clr_l,cmp,cmp_l,
+ div_w,div_l,ext,
+ falu,fbcc,fcmp,fdiv,fmove,fmul,fneg,fsqrt,ftst,
+ ib,ignore,
+ jmp,jsr,lea,link,mov3q_l,move,move_l,moveq_l,mul_w,mul_l,mvsz,neg_l,nop,
+ pea,rts,scc,shift,
+ trap,tst,tst_l,unlk,
+ unknown"
+ (const_string "unknown"))
+
+;; Index of the X or Y operand in recog_data.operand[].
+;; Should be used only within opx_type and opy_type.
+(define_attr "opx" "" (const_int 0))
+(define_attr "opy" "" (const_int 1))
+
+;; Type of the Y operand.
+;; See m68k.c: enum attr_op_type.
+(define_attr "opy_type"
+ "none,Rn,FPn,mem1,mem234,mem5,mem6,mem7,imm_q,imm_w,imm_l"
+ (cond [(eq_attr "type" "ext,fbcc,ftst,neg_l,bcc,bra,bsr,clr,clr_l,ib,ignore,
+ jmp,jsr,nop,rts,scc,trap,tst,tst_l,
+ unlk,unknown") (const_string "none")
+ (eq_attr "type" "lea,pea")
+ (symbol_ref "m68k_sched_attr_opy_type (insn, 1)")]
+ (symbol_ref "m68k_sched_attr_opy_type (insn, 0)")))
+
+;; Type of the X operand.
+;; See m68k.c: enum attr_op_type.
+(define_attr "opx_type"
+ "none,Rn,FPn,mem1,mem234,mem5,mem6,mem7,imm_q,imm_w,imm_l"
+ (cond [(eq_attr "type" "ib,ignore,nop,rts,trap,unlk,
+ unknown") (const_string "none")
+ (eq_attr "type" "pea") (const_string "mem1")
+ (eq_attr "type" "jmp,jsr")
+ (symbol_ref "m68k_sched_attr_opx_type (insn, 1)")]
+ (symbol_ref "m68k_sched_attr_opx_type (insn, 0)")))
+
+;; Access to the X operand: none, read, write, read/write, unknown.
+;; Access to the Y operand is either none (if opy_type is none)
+;; or read otherwise.
+(define_attr "opx_access" "none, r, w, rw"
+ (cond [(eq_attr "type" "ib,ignore,nop,rts,trap,unlk,
+ unknown") (const_string "none")
+ (eq_attr "type" "bcc,bra,bsr,bitr,cmp,cmp_l,fbcc,fcmp,ftst,
+ jmp,jsr,tst,tst_l") (const_string "r")
+ (eq_attr "type" "clr,clr_l,fneg,fmove,lea,
+ mov3q_l,move,move_l,moveq_l,mvsz,
+ pea,scc") (const_string "w")
+ (eq_attr "type" "alu_l,aluq_l,alux_l,bitrw,div_w,div_l,ext,
+ falu,fdiv,fmul,fsqrt,link,mul_w,mul_l,
+ neg_l,shift") (const_string "rw")]
+ ;; Should never be used.
+ (symbol_ref "(gcc_unreachable (), OPX_ACCESS_NONE)")))
+
+;; Memory accesses of the insn.
+;; 00 - no memory references
+;; 10 - memory is read
+;; i0 - indexed memory is read
+;; 01 - memory is written
+;; 0i - indexed memory is written
+;; 11 - memory is read, memory is written
+;; i1 - indexed memory is read, memory is written
+;; 1i - memory is read, indexed memory is written
+(define_attr "op_mem" "00, 10, i0, 01, 0i, 11, i1, 1i"
+ (symbol_ref "m68k_sched_attr_op_mem (insn)"))
+
+;; Instruction size in words.
+(define_attr "size" "1,2,3"
+ (symbol_ref "m68k_sched_attr_size (insn)"))
+
+;; Alternative is OK for ColdFire.
+(define_attr "ok_for_coldfire" "yes,no" (const_string "yes"))
+
+;; Define 'enabled' attribute.
+(define_attr "enabled" ""
+ (cond [(and (ne (symbol_ref "TARGET_COLDFIRE") (const_int 0))
+ (eq_attr "ok_for_coldfire" "no"))
+ (const_int 0)]
+ (const_int 1)))
+\f
+;; Mode macros for floating point operations.
+;; Valid floating point modes
+(define_mode_iterator FP [SF DF (XF "TARGET_68881")])
+;; Mnemonic infix to round result
+(define_mode_attr round [(SF "%$") (DF "%&") (XF "")])
+;; Mnemonic infix to round result for mul or div instruction
+(define_mode_attr round_mul [(SF "sgl") (DF "%&") (XF "")])
+;; Suffix specifying source operand format
+(define_mode_attr prec [(SF "s") (DF "d") (XF "x")])
+;; Allowable D registers
+(define_mode_attr dreg [(SF "d") (DF "") (XF "")])
+;; Allowable 68881 constant constraints
+(define_mode_attr const [(SF "F") (DF "G") (XF "")])
+\f
+
+(define_insn_and_split "*movdf_internal"
+ [(set (match_operand:DF 0 "push_operand" "=m, m")
+ (match_operand:DF 1 "general_operand" "f, ro<>E"))]