-(define_insn "zero_extendsidi2_internal"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (zero_extend:DI (match_operand:SI 1 "memory_operand" "R,m")))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "load")
- (set_attr "mode" "DI")
- (set_attr "length" "4,8")])
-
-(define_expand "zero_extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
- ""
- "
-{
- if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
- {
- rtx op = gen_lowpart (SImode, operands[1]);
- rtx temp = force_reg (SImode, GEN_INT (0xffff));
-
- emit_insn (gen_andsi3 (operands[0], op, temp));
- DONE;
- }
-}")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d,d")
- (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
- "!TARGET_MIPS16"
- "*
-{
- if (which_alternative == 0)
- return \"andi\\t%0,%1,0xffff\";
- else
- return mips_move_1word (operands, insn, TRUE);
-}"
- [(set_attr "type" "arith,load,load")
- (set_attr "mode" "SI")
- (set_attr "length" "4,4,8")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (zero_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
- "TARGET_MIPS16"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "load,load")
- (set_attr "mode" "SI")
- (set_attr "length" "4,8")])
-
-(define_expand "zero_extendhidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
- "TARGET_64BIT"
- "
-{
- if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
- {
- rtx op = gen_lowpart (DImode, operands[1]);
- rtx temp = force_reg (DImode, GEN_INT (0xffff));
-
- emit_insn (gen_anddi3 (operands[0], op, temp));
- DONE;
- }
-}")
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d,d")
- (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "*
-{
- if (which_alternative == 0)
- return \"andi\\t%0,%1,0xffff\";
- else
- return mips_move_1word (operands, insn, TRUE);
-}"
- [(set_attr "type" "arith,load,load")
- (set_attr "mode" "DI")
- (set_attr "length" "4,4,8")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (zero_extend:DI (match_operand:HI 1 "memory_operand" "R,m")))]
- "TARGET_64BIT && TARGET_MIPS16"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "load,load")
- (set_attr "mode" "DI")
- (set_attr "length" "4,8")])
-
-(define_expand "zero_extendqihi2"
- [(set (match_operand:HI 0 "register_operand" "")
- (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
- ""
- "
-{
- if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
- {
- rtx op0 = gen_lowpart (SImode, operands[0]);
- rtx op1 = gen_lowpart (SImode, operands[1]);
- rtx temp = force_reg (SImode, GEN_INT (0xff));
-
- emit_insn (gen_andsi3 (op0, op1, temp));
- DONE;
- }
-}")
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=d,d,d")
- (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
- "!TARGET_MIPS16"
- "*
-{
- if (which_alternative == 0)
- return \"andi\\t%0,%1,0x00ff\";
- else
- return mips_move_1word (operands, insn, TRUE);
-}"
- [(set_attr "type" "arith,load,load")
- (set_attr "mode" "HI")
- (set_attr "length" "4,4,8")])
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=d,d")
- (zero_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
- "TARGET_MIPS16"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "load,load")
- (set_attr "mode" "HI")
- (set_attr "length" "4,8")])
-
-(define_expand "zero_extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
- ""
- "
-{
- if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
- {
- rtx op = gen_lowpart (SImode, operands[1]);
- rtx temp = force_reg (SImode, GEN_INT (0xff));
-
- emit_insn (gen_andsi3 (operands[0], op, temp));
- DONE;
- }
-}")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d,d")
- (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
- "!TARGET_MIPS16"
- "*
-{
- if (which_alternative == 0)
- return \"andi\\t%0,%1,0x00ff\";
- else
- return mips_move_1word (operands, insn, TRUE);
-}"
- [(set_attr "type" "arith,load,load")
- (set_attr "mode" "SI")
- (set_attr "length" "4,4,8")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (zero_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
- "TARGET_MIPS16"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "load,load")
- (set_attr "mode" "SI")
- (set_attr "length" "4,8")])
-
-(define_expand "zero_extendqidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
- "TARGET_64BIT"
- "
-{
- if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
- {
- rtx op = gen_lowpart (DImode, operands[1]);
- rtx temp = force_reg (DImode, GEN_INT (0xff));
-
- emit_insn (gen_anddi3 (operands[0], op, temp));
- DONE;
- }
-}")
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d,d")
- (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "*
-{
- if (which_alternative == 0)
- return \"andi\\t%0,%1,0x00ff\";
- else
- return mips_move_1word (operands, insn, TRUE);
-}"
- [(set_attr "type" "arith,load,load")
- (set_attr "mode" "DI")
- (set_attr "length" "4,4,8")])
-
-;; These can be created when a paradoxical subreg operand with an implicit
-;; sign_extend operator is reloaded. Because of the subreg, this is really
-;; a zero extend.
-;; ??? It might be possible to eliminate the need for these patterns by adding
-;; more support to reload for implicit sign_extend operators.
-(define_insn "*paradoxical_extendhidi2"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (sign_extend:DI
- (subreg:SI (match_operand:HI 1 "memory_operand" "R,m") 0)))]
- "TARGET_64BIT"
- "*
-{
- return mips_move_1word (operands, insn, TRUE);
-}"
- [(set_attr "type" "load,load")
- (set_attr "mode" "DI")
- (set_attr "length" "4,8")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (zero_extend:DI (match_operand:QI 1 "memory_operand" "R,m")))]
- "TARGET_64BIT && TARGET_MIPS16"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "load,load")
- (set_attr "mode" "DI")
- (set_attr "length" "4,8")])
-\f
-;;
-;; ....................
-;;
-;; SIGN EXTENSION
-;;
-;; ....................
-
-;; Extension insns.
-;; Those for integer source operand are ordered widest source type first.
-
-;; In 64 bit mode, 32 bit values in general registers are always
-;; correctly sign extended. That means that if the target is a
-;; general register, we can sign extend from SImode to DImode just by
-;; doing a move.
-
-(define_insn "extendsidi2"
- [(set (match_operand:DI 0 "register_operand" "=d,y,d,*d,d,d")
- (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,d,y,*x,R,m")))]
- "TARGET_64BIT"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "move,move,move,hilo,load,load")
- (set_attr "mode" "DI")
- (set_attr "length" "4,4,4,4,4,8")])
-
-;; These patterns originally accepted general_operands, however, slightly
-;; better code is generated by only accepting register_operands, and then
-;; letting combine generate the lh and lb insns.
-
-(define_expand "extendhidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
- "TARGET_64BIT"
- "
-{
- if (optimize && GET_CODE (operands[1]) == MEM)
- operands[1] = force_not_mem (operands[1]);
-
- if (GET_CODE (operands[1]) != MEM)
- {
- rtx op1 = gen_lowpart (DImode, operands[1]);
- rtx temp = gen_reg_rtx (DImode);
- rtx shift = GEN_INT (48);
-
- emit_insn (gen_ashldi3 (temp, op1, shift));
- emit_insn (gen_ashrdi3 (operands[0], temp, shift));
- DONE;
- }
-}")
-
-(define_insn "extendhidi2_internal"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (sign_extend:DI (match_operand:HI 1 "memory_operand" "R,m")))]
- "TARGET_64BIT"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "load")
- (set_attr "mode" "DI")
- (set_attr "length" "4,8")])
-
-(define_expand "extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
- ""
- "
-{
- if (optimize && GET_CODE (operands[1]) == MEM)
- operands[1] = force_not_mem (operands[1]);
-
- if (GET_CODE (operands[1]) != MEM)
- {
- rtx op1 = gen_lowpart (SImode, operands[1]);
- rtx temp = gen_reg_rtx (SImode);
- rtx shift = GEN_INT (16);
-
- emit_insn (gen_ashlsi3 (temp, op1, shift));
- emit_insn (gen_ashrsi3 (operands[0], temp, shift));
- DONE;
- }
-}")
-
-(define_insn "extendhisi2_internal"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
- ""
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "load")
- (set_attr "mode" "SI")
- (set_attr "length" "4,8")])
-
-(define_expand "extendqihi2"
- [(set (match_operand:HI 0 "register_operand" "")
- (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
- ""
- "
-{
- if (optimize && GET_CODE (operands[1]) == MEM)
- operands[1] = force_not_mem (operands[1]);
-
- if (GET_CODE (operands[1]) != MEM)
- {
- rtx op0 = gen_lowpart (SImode, operands[0]);
- rtx op1 = gen_lowpart (SImode, operands[1]);
- rtx temp = gen_reg_rtx (SImode);
- rtx shift = GEN_INT (24);
-
- emit_insn (gen_ashlsi3 (temp, op1, shift));
- emit_insn (gen_ashrsi3 (op0, temp, shift));
- DONE;
- }
-}")
-
-(define_insn "extendqihi2_internal"
- [(set (match_operand:HI 0 "register_operand" "=d,d")
- (sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
- ""
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "load")
- (set_attr "mode" "SI")
- (set_attr "length" "4,8")])
-
-
-(define_expand "extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
- ""
- "
-{
- if (optimize && GET_CODE (operands[1]) == MEM)
- operands[1] = force_not_mem (operands[1]);
-
- if (GET_CODE (operands[1]) != MEM)
- {
- rtx op1 = gen_lowpart (SImode, operands[1]);
- rtx temp = gen_reg_rtx (SImode);
- rtx shift = GEN_INT (24);
-
- emit_insn (gen_ashlsi3 (temp, op1, shift));
- emit_insn (gen_ashrsi3 (operands[0], temp, shift));
- DONE;
- }
-}")
-
-(define_insn "extendqisi2_insn"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
- ""
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "load")
- (set_attr "mode" "SI")
- (set_attr "length" "4,8")])
-
-(define_expand "extendqidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
- "TARGET_64BIT"
- "
-{
- if (optimize && GET_CODE (operands[1]) == MEM)
- operands[1] = force_not_mem (operands[1]);
-
- if (GET_CODE (operands[1]) != MEM)
- {
- rtx op1 = gen_lowpart (DImode, operands[1]);
- rtx temp = gen_reg_rtx (DImode);
- rtx shift = GEN_INT (56);
-
- emit_insn (gen_ashldi3 (temp, op1, shift));
- emit_insn (gen_ashrdi3 (operands[0], temp, shift));
- DONE;
- }
-}")
-
-(define_insn "extendqidi2_insn"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (sign_extend:DI (match_operand:QI 1 "memory_operand" "R,m")))]
- "TARGET_64BIT"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "load")
- (set_attr "mode" "DI")
- (set_attr "length" "4,8")])
-
-
-(define_insn "extendsfdf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "cvt.d.s\\t%0,%1"
- [(set_attr "type" "fcvt")
- (set_attr "mode" "DF")])
-
-\f
-
-;;
-;; ....................
-;;
-;; CONVERSIONS
-;;
-;; ....................
-
-;; The SImode scratch register can not be shared with address regs used for
-;; operand zero, because then the address in the move instruction will be
-;; clobbered. We mark the scratch register as early clobbered to prevent this.
-
-;; We need the ?X in alternative 1 so that it will be chosen only if the
-;; destination is a floating point register. Otherwise, alternative 1 can
-;; have lower cost than alternative 0 (because there is one less loser), and
-;; can be chosen when it won't work (because integral reloads into FP
-;; registers are not supported).
-
-(define_insn "fix_truncdfsi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,*f,R,To")
- (fix:SI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
- (clobber (match_scratch:SI 2 "=d,*d,&d,&d"))
- (clobber (match_scratch:DF 3 "=f,?*X,f,f"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "*
-{
- rtx xoperands[10];
-
- if (which_alternative == 1)
- return \"trunc.w.d %0,%1,%2\";
-
- output_asm_insn (\"trunc.w.d %3,%1,%2\", operands);
-
- xoperands[0] = operands[0];
- xoperands[1] = operands[3];
- output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
- return \"\";
-}"
- [(set_attr "type" "fcvt")
- (set_attr "mode" "DF")
- (set_attr "length" "44,36,40,44")])
-
-
-(define_insn "fix_truncsfsi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,*f,R,To")
- (fix:SI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
- (clobber (match_scratch:SI 2 "=d,*d,&d,&d"))
- (clobber (match_scratch:SF 3 "=f,?*X,f,f"))]
- "TARGET_HARD_FLOAT"
- "*
-{
- rtx xoperands[10];
-
- if (which_alternative == 1)
- return \"trunc.w.s %0,%1,%2\";
-
- output_asm_insn (\"trunc.w.s %3,%1,%2\", operands);
-
- xoperands[0] = operands[0];
- xoperands[1] = operands[3];
- output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
- return \"\";
-}"
- [(set_attr "type" "fcvt")
- (set_attr "mode" "SF")
- (set_attr "length" "44,36,40,44")])
-
-
-;;; ??? trunc.l.d is mentioned in the appendix of the 1993 r4000/r4600 manuals
-;;; but not in the chapter that describes the FPU. It is not mentioned at all
-;;; in the 1991 manuals. The r4000 at Cygnus does not have this instruction.
-
-;;; Deleting this means that we now need two libgcc2.a libraries. One for
-;;; the 32 bit calling convention and one for the 64 bit calling convention.
-
-;;; If this is disabled, then fixuns_truncdfdi2 must be disabled also.
-
-(define_insn "fix_truncdfdi2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,*f,R,To")
- (fix:DI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
- (clobber (match_scratch:DF 2 "=f,?*X,f,f"))]
- "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
- "*
-{
- rtx xoperands[10];
-
- if (which_alternative == 1)
- return \"trunc.l.d %0,%1\";
-
- output_asm_insn (\"trunc.l.d %2,%1\", operands);
-
- xoperands[0] = operands[0];
- xoperands[1] = operands[2];
- output_asm_insn (mips_move_2words (xoperands, insn), xoperands);
- return \"\";
-}"
- [(set_attr "type" "fcvt")
- (set_attr "mode" "DF")
- (set_attr "length" "8,4,8,12")])
-
-
-;;; ??? trunc.l.s is mentioned in the appendix of the 1993 r4000/r4600 manuals
-;;; but not in the chapter that describes the FPU. It is not mentioned at all
-;;; in the 1991 manuals. The r4000 at Cygnus does not have this instruction.
-(define_insn "fix_truncsfdi2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,*f,R,To")
- (fix:DI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
- (clobber (match_scratch:DF 2 "=f,?*X,f,f"))]
- "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
- "*
-{
- rtx xoperands[10];
-
- if (which_alternative == 1)
- return \"trunc.l.s %0,%1\";
-
- output_asm_insn (\"trunc.l.s %2,%1\", operands);
-
- xoperands[0] = operands[0];
- xoperands[1] = operands[2];
- output_asm_insn (mips_move_2words (xoperands, insn), xoperands);
- return \"\";
-}"
- [(set_attr "type" "fcvt")
- (set_attr "mode" "SF")
- (set_attr "length" "8,4,8,12")])
-
-
-(define_insn "floatsidf2"
- [(set (match_operand:DF 0 "register_operand" "=f,f,f")
- (float:DF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "*
-{
- dslots_load_total++;
- if (GET_CODE (operands[1]) == MEM)
- return \"l.s\\t%0,%1%#\;cvt.d.w\\t%0,%0\";
-
- return \"mtc1\\t%1,%0%#\;cvt.d.w\\t%0,%0\";
-}"
- [(set_attr "type" "fcvt")
- (set_attr "mode" "DF")
- (set_attr "length" "12,16,12")])
-
-
-(define_insn "floatdidf2"
- [(set (match_operand:DF 0 "register_operand" "=f,f,f")
- (float:DF (match_operand:DI 1 "se_nonimmediate_operand" "d,R,m")))]
- "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
- "*
-{
- dslots_load_total++;
- if (GET_CODE (operands[1]) == MEM)
- return \"l.d\\t%0,%1%#\;cvt.d.l\\t%0,%0\";
-
- return \"dmtc1\\t%1,%0%#\;cvt.d.l\\t%0,%0\";
-}"
- [(set_attr "type" "fcvt")
- (set_attr "mode" "DF")
- (set_attr "length" "12,16,12")])
-
-
-(define_insn "floatsisf2"
- [(set (match_operand:SF 0 "register_operand" "=f,f,f")
- (float:SF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
- "TARGET_HARD_FLOAT"
- "*
-{
- dslots_load_total++;
- if (GET_CODE (operands[1]) == MEM)
- return \"l.s\\t%0,%1%#\;cvt.s.w\\t%0,%0\";
-
- return \"mtc1\\t%1,%0%#\;cvt.s.w\\t%0,%0\";
-}"
- [(set_attr "type" "fcvt")
- (set_attr "mode" "SF")
- (set_attr "length" "12,16,12")])
-
-
-(define_insn "floatdisf2"
- [(set (match_operand:SF 0 "register_operand" "=f,f,f")
- (float:SF (match_operand:DI 1 "se_nonimmediate_operand" "d,R,m")))]
- "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
- "*
-{
- dslots_load_total++;
- if (GET_CODE (operands[1]) == MEM)
- return \"l.d\\t%0,%1%#\;cvt.s.l\\t%0,%0\";
-
- return \"dmtc1\\t%1,%0%#\;cvt.s.l\\t%0,%0\";
-}"
- [(set_attr "type" "fcvt")
- (set_attr "mode" "SF")
- (set_attr "length" "12,16,12")])
-
-
-(define_expand "fixuns_truncdfsi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "
-{
- rtx reg1 = gen_reg_rtx (DFmode);
- rtx reg2 = gen_reg_rtx (DFmode);
- rtx reg3 = gen_reg_rtx (SImode);
- rtx label1 = gen_label_rtx ();
- rtx label2 = gen_label_rtx ();
- REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31);
-
- if (reg1) /* turn off complaints about unreached code */
- {
- emit_move_insn (reg1, immed_real_const_1 (offset, DFmode));
- do_pending_stack_adjust ();
-
- emit_insn (gen_cmpdf (operands[1], reg1));
- emit_jump_insn (gen_bge (label1));
-
- emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
- emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
- gen_rtx_LABEL_REF (VOIDmode, label2)));
- emit_barrier ();
-
- emit_label (label1);
- emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
- emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
- (BITMASK_HIGH, SImode)));
-
- emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
- emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
-
- emit_label (label2);
-
- /* allow REG_NOTES to be set on last insn (labels don't have enough
- fields, and can't be used for REG_NOTES anyway). */
- emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
- DONE;
- }
-}")
-
-
-(define_expand "fixuns_truncdfdi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
- "
-{
- rtx reg1 = gen_reg_rtx (DFmode);
- rtx reg2 = gen_reg_rtx (DFmode);
- rtx reg3 = gen_reg_rtx (DImode);
- rtx label1 = gen_label_rtx ();
- rtx label2 = gen_label_rtx ();
- REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 63);
-
- if (reg1) /* turn off complaints about unreached code */
- {
- emit_move_insn (reg1, immed_real_const_1 (offset, DFmode));
- do_pending_stack_adjust ();
-
- emit_insn (gen_cmpdf (operands[1], reg1));
- emit_jump_insn (gen_bge (label1));
-
- emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
- emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
- gen_rtx_LABEL_REF (VOIDmode, label2)));
- emit_barrier ();
-
- emit_label (label1);
- emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
- emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
- emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
-
- emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
- emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
-
- emit_label (label2);
-
- /* allow REG_NOTES to be set on last insn (labels don't have enough
- fields, and can't be used for REG_NOTES anyway). */
- emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
- DONE;
- }
-}")
-
-
-(define_expand "fixuns_truncsfsi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT"
- "
-{
- rtx reg1 = gen_reg_rtx (SFmode);
- rtx reg2 = gen_reg_rtx (SFmode);
- rtx reg3 = gen_reg_rtx (SImode);
- rtx label1 = gen_label_rtx ();
- rtx label2 = gen_label_rtx ();
- REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31);
-
- if (reg1) /* turn off complaints about unreached code */
- {
- emit_move_insn (reg1, immed_real_const_1 (offset, SFmode));
- do_pending_stack_adjust ();
-
- emit_insn (gen_cmpsf (operands[1], reg1));
- emit_jump_insn (gen_bge (label1));
-
- emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
- emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
- gen_rtx_LABEL_REF (VOIDmode, label2)));
- emit_barrier ();
-
- emit_label (label1);
- emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
- emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
- (BITMASK_HIGH, SImode)));
-
- emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
- emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
-
- emit_label (label2);
-
- /* allow REG_NOTES to be set on last insn (labels don't have enough
- fields, and can't be used for REG_NOTES anyway). */
- emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
- DONE;
- }
-}")
-
-
-(define_expand "fixuns_truncsfdi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
- "
-{
- rtx reg1 = gen_reg_rtx (SFmode);
- rtx reg2 = gen_reg_rtx (SFmode);
- rtx reg3 = gen_reg_rtx (DImode);
- rtx label1 = gen_label_rtx ();
- rtx label2 = gen_label_rtx ();
- REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 63);
-
- if (reg1) /* turn off complaints about unreached code */
- {
- emit_move_insn (reg1, immed_real_const_1 (offset, SFmode));
- do_pending_stack_adjust ();
-
- emit_insn (gen_cmpsf (operands[1], reg1));
- emit_jump_insn (gen_bge (label1));
-
- emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
- emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
- gen_rtx_LABEL_REF (VOIDmode, label2)));
- emit_barrier ();
-
- emit_label (label1);
- emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
- emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
- emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
-
- emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
- emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
-
- emit_label (label2);
-
- /* allow REG_NOTES to be set on last insn (labels don't have enough
- fields, and can't be used for REG_NOTES anyway). */
- emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
- DONE;
- }
-}")
-
-\f
-;;
-;; ....................
-;;
-;; DATA MOVEMENT
-;;
-;; ....................
-
-;; Bit field extract patterns which use lwl/lwr.
-
-;; ??? There could be HImode variants for the ulh/ulhu/ush macros.
-;; It isn't clear whether this will give better code.
-
-;; Only specify the mode operand 1, the rest are assumed to be word_mode.
-(define_expand "extv"
- [(set (match_operand 0 "register_operand" "")
- (sign_extract (match_operand:QI 1 "memory_operand" "")
- (match_operand 2 "immediate_operand" "")
- (match_operand 3 "immediate_operand" "")))]
- "!TARGET_MIPS16"
- "
-{
- /* If the field does not start on a byte boundary, then fail. */
- if (INTVAL (operands[3]) % 8 != 0)
- FAIL;
-
- /* MIPS I and MIPS II can only handle a 32bit field. */
- if (!TARGET_64BIT && INTVAL (operands[2]) != 32)
- FAIL;
-
- /* MIPS III and MIPS IV can handle both 32bit and 64bit fields. */
- if (TARGET_64BIT
- && INTVAL (operands[2]) != 64
- && INTVAL (operands[2]) != 32)
- FAIL;
-
- /* This can happen for a 64 bit target, when extracting a value from
- a 64 bit union member. extract_bit_field doesn't verify that our
- source matches the predicate, so we force it to be a MEM here. */
- if (GET_CODE (operands[1]) != MEM)
- FAIL;
-
- /* Change the mode to BLKmode for aliasing purposes. */
- operands[1] = adjust_address (operands[1], BLKmode, 0);
-
- /* Otherwise, emit a l[wd]l/l[wd]r pair to load the value. */
- if (INTVAL (operands[2]) == 64)
- emit_insn (gen_movdi_uld (operands[0], operands[1]));
- else
- {
- if (TARGET_64BIT)
- {
- operands[0] = gen_lowpart (SImode, operands[0]);
- if (operands[0] == NULL_RTX)
- FAIL;
- }
- emit_insn (gen_movsi_ulw (operands[0], operands[1]));
- }
- DONE;
-}")
-
-;; Only specify the mode operand 1, the rest are assumed to be word_mode.
-(define_expand "extzv"
- [(set (match_operand 0 "register_operand" "")
- (zero_extract (match_operand:QI 1 "memory_operand" "")
- (match_operand 2 "immediate_operand" "")
- (match_operand 3 "immediate_operand" "")))]
- "!TARGET_MIPS16"
- "
-{
- /* If the field does not start on a byte boundary, then fail. */
- if (INTVAL (operands[3]) % 8 != 0)
- FAIL;
-
- /* MIPS I and MIPS II can only handle a 32bit field. */
- if (!TARGET_64BIT && INTVAL (operands[2]) != 32)
- FAIL;
-
- /* MIPS III and MIPS IV can handle both 32bit and 64bit fields. */
- if (TARGET_64BIT
- && INTVAL (operands[2]) != 64
- && INTVAL (operands[2]) != 32)
- FAIL;
-
- /* This can happen for a 64 bit target, when extracting a value from
- a 64 bit union member. extract_bit_field doesn't verify that our
- source matches the predicate, so we force it to be a MEM here. */
- if (GET_CODE (operands[1]) != MEM)
- FAIL;
-
- /* Change the mode to BLKmode for aliasing purposes. */
- operands[1] = adjust_address (operands[1], BLKmode, 0);
-
- /* Otherwise, emit a lwl/lwr pair to load the value. */
- if (INTVAL (operands[2]) == 64)
- emit_insn (gen_movdi_uld (operands[0], operands[1]));
- else
- {
- if (TARGET_64BIT)
- {
- operands[0] = gen_lowpart (SImode, operands[0]);
- if (operands[0] == NULL_RTX)
- FAIL;
- }
- emit_insn (gen_movsi_ulw (operands[0], operands[1]));
- }
- DONE;
-}")
-
-;; Only specify the mode operands 0, the rest are assumed to be word_mode.
-(define_expand "insv"
- [(set (zero_extract (match_operand:QI 0 "memory_operand" "")
- (match_operand 1 "immediate_operand" "")
- (match_operand 2 "immediate_operand" ""))
- (match_operand 3 "register_operand" ""))]
- "!TARGET_MIPS16"
- "
-{
- /* If the field does not start on a byte boundary, then fail. */
- if (INTVAL (operands[2]) % 8 != 0)
- FAIL;
-
- /* MIPS I and MIPS II can only handle a 32bit field. */
- if (!TARGET_64BIT && INTVAL (operands[1]) != 32)
- FAIL;
-
- /* MIPS III and MIPS IV can handle both 32bit and 64bit fields. */
- if (TARGET_64BIT
- && INTVAL (operands[1]) != 64
- && INTVAL (operands[1]) != 32)
- FAIL;
-
- /* This can happen for a 64 bit target, when storing into a 32 bit union
- member. store_bit_field doesn't verify that our target matches the
- predicate, so we force it to be a MEM here. */
- if (GET_CODE (operands[0]) != MEM)
- FAIL;
-
- /* Change the mode to BLKmode for aliasing purposes. */
- operands[0] = adjust_address (operands[0], BLKmode, 0);
-
- /* Otherwise, emit a s[wd]l/s[wd]r pair to load the value. */
- if (INTVAL (operands[1]) == 64)
- emit_insn (gen_movdi_usd (operands[0], operands[3]));
- else
- {
- if (TARGET_64BIT)
- {
- operands[3] = gen_lowpart (SImode, operands[3]);
- if (operands[3] == NULL_RTX)
- FAIL;
- }
- emit_insn (gen_movsi_usw (operands[0], operands[3]));
- }
- DONE;
-}")
-
-;; unaligned word moves generated by the bit field patterns
-
-(define_insn "movsi_ulw"
- [(set (match_operand:SI 0 "register_operand" "=&d,&d")
- (unspec:SI [(match_operand:BLK 1 "general_operand" "R,o")] 0))]
- "!TARGET_MIPS16"
- "*
-{
- rtx offset = const0_rtx;
- rtx addr = XEXP (operands[1], 0);
- rtx mem_addr = eliminate_constant_term (addr, &offset);
- const char *ret;
-
- if (TARGET_STATS)
- mips_count_memory_refs (operands[1], 2);
-
- /* The stack/frame pointers are always aligned, so we can convert
- to the faster lw if we are referencing an aligned stack location. */
-
- if ((INTVAL (offset) & 3) == 0
- && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
- ret = \"lw\\t%0,%1\";
- else
- ret = \"ulw\\t%0,%1\";
-
- return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn);
-}"
- [(set_attr "type" "load,load")
- (set_attr "mode" "SI")
- (set_attr "length" "8,16")])
-
-(define_insn "movsi_usw"
- [(set (match_operand:BLK 0 "memory_operand" "=R,o")
- (unspec:BLK [(match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")] 1))]
- "!TARGET_MIPS16"
- "*
-{
- rtx offset = const0_rtx;
- rtx addr = XEXP (operands[0], 0);
- rtx mem_addr = eliminate_constant_term (addr, &offset);
-
- if (TARGET_STATS)
- mips_count_memory_refs (operands[0], 2);
-
- /* The stack/frame pointers are always aligned, so we can convert
- to the faster sw if we are referencing an aligned stack location. */
-
- if ((INTVAL (offset) & 3) == 0
- && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
- return \"sw\\t%z1,%0\";
-
- return \"usw\\t%z1,%0\";
-}"
- [(set_attr "type" "store")
- (set_attr "mode" "SI")
- (set_attr "length" "8,16")])
-
-;; Bit field extract patterns which use ldl/ldr.
-
-;; unaligned double word moves generated by the bit field patterns
-
-(define_insn "movdi_uld"
- [(set (match_operand:DI 0 "register_operand" "=&d,&d")
- (unspec:DI [(match_operand:BLK 1 "general_operand" "R,o")] 0))]
- ""
- "*
-{
- rtx offset = const0_rtx;
- rtx addr = XEXP (operands[1], 0);
- rtx mem_addr = eliminate_constant_term (addr, &offset);
- const char *ret;
-
- if (TARGET_STATS)
- mips_count_memory_refs (operands[1], 2);
-
- /* The stack/frame pointers are always aligned, so we can convert
- to the faster lw if we are referencing an aligned stack location. */
-
- if ((INTVAL (offset) & 7) == 0
- && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
- ret = \"ld\\t%0,%1\";
- else
- ret = \"uld\\t%0,%1\";
-
- return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn);
-}"
- [(set_attr "type" "load,load")
- (set_attr "mode" "SI")
- (set_attr "length" "8,16")])
-
-(define_insn "movdi_usd"
- [(set (match_operand:BLK 0 "memory_operand" "=R,o")
- (unspec:BLK [(match_operand:DI 1 "reg_or_0_operand" "dJ,dJ")] 111))]
- ""
- "*
-{
- rtx offset = const0_rtx;
- rtx addr = XEXP (operands[0], 0);
- rtx mem_addr = eliminate_constant_term (addr, &offset);
-
- if (TARGET_STATS)
- mips_count_memory_refs (operands[0], 2);
-
- /* The stack/frame pointers are always aligned, so we can convert
- to the faster sw if we are referencing an aligned stack location. */
-
- if ((INTVAL (offset) & 7) == 0
- && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
- return \"sd\\t%z1,%0\";
-
- return \"usd\\t%z1,%0\";
-}"
- [(set_attr "type" "store")
- (set_attr "mode" "SI")
- (set_attr "length" "8,16")])
-
-;; These two patterns support loading addresses with two instructions instead
-;; of using the macro instruction la.
-
-;; ??? mips_move_1word has support for HIGH, so this pattern may be
-;; unnecessary.
-
-(define_insn "high"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (high:SI (match_operand:SI 1 "immediate_operand" "")))]
- "mips_split_addresses && !TARGET_MIPS16"
- "lui\\t%0,%%hi(%1) # high"
- [(set_attr "type" "move")])
-
-(define_insn "low"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "immediate_operand" "")))]
- "mips_split_addresses && !TARGET_MIPS16"
- "addiu\\t%0,%1,%%lo(%2) # low"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-;; 64-bit integer moves
-
-;; Unlike most other insns, the move insns can't be split with
-;; different predicates, because register spilling and other parts of
-;; the compiler, have memoized the insn number already.
-
-(define_expand "movdi"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (match_operand:DI 1 "general_operand" ""))]
- ""
- "
-{
- if (mips_split_addresses && mips_check_split (operands[1], DImode))
- {
- enum machine_mode mode = GET_MODE (operands[0]);
- rtx tem = ((reload_in_progress | reload_completed)
- ? operands[0] : gen_reg_rtx (mode));
-
- emit_insn (gen_rtx_SET (VOIDmode, tem,
- gen_rtx_HIGH (mode, operands[1])));
-
- operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]);
- }
-
- /* If we are generating embedded PIC code, and we are referring to a
- symbol in the .text section, we must use an offset from the start
- of the function. */
- if (TARGET_EMBEDDED_PIC
- && (GET_CODE (operands[1]) == LABEL_REF
- || (GET_CODE (operands[1]) == SYMBOL_REF
- && ! SYMBOL_REF_FLAG (operands[1]))))
- {
- rtx temp;
-
- temp = embedded_pic_offset (operands[1]);
- temp = gen_rtx_PLUS (Pmode, embedded_pic_fnaddr_rtx,
- force_reg (DImode, temp));
- emit_move_insn (operands[0], force_reg (DImode, temp));
- DONE;
- }
-
- /* If operands[1] is a constant address illegal for pic, then we need to
- handle it just like LEGITIMIZE_ADDRESS does. */
- if (flag_pic && pic_address_needs_scratch (operands[1]))
- {
- rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0));
- rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
-
- if (! SMALL_INT (temp2))
- temp2 = force_reg (DImode, temp2);
-
- emit_move_insn (operands[0], gen_rtx_PLUS (DImode, temp, temp2));
- DONE;
- }
-
- /* On the mips16, we can handle a GP relative reference by adding in
- $gp. We need to check the name to see whether this is a string
- constant. */
- if (TARGET_MIPS16
- && register_operand (operands[0], DImode)
- && GET_CODE (operands[1]) == SYMBOL_REF
- && SYMBOL_REF_FLAG (operands[1]))
- {
- const char *name = XSTR (operands[1], 0);
-
- if (name[0] != '*'
- || strncmp (name + 1, LOCAL_LABEL_PREFIX,
- sizeof LOCAL_LABEL_PREFIX - 1) != 0)
- {
- rtx base_reg;
-
- if (reload_in_progress || reload_completed)
- {
- /* In movsi we use the constant table here. However, in
- this case, we're better off copying $28 into a
- register and adding, because the constant table entry
- would be 8 bytes. */
- base_reg = operands[0];
- emit_move_insn (base_reg,
- gen_rtx (CONST, DImode,
- gen_rtx (REG, DImode,
- GP_REG_FIRST + 28)));
- }
- else
- {
- base_reg = gen_reg_rtx (Pmode);
- emit_move_insn (base_reg, mips16_gp_pseudo_reg ());
- }
-
- emit_move_insn (operands[0],
- gen_rtx (PLUS, Pmode, base_reg,
- mips16_gp_offset (operands[1])));
- DONE;
- }
- }
-
- if ((reload_in_progress | reload_completed) == 0
- && !register_operand (operands[0], DImode)
- && !register_operand (operands[1], DImode)
- && (TARGET_MIPS16
- || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
- && operands[1] != CONST0_RTX (DImode))))
- {
- rtx temp = force_reg (DImode, operands[1]);
- emit_move_insn (operands[0], temp);
- DONE;
- }
-}")
-
-;; For mips16, we need a special case to handle storing $31 into
-;; memory, since we don't have a constraint to match $31. This
-;; instruction can be generated by save_restore_insns.
-
-(define_insn ""
- [(set (match_operand:DI 0 "memory_operand" "=R,m")
- (reg:DI 31))]
- "TARGET_MIPS16 && TARGET_64BIT"
- "*
-{
- operands[1] = gen_rtx (REG, DImode, 31);
- return mips_move_2words (operands, insn);
-}"
- [(set_attr "type" "store")
- (set_attr "mode" "DI")
- (set_attr "length" "4,8")])
-
-(define_insn "movdi_internal"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,R,o,*x,*d,*x")
- (match_operand:DI 1 "general_operand" "d,iF,R,o,d,d,J,*x,*d"))]
- "!TARGET_64BIT && !TARGET_MIPS16
- && (register_operand (operands[0], DImode)
- || register_operand (operands[1], DImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
- || operands[1] == CONST0_RTX (DImode))"
- "* return mips_move_2words (operands, insn); "
- [(set_attr "type" "move,arith,load,load,store,store,hilo,hilo,hilo")
- (set_attr "mode" "DI")
- (set_attr "length" "8,16,8,16,8,16,8,8,8")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,To,*d")
- (match_operand:DI 1 "general_operand" "d,d,y,K,N,R,To,d,d,*x"))]
- "!TARGET_64BIT && TARGET_MIPS16
- && (register_operand (operands[0], DImode)
- || register_operand (operands[1], DImode))"
- "* return mips_move_2words (operands, insn);"
- [(set_attr "type" "move,move,move,arith,arith,load,load,store,store,hilo")
- (set_attr "mode" "DI")
- (set_attr "length" "8,8,8,8,12,8,16,8,16,8")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "register_operand" ""))]
- "reload_completed && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
-
- [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
- (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
- "")
-
-(define_insn "movdi_internal2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*x,*d,*x,*a")
- (match_operand:DI 1 "movdi_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,J,*x,*d,*J"))]
- "TARGET_64BIT && !TARGET_MIPS16
- && (register_operand (operands[0], DImode)
- || se_register_operand (operands[1], DImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
- || operands[1] == CONST0_RTX (DImode))"
- "* return mips_move_2words (operands, insn); "
- [(set_attr "type" "move,load,arith,arith,load,load,store,store,hilo,hilo,hilo,hilo")
- (set_attr "mode" "DI")
- (set_attr "length" "4,8,4,8,4,8,4,8,4,4,4,8")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,R,m,*d")
- (match_operand:DI 1 "movdi_operand" "d,d,y,K,N,s,R,m,d,d,*x"))]
- "TARGET_64BIT && TARGET_MIPS16
- && (register_operand (operands[0], DImode)
- || se_register_operand (operands[1], DImode))"
- "* return mips_move_2words (operands, insn);"
- [(set_attr "type" "move,move,move,arith,arith,arith,load,load,store,store,hilo")
- (set_attr "mode" "DI")
- (set_attr_alternative "length"
- [(const_int 4)
- (const_int 4)
- (const_int 4)
- (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
- (const_int 4)
- (const_int 8))
- (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
- (const_int 8)
- (const_int 12))
- (if_then_else (match_operand:VOID 1 "m16_usym5_4" "")
- (const_int 4)
- (const_int 8))
- (const_int 4)
- (const_int 8)
- (const_int 4)
- (const_int 8)
- (const_int 4)])])
-
-;; On the mips16, we can split ld $r,N($r) into an add and a load,
-;; when the original load is a 4 byte instruction but the add and the
-;; load are 2 2 byte instructions.
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (mem:DI (plus:DI (match_dup 0)
- (match_operand:DI 1 "const_int_operand" ""))))]
- "TARGET_64BIT && TARGET_MIPS16 && reload_completed
- && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
- && ((INTVAL (operands[1]) < 0
- && INTVAL (operands[1]) >= -0x10)
- || (INTVAL (operands[1]) >= 32 * 8
- && INTVAL (operands[1]) <= 31 * 8 + 0x8)
- || (INTVAL (operands[1]) >= 0
- && INTVAL (operands[1]) < 32 * 8
- && (INTVAL (operands[1]) & 7) != 0))"
- [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
- (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
- "
-{
- HOST_WIDE_INT val = INTVAL (operands[1]);
-
- if (val < 0)
- operands[2] = GEN_INT (0);
- else if (val >= 32 * 8)
- {
- int off = val & 7;
-
- operands[1] = GEN_INT (0x8 + off);
- operands[2] = GEN_INT (val - off - 0x8);
- }
- else
- {
- int off = val & 7;
-
- operands[1] = GEN_INT (off);
- operands[2] = GEN_INT (val - off);
- }
-}")
-
-;; Handle input reloads in DImode.
-;; This is mainly to handle reloading HILO_REGNUM. Note that we may
-;; see it as the source or the destination, depending upon which way
-;; reload handles the instruction.
-;; Making the second operand TImode is a trick. The compiler may
-;; reuse the same register for operand 0 and operand 2. Using TImode
-;; gives us two registers, so we can always use the one which is not
-;; used.
-
-(define_expand "reload_indi"
- [(set (match_operand:DI 0 "register_operand" "=b")
- (match_operand:DI 1 "" "b"))
- (clobber (match_operand:TI 2 "register_operand" "=&d"))]
- "TARGET_64BIT"
- "
-{
- rtx scratch = gen_rtx_REG (DImode,
- (REGNO (operands[0]) == REGNO (operands[2])
- ? REGNO (operands[2]) + 1
- : REGNO (operands[2])));
-
- if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
- {
- if (GET_CODE (operands[1]) == MEM)
- {
- rtx memword, offword, hi_word, lo_word;
- rtx addr = find_replacement (&XEXP (operands[1], 0));
- rtx op1 = replace_equiv_address (operands[1], addr);
-
- scratch = gen_rtx_REG (SImode, REGNO (scratch));
- memword = adjust_address (op1, SImode, 0);
- offword = adjust_address (op1, SImode, 4);
-
- if (BYTES_BIG_ENDIAN)
- {
- hi_word = memword;
- lo_word = offword;
- }
- else
- {
- hi_word = offword;
- lo_word = memword;
- }
- emit_move_insn (scratch, hi_word);
- emit_move_insn (gen_rtx_REG (SImode, 64), scratch);
- emit_move_insn (scratch, lo_word);
- emit_move_insn (gen_rtx (REG, SImode, 65), scratch);
- emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[0]), 2));
- }
- else
- {
- emit_insn (gen_ashrdi3 (scratch, operands[1], GEN_INT (32)));
- emit_insn (gen_movdi (gen_rtx_REG (DImode, 64), scratch));
- emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32)));
- emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32)));
- emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch));
- emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[0]), 2));
- }
- DONE;
- }
- if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM)
- {
- emit_insn (gen_movdi (scratch, gen_rtx_REG (DImode, 65)));
- emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
- emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
- emit_insn (gen_movdi (operands[0], gen_rtx_REG (DImode, 64)));
- emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
- emit_insn (gen_iordi3 (operands[0], operands[0], scratch));
- emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[1]), 2));
- DONE;
- }
- /* This handles moves between a float register and HI/LO. */
- emit_move_insn (scratch, operands[1]);
- emit_move_insn (operands[0], scratch);
- DONE;
-}")
-
-;; Handle output reloads in DImode.
-
-;; Reloading HILO_REG in MIPS16 mode requires two scratch registers, so we
-;; use a TImode scratch reg.
-
-(define_expand "reload_outdi"
- [(set (match_operand:DI 0 "general_operand" "=b")
- (match_operand:DI 1 "se_register_operand" "b"))
- (clobber (match_operand:TI 2 "register_operand" "=&d"))]
- "TARGET_64BIT"
- "
-{
- rtx scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
-
- if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
- {
- emit_insn (gen_ashrdi3 (scratch, operands[1], GEN_INT (32)));
- emit_insn (gen_movdi (gen_rtx (REG, DImode, 64), scratch));
- emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32)));
- emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32)));
- emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch));
- emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[0]), 2));
- DONE;
- }
- if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM)
- {
- if (GET_CODE (operands[0]) == MEM)
- {
- rtx scratch, memword, offword, hi_word, lo_word;
- rtx addr = find_replacement (&XEXP (operands[0], 0));
- rtx op0 = replace_equiv_address (operands[0], addr);
-
- scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
- memword = adjust_address (op0, SImode, 0);
- offword = adjust_address (op0, SImode, 4);
-
- if (BYTES_BIG_ENDIAN)
- {
- hi_word = memword;
- lo_word = offword;
- }
- else
- {
- hi_word = offword;
- lo_word = memword;
- }
- emit_move_insn (scratch, gen_rtx_REG (SImode, 64));
- emit_move_insn (hi_word, scratch);
- emit_move_insn (scratch, gen_rtx_REG (SImode, 65));
- emit_move_insn (lo_word, scratch);
- emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[1]), 2));
- }
- else if (TARGET_MIPS16 && ! M16_REG_P (REGNO (operands[0])))
- {
- /* Handle the case where operand[0] is not a 'd' register,
- and hence we can not directly move from the HILO register
- into it. */
- rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
- emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65)));
- emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
- emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
- emit_insn (gen_movdi (scratch2, gen_rtx (REG, DImode, 64)));
- emit_insn (gen_ashldi3 (scratch2, scratch2, GEN_INT (32)));
- emit_insn (gen_iordi3 (scratch, scratch, scratch2));
- emit_insn (gen_movdi (operands[0], scratch));
- emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[1]), 2));
- }
- else
- {
- emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65)));
- emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
- emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
- emit_insn (gen_movdi (operands[0], gen_rtx (REG, DImode, 64)));
- emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
- emit_insn (gen_iordi3 (operands[0], operands[0], scratch));
- emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[1]), 2));
- }
- DONE;
- }
- /* This handles moves between a float register and HI/LO. */
- emit_move_insn (scratch, operands[1]);
- emit_move_insn (operands[0], scratch);
- DONE;
-}")
-
-;; 32-bit Integer moves
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "large_int" ""))]
- "!TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
- [(set (match_dup 0)
- (match_dup 2))
- (set (match_dup 0)
- (ior:SI (match_dup 0)
- (match_dup 3)))]
- "
-{
- operands[2] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1])
- & BITMASK_UPPER16,
- SImode));
- operands[3] = GEN_INT (INTVAL (operands[1]) & BITMASK_LOWER16);
-}")
-
-;; Unlike most other insns, the move insns can't be split with
-;; different predicates, because register spilling and other parts of
-;; the compiler, have memoized the insn number already.
-
-(define_expand "movsi"
- [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (match_operand:SI 1 "general_operand" ""))]
- ""
- "
-{
- if (mips_split_addresses && mips_check_split (operands[1], SImode))
- {
- enum machine_mode mode = GET_MODE (operands[0]);
- rtx tem = ((reload_in_progress | reload_completed)
- ? operands[0] : gen_reg_rtx (mode));
-
- emit_insn (gen_rtx_SET (VOIDmode, tem,
- gen_rtx_HIGH (mode, operands[1])));
-
- operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]);
- }
-
- /* If we are generating embedded PIC code, and we are referring to a
- symbol in the .text section, we must use an offset from the start
- of the function. */
- if (TARGET_EMBEDDED_PIC
- && (GET_CODE (operands[1]) == LABEL_REF
- || (GET_CODE (operands[1]) == SYMBOL_REF
- && ! SYMBOL_REF_FLAG (operands[1]))))
- {
- rtx temp;
-
- temp = embedded_pic_offset (operands[1]);
- temp = gen_rtx_PLUS (Pmode, embedded_pic_fnaddr_rtx,
- force_reg (SImode, temp));
- emit_move_insn (operands[0], force_reg (SImode, temp));
- DONE;
- }
-
- /* If operands[1] is a constant address invalid for pic, then we need to
- handle it just like LEGITIMIZE_ADDRESS does. */
- if (flag_pic && pic_address_needs_scratch (operands[1]))
- {
- rtx temp = force_reg (SImode, XEXP (XEXP (operands[1], 0), 0));
- rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
-
- if (! SMALL_INT (temp2))
- temp2 = force_reg (SImode, temp2);
-
- emit_move_insn (operands[0], gen_rtx_PLUS (SImode, temp, temp2));
- DONE;
- }
-
- /* On the mips16, we can handle a GP relative reference by adding in
- $gp. We need to check the name to see whether this is a string
- constant. */
- if (TARGET_MIPS16
- && register_operand (operands[0], SImode)
- && GET_CODE (operands[1]) == SYMBOL_REF
- && SYMBOL_REF_FLAG (operands[1]))
- {
- const char *name = XSTR (operands[1], 0);
-
- if (name[0] != '*'
- || strncmp (name + 1, LOCAL_LABEL_PREFIX,
- sizeof LOCAL_LABEL_PREFIX - 1) != 0)
- {
- rtx base_reg;
-
- if (reload_in_progress || reload_completed)
- {
- /* We need to reload this address. In this case we
- aren't going to have a chance to combine loading the
- address with the load or store. That means that we
- can either generate a 2 byte move followed by a 4
- byte addition, or a 2 byte load with a 4 byte entry
- in the constant table. Since the entry in the
- constant table might be shared, we're better off, on
- average, loading the address from the constant table. */
- emit_move_insn (operands[0],
- force_const_mem (SImode, operands[1]));
- DONE;
- }
-
- base_reg = gen_reg_rtx (Pmode);
- emit_move_insn (base_reg, mips16_gp_pseudo_reg ());
-
- emit_move_insn (operands[0],
- gen_rtx (PLUS, Pmode, base_reg,
- mips16_gp_offset (operands[1])));
- DONE;
- }
- }
-
- if ((reload_in_progress | reload_completed) == 0
- && !register_operand (operands[0], SImode)
- && !register_operand (operands[1], SImode)
- && (TARGET_MIPS16
- || GET_CODE (operands[1]) != CONST_INT
- || INTVAL (operands[1]) != 0))
- {
- rtx temp = force_reg (SImode, operands[1]);
- emit_move_insn (operands[0], temp);
- DONE;
- }
-}")
-
-;; For mips16, we need a special case to handle storing $31 into
-;; memory, since we don't have a constraint to match $31. This
-;; instruction can be generated by save_restore_insns.
-
-(define_insn ""
- [(set (match_operand:SI 0 "memory_operand" "=R,m")
- (reg:SI 31))]
- "TARGET_MIPS16"
- "*
-{
- operands[1] = gen_rtx (REG, SImode, 31);
- return mips_move_1word (operands, insn, FALSE);
-}"
- [(set_attr "type" "store")
- (set_attr "mode" "SI")
- (set_attr "length" "4,8")])
-
-;; The difference between these two is whether or not ints are allowed
-;; in FP registers (off by default, use -mdebugh to enable).
-
-(define_insn "movsi_internal1"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*f*z,*f,*f,*f,*R,*m,*x,*x,*d,*d")
- (match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*f*z,*d,*f,*R,*m,*f,*f,J,*d,*x,*a"))]
- "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
- && (register_operand (operands[0], SImode)
- || register_operand (operands[1], SImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,move,load,load,store,store,hilo,hilo,hilo,hilo")
- (set_attr "mode" "SI")
- (set_attr "length" "4,8,4,8,4,8,4,8,4,4,4,4,8,4,8,4,4,4,4")])
-
-(define_insn "movsi_internal2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*z,*x,*d,*x,*d")
- (match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*z,*d,J,*x,*d,*a"))]
- "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
- && (register_operand (operands[0], SImode)
- || register_operand (operands[1], SImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,hilo,hilo,hilo,hilo")
- (set_attr "mode" "SI")
- (set_attr "length" "4,8,4,8,4,8,4,8,4,4,4,4,4,4")])
-
-;; This is the mips16 movsi instruction. We accept a small integer as
-;; the source if the destination is a GP memory reference. This is
-;; because we want the combine pass to turn adding a GP reference to a
-;; register into a direct GP reference, but the combine pass will pass
-;; in the source as a constant if it finds an equivalent one. If the
-;; instruction is recognized, reload will force the constant back out
-;; into a register.
-
-(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,d,R,m,*d,*d")
- (match_operand:SI 1 "move_operand" "d,d,y,S,K,N,s,R,m,d,d,*x,*a"))]
- "TARGET_MIPS16
- && (register_operand (operands[0], SImode)
- || register_operand (operands[1], SImode)
- || (GET_CODE (operands[0]) == MEM
- && GET_CODE (XEXP (operands[0], 0)) == PLUS
- && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST
- && mips16_gp_offset_p (XEXP (XEXP (operands[0], 0), 1))
- && GET_CODE (operands[1]) == CONST_INT
- && (SMALL_INT (operands[1])
- || SMALL_INT_UNSIGNED (operands[1]))))"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "move,move,move,load,arith,arith,arith,load,load,store,store,hilo,hilo")
- (set_attr "mode" "SI")
- (set_attr_alternative "length"
- [(const_int 4)
- (const_int 4)
- (const_int 4)
- (const_int 8)
- (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
- (const_int 4)
- (const_int 8))
- (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
- (const_int 8)
- (const_int 12))
- (if_then_else (match_operand:VOID 1 "m16_usym8_4" "")
- (const_int 4)
- (const_int 8))
- (const_int 4)
- (const_int 8)
- (const_int 4)
- (const_int 8)
- (const_int 4)
- (const_int 4)])])
-
-;; On the mips16, we can split lw $r,N($r) into an add and a load,
-;; when the original load is a 4 byte instruction but the add and the
-;; load are 2 2 byte instructions.
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (mem:SI (plus:SI (match_dup 0)
- (match_operand:SI 1 "const_int_operand" ""))))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
- && ((INTVAL (operands[1]) < 0
- && INTVAL (operands[1]) >= -0x80)
- || (INTVAL (operands[1]) >= 32 * 4
- && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
- || (INTVAL (operands[1]) >= 0
- && INTVAL (operands[1]) < 32 * 4
- && (INTVAL (operands[1]) & 3) != 0))"
- [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
- (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
- "
-{
- HOST_WIDE_INT val = INTVAL (operands[1]);
-
- if (val < 0)
- operands[2] = GEN_INT (0);
- else if (val >= 32 * 4)
- {
- int off = val & 3;
-
- operands[1] = GEN_INT (0x7c + off);
- operands[2] = GEN_INT (val - off - 0x7c);
- }
- else
- {
- int off = val & 3;
-
- operands[1] = GEN_INT (off);
- operands[2] = GEN_INT (val - off);
- }
-}")
-
-;; On the mips16, we can split a load of certain constants into a load
-;; and an add. This turns a 4 byte instruction into 2 2 byte
-;; instructions.
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "const_int_operand" ""))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
- && INTVAL (operands[1]) >= 0x100
- && INTVAL (operands[1]) <= 0xff + 0x7f"
- [(set (match_dup 0) (match_dup 1))
- (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
- "
-{
- int val = INTVAL (operands[1]);
-
- operands[1] = GEN_INT (0xff);
- operands[2] = GEN_INT (val - 0xff);
-}")
-
-;; On the mips16, we can split a load of a negative constant into a
-;; load and a neg. That's what mips_move_1word will generate anyhow.
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "const_int_operand" ""))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
- && INTVAL (operands[1]) < 0
- && INTVAL (operands[1]) > - 0x8000"
- [(set (match_dup 0) (match_dup 1))
- (set (match_dup 0) (neg:SI (match_dup 0)))]
- "
-{
- operands[1] = GEN_INT (- INTVAL (operands[1]));
-}")
-
-;; Reload HILO_REGNUM in SI mode. This needs a scratch register in
-;; order to set the sign bit correctly in the HI register.
-
-(define_expand "reload_outsi"
- [(set (match_operand:SI 0 "general_operand" "=b")
- (match_operand:SI 1 "register_operand" "b"))
- (clobber (match_operand:SI 2 "register_operand" "=&d"))]
- "TARGET_64BIT || TARGET_MIPS16"
- "
-{
- if (TARGET_64BIT
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
- {
- emit_insn (gen_movsi (gen_rtx_REG (SImode, 65), operands[1]));
- emit_insn (gen_ashrsi3 (operands[2], operands[1], GEN_INT (31)));
- emit_insn (gen_movsi (gen_rtx (REG, SImode, 64), operands[2]));
- emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[0]), 2));
- DONE;
- }
- /* Use a mult to reload LO on mips16. ??? This is hideous. */
- if (TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == LO_REGNUM)
- {
- emit_insn (gen_movsi (operands[2], GEN_INT (1)));
- /* This is gen_mulsi3_internal, but we need to fill in the
- scratch registers. */
- emit_insn (gen_rtx (PARALLEL, VOIDmode,
- gen_rtvec (3,
- gen_rtx (SET, VOIDmode,
- operands[0],
- gen_rtx (MULT, SImode,
- operands[1],
- operands[2])),
- gen_rtx (CLOBBER, VOIDmode,
- gen_rtx (REG, SImode, 64)),
- gen_rtx (CLOBBER, VOIDmode,
- gen_rtx (REG, SImode, 66)))));
- DONE;
- }
- /* FIXME: I don't know how to get a value into the HI register. */
- if (GET_CODE (operands[0]) == REG
- && (TARGET_MIPS16 ? M16_REG_P (REGNO (operands[0]))
- : GP_REG_P (REGNO (operands[0]))))
- {
- emit_move_insn (operands[0], operands[1]);
- DONE;
- }
- /* This handles moves between a float register and HI/LO. */
- emit_move_insn (operands[2], operands[1]);
- emit_move_insn (operands[0], operands[2]);
- DONE;
-}")
-
-;; Reload a value into HI or LO. There is no mthi or mtlo on mips16,
-;; so we use a mult. ??? This is hideous, and we ought to figure out
-;; something better.
-
-;; We use no predicate for operand1, because it may be a PLUS, and there
-;; is no convenient predicate for that.
-
-(define_expand "reload_insi"
- [(set (match_operand:SI 0 "register_operand" "=b")
- (match_operand:SI 1 "" "b"))
- (clobber (match_operand:SI 2 "register_operand" "=&d"))]
- "TARGET_MIPS16"
- "
-{
- if (TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == LO_REGNUM)
- {
- emit_insn (gen_movsi (operands[2], GEN_INT (1)));
- /* This is gen_mulsi3_internal, but we need to fill in the
- scratch registers. */
- emit_insn (gen_rtx (PARALLEL, VOIDmode,
- gen_rtvec (3,
- gen_rtx (SET, VOIDmode,
- operands[0],
- gen_rtx (MULT, SImode,
- operands[1],
- operands[2])),
- gen_rtx (CLOBBER, VOIDmode,
- gen_rtx (REG, SImode, 64)),
- gen_rtx (CLOBBER, VOIDmode,
- gen_rtx (REG, SImode, 66)))));
- DONE;
- }
-
- /* If this is a plus, then this must be an add of the stack pointer against
- either a hard register or a pseudo. */
- if (TARGET_MIPS16 && GET_CODE (operands[1]) == PLUS)
- {
- rtx plus_op;
-
- if (XEXP (operands[1], 0) == stack_pointer_rtx)
- plus_op = XEXP (operands[1], 1);
- else if (XEXP (operands[1], 1) == stack_pointer_rtx)
- plus_op = XEXP (operands[1], 0);
- else
- abort ();
-
- /* We should have a register now. */
- if (GET_CODE (plus_op) != REG)
- abort ();
-
- if (REGNO (plus_op) < FIRST_PSEUDO_REGISTER)
- {
- /* We have to have at least one temporary register which is not
- overlapping plus_op. */
- if (! rtx_equal_p (plus_op, operands[0]))
- {
- emit_move_insn (operands[0], stack_pointer_rtx);
- emit_insn (gen_addsi3 (operands[0], operands[0], plus_op));
- }
- else if (! rtx_equal_p (plus_op, operands[2]))
- {
- emit_move_insn (operands[2], stack_pointer_rtx);
- emit_insn (gen_addsi3 (operands[0], plus_op, operands[2]));
- }
- else
- abort ();
- }
- else
- {
- /* We need two registers in this case. */
- if (! rtx_equal_p (operands[0], operands[2]))
- {
- emit_move_insn (operands[0], stack_pointer_rtx);
- emit_move_insn (operands[2], plus_op);
- emit_insn (gen_addsi3 (operands[0], operands[0], operands[2]));
- }
- else
- abort ();
- }
- DONE;
- }
-
- /* FIXME: I don't know how to get a value into the HI register. */
- emit_move_insn (operands[0], operands[1]);
- DONE;
-}")
-
-;; This insn is for the unspec delay for HILO.
-
-(define_insn "*HILO_delay"
- [(unspec [(match_operand 0 "register_operand" "=b")] 2 )]
- ""
- ""
- [(set_attr "type" "nop")
- (set_attr "mode" "none")
- (set_attr "can_delay" "no")])
-
-;; This insn handles moving CCmode values. It's really just a
-;; slightly simplified copy of movsi_internal2, with additional cases
-;; to move a condition register to a general register and to move
-;; between the general registers and the floating point registers.
-
-(define_insn "movcc"
- [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*d,*R,*m,*d,*f,*f,*f,*f,*R,*m")
- (match_operand:CC 1 "general_operand" "z,*d,*R,*m,*d,*d,*f,*d,*f,*R,*m,*f,*f"))]
- "ISA_HAS_8CC && TARGET_HARD_FLOAT"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "move,move,load,load,store,store,xfer,xfer,move,load,load,store,store")
- (set_attr "mode" "SI")
- (set_attr "length" "8,4,4,8,4,8,4,4,4,4,8,4,8")])
-
-;; Reload condition code registers. reload_incc and reload_outcc
-;; both handle moves from arbitrary operands into condition code
-;; registers. reload_incc handles the more common case in which
-;; a source operand is constrained to be in a condition-code
-;; register, but has not been allocated to one.
-;;
-;; Sometimes, such as in movcc, we have a CCmode destination whose
-;; constraints do not include 'z'. reload_outcc handles the case
-;; when such an operand is allocated to a condition-code register.
-;;
-;; Note that reloads from a condition code register to some
-;; other location can be done using ordinary moves. Moving
-;; into a GPR takes a single movcc, moving elsewhere takes
-;; two. We can leave these cases to the generic reload code.
-(define_expand "reload_incc"
- [(set (match_operand:CC 0 "fcc_register_operand" "=z")
- (match_operand:CC 1 "general_operand" ""))
- (clobber (match_operand:TF 2 "register_operand" "=&f"))]
- "ISA_HAS_8CC && TARGET_HARD_FLOAT"
- "
-{
- mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
- DONE;
-}")
-
-(define_expand "reload_outcc"
- [(set (match_operand:CC 0 "fcc_register_operand" "=z")
- (match_operand:CC 1 "register_operand" ""))
- (clobber (match_operand:TF 2 "register_operand" "=&f"))]
- "ISA_HAS_8CC && TARGET_HARD_FLOAT"
- "
-{
- mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
- DONE;
-}")
-
-;; MIPS4 supports loading and storing a floating point register from
-;; the sum of two general registers. We use two versions for each of
-;; these four instructions: one where the two general registers are
-;; SImode, and one where they are DImode. This is because general
-;; registers will be in SImode when they hold 32 bit values, but,
-;; since the 32 bit values are always sign extended, the [ls][wd]xc1
-;; instructions will still work correctly.
-
-;; ??? Perhaps it would be better to support these instructions by
-;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
-;; these instructions can only be used to load and store floating
-;; point registers, that would probably cause trouble in reload.
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d"))))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
- "lwxc1\\t%0,%1(%2)"
- [(set_attr "type" "load")
- (set_attr "mode" "SF")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d"))))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
- "lwxc1\\t%0,%1(%2)"
- [(set_attr "type" "load")
- (set_attr "mode" "SF")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f")
- (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d"))))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "ldxc1\\t%0,%1(%2)"
- [(set_attr "type" "load")
- (set_attr "mode" "DF")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f")
- (mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d"))))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "ldxc1\\t%0,%1(%2)"
- [(set_attr "type" "load")
- (set_attr "mode" "DF")])
-
-(define_insn ""
- [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (match_operand:SF 0 "register_operand" "f"))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
- "swxc1\\t%0,%1(%2)"
- [(set_attr "type" "store")
- (set_attr "mode" "SF")])
-
-(define_insn ""
- [(set (mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))
- (match_operand:SF 0 "register_operand" "f"))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
- "swxc1\\t%0,%1(%2)"
- [(set_attr "type" "store")
- (set_attr "mode" "SF")])
-
-(define_insn ""
- [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (match_operand:DF 0 "register_operand" "f"))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "sdxc1\\t%0,%1(%2)"
- [(set_attr "type" "store")
- (set_attr "mode" "DF")])
-
-(define_insn ""
- [(set (mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))
- (match_operand:DF 0 "register_operand" "f"))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "sdxc1\\t%0,%1(%2)"
- [(set_attr "type" "store")
- (set_attr "mode" "DF")])
-
-;; 16-bit Integer moves
-
-;; Unlike most other insns, the move insns can't be split with
-;; different predicates, because register spilling and other parts of
-;; the compiler, have memoized the insn number already.
-;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
-
-(define_expand "movhi"
- [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (match_operand:HI 1 "general_operand" ""))]
- ""
- "
-{
- if ((reload_in_progress | reload_completed) == 0
- && !register_operand (operands[0], HImode)
- && !register_operand (operands[1], HImode)
- && (TARGET_MIPS16
- || (GET_CODE (operands[1]) != CONST_INT
- || INTVAL (operands[1]) != 0)))
- {
- rtx temp = force_reg (HImode, operands[1]);
- emit_move_insn (operands[0], temp);
- DONE;
- }
-}")
-
-;; The difference between these two is whether or not ints are allowed
-;; in FP registers (off by default, use -mdebugh to enable).
-
-(define_insn "movhi_internal1"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f,*f*z,*x,*d")
- (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
- "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
- && (register_operand (operands[0], HImode)
- || register_operand (operands[1], HImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
- (set_attr "mode" "HI")
- (set_attr "length" "4,4,4,8,4,8,4,4,4,4,4")])
-
-(define_insn "movhi_internal2"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
- (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
- "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
- && (register_operand (operands[0], HImode)
- || register_operand (operands[1], HImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
- (set_attr "mode" "HI")
- (set_attr "length" "4,4,4,8,4,8,4,4,4,4")])
-
-(define_insn ""
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,m,*d")
- (match_operand:HI 1 "general_operand" "d,d,y,K,N,R,m,d,d,*x"))]
- "TARGET_MIPS16
- && (register_operand (operands[0], HImode)
- || register_operand (operands[1], HImode))"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "move,move,move,arith,arith,load,load,store,store,hilo")
- (set_attr "mode" "HI")
- (set_attr_alternative "length"
- [(const_int 4)
- (const_int 4)
- (const_int 4)
- (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
- (const_int 4)
- (const_int 8))
- (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
- (const_int 8)
- (const_int 12))
- (const_int 4)
- (const_int 8)
- (const_int 4)
- (const_int 8)
- (const_int 4)])])
-
-
-;; On the mips16, we can split lh $r,N($r) into an add and a load,
-;; when the original load is a 4 byte instruction but the add and the
-;; load are 2 2 byte instructions.
-
-(define_split
- [(set (match_operand:HI 0 "register_operand" "")
- (mem:HI (plus:SI (match_dup 0)
- (match_operand:SI 1 "const_int_operand" ""))))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
- && ((INTVAL (operands[1]) < 0
- && INTVAL (operands[1]) >= -0x80)
- || (INTVAL (operands[1]) >= 32 * 2
- && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
- || (INTVAL (operands[1]) >= 0
- && INTVAL (operands[1]) < 32 * 2
- && (INTVAL (operands[1]) & 1) != 0))"
- [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
- (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
- "
-{
- HOST_WIDE_INT val = INTVAL (operands[1]);
-
- if (val < 0)
- operands[2] = GEN_INT (0);
- else if (val >= 32 * 2)
- {
- int off = val & 1;
-
- operands[1] = GEN_INT (0x7e + off);
- operands[2] = GEN_INT (val - off - 0x7e);
- }
- else
- {
- int off = val & 1;
-
- operands[1] = GEN_INT (off);
- operands[2] = GEN_INT (val - off);
- }
-}")
-
-;; 8-bit Integer moves
-
-;; Unlike most other insns, the move insns can't be split with
-;; different predicates, because register spilling and other parts of
-;; the compiler, have memoized the insn number already.
-;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
-
-(define_expand "movqi"
- [(set (match_operand:QI 0 "nonimmediate_operand" "")
- (match_operand:QI 1 "general_operand" ""))]
- ""
- "
-{
- if ((reload_in_progress | reload_completed) == 0
- && !register_operand (operands[0], QImode)
- && !register_operand (operands[1], QImode)
- && (TARGET_MIPS16
- || (GET_CODE (operands[1]) != CONST_INT
- || INTVAL (operands[1]) != 0)))
- {
- rtx temp = force_reg (QImode, operands[1]);
- emit_move_insn (operands[0], temp);
- DONE;
- }
-}")
-
-;; The difference between these two is whether or not ints are allowed
-;; in FP registers (off by default, use -mdebugh to enable).
-
-(define_insn "movqi_internal1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f*z,*f,*x,*d")
- (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
- "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
- && (register_operand (operands[0], QImode)
- || register_operand (operands[1], QImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
- (set_attr "mode" "QI")
- (set_attr "length" "4,4,4,8,4,8,4,4,4,4,4")])
-
-(define_insn "movqi_internal2"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
- (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
- "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
- && (register_operand (operands[0], QImode)
- || register_operand (operands[1], QImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
- (set_attr "mode" "QI")
- (set_attr "length" "4,4,4,8,4,8,4,4,4,4")])
-
-(define_insn ""
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,m,*d")
- (match_operand:QI 1 "general_operand" "d,d,y,K,N,R,m,d,d,*x"))]
- "TARGET_MIPS16
- && (register_operand (operands[0], QImode)
- || register_operand (operands[1], QImode))"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "move,move,move,arith,arith,load,load,store,store,hilo")
- (set_attr "mode" "QI")
- (set_attr_alternative "length"
- [(const_int 4)
- (const_int 4)
- (const_int 4)
- (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
- (const_int 4)
- (const_int 8))
- (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
- (const_int 8)
- (const_int 12))
- (const_int 4)
- (const_int 8)
- (const_int 4)
- (const_int 8)
- (const_int 4)])])
-
-
-;; On the mips16, we can split lb $r,N($r) into an add and a load,
-;; when the original load is a 4 byte instruction but the add and the
-;; load are 2 2 byte instructions.
-
-(define_split
- [(set (match_operand:QI 0 "register_operand" "")
- (mem:QI (plus:SI (match_dup 0)
- (match_operand:SI 1 "const_int_operand" ""))))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
- && ((INTVAL (operands[1]) < 0
- && INTVAL (operands[1]) >= -0x80)
- || (INTVAL (operands[1]) >= 32
- && INTVAL (operands[1]) <= 31 + 0x7f))"
- [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
- (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
- "
-{
- HOST_WIDE_INT val = INTVAL (operands[1]);
-
- if (val < 0)
- operands[2] = GEN_INT (0);
- else
- {
- operands[1] = GEN_INT (0x7f);
- operands[2] = GEN_INT (val - 0x7f);
- }
-}")
-
-;; 32-bit floating point moves
-
-(define_expand "movsf"
- [(set (match_operand:SF 0 "nonimmediate_operand" "")
- (match_operand:SF 1 "general_operand" ""))]
- ""
- "
-{
- if ((reload_in_progress | reload_completed) == 0
- && !register_operand (operands[0], SFmode)
- && !register_operand (operands[1], SFmode)
- && (TARGET_MIPS16
- || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
- && operands[1] != CONST0_RTX (SFmode))))
- {
- rtx temp = force_reg (SFmode, operands[1]);
- emit_move_insn (operands[0], temp);
- DONE;
- }
-}")
-
-(define_insn "movsf_internal1"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,m,*f,*d,*d,*d,*d,*R,*m")
- (match_operand:SF 1 "general_operand" "f,G,R,Fm,fG,fG,*d,*f,*G*d,*R,*F*m,*d,*d"))]
- "TARGET_HARD_FLOAT
- && (register_operand (operands[0], SFmode)
- || register_operand (operands[1], SFmode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
- || operands[1] == CONST0_RTX (SFmode))"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "move,xfer,load,load,store,store,xfer,xfer,move,load,load,store,store")
- (set_attr "mode" "SF")
- (set_attr "length" "4,4,4,8,4,8,4,4,4,4,8,4,8")])
-
-
-(define_insn "movsf_internal2"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,R,m")
- (match_operand:SF 1 "general_operand" " Gd,R,Fm,d,d"))]
- "TARGET_SOFT_FLOAT && !TARGET_MIPS16
- && (register_operand (operands[0], SFmode)
- || register_operand (operands[1], SFmode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
- || operands[1] == CONST0_RTX (SFmode))"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "move,load,load,store,store")
- (set_attr "mode" "SF")
- (set_attr "length" "4,4,8,4,8")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,d,R,m")
- (match_operand:SF 1 "general_operand" "d,d,y,R,Fm,d,d"))]
- "TARGET_MIPS16
- && (register_operand (operands[0], SFmode)
- || register_operand (operands[1], SFmode))"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "move,move,move,load,load,store,store")
- (set_attr "mode" "SF")
- (set_attr "length" "4,4,4,4,8,4,8")])
-
-
-;; 64-bit floating point moves
-
-(define_expand "movdf"
- [(set (match_operand:DF 0 "nonimmediate_operand" "")
- (match_operand:DF 1 "general_operand" ""))]
- ""
- "
-{
- if ((reload_in_progress | reload_completed) == 0
- && !register_operand (operands[0], DFmode)
- && !register_operand (operands[1], DFmode)
- && (TARGET_MIPS16
- || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
- && operands[1] != CONST0_RTX (DFmode))))
- {
- rtx temp = force_reg (DFmode, operands[1]);
- emit_move_insn (operands[0], temp);
- DONE;
- }
-}")
-
-(define_insn "movdf_internal1"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,To,f,*f,*d,*d,*d,*d,*R,*T")
- (match_operand:DF 1 "general_operand" "f,R,To,fG,fG,F,*d,*f,*d*G,*R,*T*F,*d,*d"))]
- "TARGET_HARD_FLOAT && !(TARGET_FLOAT64 && !TARGET_64BIT)
- && TARGET_DOUBLE_FLOAT
- && (register_operand (operands[0], DFmode)
- || register_operand (operands[1], DFmode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
- || operands[1] == CONST0_RTX (DFmode))"
- "* return mips_move_2words (operands, insn); "
- [(set_attr "type" "move,load,load,store,store,load,xfer,xfer,move,load,load,store,store")
- (set_attr "mode" "DF")
- (set_attr "length" "4,8,16,8,16,16,8,8,8,8,16,8,16")])
-
-(define_insn "movdf_internal1a"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,R,R,To,To,*d,*d,*d,*To,*R,*d")
- (match_operand:DF 1 "general_operand" " f,To,f,G,f,G,*F,*To,*R,*d,*d,*d"))]
- "TARGET_HARD_FLOAT && (TARGET_FLOAT64 && !TARGET_64BIT)
- && TARGET_DOUBLE_FLOAT
- && (register_operand (operands[0], DFmode)
- || register_operand (operands[1], DFmode)
- || (GET_CODE (operands [0]) == MEM
- && ((GET_CODE (operands[1]) == CONST_INT
- && INTVAL (operands[1]) == 0)
- || operands[1] == CONST0_RTX (DFmode))))"
- "* return mips_move_2words (operands, insn); "
- [(set_attr "type" "move,load,store,store,store,store,load,load,load,store,store,move")
- (set_attr "mode" "DF")
- (set_attr "length" "4,8,4,4,8,8,8,8,4,8,4,4")])
-
-(define_insn "movdf_internal2"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,R,To,*d")
- (match_operand:DF 1 "general_operand" "dG,R,ToF,d,d,*f"))]
- "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
- && (register_operand (operands[0], DFmode)
- || register_operand (operands[1], DFmode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
- || operands[1] == CONST0_RTX (DFmode))"
- "* return mips_move_2words (operands, insn); "
- [(set_attr "type" "move,load,load,store,store,xfer")
- (set_attr "mode" "DF")
- (set_attr "length" "8,8,16,8,16,8")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,d,R,To")
- (match_operand:DF 1 "general_operand" "d,d,y,R,ToF,d,d"))]
- "TARGET_MIPS16
- && (register_operand (operands[0], DFmode)
- || register_operand (operands[1], DFmode))"
- "* return mips_move_2words (operands, insn);"
- [(set_attr "type" "move,move,move,load,load,store,store")
- (set_attr "mode" "DF")
- (set_attr "length" "8,8,8,8,16,8,16")])
-
-(define_split
- [(set (match_operand:DF 0 "register_operand" "")
- (match_operand:DF 1 "register_operand" ""))]
- "reload_completed && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
- [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
- (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
- "")
-
-;; Instructions to load the global pointer register.
-;; This is volatile to make sure that the scheduler won't move any symbol_ref
-;; uses in front of it. All symbol_refs implicitly use the gp reg.
-
-(define_insn "loadgp"
- [(set (reg:DI 28)
- (unspec_volatile:DI [(match_operand:DI 0 "address_operand" "")
- (match_operand:DI 1 "register_operand" "")] 2))
- (clobber (reg:DI 1))]
- ""
- "%[lui\\t$1,%%hi(%%neg(%%gp_rel(%a0)))\\n\\taddiu\\t$1,$1,%%lo(%%neg(%%gp_rel(%a0)))\\n\\tdaddu\\t$gp,$1,%1%]"
- [(set_attr "type" "move")
- (set_attr "mode" "DI")
- (set_attr "length" "12")])
-\f
-;; Block moves, see mips.c for more details.
-;; Argument 0 is the destination
-;; Argument 1 is the source
-;; Argument 2 is the length
-;; Argument 3 is the alignment
-
-(define_expand "movstrsi"
- [(parallel [(set (match_operand:BLK 0 "general_operand" "")
- (match_operand:BLK 1 "general_operand" ""))
- (use (match_operand:SI 2 "arith32_operand" ""))
- (use (match_operand:SI 3 "immediate_operand" ""))])]
- "!TARGET_MIPS16"
- "
-{
- if (operands[0]) /* avoid unused code messages */
- {
- expand_block_move (operands);
- DONE;
- }
-}")
-
-;; Insn generated by block moves
-
-(define_insn "movstrsi_internal"
- [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination
- (match_operand:BLK 1 "memory_operand" "o")) ;; source
- (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
- (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
- (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
- (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
- (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
- (use (match_operand:SI 3 "small_int" "I")) ;; alignment
- (use (const_int 0))] ;; normal block move
- ""
- "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
- [(set_attr "type" "store")
- (set_attr "mode" "none")
- (set_attr "length" "80")])
-
-;; We need mips16 versions, because an offset from the stack pointer
-;; is not offsettable, since the stack pointer can only handle 4 and 8
-;; byte loads.
-
-(define_insn ""
- [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination
- (match_operand:BLK 1 "memory_operand" "o")) ;; source
- (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
- (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
- (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
- (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
- (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
- (use (match_operand:SI 3 "small_int" "I")) ;; alignment
- (use (const_int 0))] ;; normal block move
- "TARGET_MIPS16"
- "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
- [(set_attr "type" "multi")
- (set_attr "mode" "none")
- (set_attr "length" "80")])
-
-;; Split a block move into 2 parts, the first part is everything
-;; except for the last move, and the second part is just the last
-;; store, which is exactly 1 instruction (ie, not a usw), so it can
-;; fill a delay slot. This also prevents a bug in delayed branches
-;; from showing up, which reuses one of the registers in our clobbers.
-
-(define_split
- [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
- (mem:BLK (match_operand:SI 1 "register_operand" "")))
- (clobber (match_operand:SI 4 "register_operand" ""))
- (clobber (match_operand:SI 5 "register_operand" ""))
- (clobber (match_operand:SI 6 "register_operand" ""))
- (clobber (match_operand:SI 7 "register_operand" ""))
- (use (match_operand:SI 2 "small_int" ""))
- (use (match_operand:SI 3 "small_int" ""))
- (use (const_int 0))]
-
- "reload_completed && !TARGET_DEBUG_D_MODE && INTVAL (operands[2]) > 0"
-
- ;; All but the last move
- [(parallel [(set (mem:BLK (match_dup 0))
- (mem:BLK (match_dup 1)))
- (clobber (match_dup 4))
- (clobber (match_dup 5))
- (clobber (match_dup 6))
- (clobber (match_dup 7))
- (use (match_dup 2))
- (use (match_dup 3))
- (use (const_int 1))])
-
- ;; The last store, so it can fill a delay slot
- (parallel [(set (mem:BLK (match_dup 0))
- (mem:BLK (match_dup 1)))
- (clobber (match_dup 4))
- (clobber (match_dup 5))
- (clobber (match_dup 6))
- (clobber (match_dup 7))
- (use (match_dup 2))
- (use (match_dup 3))
- (use (const_int 2))])]
-
- "")
-
-(define_insn "movstrsi_internal2"
- [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination
- (match_operand:BLK 1 "memory_operand" "o")) ;; source
- (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
- (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
- (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
- (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
- (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
- (use (match_operand:SI 3 "small_int" "I")) ;; alignment
- (use (const_int 1))] ;; all but last store
- ""
- "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);"
- [(set_attr "type" "store")
- (set_attr "mode" "none")
- (set_attr "length" "80")])
-
-(define_insn ""
- [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination
- (match_operand:BLK 1 "memory_operand" "o")) ;; source
- (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
- (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
- (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
- (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
- (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
- (use (match_operand:SI 3 "small_int" "I")) ;; alignment
- (use (const_int 1))] ;; all but last store
- "TARGET_MIPS16"
- "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);"
- [(set_attr "type" "multi")
- (set_attr "mode" "none")
- (set_attr "length" "80")])
-
-(define_insn "movstrsi_internal3"
- [(set (match_operand:BLK 0 "memory_operand" "=Ro") ;; destination
- (match_operand:BLK 1 "memory_operand" "Ro")) ;; source
- (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
- (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
- (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
- (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
- (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
- (use (match_operand:SI 3 "small_int" "I")) ;; alignment
- (use (const_int 2))] ;; just last store of block move
- ""
- "* return output_block_move (insn, operands, 4, BLOCK_MOVE_LAST);"
- [(set_attr "type" "store")
- (set_attr "mode" "none")])
-\f
-;;
-;; ....................
-;;
-;; SHIFTS
-;;
-;; ....................
-
-;; Many of these instructions uses trivial define_expands, because we
-;; want to use a different set of constraints when TARGET_MIPS16.
-
-(define_expand "ashlsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ashift:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- ""
- "
-{
- /* On the mips16, a shift of more than 8 is a four byte instruction,
- so, for a shift between 8 and 16, it is just as fast to do two
- shifts of 8 or less. If there is a lot of shifting going on, we
- may win in CSE. Otherwise combine will put the shifts back
- together again. This can be called by function_arg, so we must
- be careful not to allocate a new register if we've reached the
- reload pass. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16
- && ! reload_in_progress
- && ! reload_completed)
- {
- rtx temp = gen_reg_rtx (SImode);
-
- emit_insn (gen_ashlsi3_internal2 (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_ashlsi3_internal2 (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
-}")
-
-(define_insn "ashlsi3_internal1"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ashift:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "!TARGET_MIPS16"
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
- return \"sll\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-(define_insn "ashlsi3_internal2"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (ashift:SI (match_operand:SI 1 "register_operand" "0,d")
- (match_operand:SI 2 "arith_operand" "d,I")))]
- "TARGET_MIPS16"
- "*
-{
- if (which_alternative == 0)
- return \"sll\\t%0,%2\";
-
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
- return \"sll\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr_alternative "length"
- [(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 4)
- (const_int 8))])])
-
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (ashift:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16"
- [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 8)))
- (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))]
-"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
-
-(define_expand "ashldi3"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "se_register_operand" "")
- (match_operand:SI 2 "arith_operand" "")))
- (clobber (match_dup 3))])]
- "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
- "
-{
- if (TARGET_64BIT)
- {
- /* On the mips16, a shift of more than 8 is a four byte
- instruction, so, for a shift between 8 and 16, it is just as
- fast to do two shifts of 8 or less. If there is a lot of
- shifting going on, we may win in CSE. Otherwise combine will
- put the shifts back together again. This can be called by
- function_arg, so we must be careful not to allocate a new
- register if we've reached the reload pass. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16
- && ! reload_in_progress
- && ! reload_completed)
- {
- rtx temp = gen_reg_rtx (DImode);
-
- emit_insn (gen_ashldi3_internal4 (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_ashldi3_internal4 (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
-
- emit_insn (gen_ashldi3_internal4 (operands[0], operands[1],
- operands[2]));
- DONE;
- }
-
- operands[3] = gen_reg_rtx (SImode);
-}")
-
-
-(define_insn "ashldi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=&d")
- (ashift:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "*
-{
- operands[4] = const0_rtx;
- dslots_jump_total += 3;
- dslots_jump_filled += 2;
-
- return \"sll\\t%3,%2,26\\n\\
-\\tbgez\\t%3,1f\\n\\
-\\tsll\\t%M0,%L1,%2\\n\\
-\\t%(b\\t3f\\n\\
-\\tmove\\t%L0,%z4%)\\n\\
-\\n\\
-%~1:\\n\\
-\\t%(beq\\t%3,%z4,2f\\n\\
-\\tsll\\t%M0,%M1,%2%)\\n\\
-\\n\\
-\\tsubu\\t%3,%z4,%2\\n\\
-\\tsrl\\t%3,%L1,%3\\n\\
-\\tor\\t%M0,%M0,%3\\n\\
-%~2:\\n\\
-\\tsll\\t%L0,%L1,%2\\n\\
-%~3:\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "SI")
- (set_attr "length" "48")])
-
-
-(define_insn "ashldi3_internal2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashift:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && (INTVAL (operands[2]) & 32) != 0"
- "*
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
- operands[4] = const0_rtx;
- return \"sll\\t%M0,%L1,%2\;move\\t%L0,%z4\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 4) (ashift:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 0) (const_int 0))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 0) (ashift:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 4) (const_int 0))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_insn "ashldi3_internal3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashift:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
- "*
-{
- int amount = INTVAL (operands[2]);
-
- operands[2] = GEN_INT (amount & 31);
- operands[4] = const0_rtx;
- operands[5] = GEN_INT ((-amount) & 31);
-
- return \"sll\\t%M0,%M1,%2\;srl\\t%3,%L1,%5\;or\\t%M0,%M0,%3\;sll\\t%L0,%L1,%2\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 4)
- (ashift:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))
-
- (set (match_dup 3)
- (lshiftrt:SI (subreg:SI (match_dup 1) 0)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 4)
- (ior:SI (subreg:SI (match_dup 0) 4)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 0)
- (ashift:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))]
- "
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-}")
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 0)
- (ashift:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))
-
- (set (match_dup 3)
- (lshiftrt:SI (subreg:SI (match_dup 1) 4)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 0)
- (ior:SI (subreg:SI (match_dup 0) 0)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 4)
- (ashift:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))]
- "
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-}")
-
-
-(define_insn "ashldi3_internal4"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashift:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
- return \"dsll\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (ashift:DI (match_operand:DI 1 "se_register_operand" "0,d")
- (match_operand:SI 2 "arith_operand" "d,I")))]
- "TARGET_64BIT && TARGET_MIPS16"
- "*
-{
- if (which_alternative == 0)
- return \"dsll\\t%0,%2\";
-
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
- return \"dsll\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr_alternative "length"
- [(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 4)
- (const_int 8))])])
-
-
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
- "TARGET_MIPS16 && TARGET_64BIT && !TARGET_DEBUG_D_MODE
- && reload_completed
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16"
- [(set (match_dup 0) (ashift:DI (match_dup 1) (const_int 8)))
- (set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))]
-"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
-
-(define_expand "ashrsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- ""
- "
-{
- /* On the mips16, a shift of more than 8 is a four byte instruction,
- so, for a shift between 8 and 16, it is just as fast to do two
- shifts of 8 or less. If there is a lot of shifting going on, we
- may win in CSE. Otherwise combine will put the shifts back
- together again. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16)
- {
- rtx temp = gen_reg_rtx (SImode);
-
- emit_insn (gen_ashrsi3_internal2 (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_ashrsi3_internal2 (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
-}")
-
-(define_insn "ashrsi3_internal1"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "!TARGET_MIPS16"
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
- return \"sra\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-(define_insn "ashrsi3_internal2"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
- (match_operand:SI 2 "arith_operand" "d,I")))]
- "TARGET_MIPS16"
- "*
-{
- if (which_alternative == 0)
- return \"sra\\t%0,%2\";
-
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
- return \"sra\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr_alternative "length"
- [(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 4)
- (const_int 8))])])
-
-
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16"
- [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 8)))
- (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
-"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
-
-(define_expand "ashrdi3"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "")
- (match_operand:SI 2 "arith_operand" "")))
- (clobber (match_dup 3))])]
- "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
- "
-{
- if (TARGET_64BIT)
- {
- /* On the mips16, a shift of more than 8 is a four byte
- instruction, so, for a shift between 8 and 16, it is just as
- fast to do two shifts of 8 or less. If there is a lot of
- shifting going on, we may win in CSE. Otherwise combine will
- put the shifts back together again. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16)
- {
- rtx temp = gen_reg_rtx (DImode);
-
- emit_insn (gen_ashrdi3_internal4 (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_ashrdi3_internal4 (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
-
- emit_insn (gen_ashrdi3_internal4 (operands[0], operands[1],
- operands[2]));
- DONE;
- }
-
- operands[3] = gen_reg_rtx (SImode);
-}")
-
-
-(define_insn "ashrdi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=&d")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "*
-{
- operands[4] = const0_rtx;
- dslots_jump_total += 3;
- dslots_jump_filled += 2;
-
- return \"sll\\t%3,%2,26\\n\\
-\\tbgez\\t%3,1f\\n\\
-\\tsra\\t%L0,%M1,%2\\n\\
-\\t%(b\\t3f\\n\\
-\\tsra\\t%M0,%M1,31%)\\n\\
-\\n\\
-%~1:\\n\\
-\\t%(beq\\t%3,%z4,2f\\n\\
-\\tsrl\\t%L0,%L1,%2%)\\n\\
-\\n\\
-\\tsubu\\t%3,%z4,%2\\n\\
-\\tsll\\t%3,%M1,%3\\n\\
-\\tor\\t%L0,%L0,%3\\n\\
-%~2:\\n\\
-\\tsra\\t%M0,%M1,%2\\n\\
-%~3:\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "48")])
-
-
-(define_insn "ashrdi3_internal2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
- "*
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
- return \"sra\\t%L0,%M1,%2\;sra\\t%M0,%M1,31\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 4) (ashiftrt:SI (subreg:SI (match_dup 1) 4) (const_int 31)))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 4) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (const_int 31)))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_insn "ashrdi3_internal3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
- "*
-{
- int amount = INTVAL (operands[2]);
-
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-
- return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;sra\\t%M0,%M1,%2\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 0)
- (lshiftrt:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ashift:SI (subreg:SI (match_dup 1) 4)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 0)
- (ior:SI (subreg:SI (match_dup 0) 0)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 4)
- (ashiftrt:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))]
- "
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-}")
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 4)
- (lshiftrt:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ashift:SI (subreg:SI (match_dup 1) 0)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 4)
- (ior:SI (subreg:SI (match_dup 0) 4)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 0)
- (ashiftrt:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))]
- "
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-}")
-
-
-(define_insn "ashrdi3_internal4"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
- return \"dsra\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "0,0")
- (match_operand:SI 2 "arith_operand" "d,I")))]
- "TARGET_64BIT && TARGET_MIPS16"
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
- return \"dsra\\t%0,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr_alternative "length"
- [(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 4)
- (const_int 8))])])
-
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
- "TARGET_MIPS16 && TARGET_64BIT && !TARGET_DEBUG_D_MODE
- && reload_completed
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16"
- [(set (match_dup 0) (ashiftrt:DI (match_dup 1) (const_int 8)))
- (set (match_dup 0) (ashiftrt:DI (match_dup 0) (match_dup 2)))]
-"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
-
-(define_expand "lshrsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- ""
- "
-{
- /* On the mips16, a shift of more than 8 is a four byte instruction,
- so, for a shift between 8 and 16, it is just as fast to do two
- shifts of 8 or less. If there is a lot of shifting going on, we
- may win in CSE. Otherwise combine will put the shifts back
- together again. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16)
- {
- rtx temp = gen_reg_rtx (SImode);
-
- emit_insn (gen_lshrsi3_internal2 (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_lshrsi3_internal2 (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
-}")
-
-(define_insn "lshrsi3_internal1"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "!TARGET_MIPS16"
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
- return \"srl\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-(define_insn "lshrsi3_internal2"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
- (match_operand:SI 2 "arith_operand" "d,I")))]
- "TARGET_MIPS16"
- "*
-{
- if (which_alternative == 0)
- return \"srl\\t%0,%2\";
-
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
- return \"srl\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr_alternative "length"
- [(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 4)
- (const_int 8))])])
-
-
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16"
- [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (const_int 8)))
- (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
-"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
-
-;; If we load a byte on the mips16 as a bitfield, the resulting
-;; sequence of instructions is too complicated for combine, because it
-;; involves four instructions: a load, a shift, a constant load into a
-;; register, and an and (the key problem here is that the mips16 does
-;; not have and immediate). We recognize a shift of a load in order
-;; to make it simple enough for combine to understand.
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (lshiftrt:SI (match_operand:SI 1 "memory_operand" "R,m")
- (match_operand:SI 2 "immediate_operand" "I,I")))]
- "TARGET_MIPS16"
- "lw\\t%0,%1\;srl\\t%0,%2"
- [(set_attr "type" "load")
- (set_attr "mode" "SI")
- (set_attr_alternative "length"
- [(if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 8)
- (const_int 12))
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 12)
- (const_int 16))])])
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (lshiftrt:SI (match_operand:SI 1 "memory_operand" "")
- (match_operand:SI 2 "immediate_operand" "")))]
- "TARGET_MIPS16 && !TARGET_DEBUG_D_MODE"
- [(set (match_dup 0) (match_dup 1))
- (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
- "")
-
-(define_expand "lshrdi3"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "")
- (match_operand:SI 2 "arith_operand" "")))
- (clobber (match_dup 3))])]
- "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
- "
-{
- if (TARGET_64BIT)
- {
- /* On the mips16, a shift of more than 8 is a four byte
- instruction, so, for a shift between 8 and 16, it is just as
- fast to do two shifts of 8 or less. If there is a lot of
- shifting going on, we may win in CSE. Otherwise combine will
- put the shifts back together again. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16)
- {
- rtx temp = gen_reg_rtx (DImode);
-
- emit_insn (gen_lshrdi3_internal4 (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_lshrdi3_internal4 (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
-
- emit_insn (gen_lshrdi3_internal4 (operands[0], operands[1],
- operands[2]));
- DONE;
- }
-
- operands[3] = gen_reg_rtx (SImode);
-}")
-
-
-(define_insn "lshrdi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=&d")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "*
-{
- operands[4] = const0_rtx;
- dslots_jump_total += 3;
- dslots_jump_filled += 2;
-
- return \"sll\\t%3,%2,26\\n\\
-\\tbgez\\t%3,1f\\n\\
-\\tsrl\\t%L0,%M1,%2\\n\\
-\\t%(b\\t3f\\n\\
-\\tmove\\t%M0,%z4%)\\n\\
-\\n\\
-%~1:\\n\\
-\\t%(beq\\t%3,%z4,2f\\n\\
-\\tsrl\\t%L0,%L1,%2%)\\n\\
-\\n\\
-\\tsubu\\t%3,%z4,%2\\n\\
-\\tsll\\t%3,%M1,%3\\n\\
-\\tor\\t%L0,%L0,%3\\n\\
-%~2:\\n\\
-\\tsrl\\t%M0,%M1,%2\\n\\
-%~3:\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "48")])
-
-
-(define_insn "lshrdi3_internal2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && (INTVAL (operands[2]) & 32) != 0"
- "*
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
- operands[4] = const0_rtx;
- return \"srl\\t%L0,%M1,%2\;move\\t%M0,%z4\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 0) (lshiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 4) (const_int 0))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 4) (lshiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 0) (const_int 0))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_insn "lshrdi3_internal3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
- "*
-{
- int amount = INTVAL (operands[2]);
-
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-
- return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;srl\\t%M0,%M1,%2\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 0)
- (lshiftrt:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ashift:SI (subreg:SI (match_dup 1) 4)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 0)
- (ior:SI (subreg:SI (match_dup 0) 0)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 4)
- (lshiftrt:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))]
- "
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-}")
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 4)
- (lshiftrt:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ashift:SI (subreg:SI (match_dup 1) 0)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 4)
- (ior:SI (subreg:SI (match_dup 0) 4)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 0)
- (lshiftrt:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))]
- "
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-}")
-
-
-(define_insn "lshrdi3_internal4"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
- return \"dsrl\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "0,0")
- (match_operand:SI 2 "arith_operand" "d,I")))]
- "TARGET_64BIT && TARGET_MIPS16"
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
- return \"dsrl\\t%0,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr_alternative "length"
- [(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 4)
- (const_int 8))])])
-
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16"
- [(set (match_dup 0) (lshiftrt:DI (match_dup 1) (const_int 8)))
- (set (match_dup 0) (lshiftrt:DI (match_dup 0) (match_dup 2)))]
-"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
-
-\f
-;;
-;; ....................
-;;
-;; COMPARISONS
-;;
-;; ....................
-
-;; Flow here is rather complex:
-;;
-;; 1) The cmp{si,di,sf,df} routine is called. It deposits the
-;; arguments into the branch_cmp array, and the type into
-;; branch_type. No RTL is generated.
-;;
-;; 2) The appropriate branch define_expand is called, which then
-;; creates the appropriate RTL for the comparison and branch.
-;; Different CC modes are used, based on what type of branch is
-;; done, so that we can constrain things appropriately. There
-;; are assumptions in the rest of GCC that break if we fold the
-;; operands into the branchs for integer operations, and use cc0
-;; for floating point, so we use the fp status register instead.
-;; If needed, an appropriate temporary is created to hold the
-;; of the integer compare.
-
-(define_expand "cmpsi"
- [(set (cc0)
- (compare:CC (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "arith_operand" "")))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code message */
- {
- branch_cmp[0] = operands[0];
- branch_cmp[1] = operands[1];
- branch_type = CMP_SI;
- DONE;
- }
-}")
-
-(define_expand "tstsi"
- [(set (cc0)
- (match_operand:SI 0 "register_operand" ""))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code message */
- {
- branch_cmp[0] = operands[0];
- branch_cmp[1] = const0_rtx;
- branch_type = CMP_SI;
- DONE;
- }
-}")
-
-(define_expand "cmpdi"
- [(set (cc0)
- (compare:CC (match_operand:DI 0 "se_register_operand" "")
- (match_operand:DI 1 "se_arith_operand" "")))]
- "TARGET_64BIT"
- "
-{
- if (operands[0]) /* avoid unused code message */
- {
- branch_cmp[0] = operands[0];
- branch_cmp[1] = operands[1];
- branch_type = CMP_DI;
- DONE;
- }
-}")
-
-(define_expand "tstdi"
- [(set (cc0)
- (match_operand:DI 0 "se_register_operand" ""))]
- "TARGET_64BIT"
- "
-{
- if (operands[0]) /* avoid unused code message */
- {
- branch_cmp[0] = operands[0];
- branch_cmp[1] = const0_rtx;
- branch_type = CMP_DI;
- DONE;
- }
-}")
-
-(define_expand "cmpdf"
- [(set (cc0)
- (compare:CC (match_operand:DF 0 "register_operand" "")
- (match_operand:DF 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "
-{
- if (operands[0]) /* avoid unused code message */
- {
- branch_cmp[0] = operands[0];
- branch_cmp[1] = operands[1];
- branch_type = CMP_DF;
- DONE;
- }
-}")
-
-(define_expand "cmpsf"
- [(set (cc0)
- (compare:CC (match_operand:SF 0 "register_operand" "")
- (match_operand:SF 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT"
- "
-{
- if (operands[0]) /* avoid unused code message */
- {
- branch_cmp[0] = operands[0];
- branch_cmp[1] = operands[1];
- branch_type = CMP_SF;
- DONE;
- }
-}")
-
-\f
-;;
-;; ....................
-;;
-;; CONDITIONAL BRANCHES
-;;
-;; ....................
-
-;; Conditional branches on floating-point equality tests.
-
-(define_insn "branch_fp"
- [(set (pc)
- (if_then_else
- (match_operator:CC 0 "cmp_op"
- [(match_operand:CC 2 "register_operand" "z")
- (const_int 0)])
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- "TARGET_HARD_FLOAT"
- "*
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/0,
- /*float_p=*/1,
- /*inverted_p=*/0,
- get_attr_length (insn));
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-(define_insn "branch_fp_inverted"
- [(set (pc)
- (if_then_else
- (match_operator:CC 0 "cmp_op"
- [(match_operand:CC 2 "register_operand" "z")
- (const_int 0)])
- (pc)
- (label_ref (match_operand 1 "" ""))))]
- "TARGET_HARD_FLOAT"
- "*
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/0,
- /*float_p=*/1,
- /*inverted_p=*/1,
- get_attr_length (insn));
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-;; Conditional branches on comparisons with zero.
-
-(define_insn "branch_zero"
- [(set (pc)
- (if_then_else
- (match_operator:SI 0 "cmp_op"
- [(match_operand:SI 2 "register_operand" "d")
- (const_int 0)])
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- "!TARGET_MIPS16"
- "*
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/0,
- /*float_p=*/0,
- /*inverted_p=*/0,
- get_attr_length (insn));
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-(define_insn "branch_zero_inverted"
- [(set (pc)
- (if_then_else
- (match_operator:SI 0 "cmp_op"
- [(match_operand:SI 2 "register_operand" "d")
- (const_int 0)])
- (pc)
- (label_ref (match_operand 1 "" ""))))]
- "!TARGET_MIPS16"
- "*
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/0,
- /*float_p=*/0,
- /*inverted_p=*/1,
- get_attr_length (insn));
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-(define_insn "branch_zero_di"
- [(set (pc)
- (if_then_else
- (match_operator:DI 0 "cmp_op"
- [(match_operand:DI 2 "se_register_operand" "d")
- (const_int 0)])
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- "!TARGET_MIPS16"
- "*
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/0,
- /*float_p=*/0,
- /*inverted_p=*/0,
- get_attr_length (insn));
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-(define_insn "branch_zero_di_inverted"
- [(set (pc)
- (if_then_else
- (match_operator:DI 0 "cmp_op"
- [(match_operand:DI 2 "se_register_operand" "d")
- (const_int 0)])
- (pc)
- (label_ref (match_operand 1 "" ""))))]
- "!TARGET_MIPS16"
- "*
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/0,
- /*float_p=*/0,
- /*inverted_p=*/1,
- get_attr_length (insn));
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-;; Conditional branch on equality comparision.
-
-(define_insn "branch_equality"
- [(set (pc)
- (if_then_else
- (match_operator:SI 0 "equality_op"
- [(match_operand:SI 2 "register_operand" "d")
- (match_operand:SI 3 "register_operand" "d")])
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- "!TARGET_MIPS16"
- "*
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/1,
- /*float_p=*/0,
- /*inverted_p=*/0,
- get_attr_length (insn));
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-(define_insn "branch_equality_di"
- [(set (pc)
- (if_then_else
- (match_operator:DI 0 "equality_op"
- [(match_operand:DI 2 "se_register_operand" "d")
- (match_operand:DI 3 "se_register_operand" "d")])
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- "!TARGET_MIPS16"
- "*
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/1,
- /*float_p=*/0,
- /*inverted_p=*/0,
- get_attr_length (insn));
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-(define_insn "branch_equality_inverted"
- [(set (pc)
- (if_then_else
- (match_operator:SI 0 "equality_op"
- [(match_operand:SI 2 "register_operand" "d")
- (match_operand:SI 3 "register_operand" "d")])
- (pc)
- (label_ref (match_operand 1 "" ""))))]
- "!TARGET_MIPS16"
- "*
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/1,
- /*float_p=*/0,
- /*inverted_p=*/1,
- get_attr_length (insn));
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-(define_insn "branch_equality_di_inverted"
- [(set (pc)
- (if_then_else
- (match_operator:DI 0 "equality_op"
- [(match_operand:DI 2 "se_register_operand" "d")
- (match_operand:DI 3 "se_register_operand" "d")])
- (pc)
- (label_ref (match_operand 1 "" ""))))]
- "!TARGET_MIPS16"
- "*
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/1,
- /*float_p=*/0,
- /*inverted_p=*/1,
- get_attr_length (insn));
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-;; MIPS16 branches
-
-(define_insn ""
- [(set (pc)
- (if_then_else (match_operator:SI 0 "equality_op"
- [(match_operand:SI 1 "register_operand" "d,t")
- (const_int 0)])
- (match_operand 2 "pc_or_label_operand" "")
- (match_operand 3 "pc_or_label_operand" "")))]
- "TARGET_MIPS16"
- "*
-{
- if (operands[2] != pc_rtx)
- {
- if (which_alternative == 0)
- return \"%*b%C0z\\t%1,%2\";
- else
- return \"%*bt%C0z\\t%2\";
- }
- else
- {
- if (which_alternative == 0)
- return \"%*b%N0z\\t%1,%3\";
- else
- return \"%*bt%N0z\\t%3\";
- }
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")
- (set_attr "length" "8")])
-
-(define_insn ""
- [(set (pc)
- (if_then_else (match_operator:DI 0 "equality_op"
- [(match_operand:DI 1 "se_register_operand" "d,t")
- (const_int 0)])
- (match_operand 2 "pc_or_label_operand" "")
- (match_operand 3 "pc_or_label_operand" "")))]
- "TARGET_MIPS16"
- "*
-{
- if (operands[2] != pc_rtx)
- {
- if (which_alternative == 0)
- return \"%*b%C0z\\t%1,%2\";
- else
- return \"%*bt%C0z\\t%2\";
- }
- else
- {
- if (which_alternative == 0)
- return \"%*b%N0z\\t%1,%3\";
- else
- return \"%*bt%N0z\\t%3\";
- }
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")
- (set_attr "length" "8")])
-
-(define_expand "beq"
- [(set (pc)
- (if_then_else (eq:CC (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code warning */
- {
- gen_conditional_branch (operands, EQ);
- DONE;
- }
-}")
-
-(define_expand "bne"
- [(set (pc)
- (if_then_else (ne:CC (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code warning */
- {
- gen_conditional_branch (operands, NE);
- DONE;
- }
-}")
-
-(define_expand "bgt"
- [(set (pc)
- (if_then_else (gt:CC (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code warning */
- {
- gen_conditional_branch (operands, GT);
- DONE;
- }
-}")
-
-(define_expand "bge"
- [(set (pc)
- (if_then_else (ge:CC (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code warning */
- {
- gen_conditional_branch (operands, GE);
- DONE;
- }
-}")
-
-(define_expand "blt"
- [(set (pc)
- (if_then_else (lt:CC (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code warning */
- {
- gen_conditional_branch (operands, LT);
- DONE;
- }
-}")
-
-(define_expand "ble"
- [(set (pc)
- (if_then_else (le:CC (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code warning */
- {
- gen_conditional_branch (operands, LE);
- DONE;
- }
-}")
-
-(define_expand "bgtu"
- [(set (pc)
- (if_then_else (gtu:CC (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code warning */
- {
- gen_conditional_branch (operands, GTU);
- DONE;
- }
-}")
-
-(define_expand "bgeu"
- [(set (pc)
- (if_then_else (geu:CC (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code warning */
- {
- gen_conditional_branch (operands, GEU);
- DONE;
- }
-}")
-
-
-(define_expand "bltu"
- [(set (pc)
- (if_then_else (ltu:CC (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code warning */
- {
- gen_conditional_branch (operands, LTU);
- DONE;
- }
-}")
-
-(define_expand "bleu"
- [(set (pc)
- (if_then_else (leu:CC (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code warning */
- {
- gen_conditional_branch (operands, LEU);
- DONE;
- }
-}")
-
-\f
-;;
-;; ....................
-;;
-;; SETTING A REGISTER FROM A COMPARISON
-;;
-;; ....................
-
-(define_expand "seq"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (eq:SI (match_dup 1)
- (match_dup 2)))]
- ""
- "
-{
- if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
- FAIL;
-
- /* set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
-
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
- {
- gen_int_relational (EQ, operands[0], operands[1], operands[2], (int *)0);
- DONE;
- }
-
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
- operands[2] = force_reg (SImode, operands[2]);
-
- /* fall through and generate default code */
-}")
-
-
-(define_insn "seq_si_zero"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (eq:SI (match_operand:SI 1 "register_operand" "d")
- (const_int 0)))]
- "!TARGET_MIPS16"
- "sltu\\t%0,%1,1"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=t")
- (eq:SI (match_operand:SI 1 "register_operand" "d")
- (const_int 0)))]
- "TARGET_MIPS16"
- "sltu\\t%1,1"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-(define_insn "seq_di_zero"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (eq:DI (match_operand:DI 1 "se_register_operand" "d")
- (const_int 0)))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "sltu\\t%0,%1,1"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=t")
- (eq:DI (match_operand:DI 1 "se_register_operand" "d")
- (const_int 0)))]
- "TARGET_64BIT && TARGET_MIPS16"
- "sltu\\t%1,1"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
-
-(define_insn "seq_si"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (eq:SI (match_operand:SI 1 "register_operand" "%d,d")
- (match_operand:SI 2 "uns_arith_operand" "d,K")))]
- "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "@
- xor\\t%0,%1,%2\;sltu\\t%0,%0,1
- xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "8")])
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (eq:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "uns_arith_operand" "")))]
- "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
- && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
- [(set (match_dup 0)
- (xor:SI (match_dup 1)
- (match_dup 2)))
- (set (match_dup 0)
- (ltu:SI (match_dup 0)
- (const_int 1)))]
- "")
-
-(define_insn "seq_di"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (eq:DI (match_operand:DI 1 "se_register_operand" "%d,d")
- (match_operand:DI 2 "se_uns_arith_operand" "d,K")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "@
- xor\\t%0,%1,%2\;sltu\\t%0,%0,1
- xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (eq:DI (match_operand:DI 1 "se_register_operand" "")
- (match_operand:DI 2 "se_uns_arith_operand" "")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
- && !TARGET_MIPS16
- && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
- [(set (match_dup 0)
- (xor:DI (match_dup 1)
- (match_dup 2)))
- (set (match_dup 0)
- (ltu:DI (match_dup 0)
- (const_int 1)))]
- "")
-
-;; On the mips16 the default code is better than using sltu.
-
-(define_expand "sne"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ne:SI (match_dup 1)
- (match_dup 2)))]
- "!TARGET_MIPS16"
- "
-{
- if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
- FAIL;
-
- /* set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
-
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
- {
- gen_int_relational (NE, operands[0], operands[1], operands[2], (int *)0);
- DONE;
- }
-
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
- operands[2] = force_reg (SImode, operands[2]);
-
- /* fall through and generate default code */
-}")