+Instruction set avr3 is for the classic \s-1AVR\s0 core with up to 128K program
+memory space (\s-1MCU\s0 types: atmega103, atmega603, at43usb320, at76c711).
+.Sp
+Instruction set avr4 is for the enhanced \s-1AVR\s0 core with up to 8K program
+memory space (\s-1MCU\s0 types: atmega8, atmega83, atmega85).
+.Sp
+Instruction set avr5 is for the enhanced \s-1AVR\s0 core with up to 128K program
+memory space (\s-1MCU\s0 types: atmega16, atmega161, atmega163, atmega32, atmega323,
+atmega64, atmega128, at43usb355, at94k).
+.IP "\fB\-msize\fR" 4
+.IX Item "-msize"
+Output instruction sizes to the asm file.
+.IP "\fB\-mno\-interrupts\fR" 4
+.IX Item "-mno-interrupts"
+Generated code is not compatible with hardware interrupts.
+Code size will be smaller.
+.IP "\fB\-mcall\-prologues\fR" 4
+.IX Item "-mcall-prologues"
+Functions prologues/epilogues expanded as call to appropriate
+subroutines. Code size will be smaller.
+.IP "\fB\-mno\-tablejump\fR" 4
+.IX Item "-mno-tablejump"
+Do not generate tablejump insns which sometimes increase code size.
+The option is now deprecated in favor of the equivalent
+\&\fB\-fno\-jump\-tables\fR
+.IP "\fB\-mtiny\-stack\fR" 4
+.IX Item "-mtiny-stack"
+Change only the low 8 bits of the stack pointer.
+.IP "\fB\-mint8\fR" 4
+.IX Item "-mint8"
+Assume int to be 8 bit integer. This affects the sizes of all types: A
+char will be 1 byte, an int will be 1 byte, an long will be 2 bytes
+and long long will be 4 bytes. Please note that this option does not
+comply to the C standards, but it will provide you with smaller code
+size.
+.PP
+\fIBlackfin Options\fR
+.IX Subsection "Blackfin Options"
+.IP "\fB\-mcpu=\fR\fIcpu\fR[\fB\-\fR\fIsirevision\fR]" 4
+.IX Item "-mcpu=cpu[-sirevision]"
+Specifies the name of the target Blackfin processor. Currently, \fIcpu\fR
+can be one of \fBbf512\fR, \fBbf514\fR, \fBbf516\fR, \fBbf518\fR,
+\&\fBbf522\fR, \fBbf523\fR, \fBbf524\fR, \fBbf525\fR, \fBbf526\fR,
+\&\fBbf527\fR, \fBbf531\fR, \fBbf532\fR, \fBbf533\fR,
+\&\fBbf534\fR, \fBbf536\fR, \fBbf537\fR, \fBbf538\fR, \fBbf539\fR,
+\&\fBbf542\fR, \fBbf544\fR, \fBbf547\fR, \fBbf548\fR, \fBbf549\fR,
+\&\fBbf561\fR.
+The optional \fIsirevision\fR specifies the silicon revision of the target
+Blackfin processor. Any workarounds available for the targeted silicon revision
+will be enabled. If \fIsirevision\fR is \fBnone\fR, no workarounds are enabled.
+If \fIsirevision\fR is \fBany\fR, all workarounds for the targeted processor
+will be enabled. The \f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR macro is defined to two
+hexadecimal digits representing the major and minor numbers in the silicon
+revision. If \fIsirevision\fR is \fBnone\fR, the \f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR
+is not defined. If \fIsirevision\fR is \fBany\fR, the
+\&\f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR is defined to be \f(CW0xffff\fR.
+If this optional \fIsirevision\fR is not used, \s-1GCC\s0 assumes the latest known
+silicon revision of the targeted Blackfin processor.
+.Sp
+Support for \fBbf561\fR is incomplete. For \fBbf561\fR,
+Only the processor macro is defined.
+Without this option, \fBbf532\fR is used as the processor by default.
+The corresponding predefined processor macros for \fIcpu\fR is to
+be defined. And for \fBbfin-elf\fR toolchain, this causes the hardware \s-1BSP\s0
+provided by libgloss to be linked in if \fB\-msim\fR is not given.
+.IP "\fB\-msim\fR" 4
+.IX Item "-msim"
+Specifies that the program will be run on the simulator. This causes
+the simulator \s-1BSP\s0 provided by libgloss to be linked in. This option
+has effect only for \fBbfin-elf\fR toolchain.
+Certain other options, such as \fB\-mid\-shared\-library\fR and
+\&\fB\-mfdpic\fR, imply \fB\-msim\fR.
+.IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4
+.IX Item "-momit-leaf-frame-pointer"
+Don't keep the frame pointer in a register for leaf functions. This
+avoids the instructions to save, set up and restore frame pointers and
+makes an extra register available in leaf functions. The option
+\&\fB\-fomit\-frame\-pointer\fR removes the frame pointer for all functions
+which might make debugging harder.
+.IP "\fB\-mspecld\-anomaly\fR" 4
+.IX Item "-mspecld-anomaly"
+When enabled, the compiler will ensure that the generated code does not
+contain speculative loads after jump instructions. If this option is used,
+\&\f(CW\*(C`_\|_WORKAROUND_SPECULATIVE_LOADS\*(C'\fR is defined.
+.IP "\fB\-mno\-specld\-anomaly\fR" 4
+.IX Item "-mno-specld-anomaly"
+Don't generate extra code to prevent speculative loads from occurring.
+.IP "\fB\-mcsync\-anomaly\fR" 4
+.IX Item "-mcsync-anomaly"
+When enabled, the compiler will ensure that the generated code does not
+contain \s-1CSYNC\s0 or \s-1SSYNC\s0 instructions too soon after conditional branches.
+If this option is used, \f(CW\*(C`_\|_WORKAROUND_SPECULATIVE_SYNCS\*(C'\fR is defined.
+.IP "\fB\-mno\-csync\-anomaly\fR" 4
+.IX Item "-mno-csync-anomaly"
+Don't generate extra code to prevent \s-1CSYNC\s0 or \s-1SSYNC\s0 instructions from
+occurring too soon after a conditional branch.
+.IP "\fB\-mlow\-64k\fR" 4
+.IX Item "-mlow-64k"
+When enabled, the compiler is free to take advantage of the knowledge that
+the entire program fits into the low 64k of memory.
+.IP "\fB\-mno\-low\-64k\fR" 4
+.IX Item "-mno-low-64k"
+Assume that the program is arbitrarily large. This is the default.
+.IP "\fB\-mstack\-check\-l1\fR" 4
+.IX Item "-mstack-check-l1"
+Do stack checking using information placed into L1 scratchpad memory by the
+uClinux kernel.
+.IP "\fB\-mid\-shared\-library\fR" 4
+.IX Item "-mid-shared-library"
+Generate code that supports shared libraries via the library \s-1ID\s0 method.
+This allows for execute in place and shared libraries in an environment
+without virtual memory management. This option implies \fB\-fPIC\fR.
+With a \fBbfin-elf\fR target, this option implies \fB\-msim\fR.
+.IP "\fB\-mno\-id\-shared\-library\fR" 4
+.IX Item "-mno-id-shared-library"
+Generate code that doesn't assume \s-1ID\s0 based shared libraries are being used.
+This is the default.
+.IP "\fB\-mleaf\-id\-shared\-library\fR" 4
+.IX Item "-mleaf-id-shared-library"
+Generate code that supports shared libraries via the library \s-1ID\s0 method,
+but assumes that this library or executable won't link against any other
+\&\s-1ID\s0 shared libraries. That allows the compiler to use faster code for jumps
+and calls.
+.IP "\fB\-mno\-leaf\-id\-shared\-library\fR" 4
+.IX Item "-mno-leaf-id-shared-library"
+Do not assume that the code being compiled won't link against any \s-1ID\s0 shared
+libraries. Slower code will be generated for jump and call insns.
+.IP "\fB\-mshared\-library\-id=n\fR" 4
+.IX Item "-mshared-library-id=n"
+Specified the identification number of the \s-1ID\s0 based shared library being
+compiled. Specifying a value of 0 will generate more compact code, specifying
+other values will force the allocation of that number to the current
+library but is no more space or time efficient than omitting this option.
+.IP "\fB\-msep\-data\fR" 4
+.IX Item "-msep-data"
+Generate code that allows the data segment to be located in a different
+area of memory from the text segment. This allows for execute in place in
+an environment without virtual memory management by eliminating relocations
+against the text section.
+.IP "\fB\-mno\-sep\-data\fR" 4
+.IX Item "-mno-sep-data"
+Generate code that assumes that the data segment follows the text segment.
+This is the default.
+.IP "\fB\-mlong\-calls\fR" 4
+.IX Item "-mlong-calls"
+.PD 0
+.IP "\fB\-mno\-long\-calls\fR" 4
+.IX Item "-mno-long-calls"
+.PD
+Tells the compiler to perform function calls by first loading the
+address of the function into a register and then performing a subroutine
+call on this register. This switch is needed if the target function
+will lie outside of the 24 bit addressing range of the offset based
+version of subroutine call instruction.
+.Sp
+This feature is not enabled by default. Specifying
+\&\fB\-mno\-long\-calls\fR will restore the default behavior. Note these
+switches have no effect on how the compiler generates code to handle
+function calls via function pointers.
+.IP "\fB\-mfast\-fp\fR" 4
+.IX Item "-mfast-fp"
+Link with the fast floating-point library. This library relaxes some of
+the \s-1IEEE\s0 floating-point standard's rules for checking inputs against
+Not-a-Number (\s-1NAN\s0), in the interest of performance.
+.IP "\fB\-minline\-plt\fR" 4
+.IX Item "-minline-plt"
+Enable inlining of \s-1PLT\s0 entries in function calls to functions that are
+not known to bind locally. It has no effect without \fB\-mfdpic\fR.
+.IP "\fB\-mmulticore\fR" 4
+.IX Item "-mmulticore"
+Build standalone application for multicore Blackfin processor. Proper
+start files and link scripts will be used to support multicore.
+This option defines \f(CW\*(C`_\|_BFIN_MULTICORE\*(C'\fR. It can only be used with
+\&\fB\-mcpu=bf561\fR[\fB\-\fR\fIsirevision\fR]. It can be used with
+\&\fB\-mcorea\fR or \fB\-mcoreb\fR. If it's used without
+\&\fB\-mcorea\fR or \fB\-mcoreb\fR, single application/dual core
+programming model is used. In this model, the main function of Core B
+should be named as coreb_main. If it's used with \fB\-mcorea\fR or
+\&\fB\-mcoreb\fR, one application per core programming model is used.
+If this option is not used, single core application programming
+model is used.
+.IP "\fB\-mcorea\fR" 4
+.IX Item "-mcorea"
+Build standalone application for Core A of \s-1BF561\s0 when using
+one application per core programming model. Proper start files
+and link scripts will be used to support Core A. This option
+defines \f(CW\*(C`_\|_BFIN_COREA\*(C'\fR. It must be used with \fB\-mmulticore\fR.
+.IP "\fB\-mcoreb\fR" 4
+.IX Item "-mcoreb"
+Build standalone application for Core B of \s-1BF561\s0 when using
+one application per core programming model. Proper start files
+and link scripts will be used to support Core B. This option
+defines \f(CW\*(C`_\|_BFIN_COREB\*(C'\fR. When this option is used, coreb_main
+should be used instead of main. It must be used with
+\&\fB\-mmulticore\fR.
+.IP "\fB\-msdram\fR" 4
+.IX Item "-msdram"
+Build standalone application for \s-1SDRAM\s0. Proper start files and
+link scripts will be used to put the application into \s-1SDRAM\s0.
+Loader should initialize \s-1SDRAM\s0 before loading the application
+into \s-1SDRAM\s0. This option defines \f(CW\*(C`_\|_BFIN_SDRAM\*(C'\fR.
+.IP "\fB\-micplb\fR" 4
+.IX Item "-micplb"
+Assume that ICPLBs are enabled at runtime. This has an effect on certain
+anomaly workarounds. For Linux targets, the default is to assume ICPLBs
+are enabled; for standalone applications the default is off.
+.PP
+\fI\s-1CRIS\s0 Options\fR
+.IX Subsection "CRIS Options"
+.PP
+These options are defined specifically for the \s-1CRIS\s0 ports.
+.IP "\fB\-march=\fR\fIarchitecture-type\fR" 4
+.IX Item "-march=architecture-type"
+.PD 0
+.IP "\fB\-mcpu=\fR\fIarchitecture-type\fR" 4
+.IX Item "-mcpu=architecture-type"
+.PD
+Generate code for the specified architecture. The choices for
+\&\fIarchitecture-type\fR are \fBv3\fR, \fBv8\fR and \fBv10\fR for
+respectively \s-1ETRAX\s0\ 4, \s-1ETRAX\s0\ 100, and \s-1ETRAX\s0\ 100\ \s-1LX\s0.
+Default is \fBv0\fR except for cris-axis-linux-gnu, where the default is
+\&\fBv10\fR.
+.IP "\fB\-mtune=\fR\fIarchitecture-type\fR" 4
+.IX Item "-mtune=architecture-type"
+Tune to \fIarchitecture-type\fR everything applicable about the generated
+code, except for the \s-1ABI\s0 and the set of available instructions. The
+choices for \fIarchitecture-type\fR are the same as for
+\&\fB\-march=\fR\fIarchitecture-type\fR.
+.IP "\fB\-mmax\-stack\-frame=\fR\fIn\fR" 4
+.IX Item "-mmax-stack-frame=n"
+Warn when the stack frame of a function exceeds \fIn\fR bytes.
+.IP "\fB\-metrax4\fR" 4
+.IX Item "-metrax4"
+.PD 0
+.IP "\fB\-metrax100\fR" 4
+.IX Item "-metrax100"
+.PD
+The options \fB\-metrax4\fR and \fB\-metrax100\fR are synonyms for
+\&\fB\-march=v3\fR and \fB\-march=v8\fR respectively.
+.IP "\fB\-mmul\-bug\-workaround\fR" 4
+.IX Item "-mmul-bug-workaround"
+.PD 0
+.IP "\fB\-mno\-mul\-bug\-workaround\fR" 4
+.IX Item "-mno-mul-bug-workaround"
+.PD
+Work around a bug in the \f(CW\*(C`muls\*(C'\fR and \f(CW\*(C`mulu\*(C'\fR instructions for \s-1CPU\s0
+models where it applies. This option is active by default.
+.IP "\fB\-mpdebug\fR" 4
+.IX Item "-mpdebug"
+Enable CRIS-specific verbose debug-related information in the assembly
+code. This option also has the effect to turn off the \fB#NO_APP\fR
+formatted-code indicator to the assembler at the beginning of the
+assembly file.
+.IP "\fB\-mcc\-init\fR" 4
+.IX Item "-mcc-init"
+Do not use condition-code results from previous instruction; always emit
+compare and test instructions before use of condition codes.
+.IP "\fB\-mno\-side\-effects\fR" 4
+.IX Item "-mno-side-effects"
+Do not emit instructions with side-effects in addressing modes other than
+post-increment.
+.IP "\fB\-mstack\-align\fR" 4
+.IX Item "-mstack-align"
+.PD 0
+.IP "\fB\-mno\-stack\-align\fR" 4
+.IX Item "-mno-stack-align"
+.IP "\fB\-mdata\-align\fR" 4
+.IX Item "-mdata-align"
+.IP "\fB\-mno\-data\-align\fR" 4
+.IX Item "-mno-data-align"
+.IP "\fB\-mconst\-align\fR" 4
+.IX Item "-mconst-align"
+.IP "\fB\-mno\-const\-align\fR" 4
+.IX Item "-mno-const-align"
+.PD
+These options (no-options) arranges (eliminate arrangements) for the
+stack-frame, individual data and constants to be aligned for the maximum
+single data access size for the chosen \s-1CPU\s0 model. The default is to
+arrange for 32\-bit alignment. \s-1ABI\s0 details such as structure layout are
+not affected by these options.
+.IP "\fB\-m32\-bit\fR" 4
+.IX Item "-m32-bit"
+.PD 0
+.IP "\fB\-m16\-bit\fR" 4
+.IX Item "-m16-bit"
+.IP "\fB\-m8\-bit\fR" 4
+.IX Item "-m8-bit"
+.PD
+Similar to the stack\- data\- and const-align options above, these options
+arrange for stack-frame, writable data and constants to all be 32\-bit,
+16\-bit or 8\-bit aligned. The default is 32\-bit alignment.
+.IP "\fB\-mno\-prologue\-epilogue\fR" 4
+.IX Item "-mno-prologue-epilogue"
+.PD 0
+.IP "\fB\-mprologue\-epilogue\fR" 4
+.IX Item "-mprologue-epilogue"
+.PD
+With \fB\-mno\-prologue\-epilogue\fR, the normal function prologue and
+epilogue that sets up the stack-frame are omitted and no return
+instructions or return sequences are generated in the code. Use this
+option only together with visual inspection of the compiled code: no
+warnings or errors are generated when call-saved registers must be saved,
+or storage for local variable needs to be allocated.
+.IP "\fB\-mno\-gotplt\fR" 4
+.IX Item "-mno-gotplt"
+.PD 0
+.IP "\fB\-mgotplt\fR" 4
+.IX Item "-mgotplt"
+.PD
+With \fB\-fpic\fR and \fB\-fPIC\fR, don't generate (do generate)
+instruction sequences that load addresses for functions from the \s-1PLT\s0 part
+of the \s-1GOT\s0 rather than (traditional on other architectures) calls to the
+\&\s-1PLT\s0. The default is \fB\-mgotplt\fR.
+.IP "\fB\-melf\fR" 4
+.IX Item "-melf"
+Legacy no-op option only recognized with the cris-axis-elf and
+cris-axis-linux-gnu targets.
+.IP "\fB\-mlinux\fR" 4
+.IX Item "-mlinux"
+Legacy no-op option only recognized with the cris-axis-linux-gnu target.
+.IP "\fB\-sim\fR" 4
+.IX Item "-sim"
+This option, recognized for the cris-axis-elf arranges
+to link with input-output functions from a simulator library. Code,
+initialized data and zero-initialized data are allocated consecutively.
+.IP "\fB\-sim2\fR" 4
+.IX Item "-sim2"
+Like \fB\-sim\fR, but pass linker options to locate initialized data at
+0x40000000 and zero-initialized data at 0x80000000.
+.PP
+\fI\s-1CRX\s0 Options\fR
+.IX Subsection "CRX Options"
+.PP
+These options are defined specifically for the \s-1CRX\s0 ports.
+.IP "\fB\-mmac\fR" 4
+.IX Item "-mmac"
+Enable the use of multiply-accumulate instructions. Disabled by default.
+.IP "\fB\-mpush\-args\fR" 4
+.IX Item "-mpush-args"
+Push instructions will be used to pass outgoing arguments when functions
+are called. Enabled by default.
+.PP
+\fIDarwin Options\fR
+.IX Subsection "Darwin Options"
+.PP
+These options are defined for all architectures running the Darwin operating
+system.
+.PP
+\&\s-1FSF\s0 \s-1GCC\s0 on Darwin does not create \*(L"fat\*(R" object files; it will create
+an object file for the single architecture that it was built to
+target. Apple's \s-1GCC\s0 on Darwin does create \*(L"fat\*(R" files if multiple
+\&\fB\-arch\fR options are used; it does so by running the compiler or
+linker multiple times and joining the results together with
+\&\fIlipo\fR.
+.PP
+The subtype of the file created (like \fBppc7400\fR or \fBppc970\fR or
+\&\fBi686\fR) is determined by the flags that specify the \s-1ISA\s0
+that \s-1GCC\s0 is targetting, like \fB\-mcpu\fR or \fB\-march\fR. The
+\&\fB\-force_cpusubtype_ALL\fR option can be used to override this.
+.PP
+The Darwin tools vary in their behavior when presented with an \s-1ISA\s0
+mismatch. The assembler, \fIas\fR, will only permit instructions to
+be used that are valid for the subtype of the file it is generating,
+so you cannot put 64\-bit instructions in an \fBppc750\fR object file.
+The linker for shared libraries, \fI/usr/bin/libtool\fR, will fail
+and print an error if asked to create a shared library with a less
+restrictive subtype than its input files (for instance, trying to put
+a \fBppc970\fR object file in a \fBppc7400\fR library). The linker
+for executables, \fIld\fR, will quietly give the executable the most
+restrictive subtype of any of its input files.
+.IP "\fB\-F\fR\fIdir\fR" 4
+.IX Item "-Fdir"
+Add the framework directory \fIdir\fR to the head of the list of
+directories to be searched for header files. These directories are
+interleaved with those specified by \fB\-I\fR options and are
+scanned in a left-to-right order.
+.Sp
+A framework directory is a directory with frameworks in it. A
+framework is a directory with a \fB\*(L"Headers\*(R"\fR and/or
+\&\fB\*(L"PrivateHeaders\*(R"\fR directory contained directly in it that ends
+in \fB\*(L".framework\*(R"\fR. The name of a framework is the name of this
+directory excluding the \fB\*(L".framework\*(R"\fR. Headers associated with
+the framework are found in one of those two directories, with
+\&\fB\*(L"Headers\*(R"\fR being searched first. A subframework is a framework
+directory that is in a framework's \fB\*(L"Frameworks\*(R"\fR directory.
+Includes of subframework headers can only appear in a header of a
+framework that contains the subframework, or in a sibling subframework
+header. Two subframeworks are siblings if they occur in the same
+framework. A subframework should not have the same name as a
+framework, a warning will be issued if this is violated. Currently a
+subframework cannot have subframeworks, in the future, the mechanism
+may be extended to support this. The standard frameworks can be found
+in \fB\*(L"/System/Library/Frameworks\*(R"\fR and
+\&\fB\*(L"/Library/Frameworks\*(R"\fR. An example include looks like
+\&\f(CW\*(C`#include <Framework/header.h>\*(C'\fR, where \fBFramework\fR denotes
+the name of the framework and header.h is found in the
+\&\fB\*(L"PrivateHeaders\*(R"\fR or \fB\*(L"Headers\*(R"\fR directory.
+.IP "\fB\-iframework\fR\fIdir\fR" 4
+.IX Item "-iframeworkdir"
+Like \fB\-F\fR except the directory is a treated as a system
+directory. The main difference between this \fB\-iframework\fR and
+\&\fB\-F\fR is that with \fB\-iframework\fR the compiler does not
+warn about constructs contained within header files found via
+\&\fIdir\fR. This option is valid only for the C family of languages.
+.IP "\fB\-gused\fR" 4
+.IX Item "-gused"
+Emit debugging information for symbols that are used. For \s-1STABS\s0
+debugging format, this enables \fB\-feliminate\-unused\-debug\-symbols\fR.
+This is by default \s-1ON\s0.
+.IP "\fB\-gfull\fR" 4
+.IX Item "-gfull"
+Emit debugging information for all symbols and types.
+.IP "\fB\-mmacosx\-version\-min=\fR\fIversion\fR" 4
+.IX Item "-mmacosx-version-min=version"
+The earliest version of MacOS X that this executable will run on
+is \fIversion\fR. Typical values of \fIversion\fR include \f(CW10.1\fR,
+\&\f(CW10.2\fR, and \f(CW10.3.9\fR.
+.Sp
+If the compiler was built to use the system's headers by default,
+then the default for this option is the system version on which the
+compiler is running, otherwise the default is to make choices which
+are compatible with as many systems and code bases as possible.
+.IP "\fB\-mkernel\fR" 4
+.IX Item "-mkernel"
+Enable kernel development mode. The \fB\-mkernel\fR option sets
+\&\fB\-static\fR, \fB\-fno\-common\fR, \fB\-fno\-cxa\-atexit\fR,
+\&\fB\-fno\-exceptions\fR, \fB\-fno\-non\-call\-exceptions\fR,
+\&\fB\-fapple\-kext\fR, \fB\-fno\-weak\fR and \fB\-fno\-rtti\fR where
+applicable. This mode also sets \fB\-mno\-altivec\fR,
+\&\fB\-msoft\-float\fR, \fB\-fno\-builtin\fR and
+\&\fB\-mlong\-branch\fR for PowerPC targets.
+.IP "\fB\-mone\-byte\-bool\fR" 4
+.IX Item "-mone-byte-bool"
+Override the defaults for \fBbool\fR so that \fBsizeof(bool)==1\fR.
+By default \fBsizeof(bool)\fR is \fB4\fR when compiling for
+Darwin/PowerPC and \fB1\fR when compiling for Darwin/x86, so this
+option has no effect on x86.
+.Sp
+\&\fBWarning:\fR The \fB\-mone\-byte\-bool\fR switch causes \s-1GCC\s0
+to generate code that is not binary compatible with code generated
+without that switch. Using this switch may require recompiling all
+other modules in a program, including system libraries. Use this
+switch to conform to a non-default data model.
+.IP "\fB\-mfix\-and\-continue\fR" 4
+.IX Item "-mfix-and-continue"
+.PD 0
+.IP "\fB\-ffix\-and\-continue\fR" 4
+.IX Item "-ffix-and-continue"
+.IP "\fB\-findirect\-data\fR" 4
+.IX Item "-findirect-data"
+.PD
+Generate code suitable for fast turn around development. Needed to
+enable gdb to dynamically load \f(CW\*(C`.o\*(C'\fR files into already running
+programs. \fB\-findirect\-data\fR and \fB\-ffix\-and\-continue\fR
+are provided for backwards compatibility.
+.IP "\fB\-all_load\fR" 4
+.IX Item "-all_load"
+Loads all members of static archive libraries.
+See man \fIld\fR\|(1) for more information.
+.IP "\fB\-arch_errors_fatal\fR" 4
+.IX Item "-arch_errors_fatal"
+Cause the errors having to do with files that have the wrong architecture
+to be fatal.
+.IP "\fB\-bind_at_load\fR" 4
+.IX Item "-bind_at_load"
+Causes the output file to be marked such that the dynamic linker will
+bind all undefined references when the file is loaded or launched.
+.IP "\fB\-bundle\fR" 4
+.IX Item "-bundle"
+Produce a Mach-o bundle format file.
+See man \fIld\fR\|(1) for more information.
+.IP "\fB\-bundle_loader\fR \fIexecutable\fR" 4
+.IX Item "-bundle_loader executable"
+This option specifies the \fIexecutable\fR that will be loading the build
+output file being linked. See man \fIld\fR\|(1) for more information.
+.IP "\fB\-dynamiclib\fR" 4
+.IX Item "-dynamiclib"
+When passed this option, \s-1GCC\s0 will produce a dynamic library instead of
+an executable when linking, using the Darwin \fIlibtool\fR command.
+.IP "\fB\-force_cpusubtype_ALL\fR" 4
+.IX Item "-force_cpusubtype_ALL"
+This causes \s-1GCC\s0's output file to have the \fI\s-1ALL\s0\fR subtype, instead of
+one controlled by the \fB\-mcpu\fR or \fB\-march\fR option.
+.IP "\fB\-allowable_client\fR \fIclient_name\fR" 4
+.IX Item "-allowable_client client_name"
+.PD 0
+.IP "\fB\-client_name\fR" 4
+.IX Item "-client_name"
+.IP "\fB\-compatibility_version\fR" 4
+.IX Item "-compatibility_version"
+.IP "\fB\-current_version\fR" 4
+.IX Item "-current_version"
+.IP "\fB\-dead_strip\fR" 4
+.IX Item "-dead_strip"
+.IP "\fB\-dependency\-file\fR" 4
+.IX Item "-dependency-file"
+.IP "\fB\-dylib_file\fR" 4
+.IX Item "-dylib_file"
+.IP "\fB\-dylinker_install_name\fR" 4
+.IX Item "-dylinker_install_name"
+.IP "\fB\-dynamic\fR" 4
+.IX Item "-dynamic"
+.IP "\fB\-exported_symbols_list\fR" 4
+.IX Item "-exported_symbols_list"
+.IP "\fB\-filelist\fR" 4
+.IX Item "-filelist"
+.IP "\fB\-flat_namespace\fR" 4
+.IX Item "-flat_namespace"
+.IP "\fB\-force_flat_namespace\fR" 4
+.IX Item "-force_flat_namespace"
+.IP "\fB\-headerpad_max_install_names\fR" 4
+.IX Item "-headerpad_max_install_names"
+.IP "\fB\-image_base\fR" 4
+.IX Item "-image_base"
+.IP "\fB\-init\fR" 4
+.IX Item "-init"
+.IP "\fB\-install_name\fR" 4
+.IX Item "-install_name"
+.IP "\fB\-keep_private_externs\fR" 4
+.IX Item "-keep_private_externs"
+.IP "\fB\-multi_module\fR" 4
+.IX Item "-multi_module"
+.IP "\fB\-multiply_defined\fR" 4
+.IX Item "-multiply_defined"
+.IP "\fB\-multiply_defined_unused\fR" 4
+.IX Item "-multiply_defined_unused"
+.IP "\fB\-noall_load\fR" 4
+.IX Item "-noall_load"
+.IP "\fB\-no_dead_strip_inits_and_terms\fR" 4
+.IX Item "-no_dead_strip_inits_and_terms"
+.IP "\fB\-nofixprebinding\fR" 4
+.IX Item "-nofixprebinding"
+.IP "\fB\-nomultidefs\fR" 4
+.IX Item "-nomultidefs"
+.IP "\fB\-noprebind\fR" 4
+.IX Item "-noprebind"
+.IP "\fB\-noseglinkedit\fR" 4
+.IX Item "-noseglinkedit"
+.IP "\fB\-pagezero_size\fR" 4
+.IX Item "-pagezero_size"
+.IP "\fB\-prebind\fR" 4
+.IX Item "-prebind"
+.IP "\fB\-prebind_all_twolevel_modules\fR" 4
+.IX Item "-prebind_all_twolevel_modules"
+.IP "\fB\-private_bundle\fR" 4
+.IX Item "-private_bundle"
+.IP "\fB\-read_only_relocs\fR" 4
+.IX Item "-read_only_relocs"
+.IP "\fB\-sectalign\fR" 4
+.IX Item "-sectalign"
+.IP "\fB\-sectobjectsymbols\fR" 4
+.IX Item "-sectobjectsymbols"
+.IP "\fB\-whyload\fR" 4
+.IX Item "-whyload"
+.IP "\fB\-seg1addr\fR" 4
+.IX Item "-seg1addr"
+.IP "\fB\-sectcreate\fR" 4
+.IX Item "-sectcreate"
+.IP "\fB\-sectobjectsymbols\fR" 4
+.IX Item "-sectobjectsymbols"
+.IP "\fB\-sectorder\fR" 4
+.IX Item "-sectorder"
+.IP "\fB\-segaddr\fR" 4
+.IX Item "-segaddr"
+.IP "\fB\-segs_read_only_addr\fR" 4
+.IX Item "-segs_read_only_addr"
+.IP "\fB\-segs_read_write_addr\fR" 4
+.IX Item "-segs_read_write_addr"
+.IP "\fB\-seg_addr_table\fR" 4
+.IX Item "-seg_addr_table"
+.IP "\fB\-seg_addr_table_filename\fR" 4
+.IX Item "-seg_addr_table_filename"
+.IP "\fB\-seglinkedit\fR" 4
+.IX Item "-seglinkedit"
+.IP "\fB\-segprot\fR" 4
+.IX Item "-segprot"
+.IP "\fB\-segs_read_only_addr\fR" 4
+.IX Item "-segs_read_only_addr"
+.IP "\fB\-segs_read_write_addr\fR" 4
+.IX Item "-segs_read_write_addr"
+.IP "\fB\-single_module\fR" 4
+.IX Item "-single_module"
+.IP "\fB\-static\fR" 4
+.IX Item "-static"
+.IP "\fB\-sub_library\fR" 4
+.IX Item "-sub_library"
+.IP "\fB\-sub_umbrella\fR" 4
+.IX Item "-sub_umbrella"
+.IP "\fB\-twolevel_namespace\fR" 4
+.IX Item "-twolevel_namespace"
+.IP "\fB\-umbrella\fR" 4
+.IX Item "-umbrella"
+.IP "\fB\-undefined\fR" 4
+.IX Item "-undefined"
+.IP "\fB\-unexported_symbols_list\fR" 4
+.IX Item "-unexported_symbols_list"
+.IP "\fB\-weak_reference_mismatches\fR" 4
+.IX Item "-weak_reference_mismatches"
+.IP "\fB\-whatsloaded\fR" 4
+.IX Item "-whatsloaded"
+.PD
+These options are passed to the Darwin linker. The Darwin linker man page
+describes them in detail.
+.PP
+\fI\s-1DEC\s0 Alpha Options\fR
+.IX Subsection "DEC Alpha Options"
+.PP
+These \fB\-m\fR options are defined for the \s-1DEC\s0 Alpha implementations:
+.IP "\fB\-mno\-soft\-float\fR" 4
+.IX Item "-mno-soft-float"
+.PD 0
+.IP "\fB\-msoft\-float\fR" 4
+.IX Item "-msoft-float"
+.PD
+Use (do not use) the hardware floating-point instructions for
+floating-point operations. When \fB\-msoft\-float\fR is specified,
+functions in \fIlibgcc.a\fR will be used to perform floating-point
+operations. Unless they are replaced by routines that emulate the
+floating-point operations, or compiled in such a way as to call such
+emulations routines, these routines will issue floating-point
+operations. If you are compiling for an Alpha without floating-point
+operations, you must ensure that the library is built so as not to call
+them.
+.Sp
+Note that Alpha implementations without floating-point operations are
+required to have floating-point registers.
+.IP "\fB\-mfp\-reg\fR" 4
+.IX Item "-mfp-reg"
+.PD 0
+.IP "\fB\-mno\-fp\-regs\fR" 4
+.IX Item "-mno-fp-regs"
+.PD
+Generate code that uses (does not use) the floating-point register set.
+\&\fB\-mno\-fp\-regs\fR implies \fB\-msoft\-float\fR. If the floating-point
+register set is not used, floating point operands are passed in integer
+registers as if they were integers and floating-point results are passed
+in \f(CW$0\fR instead of \f(CW$f0\fR. This is a non-standard calling sequence,
+so any function with a floating-point argument or return value called by code
+compiled with \fB\-mno\-fp\-regs\fR must also be compiled with that
+option.
+.Sp
+A typical use of this option is building a kernel that does not use,
+and hence need not save and restore, any floating-point registers.
+.IP "\fB\-mieee\fR" 4
+.IX Item "-mieee"
+The Alpha architecture implements floating-point hardware optimized for
+maximum performance. It is mostly compliant with the \s-1IEEE\s0 floating
+point standard. However, for full compliance, software assistance is
+required. This option generates code fully \s-1IEEE\s0 compliant code
+\&\fIexcept\fR that the \fIinexact-flag\fR is not maintained (see below).
+If this option is turned on, the preprocessor macro \f(CW\*(C`_IEEE_FP\*(C'\fR is
+defined during compilation. The resulting code is less efficient but is
+able to correctly support denormalized numbers and exceptional \s-1IEEE\s0
+values such as not-a-number and plus/minus infinity. Other Alpha
+compilers call this option \fB\-ieee_with_no_inexact\fR.
+.IP "\fB\-mieee\-with\-inexact\fR" 4
+.IX Item "-mieee-with-inexact"
+This is like \fB\-mieee\fR except the generated code also maintains
+the \s-1IEEE\s0 \fIinexact-flag\fR. Turning on this option causes the
+generated code to implement fully-compliant \s-1IEEE\s0 math. In addition to
+\&\f(CW\*(C`_IEEE_FP\*(C'\fR, \f(CW\*(C`_IEEE_FP_EXACT\*(C'\fR is defined as a preprocessor
+macro. On some Alpha implementations the resulting code may execute
+significantly slower than the code generated by default. Since there is
+very little code that depends on the \fIinexact-flag\fR, you should
+normally not specify this option. Other Alpha compilers call this
+option \fB\-ieee_with_inexact\fR.
+.IP "\fB\-mfp\-trap\-mode=\fR\fItrap-mode\fR" 4
+.IX Item "-mfp-trap-mode=trap-mode"
+This option controls what floating-point related traps are enabled.
+Other Alpha compilers call this option \fB\-fptm\fR \fItrap-mode\fR.
+The trap mode can be set to one of four values:
+.RS 4
+.IP "\fBn\fR" 4
+.IX Item "n"
+This is the default (normal) setting. The only traps that are enabled
+are the ones that cannot be disabled in software (e.g., division by zero
+trap).
+.IP "\fBu\fR" 4
+.IX Item "u"
+In addition to the traps enabled by \fBn\fR, underflow traps are enabled
+as well.
+.IP "\fBsu\fR" 4
+.IX Item "su"
+Like \fBu\fR, but the instructions are marked to be safe for software
+completion (see Alpha architecture manual for details).
+.IP "\fBsui\fR" 4
+.IX Item "sui"
+Like \fBsu\fR, but inexact traps are enabled as well.
+.RE
+.RS 4
+.RE
+.IP "\fB\-mfp\-rounding\-mode=\fR\fIrounding-mode\fR" 4
+.IX Item "-mfp-rounding-mode=rounding-mode"
+Selects the \s-1IEEE\s0 rounding mode. Other Alpha compilers call this option
+\&\fB\-fprm\fR \fIrounding-mode\fR. The \fIrounding-mode\fR can be one
+of:
+.RS 4
+.IP "\fBn\fR" 4
+.IX Item "n"
+Normal \s-1IEEE\s0 rounding mode. Floating point numbers are rounded towards
+the nearest machine number or towards the even machine number in case
+of a tie.
+.IP "\fBm\fR" 4
+.IX Item "m"
+Round towards minus infinity.
+.IP "\fBc\fR" 4
+.IX Item "c"
+Chopped rounding mode. Floating point numbers are rounded towards zero.
+.IP "\fBd\fR" 4
+.IX Item "d"
+Dynamic rounding mode. A field in the floating point control register
+(\fIfpcr\fR, see Alpha architecture reference manual) controls the
+rounding mode in effect. The C library initializes this register for
+rounding towards plus infinity. Thus, unless your program modifies the
+\&\fIfpcr\fR, \fBd\fR corresponds to round towards plus infinity.
+.RE
+.RS 4
+.RE
+.IP "\fB\-mtrap\-precision=\fR\fItrap-precision\fR" 4
+.IX Item "-mtrap-precision=trap-precision"
+In the Alpha architecture, floating point traps are imprecise. This
+means without software assistance it is impossible to recover from a
+floating trap and program execution normally needs to be terminated.
+\&\s-1GCC\s0 can generate code that can assist operating system trap handlers
+in determining the exact location that caused a floating point trap.
+Depending on the requirements of an application, different levels of
+precisions can be selected:
+.RS 4
+.IP "\fBp\fR" 4
+.IX Item "p"
+Program precision. This option is the default and means a trap handler
+can only identify which program caused a floating point exception.
+.IP "\fBf\fR" 4
+.IX Item "f"
+Function precision. The trap handler can determine the function that
+caused a floating point exception.
+.IP "\fBi\fR" 4
+.IX Item "i"
+Instruction precision. The trap handler can determine the exact
+instruction that caused a floating point exception.
+.RE
+.RS 4