+/*
+ * Copyright © 2011, 2012, Titanium Mirror, Inc..
+ * All Rights Reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of Titanium Mirror, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
/*
* File: adc_random.c
*
unsigned char adc_random()
{
- static bit save_ansa2;
- static bit save_trisa2;
+ static bit save_ansa0;
+ static bit save_trisa0;
unsigned char accumulate = 0;
/* Turn on the FVR, configured for 1.024V to the ADC */
FVRCON = 0b10000001;
while (!FVRRDY); /* wait for ready signal */
- /* Configure RA2 (AN2) for ADC input */
- save_ansa2 = ANSA2;
- ANSA2 = 1;
- save_trisa2 = TRISA2;
- TRISA2 = 1;
+ /* Configure RA0 (AN0) for ADC input */
+ save_ansa0 = ANSA0;
+ ANSA0 = 1;
+ save_trisa0 = TRISA0;
+ TRISA0 = 1;
ADCON1 = 0b11110011; /* Right justified result, Frc clk, FVR/Vss refs */
- ADCON0 = 0b00001001; /* Enable channel AN2, enable ADC */
+ ADCON0 = 0b00000001; /* Enable channel AN0, enable ADC */
/* Sample the ADC several times, accumulating the LSB of the result */
for (unsigned i = 0; i < 128; i++) {
/* Turn off ADC, FVR, and revert PORTA changes */
ADON = 0;
FVREN = 0;
- TRISA2 = save_trisa2;
- ANSA2 = save_ansa2;
+ TRISA0 = save_trisa0;
+ ANSA0 = save_ansa0;
/* Return the result */
return accumulate;