-.\" Automatically generated by Pod::Man v1.37, Pod::Parser v1.32
+.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05)
.\"
.\" Standard preamble:
.\" ========================================================================
. ds R" ''
'br\}
.\"
+.\" Escape single quotes in literal strings from groff's Unicode transform.
+.ie \n(.g .ds Aq \(aq
+.el .ds Aq '
+.\"
.\" If the F register is turned on, we'll generate index entries on stderr for
.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index
.\" entries marked with X<> in POD. Of course, you'll have to process the
.\" output yourself in some meaningful fashion.
-.if \nF \{\
+.ie \nF \{\
. de IX
. tm Index:\\$1\t\\n%\t"\\$2"
..
. nr % 0
. rr F
.\}
-.\"
-.\" For nroff, turn off justification. Always turn off hyphenation; it makes
-.\" way too many mistakes in technical documents.
-.hy 0
+.el \{\
+. de IX
+..
+.\}
.\"
.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2).
.\" Fear. Run. Save yourself. No user-serviceable parts.
.\" ========================================================================
.\"
.IX Title "AS 1"
-.TH AS 1 "2007-08-28" "binutils-2.18" "GNU Development Tools"
+.TH AS 1 "2009-10-16" "binutils-2.20" "GNU Development Tools"
+.\" For nroff, turn off justification. Always turn off hyphenation; it makes
+.\" way too many mistakes in technical documents.
+.if n .ad l
+.nh
.SH "NAME"
AS \- the portable GNU assembler.
.SH "SYNOPSIS"
.IX Header "SYNOPSIS"
-as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-\-alternate\fR] [\fB\-D\fR]
+as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-\-alternate\fR] [\fB\-D\fR]
[\fB\-\-debug\-prefix\-map\fR \fIold\fR=\fInew\fR]
[\fB\-\-defsym\fR \fIsym\fR=\fIval\fR] [\fB\-f\fR] [\fB\-g\fR] [\fB\-\-gstabs\fR]
[\fB\-\-gstabs+\fR] [\fB\-\-gdwarf\-2\fR] [\fB\-\-help\fR] [\fB\-I\fR \fIdir\fR] [\fB\-J\fR]
\&\fITarget Alpha options:\fR
[\fB\-m\fR\fIcpu\fR]
[\fB\-mdebug\fR | \fB\-no\-mdebug\fR]
+ [\fB\-replace\fR | \fB\-noreplace\fR]
[\fB\-relax\fR] [\fB\-g\fR] [\fB\-G\fR\fIsize\fR]
[\fB\-F\fR] [\fB\-32addr\fR]
.PP
\&\fITarget D30V options:\fR
[\fB\-O\fR|\fB\-n\fR|\fB\-N\fR]
.PP
+\&\fITarget H8/300 options:\fR
+ [\-h\-tick\-hex]
+.PP
\&\fITarget i386 options:\fR
[\fB\-\-32\fR|\fB\-\-64\fR] [\fB\-n\fR]
- [\fB\-march\fR=\fI\s-1CPU\s0\fR] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR]
+ [\fB\-march\fR=\fI\s-1CPU\s0\fR[+\fI\s-1EXTENSION\s0\fR...]] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR]
.PP
\&\fITarget i960 options:\fR
[\fB\-ACA\fR|\fB\-ACA_A\fR|\fB\-ACB\fR|\fB\-ACC\fR|\fB\-AKA\fR|\fB\-AKB\fR|
[\fB\-mip2022\fR|\fB\-mip2022ext\fR]
.PP
\&\fITarget M32C options:\fR
- [\fB\-m32c\fR|\fB\-m16c\fR]
+ [\fB\-m32c\fR|\fB\-m16c\fR] [\-relax] [\-h\-tick\-hex]
.PP
\&\fITarget M32R options:\fR
[\fB\-\-m32rx\fR|\fB\-\-[no\-]warn\-explicit\-parallel\-conflicts\fR|
\&\fITarget \s-1MCORE\s0 options:\fR
[\fB\-jsri2bsr\fR] [\fB\-sifilter\fR] [\fB\-relax\fR]
[\fB\-mcpu=[210|340]\fR]
+\&\fITarget \s-1MICROBLAZE\s0 options:\fR
.PP
\&\fITarget \s-1MIPS\s0 options:\fR
[\fB\-nocpp\fR] [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR[\fIoptimization level\fR]]
\&\fITarget \s-1PDP11\s0 options:\fR
[\fB\-mpic\fR|\fB\-mno\-pic\fR] [\fB\-mall\fR] [\fB\-mno\-extensions\fR]
[\fB\-m\fR\fIextension\fR|\fB\-mno\-\fR\fIextension\fR]
- [\fB\-m\fR\fIcpu\fR] [\fB\-m\fR\fImachine\fR]
+ [\fB\-m\fR\fIcpu\fR] [\fB\-m\fR\fImachine\fR]
.PP
\&\fITarget picoJava options:\fR
[\fB\-mb\fR|\fB\-me\fR]
.PP
\&\fITarget PowerPC options:\fR
[\fB\-mpwrx\fR|\fB\-mpwr2\fR|\fB\-mpwr\fR|\fB\-m601\fR|\fB\-mppc\fR|\fB\-mppc32\fR|\fB\-m603\fR|\fB\-m604\fR|
- \fB\-m403\fR|\fB\-m405\fR|\fB\-mppc64\fR|\fB\-m620\fR|\fB\-mppc64bridge\fR|\fB\-mbooke\fR|
- \fB\-mbooke32\fR|\fB\-mbooke64\fR]
- [\fB\-mcom\fR|\fB\-many\fR|\fB\-maltivec\fR] [\fB\-memb\fR]
+ \fB\-m403\fR|\fB\-m405\fR|\fB\-mppc64\fR|\fB\-m620\fR|\fB\-mppc64bridge\fR|\fB\-mbooke\fR]
+ [\fB\-mcom\fR|\fB\-many\fR|\fB\-maltivec\fR|\fB\-mvsx\fR] [\fB\-memb\fR]
[\fB\-mregnames\fR|\fB\-mno\-regnames\fR]
[\fB\-mrelocatable\fR|\fB\-mrelocatable\-lib\fR]
[\fB\-mlittle\fR|\fB\-mlittle\-endian\fR|\fB\-mbig\fR|\fB\-mbig\-endian\fR]
[\fB\-msolaris\fR|\fB\-mno\-solaris\fR]
.PP
+\&\fITarget s390 options:\fR
+ [\fB\-m31\fR|\fB\-m64\fR] [\fB\-mesa\fR|\fB\-mzarch\fR] [\fB\-march\fR=\fI\s-1CPU\s0\fR]
+ [\fB\-mregnames\fR|\fB\-mno\-regnames\fR]
+ [\fB\-mwarn\-areg\-zero\fR]
+.PP
+\&\fITarget \s-1SCORE\s0 options:\fR
+ [\fB\-EB\fR][\fB\-EL\fR][\fB\-FIXDD\fR][\fB\-NWARN\fR]
+ [\fB\-SCORE5\fR][\fB\-SCORE5U\fR][\fB\-SCORE7\fR][\fB\-SCORE3\fR]
+ [\fB\-march=score7\fR][\fB\-march=score3\fR]
+ [\fB\-USE_R1\fR][\fB\-KPIC\fR][\fB\-O0\fR][\fB\-G\fR \fInum\fR][\fB\-V\fR]
+.PP
\&\fITarget \s-1SPARC\s0 options:\fR
[\fB\-Av6\fR|\fB\-Av7\fR|\fB\-Av8\fR|\fB\-Asparclet\fR|\fB\-Asparclite\fR
\fB\-Av8plus\fR|\fB\-Av8plusa\fR|\fB\-Av9\fR|\fB\-Av9a\fR]
Read command-line options from \fIfile\fR. The options read are
inserted in place of the original @\fIfile\fR option. If \fIfile\fR
does not exist, or cannot be read, then the option will be treated
-literally, and not removed.
+literally, and not removed.
.Sp
Options in \fIfile\fR are separated by whitespace. A whitespace
character may be included in an option by surrounding the entire
backslash) may be included by prefixing the character to be included
with a backslash. The \fIfile\fR may itself contain additional
@\fIfile\fR options; any such options will be processed recursively.
-.IP "\fB\-a[cdhlmns]\fR" 4
-.IX Item "-a[cdhlmns]"
+.IP "\fB\-a[cdghlmns]\fR" 4
+.IX Item "-a[cdghlmns]"
Turn on listings, in any of a variety of ways:
.RS 4
.IP "\fB\-ac\fR" 4
.IP "\fB\-ad\fR" 4
.IX Item "-ad"
omit debugging directives
+.IP "\fB\-ag\fR" 4
+.IX Item "-ag"
+include general information, like as version and options passed
.IP "\fB\-ah\fR" 4
.IX Item "-ah"
include high-level source
\&\fIvalue\fR must be an integer constant. As in C, a leading \fB0x\fR
indicates a hexadecimal value, and a leading \fB0\fR indicates an octal
value. The value of the symbol can be overridden inside a source file via the
-use of a \f(CW\*(C`.set\*(C'\fR pseudo\-op.
+use of a \f(CW\*(C`.set\*(C'\fR pseudo-op.
.IP "\fB\-f\fR" 4
.IX Item "-f"
\&\*(L"fast\*(R"\-\-\-skip whitespace and comment preprocessing (assume source is
.IP "\fB\-m16c\fR" 4
.IX Item "-m16c"
Assemble M16C instructions (the default).
+.IP "\fB\-relax\fR" 4
+.IX Item "-relax"
+Enable support for link-time relaxations.
+.IP "\fB\-h\-tick\-hex\fR" 4
+.IX Item "-h-tick-hex"
+Support H'00 style hex constants in addition to 0x00 style.
.PP
The following options are available when as is configured for the
Renesas M32R (formerly Mitsubishi M32R) series.
.IP "\fB\-\-warn\-explicit\-parallel\-conflicts or \-\-Wp\fR" 4
.IX Item "--warn-explicit-parallel-conflicts or --Wp"
Produce warning messages when questionable parallel constructs are
-encountered.
+encountered.
.IP "\fB\-\-no\-warn\-explicit\-parallel\-conflicts or \-\-Wnp\fR" 4
.IX Item "--no-warn-explicit-parallel-conflicts or --Wnp"
Do not produce warning messages when questionable parallel constructs are
-encountered.
+encountered.
.PP
The following options are available when as is configured for the
Motorola 68000 series.
see \fBPDP\-11\-Options\fR.
.IP "\fB\-mpic | \-mno\-pic\fR" 4
.IX Item "-mpic | -mno-pic"
-Generate position-independent (or position\-dependent) code. The
+Generate position-independent (or position-dependent) code. The
default is \fB\-mpic\fR.
.IP "\fB\-mall\fR" 4
.IX Item "-mall"
Specify to use the 16\-bit integer \s-1ABI\s0.
.IP "\fB\-mlong\fR" 4
.IX Item "-mlong"
-Specify to use the 32\-bit integer \s-1ABI\s0.
+Specify to use the 32\-bit integer \s-1ABI\s0.
.IP "\fB\-mshort\-double\fR" 4
.IX Item "-mshort-double"
-Specify to use the 32\-bit double \s-1ABI\s0.
+Specify to use the 32\-bit double \s-1ABI\s0.
.IP "\fB\-mlong\-double\fR" 4
.IX Item "-mlong-double"
-Specify to use the 64\-bit double \s-1ABI\s0.
+Specify to use the 64\-bit double \s-1ABI\s0.
.IP "\fB\-\-force\-long\-branches\fR" 4
.IX Item "--force-long-branches"
Relative branches are turned into absolute ones. This concerns
Warn when the assembler switches to another architecture.
.PP
The following options are available when as is configured for the 'c54x
-architecture.
+architecture.
.IP "\fB\-mfar\-mode\fR" 4
.IX Item "-mfar-mode"
Enable extended addressing mode. All addresses and relocations will assume
.PP
See the info pages for documentation of the MMIX-specific options.
.PP
+The following options are available when as is configured for the s390
+processor family.
+.IP "\fB\-m31\fR" 4
+.IX Item "-m31"
+.PD 0
+.IP "\fB\-m64\fR" 4
+.IX Item "-m64"
+.PD
+Select the word size, either 31/32 bits or 64 bits.
+.IP "\fB\-mesa\fR" 4
+.IX Item "-mesa"
+.PD 0
+.IP "\fB\-mzarch\fR" 4
+.IX Item "-mzarch"
+.PD
+Select the architecture mode, either the Enterprise System
+Architecture (esa) or the z/Architecture mode (zarch).
+.IP "\fB\-march=\fR\fIprocessor\fR" 4
+.IX Item "-march=processor"
+Specify which s390 processor variant is the target, \fBg6\fR, \fBg6\fR,
+\&\fBz900\fR, \fBz990\fR, \fBz9\-109\fR, \fBz9\-ec\fR, or \fBz10\fR.
+.IP "\fB\-mregnames\fR" 4
+.IX Item "-mregnames"
+.PD 0
+.IP "\fB\-mno\-regnames\fR" 4
+.IX Item "-mno-regnames"
+.PD
+Allow or disallow symbolic names for registers.
+.IP "\fB\-mwarn\-areg\-zero\fR" 4
+.IX Item "-mwarn-areg-zero"
+Warn whenever the operand for a base or index register has been specified
+but evaluates to zero.
+.PP
The following options are available when as is configured for
an Xtensa processor.
.IP "\fB\-\-text\-section\-literals | \-\-no\-text\-section\-literals\fR" 4
The default is \fB\-\-transform\fR;
\&\fB\-\-no\-transform\fR should be used only in the rare cases when the
instructions must be exactly as specified in the assembly source.
+.IP "\fB\-\-rename\-section\fR \fIoldname\fR\fB=\fR\fInewname\fR" 4
+.IX Item "--rename-section oldname=newname"
+When generating output sections, rename the \fIoldname\fR section to
+\&\fInewname\fR.
.PP
The following options are available when as is configured for
a Z80 family processor.
.IP "\fB\-Wup\fR" 4
.IX Item "-Wup"
.PD
-Issue a warning for undocumented Z80 instructions that do not work on R800.
+Issue a warning for undocumented Z80 instructions that do not work on R800.
.IP "\fB\-forbid\-undocumented\-instructions\fR" 4
.IX Item "-forbid-undocumented-instructions"
.PD 0
.SH "COPYRIGHT"
.IX Header "COPYRIGHT"
Copyright (c) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002,
-2006, 2007 Free Software Foundation, Inc.
+2006, 2007, 2008, 2009 Free Software Foundation, Inc.
.PP
Permission is granted to copy, distribute and/or modify this document
-under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.1
+under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3
or any later version published by the Free Software Foundation;
with no Invariant Sections, with no Front-Cover Texts, and with no
Back-Cover Texts. A copy of the license is included in the
projects / msp430-binutils.git / blobdiff