This file documents the GNU Assembler "as".
Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002,
-2006, 2007 Free Software Foundation, Inc.
+2006, 2007, 2008, 2009 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document
-under the terms of the GNU Free Documentation License, Version 1.1 or
+under the terms of the GNU Free Documentation License, Version 1.3 or
any later version published by the Free Software Foundation; with no
Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
Texts. A copy of the license is included in the section entitled "GNU
********
This file is a user guide to the GNU assembler `as' (GNU Binutils)
-version 2.17.90.
+version 2.20.
This document is distributed under the terms of the GNU Free
Documentation License. A copy of the license is included in the
* Symbols:: Symbols
* Expressions:: Expressions
* Pseudo Ops:: Assembler Directives
+
+* Object Attributes:: Object Attributes
* Machine Dependencies:: Machine Dependent Features
* Reporting Bugs:: Reporting Bugs
* Acknowledgements:: Who Did What
Here is a brief summary of how to invoke `as'. For details, see *Note
Command-Line Options: Invoking.
- as [-a[cdhlns][=FILE]] [-alternate] [-D]
+ as [-a[cdghlns][=FILE]] [-alternate] [-D]
[-debug-prefix-map OLD=NEW]
[-defsym SYM=VAL] [-f] [-g] [-gstabs]
[-gstabs+] [-gdwarf-2] [-help] [-I DIR] [-J]
_Target Alpha options:_
[-mCPU]
[-mdebug | -no-mdebug]
+ [-replace | -noreplace]
[-relax] [-g] [-GSIZE]
[-F] [-32addr]
_Target D30V options:_
[-O|-n|-N]
+ _Target H8/300 options:_
+ [-h-tick-hex]
+
_Target i386 options:_
[-32|-64] [-n]
- [-march=CPU] [-mtune=CPU]
+ [-march=CPU[+EXTENSION...]] [-mtune=CPU]
_Target i960 options:_
[-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB|
[-mip2022|-mip2022ext]
_Target M32C options:_
- [-m32c|-m16c]
+ [-m32c|-m16c] [-relax] [-h-tick-hex]
_Target M32R options:_
[-m32rx|-[no-]warn-explicit-parallel-conflicts|
_Target MCORE options:_
[-jsri2bsr] [-sifilter] [-relax]
[-mcpu=[210|340]]
+ _Target MICROBLAZE options:_
_Target MIPS options:_
[-nocpp] [-EL] [-EB] [-O[OPTIMIZATION LEVEL]]
_Target PowerPC options:_
[-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|
- -m403|-m405|-mppc64|-m620|-mppc64bridge|-mbooke|
- -mbooke32|-mbooke64]
- [-mcom|-many|-maltivec] [-memb]
+ -m403|-m405|-mppc64|-m620|-mppc64bridge|-mbooke]
+ [-mcom|-many|-maltivec|-mvsx] [-memb]
[-mregnames|-mno-regnames]
[-mrelocatable|-mrelocatable-lib]
[-mlittle|-mlittle-endian|-mbig|-mbig-endian]
[-msolaris|-mno-solaris]
+ _Target s390 options:_
+ [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
+ [-mregnames|-mno-regnames]
+ [-mwarn-areg-zero]
+
+ _Target SCORE options:_
+ [-EB][-EL][-FIXDD][-NWARN]
+ [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
+ [-march=score7][-march=score3]
+ [-USE_R1][-KPIC][-O0][-G NUM][-V]
+
_Target SPARC options:_
[-Av6|-Av7|-Av8|-Asparclet|-Asparclite
-Av8plus|-Av8plusa|-Av9|-Av9a]
additional @FILE options; any such options will be processed
recursively.
-`-a[cdhlmns]'
+`-a[cdghlmns]'
Turn on listings, in any of a variety of ways:
`-ac'
`-ad'
omit debugging directives
+ `-ag'
+ include general information, like as version and options
+ passed
+
`-ah'
include high-level source
`-m16c'
Assemble M16C instructions (the default).
+`-relax'
+ Enable support for link-time relaxations.
+
+`-h-tick-hex'
+ Support H'00 style hex constants in addition to 0x00 style.
+
The following options are available when as is configured for the
Renesas M32R (formerly Mitsubishi M32R) series.
See the info pages for documentation of the MMIX-specific options.
+ The following options are available when as is configured for the
+s390 processor family.
+
+`-m31'
+`-m64'
+ Select the word size, either 31/32 bits or 64 bits.
+
+`-mesa'
+
+`-mzarch'
+ Select the architecture mode, either the Enterprise System
+ Architecture (esa) or the z/Architecture mode (zarch).
+
+`-march=PROCESSOR'
+ Specify which s390 processor variant is the target, `g6', `g6',
+ `z900', `z990', `z9-109', `z9-ec', or `z10'.
+
+`-mregnames'
+`-mno-regnames'
+ Allow or disallow symbolic names for registers.
+
+`-mwarn-areg-zero'
+ Warn whenever the operand for a base or index register has been
+ specified but evaluates to zero.
+
The following options are available when as is configured for an
Xtensa processor.
should be used only in the rare cases when the instructions must
be exactly as specified in the assembly source.
+`--rename-section OLDNAME=NEWNAME'
+ When generating output sections, rename the OLDNAME section to
+ NEWNAME.
+
The following options are available when as is configured for a Z80
family processor.
`-z80'
* Menu:
-* a:: -a[cdhlns] enable listings
+* a:: -a[cdghlns] enable listings
* alternate:: --alternate enable alternate macro syntax
* D:: -D for compatibility
* f:: -f to work faster
\1f
File: as.info, Node: a, Next: alternate, Up: Invoking
-2.1 Enable Listings: `-a[cdhlns]'
-=================================
+2.1 Enable Listings: `-a[cdghlns]'
+==================================
These options enable listing output from the assembler. By itself,
`-a' requests high-level, assembly, and symbols listing. You can use
listings require that a compiler debugging option like `-g' be used,
and that assembly listings (`-al') be requested also.
+ Use the `-ag' option to print a first section with general assembly
+information, like as version, switches passed, or time stamp.
+
Use the `-ac' option to omit false conditionals from a listing. Any
lines which are not assembled because of a false `.if' (or `.ifdef', or
any other conditional), or a true `.if' followed by an `.else', will be
considered a comment and is ignored. The line comment character is `;'
on the ARC; `@' on the ARM; `;' for the H8/300 family; `;' for the HPPA;
`#' on the i386 and x86-64; `#' on the i960; `;' for the PDP-11; `;'
-for picoJava; `#' for Motorola PowerPC; `!' for the Renesas / SuperH SH;
-`!' on the SPARC; `#' on the ip2k; `#' on the m32c; `#' on the m32r;
-`|' on the 680x0; `#' on the 68HC11 and 68HC12; `#' on the Vax; `;' for
-the Z80; `!' for the Z8000; `#' on the V850; `#' for Xtensa systems;
-see *Note Machine Dependencies::.
+for picoJava; `#' for Motorola PowerPC; `#' for IBM S/390; `#' for the
+Sunplus SCORE; `!' for the Renesas / SuperH SH; `!' on the SPARC; `#'
+on the ip2k; `#' on the m32c; `#' on the m32r; `|' on the 680x0; `#' on
+the 68HC11 and 68HC12; `#' on the Vax; `;' for the Z80; `!' for the
+Z8000; `#' on the V850; `#' for Xtensa systems; see *Note Machine
+Dependencies::.
On some machines there are two different line comment characters.
One character only begins a comment if it is the first non-whitespace
In the same way, using a double equals sign `='`=' here represents an
equivalent of the `.eqv' directive. *Note `.eqv': Eqv.
+ Blackfin does not support symbol assignment with `='.
+
\1f
File: as.info, Node: Symbol Names, Next: Dot, Prev: Setting Symbols, Up: Symbols
are redefined by another occurrence of the same local label.
Dollar labels are defined in exactly the same way as ordinary local
-labels, except that instead of being terminated by a colon, they are
-terminated by a dollar sign, e.g., `55$'.
+labels, except that they have a dollar sign suffix to their numeric
+value, e.g., `55$:'.
They can also be distinguished from ordinary local labels by their
transformed names which use ASCII character `\001' (control-A) as the
arguments.
\1f
-File: as.info, Node: Pseudo Ops, Next: Machine Dependencies, Prev: Expressions, Up: Top
+File: as.info, Node: Pseudo Ops, Next: Object Attributes, Prev: Expressions, Up: Top
7 Assembler Directives
**********************
* Abort:: `.abort'
-* ABORT (COFF):: `.ABORT'
+* ABORT (COFF):: `.ABORT'
* Align:: `.align ABS-EXPR , ABS-EXPR'
* Altmacro:: `.altmacro'
* Asciz:: `.asciz "STRING"'...
* Balign:: `.balign ABS-EXPR , ABS-EXPR'
* Byte:: `.byte EXPRESSIONS'
-* Comm:: `.comm SYMBOL , LENGTH '
-
* CFI directives:: `.cfi_startproc [simple]', `.cfi_endproc', etc.
-
+* Comm:: `.comm SYMBOL , LENGTH '
* Data:: `.data SUBSECTION'
* Def:: `.def NAME'
* Exitm:: `.exitm'
* Extern:: `.extern'
* Fail:: `.fail'
-
-* File:: `.file STRING'
-
+* File:: `.file'
* Fill:: `.fill REPEAT , SIZE , VALUE'
* Float:: `.float FLONUMS'
* Func:: `.func'
* Global:: `.global SYMBOL', `.globl SYMBOL'
+* Gnu_attribute:: `.gnu_attribute TAG,VALUE'
* Hidden:: `.hidden NAMES'
* hword:: `.hword EXPRESSIONS'
* Linkonce:: `.linkonce [TYPE]'
* List:: `.list'
* Ln:: `.ln LINE-NUMBER'
+* Loc:: `.loc FILENO LINENO'
+* Loc_mark_labels:: `.loc_mark_labels ENABLE'
-* LNS directives:: `.file', `.loc', etc.
+* Local:: `.local NAMES'
* Long:: `.long EXPRESSIONS'
* Scl:: `.scl CLASS'
-* Section:: `.section NAME'
+* Section:: `.section NAME[, FLAGS]'
* Set:: `.set SYMBOL, EXPRESSION'
* Short:: `.short EXPRESSIONS'
* Size:: `.size [NAME , EXPRESSION]'
* Skip:: `.skip SIZE , FILL'
+
* Sleb128:: `.sleb128 EXPRESSIONS'
+
* Space:: `.space SIZE , FILL'
* Stab:: `.stabd, .stabn, .stabs'
-* String:: `.string "STR"'
+* String:: `.string "STR"', `.string8 "STR"', `.string16 "STR"', `.string32 "STR"', `.string64 "STR"'
* Struct:: `.struct EXPRESSION'
* SubSection:: `.subsection'
is already a multiple of 8, no change is needed. For the tic54x, the
first expression is the alignment request in words.
- For other systems, including the i386 using a.out format, and the
-arm and strongarm, it is the number of low-order zero bits the location
-counter must have after advancement. For example `.align 3' advances
-the location counter until it a multiple of 8. If the location counter
-is already a multiple of 8, no change is needed.
+ For other systems, including ppc, i386 using a.out format, arm and
+strongarm, it is the number of low-order zero bits the location counter
+must have after advancement. For example `.align 3' advances the
+location counter until it a multiple of 8. If the location counter is
+already a multiple of 8, no change is needed.
This inconsistency is due to the different behaviors of the various
native assemblers for these systems which GAS must emulate. GAS also
have a consistent behavior across all architectures (but are specific
to GAS).
+\1f
+File: as.info, Node: Altmacro, Next: Ascii, Prev: Align, Up: Pseudo Ops
+
+7.4 `.altmacro'
+===============
+
+Enable alternate macro mode, enabling:
+
+`LOCAL NAME [ , ... ]'
+ One additional directive, `LOCAL', is available. It is used to
+ generate a string replacement for each of the NAME arguments, and
+ replace any instances of NAME in each macro expansion. The
+ replacement string is unique in the assembly, and different for
+ each separate macro expansion. `LOCAL' allows you to write macros
+ that define symbols, without fear of conflict between separate
+ macro expansions.
+
+`String delimiters'
+ You can write strings delimited in these other ways besides
+ `"STRING"':
+
+ `'STRING''
+ You can delimit strings with single-quote characters.
+
+ `<STRING>'
+ You can delimit strings with matching angle brackets.
+
+`single-character string escape'
+ To include any single character literally in a string (even if the
+ character would otherwise have some special meaning), you can
+ prefix the character with `!' (an exclamation mark). For example,
+ you can write `<4.3 !> 5.4!!>' to get the literal text `4.3 >
+ 5.4!'.
+
+`Expression results as strings'
+ You can write `%EXPR' to evaluate the expression EXPR and use the
+ result as a string.
+
\1f
File: as.info, Node: Ascii, Next: Asciz, Prev: Altmacro, Up: Pseudo Ops
-7.4 `.ascii "STRING"'...
+7.5 `.ascii "STRING"'...
========================
`.ascii' expects zero or more string literals (*note Strings::)
\1f
File: as.info, Node: Asciz, Next: Balign, Prev: Ascii, Up: Pseudo Ops
-7.5 `.asciz "STRING"'...
+7.6 `.asciz "STRING"'...
========================
`.asciz' is just like `.ascii', but each string is followed by a zero
\1f
File: as.info, Node: Balign, Next: Byte, Prev: Asciz, Up: Pseudo Ops
-7.6 `.balign[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR'
+7.7 `.balign[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR'
==============================================
Pad the location counter (in the current subsection) to a particular
3 bytes, the fill value is undefined.
\1f
-File: as.info, Node: Byte, Next: Comm, Prev: Balign, Up: Pseudo Ops
+File: as.info, Node: Byte, Next: CFI directives, Prev: Balign, Up: Pseudo Ops
-7.7 `.byte EXPRESSIONS'
+7.8 `.byte EXPRESSIONS'
=======================
`.byte' expects zero or more expressions, separated by commas. Each
expression is assembled into the next byte.
\1f
-File: as.info, Node: Comm, Next: CFI directives, Prev: Byte, Up: Pseudo Ops
-
-7.8 `.comm SYMBOL , LENGTH '
-============================
-
-`.comm' declares a common symbol named SYMBOL. When linking, a common
-symbol in one object file may be merged with a defined or common symbol
-of the same name in another object file. If `ld' does not see a
-definition for the symbol-just one or more common symbols-then it will
-allocate LENGTH bytes of uninitialized memory. LENGTH must be an
-absolute expression. If `ld' sees multiple common symbols with the
-same name, and they do not all have the same size, it will allocate
-space using the largest size.
-
- When using ELF, the `.comm' directive takes an optional third
-argument. This is the desired alignment of the symbol, specified as a
-byte boundary (for example, an alignment of 16 means that the least
-significant 4 bits of the address should be zero). The alignment must
-be an absolute expression, and it must be a power of two. If `ld'
-allocates uninitialized memory for the common symbol, it will use the
-alignment when placing the symbol. If no alignment is specified, `as'
-will set the alignment to the largest power of two less than or equal
-to the size of the symbol, up to a maximum of 16.
-
- The syntax for `.comm' differs slightly on the HPPA. The syntax is
-`SYMBOL .comm, LENGTH'; SYMBOL is optional.
-
-\1f
-File: as.info, Node: CFI directives, Next: Data, Prev: Comm, Up: Pseudo Ops
+File: as.info, Node: CFI directives, Next: Comm, Prev: Byte, Up: Pseudo Ops
7.9 `.cfi_startproc [simple]'
=============================
have an entry in `.eh_frame'. It initializes some internal data
structures. Don't forget to close the function by `.cfi_endproc'.
+7.10 `.cfi_sections SECTION_LIST'
+=================================
+
+`.cfi_sections' may be used to specify whether CFI directives should
+emit `.eh_frame' section and/or `.debug_frame' section. If
+SECTION_LIST is `.eh_frame', `.eh_frame' is emitted, if SECTION_LIST is
+`.debug_frame', `.debug_frame' is emitted. To emit both use
+`.eh_frame, .debug_frame'. The default if this directive is not used
+is `.cfi_sections .eh_frame'.
+
Unless `.cfi_startproc' is used along with parameter `simple' it
also emits some architecture dependent initial CFI instructions.
-7.10 `.cfi_endproc'
+7.11 `.cfi_endproc'
===================
`.cfi_endproc' is used at the end of a function where it closes its
unwind entry previously opened by `.cfi_startproc', and emits it to
`.eh_frame'.
-7.11 `.cfi_personality ENCODING [, EXP]'
+7.12 `.cfi_personality ENCODING [, EXP]'
========================================
`.cfi_personality' defines personality routine and its encoding.
routine itself. The default after `.cfi_startproc' is
`.cfi_personality 0xff', no personality routine.
-7.12 `.cfi_lsda ENCODING [, EXP]'
+7.13 `.cfi_lsda ENCODING [, EXP]'
=================================
`.cfi_lsda' defines LSDA and its encoding. ENCODING must be a constant
argument should be a constant or a symbol name. The default after
`.cfi_startproc' is `.cfi_lsda 0xff', no LSDA.
-7.13 `.cfi_def_cfa REGISTER, OFFSET'
+7.14 `.cfi_def_cfa REGISTER, OFFSET'
====================================
`.cfi_def_cfa' defines a rule for computing CFA as: take address from
REGISTER and add OFFSET to it.
-7.14 `.cfi_def_cfa_register REGISTER'
+7.15 `.cfi_def_cfa_register REGISTER'
=====================================
`.cfi_def_cfa_register' modifies a rule for computing CFA. From now on
REGISTER will be used instead of the old one. Offset remains the same.
-7.15 `.cfi_def_cfa_offset OFFSET'
+7.16 `.cfi_def_cfa_offset OFFSET'
=================================
`.cfi_def_cfa_offset' modifies a rule for computing CFA. Register
remains the same, but OFFSET is new. Note that it is the absolute
offset that will be added to a defined register to compute CFA address.
-7.16 `.cfi_adjust_cfa_offset OFFSET'
+7.17 `.cfi_adjust_cfa_offset OFFSET'
====================================
Same as `.cfi_def_cfa_offset' but OFFSET is a relative value that is
added/substracted from the previous offset.
-7.17 `.cfi_offset REGISTER, OFFSET'
+7.18 `.cfi_offset REGISTER, OFFSET'
===================================
Previous value of REGISTER is saved at offset OFFSET from CFA.
-7.18 `.cfi_rel_offset REGISTER, OFFSET'
+7.19 `.cfi_rel_offset REGISTER, OFFSET'
=======================================
Previous value of REGISTER is saved at offset OFFSET from the current
displacement of the CFA register from the CFA. This is often easier to
use, because the number will match the code it's annotating.
-7.19 `.cfi_register REGISTER1, REGISTER2'
+7.20 `.cfi_register REGISTER1, REGISTER2'
=========================================
Previous value of REGISTER1 is saved in register REGISTER2.
-7.20 `.cfi_restore REGISTER'
+7.21 `.cfi_restore REGISTER'
============================
`.cfi_restore' says that the rule for REGISTER is now the same as it
was at the beginning of the function, after all initial instruction
added by `.cfi_startproc' were executed.
-7.21 `.cfi_undefined REGISTER'
+7.22 `.cfi_undefined REGISTER'
==============================
From now on the previous value of REGISTER can't be restored anymore.
-7.22 `.cfi_same_value REGISTER'
+7.23 `.cfi_same_value REGISTER'
===============================
Current value of REGISTER is the same like in the previous frame, i.e.
no restoration needed.
-7.23 `.cfi_remember_state',
+7.24 `.cfi_remember_state',
===========================
First save all current rules for all registers by `.cfi_remember_state',
everything is hopelessly bad, use `.cfi_restore_state' to restore the
previous saved state.
-7.24 `.cfi_return_column REGISTER'
+7.25 `.cfi_return_column REGISTER'
==================================
Change return column REGISTER, i.e. the return address is either
directly in REGISTER or can be accessed by rules for REGISTER.
-7.25 `.cfi_signal_frame'
+7.26 `.cfi_signal_frame'
========================
Mark current function as signal trampoline.
-7.26 `.cfi_window_save'
+7.27 `.cfi_window_save'
=======================
SPARC register window has been saved.
-7.27 `.cfi_escape' EXPRESSION[, ...]
+7.28 `.cfi_escape' EXPRESSION[, ...]
====================================
Allows the user to add arbitrary bytes to the unwind info. One might
use this to add OS-specific CFI opcodes, or generic CFI opcodes that
GAS does not yet support.
-\1f
-File: as.info, Node: LNS directives, Next: Long, Prev: Ln, Up: Pseudo Ops
-
-7.28 `.file FILENO FILENAME'
-============================
-
-When emitting dwarf2 line number information `.file' assigns filenames
-to the `.debug_line' file name table. The FILENO operand should be a
-unique positive integer to use as the index of the entry in the table.
-The FILENAME operand is a C string literal.
+7.29 `.cfi_val_encoded_addr REGISTER, ENCODING, LABEL'
+======================================================
- The detail of filename indices is exposed to the user because the
-filename table is shared with the `.debug_info' section of the dwarf2
-debugging information, and thus the user must know the exact indices
-that table entries will have.
-
-7.29 `.loc FILENO LINENO [COLUMN] [OPTIONS]'
-============================================
-
-The `.loc' directive will add row to the `.debug_line' line number
-matrix corresponding to the immediately following assembly instruction.
-The FILENO, LINENO, and optional COLUMN arguments will be applied to
-the `.debug_line' state machine before the row is added.
-
- The OPTIONS are a sequence of the following tokens in any order:
+The current value of REGISTER is LABEL. The value of LABEL will be
+encoded in the output file according to ENCODING; see the description
+of `.cfi_personality' for details on this encoding.
-`basic_block'
- This option will set the `basic_block' register in the
- `.debug_line' state machine to `true'.
+ The usefulness of equating a register to a fixed label is probably
+limited to the return address register. Here, it can be useful to mark
+a code segment that has only one return address which is reached by a
+direct branch and no copy of the return address exists in memory or
+another register.
-`prologue_end'
- This option will set the `prologue_end' register in the
- `.debug_line' state machine to `true'.
+\1f
+File: as.info, Node: Comm, Next: Data, Prev: CFI directives, Up: Pseudo Ops
-`epilogue_begin'
- This option will set the `epilogue_begin' register in the
- `.debug_line' state machine to `true'.
+7.30 `.comm SYMBOL , LENGTH '
+=============================
-`is_stmt VALUE'
- This option will set the `is_stmt' register in the `.debug_line'
- state machine to `value', which must be either 0 or 1.
+`.comm' declares a common symbol named SYMBOL. When linking, a common
+symbol in one object file may be merged with a defined or common symbol
+of the same name in another object file. If `ld' does not see a
+definition for the symbol-just one or more common symbols-then it will
+allocate LENGTH bytes of uninitialized memory. LENGTH must be an
+absolute expression. If `ld' sees multiple common symbols with the
+same name, and they do not all have the same size, it will allocate
+space using the largest size.
-`isa VALUE'
- This directive will set the `isa' register in the `.debug_line'
- state machine to VALUE, which must be an unsigned integer.
+ When using ELF or (as a GNU extension) PE, the `.comm' directive
+takes an optional third argument. This is the desired alignment of the
+symbol, specified for ELF as a byte boundary (for example, an alignment
+of 16 means that the least significant 4 bits of the address should be
+zero), and for PE as a power of two (for example, an alignment of 5
+means aligned to a 32-byte boundary). The alignment must be an
+absolute expression, and it must be a power of two. If `ld' allocates
+uninitialized memory for the common symbol, it will use the alignment
+when placing the symbol. If no alignment is specified, `as' will set
+the alignment to the largest power of two less than or equal to the
+size of the symbol, up to a maximum of 16 on ELF, or the default
+section alignment of 4 on PE(1).
+ The syntax for `.comm' differs slightly on the HPPA. The syntax is
+`SYMBOL .comm, LENGTH'; SYMBOL is optional.
-7.30 `.loc_mark_blocks ENABLE'
-==============================
+ ---------- Footnotes ----------
-The `.loc_mark_blocks' directive makes the assembler emit an entry to
-the `.debug_line' line number matrix with the `basic_block' register in
-the state machine set whenever a code label is seen. The ENABLE
-argument should be either 1 or 0, to enable or disable this function
-respectively.
+ (1) This is not the same as the executable image file alignment
+controlled by `ld''s `--section-alignment' option; image file sections
+in PE are aligned to multiples of 4096, which is far too large an
+alignment for ordinary variables. It is rather the default alignment
+for (non-debug) sections within object (`*.o') files, which are less
+strictly aligned.
\1f
-File: as.info, Node: Data, Next: Def, Prev: CFI directives, Up: Pseudo Ops
+File: as.info, Node: Data, Next: Def, Prev: Comm, Up: Pseudo Ops
7.31 `.data SUBSECTION'
=======================
\1f
File: as.info, Node: File, Next: Fill, Prev: Fail, Up: Pseudo Ops
-7.51 `.file STRING'
-===================
+7.51 `.file'
+============
+
+There are two different versions of the `.file' directive. Targets
+that support DWARF2 line number information use the DWARF2 version of
+`.file'. Other targets use the default version.
-`.file' tells `as' that we are about to start a new logical file.
-STRING is the new file name. In general, the filename is recognized
+Default Version
+---------------
+
+This version of the `.file' directive tells `as' that we are about to
+start a new logical file. The syntax is:
+
+ .file STRING
+
+ STRING is the new file name. In general, the filename is recognized
whether or not it is surrounded by quotes `"'; but if you wish to
specify an empty file name, you must give the quotes-`""'. This
statement may go away in future: it is only recognized to be compatible
with old `as' programs.
+DWARF2 Version
+--------------
+
+When emitting DWARF2 line number information, `.file' assigns filenames
+to the `.debug_line' file name table. The syntax is:
+
+ .file FILENO FILENAME
+
+ The FILENO operand should be a unique positive integer to use as the
+index of the entry in the table. The FILENAME operand is a C string
+literal.
+
+ The detail of filename indices is exposed to the user because the
+filename table is shared with the `.debug_info' section of the DWARF2
+debugging information, and thus the user must know the exact indices
+that table entries will have.
+
\1f
File: as.info, Node: Fill, Next: Float, Prev: File, Up: Pseudo Ops
function must be terminated with `.endfunc'.
\1f
-File: as.info, Node: Global, Next: Hidden, Prev: Func, Up: Pseudo Ops
+File: as.info, Node: Global, Next: Gnu_attribute, Prev: Func, Up: Pseudo Ops
7.55 `.global SYMBOL', `.globl SYMBOL'
======================================
as well. *Note HPPA Assembler Directives: HPPA Directives.
\1f
-File: as.info, Node: Hidden, Next: hword, Prev: Global, Up: Pseudo Ops
+File: as.info, Node: Gnu_attribute, Next: Hidden, Prev: Global, Up: Pseudo Ops
+
+7.56 `.gnu_attribute TAG,VALUE'
+===============================
+
+Record a GNU object attribute for this file. *Note Object Attributes::.
+
+\1f
+File: as.info, Node: Hidden, Next: hword, Prev: Gnu_attribute, Up: Pseudo Ops
-7.56 `.hidden NAMES'
+7.57 `.hidden NAMES'
====================
This is one of the ELF visibility directives. The other two are
\1f
File: as.info, Node: hword, Next: Ident, Prev: Hidden, Up: Pseudo Ops
-7.57 `.hword EXPRESSIONS'
+7.58 `.hword EXPRESSIONS'
=========================
This expects zero or more EXPRESSIONS, and emits a 16 bit number for
\1f
File: as.info, Node: Ident, Next: If, Prev: hword, Up: Pseudo Ops
-7.58 `.ident'
+7.59 `.ident'
=============
This directive is used by some assemblers to place tags in object
\1f
File: as.info, Node: If, Next: Incbin, Prev: Ident, Up: Pseudo Ops
-7.59 `.if ABSOLUTE EXPRESSION'
+7.60 `.if ABSOLUTE EXPRESSION'
==============================
`.if' marks the beginning of a section of code which is only considered
\1f
File: as.info, Node: Incbin, Next: Include, Prev: If, Up: Pseudo Ops
-7.60 `.incbin "FILE"[,SKIP[,COUNT]]'
+7.61 `.incbin "FILE"[,SKIP[,COUNT]]'
====================================
The `incbin' directive includes FILE verbatim at the current location.
\1f
File: as.info, Node: Include, Next: Int, Prev: Incbin, Up: Pseudo Ops
-7.61 `.include "FILE"'
+7.62 `.include "FILE"'
======================
This directive provides a way to include supporting files at specified
\1f
File: as.info, Node: Int, Next: Internal, Prev: Include, Up: Pseudo Ops
-7.62 `.int EXPRESSIONS'
+7.63 `.int EXPRESSIONS'
=======================
Expect zero or more EXPRESSIONS, of any section, separated by commas.
\1f
File: as.info, Node: Internal, Next: Irp, Prev: Int, Up: Pseudo Ops
-7.63 `.internal NAMES'
+7.64 `.internal NAMES'
======================
This is one of the ELF visibility directives. The other two are
\1f
File: as.info, Node: Irp, Next: Irpc, Prev: Internal, Up: Pseudo Ops
-7.64 `.irp SYMBOL,VALUES'...
+7.65 `.irp SYMBOL,VALUES'...
============================
Evaluate a sequence of statements assigning different values to SYMBOL.
\1f
File: as.info, Node: Irpc, Next: Lcomm, Prev: Irp, Up: Pseudo Ops
-7.65 `.irpc SYMBOL,VALUES'...
+7.66 `.irpc SYMBOL,VALUES'...
=============================
Evaluate a sequence of statements assigning different values to SYMBOL.
\1f
File: as.info, Node: Lcomm, Next: Lflags, Prev: Irpc, Up: Pseudo Ops
-7.66 `.lcomm SYMBOL , LENGTH'
+7.67 `.lcomm SYMBOL , LENGTH'
=============================
Reserve LENGTH (an absolute expression) bytes for a local common
\1f
File: as.info, Node: Lflags, Next: Line, Prev: Lcomm, Up: Pseudo Ops
-7.67 `.lflags'
+7.68 `.lflags'
==============
`as' accepts this directive, for compatibility with other assemblers,
\1f
File: as.info, Node: Line, Next: Linkonce, Prev: Lflags, Up: Pseudo Ops
-7.68 `.line LINE-NUMBER'
+7.69 `.line LINE-NUMBER'
========================
- Change the logical line number. LINE-NUMBER must be an absolute
+Change the logical line number. LINE-NUMBER must be an absolute
expression. The next line has that logical line number. Therefore any
other statements on the current line (after a statement separator
character) are reported as on logical line number LINE-NUMBER - 1. One
day `as' will no longer support this directive: it is recognized only
for compatibility with existing assembler programs.
- Even though this is a directive associated with the `a.out' or
-`b.out' object-code formats, `as' still recognizes it when producing
-COFF output, and treats `.line' as though it were the COFF `.ln' _if_
-it is found outside a `.def'/`.endef' pair.
+Even though this is a directive associated with the `a.out' or `b.out'
+object-code formats, `as' still recognizes it when producing COFF
+output, and treats `.line' as though it were the COFF `.ln' _if_ it is
+found outside a `.def'/`.endef' pair.
Inside a `.def', `.line' is, instead, one of the directives used by
compilers to generate auxiliary symbol information for debugging.
\1f
File: as.info, Node: Linkonce, Next: List, Prev: Line, Up: Pseudo Ops
-7.69 `.linkonce [TYPE]'
+7.70 `.linkonce [TYPE]'
=======================
Mark the current section so that the linker only includes a single copy
Warn if any of the duplicates do not have exactly the same
contents.
-\1f
-File: as.info, Node: Ln, Next: LNS directives, Prev: List, Up: Pseudo Ops
-
-7.70 `.ln LINE-NUMBER'
-======================
-
-`.ln' is a synonym for `.line'.
-
-\1f
-File: as.info, Node: MRI, Next: Noaltmacro, Prev: Macro, Up: Pseudo Ops
-
-7.71 `.mri VAL'
-===============
-
-If VAL is non-zero, this tells `as' to enter MRI mode. If VAL is zero,
-this tells `as' to exit MRI mode. This change affects code assembled
-until the next `.mri' directive, or until the end of the file. *Note
-MRI mode: M.
-
\1f
File: as.info, Node: List, Next: Ln, Prev: Linkonce, Up: Pseudo Ops
-7.72 `.list'
+7.71 `.list'
============
Control (in conjunction with the `.nolist' directive) whether or not
initial value of the listing counter is one.
\1f
-File: as.info, Node: Long, Next: Macro, Prev: LNS directives, Up: Pseudo Ops
+File: as.info, Node: Ln, Next: Loc, Prev: List, Up: Pseudo Ops
+
+7.72 `.ln LINE-NUMBER'
+======================
+
+`.ln' is a synonym for `.line'.
+
+\1f
+File: as.info, Node: Loc, Next: Loc_mark_labels, Prev: Ln, Up: Pseudo Ops
+
+7.73 `.loc FILENO LINENO [COLUMN] [OPTIONS]'
+============================================
+
+When emitting DWARF2 line number information, the `.loc' directive will
+add a row to the `.debug_line' line number matrix corresponding to the
+immediately following assembly instruction. The FILENO, LINENO, and
+optional COLUMN arguments will be applied to the `.debug_line' state
+machine before the row is added.
+
+ The OPTIONS are a sequence of the following tokens in any order:
+
+`basic_block'
+ This option will set the `basic_block' register in the
+ `.debug_line' state machine to `true'.
+
+`prologue_end'
+ This option will set the `prologue_end' register in the
+ `.debug_line' state machine to `true'.
+
+`epilogue_begin'
+ This option will set the `epilogue_begin' register in the
+ `.debug_line' state machine to `true'.
+
+`is_stmt VALUE'
+ This option will set the `is_stmt' register in the `.debug_line'
+ state machine to `value', which must be either 0 or 1.
+
+`isa VALUE'
+ This directive will set the `isa' register in the `.debug_line'
+ state machine to VALUE, which must be an unsigned integer.
+
+`discriminator VALUE'
+ This directive will set the `discriminator' register in the
+ `.debug_line' state machine to VALUE, which must be an unsigned
+ integer.
+
+
+\1f
+File: as.info, Node: Loc_mark_labels, Next: Local, Prev: Loc, Up: Pseudo Ops
+
+7.74 `.loc_mark_labels ENABLE'
+==============================
+
+When emitting DWARF2 line number information, the `.loc_mark_labels'
+directive makes the assembler emit an entry to the `.debug_line' line
+number matrix with the `basic_block' register in the state machine set
+whenever a code label is seen. The ENABLE argument should be either 1
+or 0, to enable or disable this function respectively.
+
+\1f
+File: as.info, Node: Local, Next: Long, Prev: Loc_mark_labels, Up: Pseudo Ops
+
+7.75 `.local NAMES'
+===================
+
+This directive, which is available for ELF targets, marks each symbol in
+the comma-separated list of `names' as a local symbol so that it will
+not be externally visible. If the symbols do not already exist, they
+will be created.
+
+ For targets where the `.lcomm' directive (*note Lcomm::) does not
+accept an alignment argument, which is the case for most ELF targets,
+the `.local' directive can be used in combination with `.comm' (*note
+Comm::) to define aligned local common data.
+
+\1f
+File: as.info, Node: Long, Next: Macro, Prev: Local, Up: Pseudo Ops
-7.73 `.long EXPRESSIONS'
+7.76 `.long EXPRESSIONS'
========================
`.long' is the same as `.int'. *Note `.int': Int.
\1f
File: as.info, Node: Macro, Next: MRI, Prev: Long, Up: Pseudo Ops
-7.74 `.macro'
+7.77 `.macro'
=============
The commands `.macro' and `.endm' allow you to define macros that
Altmacro.
\1f
-File: as.info, Node: Altmacro, Next: Ascii, Prev: Align, Up: Pseudo Ops
-
-7.75 `.altmacro'
-================
-
-Enable alternate macro mode, enabling:
-
-`LOCAL NAME [ , ... ]'
- One additional directive, `LOCAL', is available. It is used to
- generate a string replacement for each of the NAME arguments, and
- replace any instances of NAME in each macro expansion. The
- replacement string is unique in the assembly, and different for
- each separate macro expansion. `LOCAL' allows you to write macros
- that define symbols, without fear of conflict between separate
- macro expansions.
-
-`String delimiters'
- You can write strings delimited in these other ways besides
- `"STRING"':
-
- `'STRING''
- You can delimit strings with single-quote characters.
-
- `<STRING>'
- You can delimit strings with matching angle brackets.
+File: as.info, Node: MRI, Next: Noaltmacro, Prev: Macro, Up: Pseudo Ops
-`single-character string escape'
- To include any single character literally in a string (even if the
- character would otherwise have some special meaning), you can
- prefix the character with `!' (an exclamation mark). For example,
- you can write `<4.3 !> 5.4!!>' to get the literal text `4.3 >
- 5.4!'.
+7.78 `.mri VAL'
+===============
-`Expression results as strings'
- You can write `%EXPR' to evaluate the expression EXPR and use the
- result as a string.
+If VAL is non-zero, this tells `as' to enter MRI mode. If VAL is zero,
+this tells `as' to exit MRI mode. This change affects code assembled
+until the next `.mri' directive, or until the end of the file. *Note
+MRI mode: M.
\1f
File: as.info, Node: Noaltmacro, Next: Nolist, Prev: MRI, Up: Pseudo Ops
-7.76 `.noaltmacro'
+7.79 `.noaltmacro'
==================
Disable alternate macro mode. *Note Altmacro::.
\1f
File: as.info, Node: Nolist, Next: Octa, Prev: Noaltmacro, Up: Pseudo Ops
-7.77 `.nolist'
+7.80 `.nolist'
==============
Control (in conjunction with the `.list' directive) whether or not
\1f
File: as.info, Node: Octa, Next: Org, Prev: Nolist, Up: Pseudo Ops
-7.78 `.octa BIGNUMS'
+7.81 `.octa BIGNUMS'
====================
This directive expects zero or more bignums, separated by commas. For
\1f
File: as.info, Node: Org, Next: P2align, Prev: Octa, Up: Pseudo Ops
-7.79 `.org NEW-LC , FILL'
+7.82 `.org NEW-LC , FILL'
=========================
Advance the location counter of the current section to NEW-LC. NEW-LC
\1f
File: as.info, Node: P2align, Next: PopSection, Prev: Org, Up: Pseudo Ops
-7.80 `.p2align[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR'
+7.83 `.p2align[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR'
================================================
Pad the location counter (in the current subsection) to a particular
bytes depends upon the endianness of the processor). If it skips 1 or
3 bytes, the fill value is undefined.
-\1f
-File: as.info, Node: Previous, Next: Print, Prev: PopSection, Up: Pseudo Ops
-
-7.81 `.previous'
-================
-
-This is one of the ELF section stack manipulation directives. The
-others are `.section' (*note Section::), `.subsection' (*note
-SubSection::), `.pushsection' (*note PushSection::), and `.popsection'
-(*note PopSection::).
-
- This directive swaps the current section (and subsection) with most
-recently referenced section (and subsection) prior to this one.
-Multiple `.previous' directives in a row will flip between two sections
-(and their subsections).
-
- In terms of the section stack, this directive swaps the current
-section with the top section on the section stack.
-
\1f
File: as.info, Node: PopSection, Next: Previous, Prev: P2align, Up: Pseudo Ops
-7.82 `.popsection'
+7.84 `.popsection'
==================
This is one of the ELF section stack manipulation directives. The
the top section (and subsection) on the section stack. This section is
popped off the stack.
+\1f
+File: as.info, Node: Previous, Next: Print, Prev: PopSection, Up: Pseudo Ops
+
+7.85 `.previous'
+================
+
+This is one of the ELF section stack manipulation directives. The
+others are `.section' (*note Section::), `.subsection' (*note
+SubSection::), `.pushsection' (*note PushSection::), and `.popsection'
+(*note PopSection::).
+
+ This directive swaps the current section (and subsection) with most
+recently referenced section/subsection pair prior to this one. Multiple
+`.previous' directives in a row will flip between two sections (and
+their subsections). For example:
+
+ .section A
+ .subsection 1
+ .word 0x1234
+ .subsection 2
+ .word 0x5678
+ .previous
+ .word 0x9abc
+
+ Will place 0x1234 and 0x9abc into subsection 1 and 0x5678 into
+subsection 2 of section A. Whilst:
+
+ .section A
+ .subsection 1
+ # Now in section A subsection 1
+ .word 0x1234
+ .section B
+ .subsection 0
+ # Now in section B subsection 0
+ .word 0x5678
+ .subsection 1
+ # Now in section B subsection 1
+ .word 0x9abc
+ .previous
+ # Now in section B subsection 0
+ .word 0xdef0
+
+ Will place 0x1234 into section A, 0x5678 and 0xdef0 into subsection
+0 of section B and 0x9abc into subsection 1 of section B.
+
+ In terms of the section stack, this directive swaps the current
+section with the top section on the section stack.
+
\1f
File: as.info, Node: Print, Next: Protected, Prev: Previous, Up: Pseudo Ops
-7.83 `.print STRING'
+7.86 `.print STRING'
====================
`as' will print STRING on the standard output during assembly. You
\1f
File: as.info, Node: Protected, Next: Psize, Prev: Print, Up: Pseudo Ops
-7.84 `.protected NAMES'
+7.87 `.protected NAMES'
=======================
This is one of the ELF visibility directives. The other two are
\1f
File: as.info, Node: Psize, Next: Purgem, Prev: Protected, Up: Pseudo Ops
-7.85 `.psize LINES , COLUMNS'
+7.88 `.psize LINES , COLUMNS'
=============================
Use this directive to declare the number of lines--and, optionally, the
\1f
File: as.info, Node: Purgem, Next: PushSection, Prev: Psize, Up: Pseudo Ops
-7.86 `.purgem NAME'
+7.89 `.purgem NAME'
===================
Undefine the macro NAME, so that later uses of the string will not be
\1f
File: as.info, Node: PushSection, Next: Quad, Prev: Purgem, Up: Pseudo Ops
-7.87 `.pushsection NAME , SUBSECTION'
-=====================================
+7.90 `.pushsection NAME [, SUBSECTION] [, "FLAGS"[, @TYPE[,ARGUMENTS]]]'
+========================================================================
This is one of the ELF section stack manipulation directives. The
others are `.section' (*note Section::), `.subsection' (*note
This directive pushes the current section (and subsection) onto the
top of the section stack, and then replaces the current section and
-subsection with `name' and `subsection'.
+subsection with `name' and `subsection'. The optional `flags', `type'
+and `arguments' are treated the same as in the `.section' (*note
+Section::) directive.
\1f
File: as.info, Node: Quad, Next: Reloc, Prev: PushSection, Up: Pseudo Ops
-7.88 `.quad BIGNUMS'
+7.91 `.quad BIGNUMS'
====================
`.quad' expects zero or more bignums, separated by commas. For each
\1f
File: as.info, Node: Reloc, Next: Rept, Prev: Quad, Up: Pseudo Ops
-7.89 `.reloc OFFSET, RELOC_NAME[, EXPRESSION]'
+7.92 `.reloc OFFSET, RELOC_NAME[, EXPRESSION]'
==============================================
Generate a relocation at OFFSET of type RELOC_NAME with value
\1f
File: as.info, Node: Rept, Next: Sbttl, Prev: Reloc, Up: Pseudo Ops
-7.90 `.rept COUNT'
+7.93 `.rept COUNT'
==================
Repeat the sequence of lines between the `.rept' directive and the next
\1f
File: as.info, Node: Sbttl, Next: Scl, Prev: Rept, Up: Pseudo Ops
-7.91 `.sbttl "SUBHEADING"'
+7.94 `.sbttl "SUBHEADING"'
==========================
Use SUBHEADING as the title (third line, immediately after the title
\1f
File: as.info, Node: Scl, Next: Section, Prev: Sbttl, Up: Pseudo Ops
-7.92 `.scl CLASS'
+7.95 `.scl CLASS'
=================
Set the storage-class value for a symbol. This directive may only be
\1f
File: as.info, Node: Section, Next: Set, Prev: Scl, Up: Pseudo Ops
-7.93 `.section NAME'
+7.96 `.section NAME'
====================
Use the `.section' directive to assemble the following code into a
following ways:
.section NAME[, "FLAGS"]
- .section NAME[, SUBSEGMENT]
+ .section NAME[, SUBSECTION]
If the optional argument is quoted, it is taken as flags to use for
the section. Each flag is a single character. The following flags are
`a'
ignored. (For compatibility with the ELF version)
+`y'
+ section is not readable (meaningful for PE targets)
+
If no flags are specified, the default flags depend upon the section
name. If the section name is not recognized, the default will be for
the section to be loaded and writable. Note the `n' and `w' flags
all.
If the optional argument to the `.section' directive is not quoted,
-it is taken as a subsegment number (*note Sub-Sections::).
+it is taken as a subsection number (*note Sub-Sections::).
ELF Version
-----------
must contain zero terminated strings where each character is ENTSIZE
bytes long. The linker may remove duplicates within sections with the
same name, same entity size and same flags. ENTSIZE must be an
-absolute expression.
+absolute expression. For sections with both `M' and `S', a string
+which is a suffix of a larger string is considered a duplicate. Thus
+`"def"' will be merged with `"abcdef"'; A reference to the first
+`"def"' will be changed to a reference to `"abcdef"+3'.
If FLAGS contains the `G' symbol then the TYPE argument must be
present along with an additional field like this:
\1f
File: as.info, Node: Set, Next: Short, Prev: Section, Up: Pseudo Ops
-7.94 `.set SYMBOL, EXPRESSION'
+7.97 `.set SYMBOL, EXPRESSION'
==============================
Set the value of SYMBOL to EXPRESSION. This changes SYMBOL's value and
\1f
File: as.info, Node: Short, Next: Single, Prev: Set, Up: Pseudo Ops
-7.95 `.short EXPRESSIONS'
+7.98 `.short EXPRESSIONS'
=========================
`.short' is normally the same as `.word'. *Note `.word': Word.
\1f
File: as.info, Node: Single, Next: Size, Prev: Short, Up: Pseudo Ops
-7.96 `.single FLONUMS'
+7.99 `.single FLONUMS'
======================
This directive assembles zero or more flonums, separated by commas. It
\1f
File: as.info, Node: Size, Next: Skip, Prev: Single, Up: Pseudo Ops
-7.97 `.size'
-============
+7.100 `.size'
+=============
This directive is used to set the size associated with a symbol.
arithmetic. This directive is typically used to set the size of
function symbols.
-\1f
-File: as.info, Node: Sleb128, Next: Space, Prev: Skip, Up: Pseudo Ops
-
-7.98 `.sleb128 EXPRESSIONS'
-===========================
-
-SLEB128 stands for "signed little endian base 128." This is a compact,
-variable length representation of numbers used by the DWARF symbolic
-debugging format. *Note `.uleb128': Uleb128.
-
\1f
File: as.info, Node: Skip, Next: Sleb128, Prev: Size, Up: Pseudo Ops
-7.99 `.skip SIZE , FILL'
-========================
+7.101 `.skip SIZE , FILL'
+=========================
This directive emits SIZE bytes, each of value FILL. Both SIZE and
FILL are absolute expressions. If the comma and FILL are omitted, FILL
is assumed to be zero. This is the same as `.space'.
+\1f
+File: as.info, Node: Sleb128, Next: Space, Prev: Skip, Up: Pseudo Ops
+
+7.102 `.sleb128 EXPRESSIONS'
+============================
+
+SLEB128 stands for "signed little endian base 128." This is a compact,
+variable length representation of numbers used by the DWARF symbolic
+debugging format. *Note `.uleb128': Uleb128.
+
\1f
File: as.info, Node: Space, Next: Stab, Prev: Sleb128, Up: Pseudo Ops
-7.100 `.space SIZE , FILL'
+7.103 `.space SIZE , FILL'
==========================
This directive emits SIZE bytes, each of value FILL. Both SIZE and
\1f
File: as.info, Node: Stab, Next: String, Prev: Space, Up: Pseudo Ops
-7.101 `.stabd, .stabn, .stabs'
+7.104 `.stabd, .stabn, .stabs'
==============================
There are three directives that begin `.stab'. All emit symbols (*note
\1f
File: as.info, Node: String, Next: Struct, Prev: Stab, Up: Pseudo Ops
-7.102 `.string' "STR"
-=====================
+7.105 `.string' "STR", `.string8' "STR", `.string16'
+====================================================
+
+"STR", `.string32' "STR", `.string64' "STR"
-Copy the characters in STR to the object file. You may specify more
+ Copy the characters in STR to the object file. You may specify more
than one string to copy, separated by commas. Unless otherwise
specified for a particular machine, the assembler marks the end of each
string with a 0 byte. You can use any of the escape sequences
described in *Note Strings: Strings.
+ The variants `string16', `string32' and `string64' differ from the
+`string' pseudo opcode in that each 8-bit character from STR is copied
+and expanded to 16, 32 or 64 bits respectively. The expanded characters
+are stored in target endianness byte order.
+
+ Example:
+ .string32 "BYE"
+ expands to:
+ .string "B\0\0\0Y\0\0\0E\0\0\0" /* On little endian targets. */
+ .string "\0\0\0B\0\0\0Y\0\0\0E" /* On big endian targets. */
+
\1f
File: as.info, Node: Struct, Next: SubSection, Prev: String, Up: Pseudo Ops
-7.103 `.struct EXPRESSION'
+7.106 `.struct EXPRESSION'
==========================
Switch to the absolute section, and set the section offset to
\1f
File: as.info, Node: SubSection, Next: Symver, Prev: Struct, Up: Pseudo Ops
-7.104 `.subsection NAME'
+7.107 `.subsection NAME'
========================
This is one of the ELF section stack manipulation directives. The
\1f
File: as.info, Node: Symver, Next: Tag, Prev: SubSection, Up: Pseudo Ops
-7.105 `.symver'
+7.108 `.symver'
===============
Use the `.symver' directive to bind symbols to specific version nodes
\1f
File: as.info, Node: Tag, Next: Text, Prev: Symver, Up: Pseudo Ops
-7.106 `.tag STRUCTNAME'
+7.109 `.tag STRUCTNAME'
=======================
This directive is generated by compilers to include auxiliary debugging
\1f
File: as.info, Node: Text, Next: Title, Prev: Tag, Up: Pseudo Ops
-7.107 `.text SUBSECTION'
+7.110 `.text SUBSECTION'
========================
Tells `as' to assemble the following statements onto the end of the
\1f
File: as.info, Node: Title, Next: Type, Prev: Text, Up: Pseudo Ops
-7.108 `.title "HEADING"'
+7.111 `.title "HEADING"'
========================
Use HEADING as the title (second line, immediately after the source
\1f
File: as.info, Node: Type, Next: Uleb128, Prev: Title, Up: Pseudo Ops
-7.109 `.type'
+7.112 `.type'
=============
This directive is used to set the type of a symbol.
The syntaxes supported are:
- .type <name> STT_FUNCTION
- .type <name> STT_OBJECT
+ .type <name> STT_<TYPE_IN_UPPER_CASE>
+ .type <name>,#<type>
+ .type <name>,@<type>
+ .type <name>,%<type>
+ .type <name>,"<type>"
+
+ The types supported are:
+
+`STT_FUNC'
+`function'
+ Mark the symbol as being a function name.
+
+`STT_GNU_IFUNC'
+`gnu_indirect_function'
+ Mark the symbol as an indirect function when evaluated during reloc
+ processing. (This is only supported on Linux targeted assemblers).
+
+`STT_OBJECT'
+`object'
+ Mark the symbol as being a data object.
+
+`STT_TLS'
+`tls_object'
+ Mark the symbol as being a thead-local data object.
+
+`STT_COMMON'
+`common'
+ Mark the symbol as being a common data object.
- .type <name>,#function
- .type <name>,#object
+`STT_NOTYPE'
+`notype'
+ Does not mark the symbol in any way. It is supported just for
+ completeness.
- .type <name>,@function
- .type <name>,@object
+`gnu_unique_object'
+ Marks the symbol as being a globally unique data object. The
+ dynamic linker will make sure that in the entire process there is
+ just one symbol with this name and type in use. (This is only
+ supported on Linux targeted assemblers).
- .type <name>,%function
- .type <name>,%object
- .type <name>,"function"
- .type <name>,"object"
+ Note: Some targets support extra types in addition to those listed
+above.
\1f
File: as.info, Node: Uleb128, Next: Val, Prev: Type, Up: Pseudo Ops
-7.110 `.uleb128 EXPRESSIONS'
+7.113 `.uleb128 EXPRESSIONS'
============================
ULEB128 stands for "unsigned little endian base 128." This is a
\1f
File: as.info, Node: Val, Next: Version, Prev: Uleb128, Up: Pseudo Ops
-7.111 `.val ADDR'
+7.114 `.val ADDR'
=================
This directive, permitted only within `.def'/`.endef' pairs, records
\1f
File: as.info, Node: Version, Next: VTableEntry, Prev: Val, Up: Pseudo Ops
-7.112 `.version "STRING"'
+7.115 `.version "STRING"'
=========================
This directive creates a `.note' section and places into it an ELF
\1f
File: as.info, Node: VTableEntry, Next: VTableInherit, Prev: Version, Up: Pseudo Ops
-7.113 `.vtable_entry TABLE, OFFSET'
+7.116 `.vtable_entry TABLE, OFFSET'
===================================
This directive finds or creates a symbol `table' and creates a
\1f
File: as.info, Node: VTableInherit, Next: Warning, Prev: VTableEntry, Up: Pseudo Ops
-7.114 `.vtable_inherit CHILD, PARENT'
+7.117 `.vtable_inherit CHILD, PARENT'
=====================================
This directive finds the symbol `child' and finds or creates the symbol
\1f
File: as.info, Node: Warning, Next: Weak, Prev: VTableInherit, Up: Pseudo Ops
-7.115 `.warning "STRING"'
+7.118 `.warning "STRING"'
=========================
Similar to the directive `.error' (*note `.error "STRING"': Error.),
\1f
File: as.info, Node: Weak, Next: Weakref, Prev: Warning, Up: Pseudo Ops
-7.116 `.weak NAMES'
+7.119 `.weak NAMES'
===================
This directive sets the weak attribute on the comma separated list of
\1f
File: as.info, Node: Weakref, Next: Word, Prev: Weak, Up: Pseudo Ops
-7.117 `.weakref ALIAS, TARGET'
+7.120 `.weakref ALIAS, TARGET'
==============================
This directive creates an alias to the target symbol that enables the
\1f
File: as.info, Node: Word, Next: Deprecated, Prev: Weakref, Up: Pseudo Ops
-7.118 `.word EXPRESSIONS'
+7.121 `.word EXPRESSIONS'
=========================
This directive expects zero or more EXPRESSIONS, of any section,
\1f
File: as.info, Node: Deprecated, Prev: Word, Up: Pseudo Ops
-7.119 Deprecated Directives
+7.122 Deprecated Directives
===========================
One day these directives won't work. They are included for
.line
\1f
-File: as.info, Node: Machine Dependencies, Next: Reporting Bugs, Prev: Pseudo Ops, Up: Top
+File: as.info, Node: Object Attributes, Next: Machine Dependencies, Prev: Pseudo Ops, Up: Top
-8 Machine Dependent Features
+8 Object Attributes
+*******************
+
+`as' assembles source files written for a specific architecture into
+object files for that architecture. But not all object files are alike.
+Many architectures support incompatible variations. For instance,
+floating point arguments might be passed in floating point registers if
+the object file requires hardware floating point support--or floating
+point arguments might be passed in integer registers if the object file
+supports processors with no hardware floating point unit. Or, if two
+objects are built for different generations of the same architecture,
+the combination may require the newer generation at run-time.
+
+ This information is useful during and after linking. At link time,
+`ld' can warn about incompatible object files. After link time, tools
+like `gdb' can use it to process the linked file correctly.
+
+ Compatibility information is recorded as a series of object
+attributes. Each attribute has a "vendor", "tag", and "value". The
+vendor is a string, and indicates who sets the meaning of the tag. The
+tag is an integer, and indicates what property the attribute describes.
+The value may be a string or an integer, and indicates how the
+property affects this object. Missing attributes are the same as
+attributes with a zero value or empty string value.
+
+ Object attributes were developed as part of the ABI for the ARM
+Architecture. The file format is documented in `ELF for the ARM
+Architecture'.
+
+* Menu:
+
+* GNU Object Attributes:: GNU Object Attributes
+* Defining New Object Attributes:: Defining New Object Attributes
+
+\1f
+File: as.info, Node: GNU Object Attributes, Next: Defining New Object Attributes, Up: Object Attributes
+
+8.1 GNU Object Attributes
+=========================
+
+The `.gnu_attribute' directive records an object attribute with vendor
+`gnu'.
+
+ Except for `Tag_compatibility', which has both an integer and a
+string for its value, GNU attributes have a string value if the tag
+number is odd and an integer value if the tag number is even. The
+second bit (`TAG & 2' is set for architecture-independent attributes
+and clear for architecture-dependent ones.
+
+8.1.1 Common GNU attributes
+---------------------------
+
+These attributes are valid on all architectures.
+
+Tag_compatibility (32)
+ The compatibility attribute takes an integer flag value and a
+ vendor name. If the flag value is 0, the file is compatible with
+ other toolchains. If it is 1, then the file is only compatible
+ with the named toolchain. If it is greater than 1, the file can
+ only be processed by other toolchains under some private
+ arrangement indicated by the flag value and the vendor name.
+
+8.1.2 MIPS Attributes
+---------------------
+
+Tag_GNU_MIPS_ABI_FP (4)
+ The floating-point ABI used by this object file. The value will
+ be:
+
+ * 0 for files not affected by the floating-point ABI.
+
+ * 1 for files using the hardware floating-point with a standard
+ double-precision FPU.
+
+ * 2 for files using the hardware floating-point ABI with a
+ single-precision FPU.
+
+ * 3 for files using the software floating-point ABI.
+
+ * 4 for files using the hardware floating-point ABI with 64-bit
+ wide double-precision floating-point registers and 32-bit
+ wide general purpose registers.
+
+8.1.3 PowerPC Attributes
+------------------------
+
+Tag_GNU_Power_ABI_FP (4)
+ The floating-point ABI used by this object file. The value will
+ be:
+
+ * 0 for files not affected by the floating-point ABI.
+
+ * 1 for files using double-precision hardware floating-point
+ ABI.
+
+ * 2 for files using the software floating-point ABI.
+
+ * 3 for files using single-precision hardware floating-point
+ ABI.
+
+Tag_GNU_Power_ABI_Vector (8)
+ The vector ABI used by this object file. The value will be:
+
+ * 0 for files not affected by the vector ABI.
+
+ * 1 for files using general purpose registers to pass vectors.
+
+ * 2 for files using AltiVec registers to pass vectors.
+
+ * 3 for files using SPE registers to pass vectors.
+
+\1f
+File: as.info, Node: Defining New Object Attributes, Prev: GNU Object Attributes, Up: Object Attributes
+
+8.2 Defining New Object Attributes
+==================================
+
+If you want to define a new GNU object attribute, here are the places
+you will need to modify. New attributes should be discussed on the
+`binutils' mailing list.
+
+ * This manual, which is the official register of attributes.
+
+ * The header for your architecture `include/elf', to define the tag.
+
+ * The `bfd' support file for your architecture, to merge the
+ attribute and issue any appropriate link warnings.
+
+ * Test cases in `ld/testsuite' for merging and link warnings.
+
+ * `binutils/readelf.c' to display your attribute.
+
+ * GCC, if you want the compiler to mark the attribute automatically.
+
+\1f
+File: as.info, Node: Machine Dependencies, Next: Reporting Bugs, Prev: Object Attributes, Up: Top
+
+9 Machine Dependent Features
****************************
The machine instruction sets are (almost by definition) different on
* AVR-Dependent:: AVR Dependent Features
-* BFIN-Dependent:: BFIN Dependent Features
+* Blackfin-Dependent:: Blackfin Dependent Features
* CR16-Dependent:: CR16 Dependent Features
* IP2K-Dependent:: IP2K Dependent Features
+* LM32-Dependent:: LM32 Dependent Features
+
* M32C-Dependent:: M32C Dependent Features
* M32R-Dependent:: M32R Dependent Features
* M68HC11-Dependent:: M68HC11 and 68HC12 Dependent Features
+* MicroBlaze-Dependent:: MICROBLAZE Dependent Features
+
* MIPS-Dependent:: MIPS Dependent Features
* MMIX-Dependent:: MMIX Dependent Features
* PPC-Dependent:: PowerPC Dependent Features
+* S/390-Dependent:: IBM S/390 Dependent Features
+
+* SCORE-Dependent:: SCORE Dependent Features
+
* Sparc-Dependent:: SPARC Dependent Features
* TIC54X-Dependent:: TI TMS320C54x Dependent Features
\1f
File: as.info, Node: Alpha-Dependent, Next: ARC-Dependent, Up: Machine Dependencies
-8.1 Alpha Dependent Features
+9.1 Alpha Dependent Features
============================
* Menu:
\1f
File: as.info, Node: Alpha Notes, Next: Alpha Options, Up: Alpha-Dependent
-8.1.1 Notes
+9.1.1 Notes
-----------
The documentation here is primarily for the ELF object format. `as'
\1f
File: as.info, Node: Alpha Options, Next: Alpha Syntax, Prev: Alpha Notes, Up: Alpha-Dependent
-8.1.2 Options
+9.1.2 Options
-------------
`-mCPU'
can be represented. However, the option can still be useful in
specific applications.
+`-replace'
+
+`-noreplace'
+ Enables or disables the optimization of procedure calls, both at
+ assemblage and at link time. These options are only available for
+ VMS targets and `-replace' is the default. See section 1.4.1 of
+ the OpenVMS Linker Utility Manual.
+
`-g'
This option is used when the compiler generates debug information.
When `gcc' is using `mips-tfile' to generate debug information
\1f
File: as.info, Node: Alpha Syntax, Next: Alpha Floating Point, Prev: Alpha Options, Up: Alpha-Dependent
-8.1.3 Syntax
+9.1.3 Syntax
------------
The assembler syntax closely follow the Alpha Reference Manual;
\1f
File: as.info, Node: Alpha-Chars, Next: Alpha-Regs, Up: Alpha Syntax
-8.1.3.1 Special Characters
+9.1.3.1 Special Characters
..........................
`#' is the line comment character.
\1f
File: as.info, Node: Alpha-Regs, Next: Alpha-Relocs, Prev: Alpha-Chars, Up: Alpha Syntax
-8.1.3.2 Register Names
+9.1.3.2 Register Names
......................
The 32 integer registers are referred to as `$N' or `$rN'. In
\1f
File: as.info, Node: Alpha-Relocs, Prev: Alpha-Regs, Up: Alpha Syntax
-8.1.3.3 Relocations
+9.1.3.3 Relocations
...................
Some of these relocations are available for ECOFF, but mostly only for
\1f
File: as.info, Node: Alpha Floating Point, Next: Alpha Directives, Prev: Alpha Syntax, Up: Alpha-Dependent
-8.1.4 Floating Point
+9.1.4 Floating Point
--------------------
The Alpha family uses both IEEE and VAX floating-point numbers.
\1f
File: as.info, Node: Alpha Directives, Next: Alpha Opcodes, Prev: Alpha Floating Point, Up: Alpha-Dependent
-8.1.5 Alpha Assembler Directives
+9.1.5 Alpha Assembler Directives
--------------------------------
`as' for the Alpha supports many additional directives for
\1f
File: as.info, Node: Alpha Opcodes, Prev: Alpha Directives, Up: Alpha-Dependent
-8.1.6 Opcodes
+9.1.6 Opcodes
-------------
For detailed information on the Alpha machine instruction set, see the
\1f
File: as.info, Node: ARC-Dependent, Next: ARM-Dependent, Prev: Alpha-Dependent, Up: Machine Dependencies
-8.2 ARC Dependent Features
+9.2 ARC Dependent Features
==========================
* Menu:
\1f
File: as.info, Node: ARC Options, Next: ARC Syntax, Up: ARC-Dependent
-8.2.1 Options
+9.2.1 Options
-------------
`-marc[5|6|7|8]'
\1f
File: as.info, Node: ARC Syntax, Next: ARC Floating Point, Prev: ARC Options, Up: ARC-Dependent
-8.2.2 Syntax
+9.2.2 Syntax
------------
* Menu:
\1f
File: as.info, Node: ARC-Chars, Next: ARC-Regs, Up: ARC Syntax
-8.2.2.1 Special Characters
+9.2.2.1 Special Characters
..........................
*TODO*
\1f
File: as.info, Node: ARC-Regs, Prev: ARC-Chars, Up: ARC Syntax
-8.2.2.2 Register Names
+9.2.2.2 Register Names
......................
*TODO*
\1f
File: as.info, Node: ARC Floating Point, Next: ARC Directives, Prev: ARC Syntax, Up: ARC-Dependent
-8.2.3 Floating Point
+9.2.3 Floating Point
--------------------
The ARC core does not currently have hardware floating point support.
\1f
File: as.info, Node: ARC Directives, Next: ARC Opcodes, Prev: ARC Floating Point, Up: ARC-Dependent
-8.2.4 ARC Machine Directives
+9.2.4 ARC Machine Directives
----------------------------
The ARC version of `as' supports the following additional machine
indicates the absence or presence of conditional suffixes and
flag setting by the extension instruction. It is also
possible to specify that an instruction sets the flags and is
- condtional by using `SUFFIX_CODE' | `SUFFIX_FLAG'.
+ conditional by using `SUFFIX_CODE' | `SUFFIX_FLAG'.
*SYNTAXCLASS
Determines the syntax class for the instruction. It can have
\1f
File: as.info, Node: ARC Opcodes, Prev: ARC Directives, Up: ARC-Dependent
-8.2.5 Opcodes
+9.2.5 Opcodes
-------------
For information on the ARC instruction set, see `ARC Programmers
\1f
File: as.info, Node: ARM-Dependent, Next: AVR-Dependent, Prev: ARC-Dependent, Up: Machine Dependencies
-8.3 ARM Dependent Features
+9.3 ARM Dependent Features
==========================
* Menu:
* ARM Directives:: ARM Machine Directives
* ARM Opcodes:: Opcodes
* ARM Mapping Symbols:: Mapping Symbols
+* ARM Unwinding Tutorial:: Unwinding
\1f
File: as.info, Node: ARM Options, Next: ARM Syntax, Up: ARM-Dependent
-8.3.1 Options
+9.3.1 Options
-------------
`-mcpu=PROCESSOR[+EXTENSION...]'
`arm710c', `arm7100', `arm7500', `arm7500fe', `arm7t', `arm7tdmi',
`arm7tdmi-s', `arm8', `arm810', `strongarm', `strongarm1',
`strongarm110', `strongarm1100', `strongarm1110', `arm9', `arm920',
- `arm920t', `arm922t', `arm940t', `arm9tdmi', `arm9e', `arm926e',
- `arm926ej-s', `arm946e-r0', `arm946e', `arm946e-s', `arm966e-r0',
- `arm966e', `arm966e-s', `arm968e-s', `arm10t', `arm10tdmi',
- `arm10e', `arm1020', `arm1020t', `arm1020e', `arm1022e',
- `arm1026ej-s', `arm1136j-s', `arm1136jf-s', `arm1156t2-s',
- `arm1156t2f-s', `arm1176jz-s', `arm1176jzf-s', `mpcore',
- `mpcorenovfp', `cortex-a8', `cortex-r4', `cortex-m3', `ep9312'
- (ARM920 with Cirrus Maverick coprocessor), `i80200' (Intel XScale
- processor) `iwmmxt' (Intel(r) XScale processor with Wireless
- MMX(tm) technology coprocessor) and `xscale'. The special name
- `all' may be used to allow the assembler to accept instructions
- valid for any ARM processor.
+ `arm920t', `arm922t', `arm940t', `arm9tdmi', `fa526' (Faraday
+ FA526 processor), `fa626' (Faraday FA626 processor), `arm9e',
+ `arm926e', `arm926ej-s', `arm946e-r0', `arm946e', `arm946e-s',
+ `arm966e-r0', `arm966e', `arm966e-s', `arm968e-s', `arm10t',
+ `arm10tdmi', `arm10e', `arm1020', `arm1020t', `arm1020e',
+ `arm1022e', `arm1026ej-s', `fa626te' (Faraday FA626TE processor),
+ `fa726te' (Faraday FA726TE processor), `arm1136j-s', `arm1136jf-s',
+ `arm1156t2-s', `arm1156t2f-s', `arm1176jz-s', `arm1176jzf-s',
+ `mpcore', `mpcorenovfp', `cortex-a8', `cortex-a9', `cortex-r4',
+ `cortex-m3', `cortex-m1', `cortex-m0', `ep9312' (ARM920 with
+ Cirrus Maverick coprocessor), `i80200' (Intel XScale processor)
+ `iwmmxt' (Intel(r) XScale processor with Wireless MMX(tm)
+ technology coprocessor) and `xscale'. The special name `all' may
+ be used to allow the assembler to accept instructions valid for
+ any ARM processor.
In addition to the basic instruction set, the assembler can be
told to accept various extension mnemonics that extend the
floating point unit. The following format options are recognized:
`softfpa', `fpe', `fpe2', `fpe3', `fpa', `fpa10', `fpa11',
`arm7500fe', `softvfp', `softvfp+vfp', `vfp', `vfp10', `vfp10-r0',
- `vfp9', `vfpxd', `arm1020t', `arm1020e', `arm1136jf-s' and
- `maverick'.
+ `vfp9', `vfpxd', `vfpv2' `vfpv3' `vfpv3-d16' `arm1020t',
+ `arm1020e', `arm1136jf-s', `maverick' and `neon'.
In addition to determining which instructions are assembled, this
option also affects the way in which the `.double' assembler
This option specifies that the output generated by the assembler
should be marked as supporting interworking.
+`-mimplicit-it=never'
+`-mimplicit-it=always'
+`-mimplicit-it=arm'
+`-mimplicit-it=thumb'
+ The `-mimplicit-it' option controls the behavior of the assembler
+ when conditional instructions are not enclosed in IT blocks.
+ There are four possible behaviors. If `never' is specified, such
+ constructs cause a warning in ARM code and an error in Thumb-2
+ code. If `always' is specified, such constructs are accepted in
+ both ARM and Thumb-2 code, where the IT instruction is added
+ implicitly. If `arm' is specified, such constructs are accepted
+ in ARM code and cause an error in Thumb-2 code. If `thumb' is
+ specified, such constructs cause a warning in ARM code and are
+ accepted in Thumb-2 code. If you omit this option, the behavior
+ is equivalent to `-mimplicit-it=arm'.
+
`-mapcs `[26|32]''
This option specifies that the output generated by the assembler
should be marked as supporting the indicated version of the Arm
This option specifies that the output of the assembler should be
marked as position-independent code (PIC).
+`--fix-v4bx'
+ Allow `BX' instructions in ARMv4 code. This is intended for use
+ with the linker option of the same name.
+
+`-mwarn-deprecated'
+`-mno-warn-deprecated'
+ Enable or disable warnings about using deprecated options or
+ features. The default is to warn.
+
\1f
File: as.info, Node: ARM Syntax, Next: ARM Floating Point, Prev: ARM Options, Up: ARM-Dependent
-8.3.2 Syntax
+9.3.2 Syntax
------------
* Menu:
+* ARM-Instruction-Set:: Instruction Set
* ARM-Chars:: Special Characters
* ARM-Regs:: Register Names
* ARM-Relocations:: Relocations
\1f
-File: as.info, Node: ARM-Chars, Next: ARM-Regs, Up: ARM Syntax
+File: as.info, Node: ARM-Instruction-Set, Next: ARM-Chars, Up: ARM Syntax
+
+9.3.2.1 Instruction Set Syntax
+..............................
+
+Two slightly different syntaxes are support for ARM and THUMB
+instructions. The default, `divided', uses the old style where ARM and
+THUMB instructions had their own, separate syntaxes. The new,
+`unified' syntax, which can be selected via the `.syntax' directive,
+and has the following main features:
+
+*
+ Immediate operands do not require a `#' prefix.
+
+*
+ The `IT' instruction may appear, and if it does it is validated
+ against subsequent conditional affixes. In ARM mode it does not
+ generate machine code, in THUMB mode it does.
+
+*
+ For ARM instructions the conditional affixes always appear at the
+ end of the instruction. For THUMB instructions conditional
+ affixes can be used, but only inside the scope of an `IT'
+ instruction.
+
+*
+ All of the instructions new to the V6T2 architecture (and later)
+ are available. (Only a few such instructions can be written in the
+ `divided' syntax).
+
+*
+ The `.N' and `.W' suffixes are recognized and honored.
+
+*
+ All instructions set the flags if and only if they have an `s'
+ affix.
+
+\1f
+File: as.info, Node: ARM-Chars, Next: ARM-Regs, Prev: ARM-Instruction-Set, Up: ARM Syntax
-8.3.2.1 Special Characters
+9.3.2.2 Special Characters
..........................
The presence of a `@' on a line indicates the start of a comment that
\1f
File: as.info, Node: ARM-Regs, Next: ARM-Relocations, Prev: ARM-Chars, Up: ARM Syntax
-8.3.2.2 Register Names
+9.3.2.3 Register Names
......................
*TODO* Explain about ARM register naming, and the predefined names.
\1f
File: as.info, Node: ARM Floating Point, Next: ARM Directives, Prev: ARM Syntax, Up: ARM-Dependent
-8.3.3 Floating Point
+9.3.3 Floating Point
--------------------
The ARM family uses IEEE floating-point numbers.
\1f
File: as.info, Node: ARM-Relocations, Prev: ARM-Regs, Up: ARM Syntax
-8.3.3.1 ARM relocation generation
+9.3.3.1 ARM relocation generation
.................................
Specific data relocations can be generated by putting the relocation
\1f
File: as.info, Node: ARM Directives, Next: ARM Opcodes, Prev: ARM Floating Point, Up: ARM-Dependent
-8.3.4 ARM Machine Directives
+9.3.4 ARM Machine Directives
----------------------------
+`.2byte EXPRESSION [, EXPRESSION]*'
+`.4byte EXPRESSION [, EXPRESSION]*'
+`.8byte EXPRESSION [, EXPRESSION]*'
+ These directives write 2, 4 or 8 byte values to the output section.
+
`.align EXPRESSION [, EXPRESSION]'
This is the generic .ALIGN directive. For the ARM however if the
first argument is zero (ie no alignment is needed) the assembler
byte boundary). This is for compatibility with ARM's own
assembler.
-`NAME .req REGISTER NAME'
- This creates an alias for REGISTER NAME called NAME. For example:
+`.arch NAME'
+ Select the target architecture. Valid values for NAME are the
+ same as for the `-march' commandline option.
- foo .req r0
+`.arm'
+ This performs the same action as .CODE 32.
-`.unreq ALIAS-NAME'
- This undefines a register alias which was previously defined using
- the `req', `dn' or `qn' directives. For example:
+`.pad #COUNT'
+ Generate unwinder annotations for a stack adjustment of COUNT
+ bytes. A positive value indicates the function prologue allocated
+ stack space by decrementing the stack pointer.
- foo .req r0
- .unreq foo
+`.bss'
+ This directive switches to the `.bss' section.
- An error occurs if the name is undefined. Note - this pseudo op
- can be used to delete builtin in register name aliases (eg 'r0').
- This should only be done if it is really necessary.
+`.cantunwind'
+ Prevents unwinding through the current function. No personality
+ routine or exception table data is required or permitted.
+
+`.code `[16|32]''
+ This directive selects the instruction set being generated. The
+ value 16 selects Thumb, with the value 32 selecting ARM.
+
+`.cpu NAME'
+ Select the target processor. Valid values for NAME are the same as
+ for the `-mcpu' commandline option.
`NAME .dn REGISTER NAME [.TYPE] [[INDEX]]'
Aliases created using `dn' or `qn' can be destroyed using `unreq'.
-`.code `[16|32]''
- This directive selects the instruction set being generated. The
- value 16 selects Thumb, with the value 32 selecting ARM.
+`.eabi_attribute TAG, VALUE'
+ Set the EABI object attribute TAG to VALUE.
+
+ The TAG is either an attribute number, or one of the following:
+ `Tag_CPU_raw_name', `Tag_CPU_name', `Tag_CPU_arch',
+ `Tag_CPU_arch_profile', `Tag_ARM_ISA_use', `Tag_THUMB_ISA_use',
+ `Tag_VFP_arch', `Tag_WMMX_arch', `Tag_Advanced_SIMD_arch',
+ `Tag_PCS_config', `Tag_ABI_PCS_R9_use', `Tag_ABI_PCS_RW_data',
+ `Tag_ABI_PCS_RO_data', `Tag_ABI_PCS_GOT_use',
+ `Tag_ABI_PCS_wchar_t', `Tag_ABI_FP_rounding',
+ `Tag_ABI_FP_denormal', `Tag_ABI_FP_exceptions',
+ `Tag_ABI_FP_user_exceptions', `Tag_ABI_FP_number_model',
+ `Tag_ABI_align8_needed', `Tag_ABI_align8_preserved',
+ `Tag_ABI_enum_size', `Tag_ABI_HardFP_use', `Tag_ABI_VFP_args',
+ `Tag_ABI_WMMX_args', `Tag_ABI_optimization_goals',
+ `Tag_ABI_FP_optimization_goals', `Tag_compatibility',
+ `Tag_CPU_unaligned_access', `Tag_VFP_HP_extension',
+ `Tag_ABI_FP_16bit_format', `Tag_nodefaults',
+ `Tag_also_compatible_with', `Tag_conformance', `Tag_T2EE_use',
+ `Tag_Virtualization_use', `Tag_MPextension_use'
+
+ The VALUE is either a `number', `"string"', or `number, "string"'
+ depending on the tag.
-`.thumb'
- This performs the same action as .CODE 16.
+`.even'
+ This directive aligns to an even-numbered address.
-`.arm'
- This performs the same action as .CODE 32.
+`.extend EXPRESSION [, EXPRESSION]*'
+`.ldouble EXPRESSION [, EXPRESSION]*'
+ These directives write 12byte long double floating-point values to
+ the output section. These are not compatible with current ARM
+ processors or ABIs.
+
+`.fnend'
+ Marks the end of a function with an unwind table entry. The
+ unwind index table entry is created when this directive is
+ processed.
+
+ If no personality routine has been specified then standard
+ personality routine 0 or 1 will be used, depending on the number
+ of unwind opcodes required.
+
+`.fnstart'
+ Marks the start of a function with an unwind table entry.
`.force_thumb'
This directive forces the selection of Thumb instructions, even if
the target processor does not support those instructions
-`.thumb_func'
- This directive specifies that the following symbol is the name of a
- Thumb encoded function. This information is necessary in order to
- allow the assembler and linker to generate correct code for
- interworking between Arm and Thumb instructions and should be used
- even if interworking is not going to be performed. The presence
- of this directive also implies `.thumb'
+`.fpu NAME'
+ Select the floating-point unit to assemble for. Valid values for
+ NAME are the same as for the `-mfpu' commandline option.
- This directive is not neccessary when generating EABI objects. On
- these targets the encoding is implicit when generating Thumb code.
+`.handlerdata'
+ Marks the end of the current function, and the start of the
+ exception table entry for that function. Anything between this
+ directive and the `.fnend' directive will be added to the
+ exception table entry.
-`.thumb_set'
- This performs the equivalent of a `.set' directive in that it
- creates a symbol which is an alias for another symbol (possibly
- not yet defined). This directive also has the added property in
- that it marks the aliased symbol as being a thumb function entry
- point, in the same way that the `.thumb_func' directive does.
+ Must be preceded by a `.personality' or `.personalityindex'
+ directive.
+
+`.inst OPCODE [ , ... ]'
+
+`.inst.n OPCODE [ , ... ]'
+
+`.inst.w OPCODE [ , ... ]'
+ Generates the instruction corresponding to the numerical value
+ OPCODE. `.inst.n' and `.inst.w' allow the Thumb instruction size
+ to be specified explicitly, overriding the normal encoding rules.
+
+`.ldouble EXPRESSION [, EXPRESSION]*'
+ See `.extend'.
`.ltorg'
This directive causes the current contents of the literal pool to
any time a section change occurred. This is no longer done, since
it prevents accurate control of the placement of literal pools.
-`.pool'
- This is a synonym for .ltorg.
-
-`.unwind_fnstart'
- Marks the start of a function with an unwind table entry.
+`.movsp REG [, #OFFSET]'
+ Tell the unwinder that REG contains an offset from the current
+ stack pointer. If OFFSET is not specified then it is assumed to be
+ zero.
-`.unwind_fnend'
- Marks the end of a function with an unwind table entry. The
- unwind index table entry is created when this directive is
- processed.
+`.object_arch NAME'
+ Override the architecture recorded in the EABI object attribute
+ section. Valid values for NAME are the same as for the `.arch'
+ directive. Typically this is useful when code uses runtime
+ detection of CPU features.
- If no personality routine has been specified then standard
- personality routine 0 or 1 will be used, depending on the number
- of unwind opcodes required.
+`.packed EXPRESSION [, EXPRESSION]*'
+ This directive writes 12-byte packed floating-point values to the
+ output section. These are not compatible with current ARM
+ processors or ABIs.
-`.cantunwind'
- Prevents unwinding through the current function. No personality
- routine or exception table data is required or permitted.
+`.pad #COUNT'
+ Generate unwinder annotations for a stack adjustment of COUNT
+ bytes. A positive value indicates the function prologue allocated
+ stack space by decrementing the stack pointer.
`.personality NAME'
Sets the personality routine for the current function to NAME.
Sets the personality routine for the current function to the EABI
standard routine number INDEX
-`.handlerdata'
- Marks the end of the current function, and the start of the
- exception table entry for that function. Anything between this
- directive and the `.fnend' directive will be added to the
- exception table entry.
+`.pool'
+ This is a synonym for .ltorg.
- Must be preceded by a `.personality' or `.personalityindex'
- directive.
+`NAME .req REGISTER NAME'
+ This creates an alias for REGISTER NAME called NAME. For example:
+
+ foo .req r0
`.save REGLIST'
Generate unwinder annotations to restore the registers in REGLIST.
.save wr10
wstrd wr10, [sp, #-8]!
-`.vsave VFP-REGLIST'
- Generate unwinder annotations to restore the VFP registers in
- VFP-REGLIST using FLDMD. Also works for VFPv3 registers that are
- to be restored using VLDM. The format of VFP-REGLIST is the same
- as the corresponding store-multiple instruction.
-
- _VFP registers_
- .vsave {d8, d9, d10}
- fstmdd sp!, {d8, d9, d10}
- _VFPv3 registers_
- .vsave {d15, d16, d17}
- vstm sp!, {d15, d16, d17}
-
- Since FLDMX and FSTMX are now deprecated, this directive should be
- used in favour of `.save' for saving VFP registers for ARMv6 and
- above.
-
-`.pad #COUNT'
- Generate unwinder annotations for a stack adjustment of COUNT
- bytes. A positive value indicates the function prologue allocated
- stack space by decrementing the stack pointer.
-
-`.movsp REG [, #OFFSET]'
- Tell the unwinder that REG contains an offset from the current
- stack pointer. If OFFSET is not specified then it is assumed to be
- zero.
-
`.setfp FPREG, SPREG [, #OFFSET]'
- Make all unwinder annotations relaive to a frame pointer. Without
- this the unwinder will use offsets from the stack pointer.
+ Make all unwinder annotations relative to a frame pointer.
+ Without this the unwinder will use offsets from the stack pointer.
The syntax of this directive is the same as the `sub' or `mov'
instruction used to set the frame pointer. SPREG must be either
.setfp fp, ip, #4
sub fp, ip, #4
-`.raw OFFSET, BYTE1, ...'
+`.secrel32 EXPRESSION [, EXPRESSION]*'
+ This directive emits relocations that evaluate to the
+ section-relative offset of each expression's symbol. This
+ directive is only supported for PE targets.
+
+`.syntax [`unified' | `divided']'
+ This directive sets the Instruction Set Syntax as described in the
+ *Note ARM-Instruction-Set:: section.
+
+`.thumb'
+ This performs the same action as .CODE 16.
+
+`.thumb_func'
+ This directive specifies that the following symbol is the name of a
+ Thumb encoded function. This information is necessary in order to
+ allow the assembler and linker to generate correct code for
+ interworking between Arm and Thumb instructions and should be used
+ even if interworking is not going to be performed. The presence
+ of this directive also implies `.thumb'
+
+ This directive is not neccessary when generating EABI objects. On
+ these targets the encoding is implicit when generating Thumb code.
+
+`.thumb_set'
+ This performs the equivalent of a `.set' directive in that it
+ creates a symbol which is an alias for another symbol (possibly
+ not yet defined). This directive also has the added property in
+ that it marks the aliased symbol as being a thumb function entry
+ point, in the same way that the `.thumb_func' directive does.
+
+`.unreq ALIAS-NAME'
+ This undefines a register alias which was previously defined using
+ the `req', `dn' or `qn' directives. For example:
+
+ foo .req r0
+ .unreq foo
+
+ An error occurs if the name is undefined. Note - this pseudo op
+ can be used to delete builtin in register name aliases (eg 'r0').
+ This should only be done if it is really necessary.
+
+`.unwind_raw OFFSET, BYTE1, ...'
Insert one of more arbitary unwind opcode bytes, which are known
to adjust the stack pointer by OFFSET bytes.
For example `.unwind_raw 4, 0xb1, 0x01' is equivalent to `.save
{r0}'
-`.cpu NAME'
- Select the target processor. Valid values for NAME are the same as
- for the `-mcpu' commandline option.
-
-`.arch NAME'
- Select the target architecture. Valid values for NAME are the
- same as for the `-march' commandline option.
-
-`.object_arch NAME'
- Override the architecture recorded in the EABI object attribute
- section. Valid values for NAME are the same as for the `.arch'
- directive. Typically this is useful when code uses runtime
- detection of CPU features.
+`.vsave VFP-REGLIST'
+ Generate unwinder annotations to restore the VFP registers in
+ VFP-REGLIST using FLDMD. Also works for VFPv3 registers that are
+ to be restored using VLDM. The format of VFP-REGLIST is the same
+ as the corresponding store-multiple instruction.
-`.fpu NAME'
- Select the floating point unit to assemble for. Valid values for
- NAME are the same as for the `-mfpu' commandline option.
+ _VFP registers_
+ .vsave {d8, d9, d10}
+ fstmdd sp!, {d8, d9, d10}
+ _VFPv3 registers_
+ .vsave {d15, d16, d17}
+ vstm sp!, {d15, d16, d17}
-`.eabi_attribute TAG, VALUE'
- Set the EABI object attribute number TAG to VALUE. The value is
- either a `number', `"string"', or `number, "string"' depending on
- the tag.
+ Since FLDMX and FSTMX are now deprecated, this directive should be
+ used in favour of `.save' for saving VFP registers for ARMv6 and
+ above.
\1f
File: as.info, Node: ARM Opcodes, Next: ARM Mapping Symbols, Prev: ARM Directives, Up: ARM-Dependent
-8.3.5 Opcodes
+9.3.5 Opcodes
-------------
`as' implements all the standard ARM opcodes. It also implements
Ltd.
\1f
-File: as.info, Node: ARM Mapping Symbols, Prev: ARM Opcodes, Up: ARM-Dependent
+File: as.info, Node: ARM Mapping Symbols, Next: ARM Unwinding Tutorial, Prev: ARM Opcodes, Up: ARM-Dependent
-8.3.6 Mapping Symbols
+9.3.6 Mapping Symbols
---------------------
The ARM ELF specification requires that special symbols be inserted
new EABI and so tools cannot rely upon their presence.
\1f
-File: as.info, Node: AVR-Dependent, Next: BFIN-Dependent, Prev: ARM-Dependent, Up: Machine Dependencies
+File: as.info, Node: ARM Unwinding Tutorial, Prev: ARM Mapping Symbols, Up: ARM-Dependent
-8.4 AVR Dependent Features
+9.3.7 Unwinding
+---------------
+
+The ABI for the ARM Architecture specifies a standard format for
+exception unwind information. This information is used when an
+exception is thrown to determine where control should be transferred.
+In particular, the unwind information is used to determine which
+function called the function that threw the exception, and which
+function called that one, and so forth. This information is also used
+to restore the values of callee-saved registers in the function
+catching the exception.
+
+ If you are writing functions in assembly code, and those functions
+call other functions that throw exceptions, you must use assembly
+pseudo ops to ensure that appropriate exception unwind information is
+generated. Otherwise, if one of the functions called by your assembly
+code throws an exception, the run-time library will be unable to unwind
+the stack through your assembly code and your program will not behave
+correctly.
+
+ To illustrate the use of these pseudo ops, we will examine the code
+that G++ generates for the following C++ input:
+
+
+void callee (int *);
+
+int
+caller ()
+{
+ int i;
+ callee (&i);
+ return i;
+}
+
+ This example does not show how to throw or catch an exception from
+assembly code. That is a much more complex operation and should always
+be done in a high-level language, such as C++, that directly supports
+exceptions.
+
+ The code generated by one particular version of G++ when compiling
+the example above is:
+
+
+_Z6callerv:
+ .fnstart
+.LFB2:
+ @ Function supports interworking.
+ @ args = 0, pretend = 0, frame = 8
+ @ frame_needed = 1, uses_anonymous_args = 0
+ stmfd sp!, {fp, lr}
+ .save {fp, lr}
+.LCFI0:
+ .setfp fp, sp, #4
+ add fp, sp, #4
+.LCFI1:
+ .pad #8
+ sub sp, sp, #8
+.LCFI2:
+ sub r3, fp, #8
+ mov r0, r3
+ bl _Z6calleePi
+ ldr r3, [fp, #-8]
+ mov r0, r3
+ sub sp, fp, #4
+ ldmfd sp!, {fp, lr}
+ bx lr
+.LFE2:
+ .fnend
+
+ Of course, the sequence of instructions varies based on the options
+you pass to GCC and on the version of GCC in use. The exact
+instructions are not important since we are focusing on the pseudo ops
+that are used to generate unwind information.
+
+ An important assumption made by the unwinder is that the stack frame
+does not change during the body of the function. In particular, since
+we assume that the assembly code does not itself throw an exception,
+the only point where an exception can be thrown is from a call, such as
+the `bl' instruction above. At each call site, the same saved
+registers (including `lr', which indicates the return address) must be
+located in the same locations relative to the frame pointer.
+
+ The `.fnstart' (*note .fnstart pseudo op: arm_fnstart.) pseudo op
+appears immediately before the first instruction of the function while
+the `.fnend' (*note .fnend pseudo op: arm_fnend.) pseudo op appears
+immediately after the last instruction of the function. These pseudo
+ops specify the range of the function.
+
+ Only the order of the other pseudos ops (e.g., `.setfp' or `.pad')
+matters; their exact locations are irrelevant. In the example above,
+the compiler emits the pseudo ops with particular instructions. That
+makes it easier to understand the code, but it is not required for
+correctness. It would work just as well to emit all of the pseudo ops
+other than `.fnend' in the same order, but immediately after `.fnstart'.
+
+ The `.save' (*note .save pseudo op: arm_save.) pseudo op indicates
+registers that have been saved to the stack so that they can be
+restored before the function returns. The argument to the `.save'
+pseudo op is a list of registers to save. If a register is
+"callee-saved" (as specified by the ABI) and is modified by the
+function you are writing, then your code must save the value before it
+is modified and restore the original value before the function returns.
+If an exception is thrown, the run-time library restores the values of
+these registers from their locations on the stack before returning
+control to the exception handler. (Of course, if an exception is not
+thrown, the function that contains the `.save' pseudo op restores these
+registers in the function epilogue, as is done with the `ldmfd'
+instruction above.)
+
+ You do not have to save callee-saved registers at the very beginning
+of the function and you do not need to use the `.save' pseudo op
+immediately following the point at which the registers are saved.
+However, if you modify a callee-saved register, you must save it on the
+stack before modifying it and before calling any functions which might
+throw an exception. And, you must use the `.save' pseudo op to
+indicate that you have done so.
+
+ The `.pad' (*note .pad: arm_pad.) pseudo op indicates a modification
+of the stack pointer that does not save any registers. The argument is
+the number of bytes (in decimal) that are subtracted from the stack
+pointer. (On ARM CPUs, the stack grows downwards, so subtracting from
+the stack pointer increases the size of the stack.)
+
+ The `.setfp' (*note .setfp pseudo op: arm_setfp.) pseudo op
+indicates the register that contains the frame pointer. The first
+argument is the register that is set, which is typically `fp'. The
+second argument indicates the register from which the frame pointer
+takes its value. The third argument, if present, is the value (in
+decimal) added to the register specified by the second argument to
+compute the value of the frame pointer. You should not modify the
+frame pointer in the body of the function.
+
+ If you do not use a frame pointer, then you should not use the
+`.setfp' pseudo op. If you do not use a frame pointer, then you should
+avoid modifying the stack pointer outside of the function prologue.
+Otherwise, the run-time library will be unable to find saved registers
+when it is unwinding the stack.
+
+ The pseudo ops described above are sufficient for writing assembly
+code that calls functions which may throw exceptions. If you need to
+know more about the object-file format used to represent unwind
+information, you may consult the `Exception Handling ABI for the ARM
+Architecture' available from `http://infocenter.arm.com'.
+
+\1f
+File: as.info, Node: AVR-Dependent, Next: Blackfin-Dependent, Prev: ARM-Dependent, Up: Machine Dependencies
+
+9.4 AVR Dependent Features
==========================
* Menu:
\1f
File: as.info, Node: AVR Options, Next: AVR Syntax, Up: AVR-Dependent
-8.4.1 Options
+9.4.1 Options
-------------
`-mmcu=MCU'
Instruction set avr1 is for the minimal AVR core, not supported by
the C compiler, only for assembler programs (MCU types: at90s1200,
- attiny10, attiny11, attiny12, attiny15, attiny28).
+ attiny11, attiny12, attiny15, attiny28).
Instruction set avr2 (default) is for the classic AVR core with up
to 8K program memory space (MCU types: at90s2313, at90s2323,
- attiny22, attiny26, at90s2333, at90s2343, at90s4414, at90s4433,
- at90s4434, at90s8515, at90c8534, at90s8535, at86rf401, attiny13,
- attiny2313, attiny261, attiny461, attiny861, attiny24, attiny44,
- attiny84, attiny25, attiny45, attiny85).
+ at90s2333, at90s2343, attiny22, attiny26, at90s4414, at90s4433,
+ at90s4434, at90s8515, at90c8534, at90s8535).
+
+ Instruction set avr25 is for the classic AVR core with up to 8K
+ program memory space plus the MOVW instruction (MCU types:
+ attiny13, attiny13a, attiny2313, attiny2313a, attiny24, attiny24a,
+ attiny4313, attiny44, attiny44a, attiny84, attiny25, attiny45,
+ attiny85, attiny261, attiny261a, attiny461, attiny861, attiny861a,
+ attiny87, attiny43u, attiny48, attiny88, at86rf401, ata6289).
Instruction set avr3 is for the classic AVR core with up to 128K
- program memory space (MCU types: atmega103, atmega603, at43usb320,
- at43usb355, at76c711).
+ program memory space (MCU types: at43usb355, at76c711).
+
+ Instruction set avr31 is for the classic AVR core with exactly
+ 128K program memory space (MCU types: atmega103, at43usb320).
+
+ Instruction set avr35 is for classic AVR core plus MOVW, CALL, and
+ JMP instructions (MCU types: attiny167, attiny327, at90usb82,
+ at90usb162, atmega8u2, atmega16u2, atmega32u2).
Instruction set avr4 is for the enhanced AVR core with up to 8K
- program memory space (MCU types: atmega48, atmega8, atmega83,
- atmega85, atmega88, atmega8515, atmega8535, atmega8hva, at90pwm1,
- at90pwm2, at90pwm3).
+ program memory space (MCU types: atmega48, atmega48p,atmega8,
+ atmega88, atmega88p, atmega8515, atmega8535, atmega8hva,
+ atmega4hvd, atmega8hvd, at90pwm1, at90pwm2, at90pwm2b, at90pwm3,
+ at90pwm3b, at90pwm81, atmega8m1, atmega8c1).
Instruction set avr5 is for the enhanced AVR core with up to 128K
program memory space (MCU types: atmega16, atmega161, atmega162,
atmega163, atmega164p, atmega165, atmega165p, atmega168,
- atmega169, atmega169p, atmega32, atmega323, atmega324p, atmega325,
- atmega325p, atmega329, atmega329p, atmega3250, atmega3250p,
- atmega3290, atmega3290p, atmega406, atmega64, atmega640,
- atmega644, atmega644p, atmega128, atmega1280, atmega1281,
- atmega645, atmega649, atmega6450, atmega6490, atmega16hva,
- at90can32, at90can64, at90can128, at90usb82, at90usb162,
- at90usb646, at90usb647, at90usb1286, at90usb1287, at94k).
-
- Instruction set avr6 is for the enhanced AVR core with 256K program
- memory space (MCU types: atmega2560, atmega2561).
+ atmega168p, atmega169, atmega169p, atmega16c1, atmega32,
+ atmega323, atmega324p, atmega325, atmega325p, atmega3250,
+ atmega3250p, atmega328p, atmega329, atmega329p, atmega3290,
+ atmega3290p, atmega406, atmega64, atmega640, atmega644,
+ atmega644p, atmega644pa, atmega645, atmega6450, atmega649,
+ atmega6490, atmega16hva, atmega16hvb, atmega32hvb, at90can32,
+ at90can64, at90pwm216, at90pwm316, atmega32c1, atmega64c1,
+ atmega16m1, atmega32m1, atmega64m1, atmega16u4, atmega32u4,
+ atmega32u6, at90usb646, at90usb647, at94k, at90scr100).
+
+ Instruction set avr51 is for the enhanced AVR core with exactly
+ 128K program memory space (MCU types: atmega128, atmega1280,
+ atmega1281, atmega1284p, atmega128rfa1, at90can128, at90usb1286,
+ at90usb1287, m3000f, m3000s, m3001b).
+
+ Instruction set avr6 is for the enhanced AVR core with a 3-byte PC
+ (MCU types: atmega2560, atmega2561).
`-mall-opcodes'
Accept all AVR opcodes, even if not supported by `-mmcu'.
\1f
File: as.info, Node: AVR Syntax, Next: AVR Opcodes, Prev: AVR Options, Up: AVR-Dependent
-8.4.2 Syntax
+9.4.2 Syntax
------------
* Menu:
\1f
File: as.info, Node: AVR-Chars, Next: AVR-Regs, Up: AVR Syntax
-8.4.2.1 Special Characters
+9.4.2.1 Special Characters
..........................
The presence of a `;' on a line indicates the start of a comment that
\1f
File: as.info, Node: AVR-Regs, Next: AVR-Modifiers, Prev: AVR-Chars, Up: AVR Syntax
-8.4.2.2 Register Names
+9.4.2.2 Register Names
......................
The AVR has 32 x 8-bit general purpose working registers `r0', `r1',
\1f
File: as.info, Node: AVR-Modifiers, Prev: AVR-Regs, Up: AVR Syntax
-8.4.2.3 Relocatable Expression Modifiers
+9.4.2.3 Relocatable Expression Modifiers
........................................
The assembler supports several modifiers when using relocatable
\1f
File: as.info, Node: AVR Opcodes, Prev: AVR Syntax, Up: AVR-Dependent
-8.4.3 Opcodes
+9.4.3 Opcodes
-------------
For detailed information on the AVR machine instruction set, see
1001010000011001 eijmp
\1f
-File: as.info, Node: BFIN-Dependent, Next: CR16-Dependent, Prev: AVR-Dependent, Up: Machine Dependencies
+File: as.info, Node: Blackfin-Dependent, Next: CR16-Dependent, Prev: AVR-Dependent, Up: Machine Dependencies
-8.5 Blackfin Dependent Features
+9.5 Blackfin Dependent Features
===============================
* Menu:
-* BFIN Syntax:: BFIN Syntax
-* BFIN Directives:: BFIN Directives
+* Blackfin Options:: Blackfin Options
+* Blackfin Syntax:: Blackfin Syntax
+* Blackfin Directives:: Blackfin Directives
+
+\1f
+File: as.info, Node: Blackfin Options, Next: Blackfin Syntax, Up: Blackfin-Dependent
+
+9.5.1 Options
+-------------
+
+`-mcpu=PROCESSOR[-SIREVISION]'
+ This option specifies the target processor. The optional
+ SIREVISION is not used in assembler. It's here such that GCC can
+ easily pass down its `-mcpu=' option. The assembler will issue an
+ error message if an attempt is made to assemble an instruction
+ which will not execute on the target processor. The following
+ processor names are recognized: `bf512', `bf514', `bf516', `bf518',
+ `bf522', `bf523', `bf524', `bf525', `bf526', `bf527', `bf531',
+ `bf532', `bf533', `bf534', `bf535' (not implemented yet), `bf536',
+ `bf537', `bf538', `bf539', `bf542', `bf542m', `bf544', `bf544m',
+ `bf547', `bf547m', `bf548', `bf548m', `bf549', `bf549m', and
+ `bf561'.
+
\1f
-File: as.info, Node: BFIN Syntax, Next: BFIN Directives, Up: BFIN-Dependent
+File: as.info, Node: Blackfin Syntax, Next: Blackfin Directives, Prev: Blackfin Options, Up: Blackfin-Dependent
-8.5.1 Syntax
+9.5.2 Syntax
------------
`Special Characters'
\1f
-File: as.info, Node: BFIN Directives, Prev: BFIN Syntax, Up: BFIN-Dependent
+File: as.info, Node: Blackfin Directives, Prev: Blackfin Syntax, Up: Blackfin-Dependent
-8.5.2 Directives
+9.5.3 Directives
----------------
The following directives are provided for compatibility with the VDSP
Define and initialize a 32 bit data object.
\1f
-File: as.info, Node: CR16-Dependent, Next: CRIS-Dependent, Prev: BFIN-Dependent, Up: Machine Dependencies
+File: as.info, Node: CR16-Dependent, Next: CRIS-Dependent, Prev: Blackfin-Dependent, Up: Machine Dependencies
-8.6 CR16 Dependent Features
+9.6 CR16 Dependent Features
===========================
* Menu:
\1f
File: as.info, Node: CR16 Operand Qualifiers, Up: CR16-Dependent
-8.6.1 CR16 Operand Qualifiers
+9.6.1 CR16 Operand Qualifiers
-----------------------------
The National Semiconductor CR16 target of `as' has a few machine
accordingly. The linker uses the relocation entry to update the
operand address at link time.'
+`got/GOT'
+ - `Specifies the CR16 Assembler generates a relocation entry for
+ the operand, offset from Global Offset Table. The linker uses this
+ relocation entry to update the operand address at link time'
+
+`cgot/cGOT'
+ - `Specifies the CompactRISC Assembler generates a relocation
+ entry for the operand, where pc has implied bit, the expression is
+ adjusted accordingly. The linker uses the relocation entry to
+ update the operand address at link time.'
+
CR16 target operand qualifiers and its size (in bits):
`Immediate Operand'
This .long directive, the address of _myfunc, shifted right by 1 at link time.
+ 4 `loadd _data1@GOT(r12), (r1,r0)'
+
+ This loads the address of _data1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r2-r1.
+
+ 5 `loadd _myfunc@cGOT(r12), (r1,r0)'
+
+ This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0.
+
\1f
File: as.info, Node: CRIS-Dependent, Next: D10V-Dependent, Prev: CR16-Dependent, Up: Machine Dependencies
-8.7 CRIS Dependent Features
+9.7 CRIS Dependent Features
===========================
* Menu:
\1f
File: as.info, Node: CRIS-Opts, Next: CRIS-Expand, Up: CRIS-Dependent
-8.7.1 Command-line Options
+9.7.1 Command-line Options
--------------------------
The CRIS version of `as' has these machine-dependent command-line
\1f
File: as.info, Node: CRIS-Expand, Next: CRIS-Symbols, Prev: CRIS-Opts, Up: CRIS-Dependent
-8.7.2 Instruction expansion
+9.7.2 Instruction expansion
---------------------------
`as' will silently choose an instruction that fits the operand size for
\1f
File: as.info, Node: CRIS-Symbols, Next: CRIS-Syntax, Prev: CRIS-Expand, Up: CRIS-Dependent
-8.7.3 Symbols
+9.7.3 Symbols
-------------
Some symbols are defined by the assembler. They're intended to be used
\1f
File: as.info, Node: CRIS-Syntax, Prev: CRIS-Symbols, Up: CRIS-Dependent
-8.7.4 Syntax
+9.7.4 Syntax
------------
There are different aspects of the CRIS assembly syntax.
\1f
File: as.info, Node: CRIS-Chars, Next: CRIS-Pic, Up: CRIS-Syntax
-8.7.4.1 Special Characters
+9.7.4.1 Special Characters
..........................
The character `#' is a line comment character. It starts a comment if
\1f
File: as.info, Node: CRIS-Pic, Next: CRIS-Regs, Prev: CRIS-Chars, Up: CRIS-Syntax
-8.7.4.2 Symbols in position-independent code
+9.7.4.2 Symbols in position-independent code
............................................
When generating position-independent code (SVR4 PIC) for use in
\1f
File: as.info, Node: CRIS-Regs, Next: CRIS-Pseudos, Prev: CRIS-Pic, Up: CRIS-Syntax
-8.7.4.3 Register names
+9.7.4.3 Register names
......................
A `$' character may always prefix a general or special register name in
\1f
File: as.info, Node: CRIS-Pseudos, Prev: CRIS-Regs, Up: CRIS-Syntax
-8.7.4.4 Assembler Directives
+9.7.4.4 Assembler Directives
............................
There are a few CRIS-specific pseudo-directives in addition to the
\1f
File: as.info, Node: D10V-Dependent, Next: D30V-Dependent, Prev: CRIS-Dependent, Up: Machine Dependencies
-8.8 D10V Dependent Features
+9.8 D10V Dependent Features
===========================
* Menu:
\1f
File: as.info, Node: D10V-Opts, Next: D10V-Syntax, Up: D10V-Dependent
-8.8.1 D10V Options
+9.8.1 D10V Options
------------------
The Mitsubishi D10V version of `as' has a few machine dependent options.
\1f
File: as.info, Node: D10V-Syntax, Next: D10V-Float, Prev: D10V-Opts, Up: D10V-Dependent
-8.8.2 Syntax
+9.8.2 Syntax
------------
The D10V syntax is based on the syntax in Mitsubishi's D10V
\1f
File: as.info, Node: D10V-Size, Next: D10V-Subs, Up: D10V-Syntax
-8.8.2.1 Size Modifiers
+9.8.2.1 Size Modifiers
......................
The D10V version of `as' uses the instruction names in the D10V
\1f
File: as.info, Node: D10V-Subs, Next: D10V-Chars, Prev: D10V-Size, Up: D10V-Syntax
-8.8.2.2 Sub-Instructions
+9.8.2.2 Sub-Instructions
........................
The D10V assembler takes as input a series of instructions, either
\1f
File: as.info, Node: D10V-Chars, Next: D10V-Regs, Prev: D10V-Subs, Up: D10V-Syntax
-8.8.2.3 Special Characters
+9.8.2.3 Special Characters
..........................
`;' and `#' are the line comment characters. Sub-instructions may be
\1f
File: as.info, Node: D10V-Regs, Next: D10V-Addressing, Prev: D10V-Chars, Up: D10V-Syntax
-8.8.2.4 Register Names
+9.8.2.4 Register Names
......................
You can use the predefined symbols `r0' through `r15' to refer to the
\1f
File: as.info, Node: D10V-Addressing, Next: D10V-Word, Prev: D10V-Regs, Up: D10V-Syntax
-8.8.2.5 Addressing Modes
+9.8.2.5 Addressing Modes
........................
`as' understands the following addressing modes for the D10V. `RN' in
\1f
File: as.info, Node: D10V-Word, Prev: D10V-Addressing, Up: D10V-Syntax
-8.8.2.6 @WORD Modifier
+9.8.2.6 @WORD Modifier
......................
Any symbol followed by `@word' will be replaced by the symbol's value
\1f
File: as.info, Node: D10V-Float, Next: D10V-Opcodes, Prev: D10V-Syntax, Up: D10V-Dependent
-8.8.3 Floating Point
+9.8.3 Floating Point
--------------------
The D10V has no hardware floating point, but the `.float' and `.double'
\1f
File: as.info, Node: D10V-Opcodes, Prev: D10V-Float, Up: D10V-Dependent
-8.8.4 Opcodes
+9.8.4 Opcodes
-------------
For detailed information on the D10V machine instruction set, see `D10V
\1f
File: as.info, Node: D30V-Dependent, Next: H8/300-Dependent, Prev: D10V-Dependent, Up: Machine Dependencies
-8.9 D30V Dependent Features
+9.9 D30V Dependent Features
===========================
* Menu:
\1f
File: as.info, Node: D30V-Opts, Next: D30V-Syntax, Up: D30V-Dependent
-8.9.1 D30V Options
+9.9.1 D30V Options
------------------
The Mitsubishi D30V version of `as' has a few machine dependent options.
\1f
File: as.info, Node: D30V-Syntax, Next: D30V-Float, Prev: D30V-Opts, Up: D30V-Dependent
-8.9.2 Syntax
+9.9.2 Syntax
------------
The D30V syntax is based on the syntax in Mitsubishi's D30V
\1f
File: as.info, Node: D30V-Size, Next: D30V-Subs, Up: D30V-Syntax
-8.9.2.1 Size Modifiers
+9.9.2.1 Size Modifiers
......................
The D30V version of `as' uses the instruction names in the D30V
\1f
File: as.info, Node: D30V-Subs, Next: D30V-Chars, Prev: D30V-Size, Up: D30V-Syntax
-8.9.2.2 Sub-Instructions
+9.9.2.2 Sub-Instructions
........................
The D30V assembler takes as input a series of instructions, either
\1f
File: as.info, Node: D30V-Chars, Next: D30V-Guarded, Prev: D30V-Subs, Up: D30V-Syntax
-8.9.2.3 Special Characters
+9.9.2.3 Special Characters
..........................
`;' and `#' are the line comment characters. Sub-instructions may be
\1f
File: as.info, Node: D30V-Guarded, Next: D30V-Regs, Prev: D30V-Chars, Up: D30V-Syntax
-8.9.2.4 Guarded Execution
+9.9.2.4 Guarded Execution
.........................
`as' supports the full range of guarded execution directives for each
\1f
File: as.info, Node: D30V-Regs, Next: D30V-Addressing, Prev: D30V-Guarded, Up: D30V-Syntax
-8.9.2.5 Register Names
+9.9.2.5 Register Names
......................
You can use the predefined symbols `r0' through `r63' to refer to the
\1f
File: as.info, Node: D30V-Addressing, Prev: D30V-Regs, Up: D30V-Syntax
-8.9.2.6 Addressing Modes
+9.9.2.6 Addressing Modes
........................
`as' understands the following addressing modes for the D30V. `RN' in
\1f
File: as.info, Node: D30V-Float, Next: D30V-Opcodes, Prev: D30V-Syntax, Up: D30V-Dependent
-8.9.3 Floating Point
+9.9.3 Floating Point
--------------------
The D30V has no hardware floating point, but the `.float' and `.double'
\1f
File: as.info, Node: D30V-Opcodes, Prev: D30V-Float, Up: D30V-Dependent
-8.9.4 Opcodes
+9.9.4 Opcodes
-------------
For detailed information on the D30V machine instruction set, see `D30V
\1f
File: as.info, Node: H8/300-Dependent, Next: HPPA-Dependent, Prev: D30V-Dependent, Up: Machine Dependencies
-8.10 H8/300 Dependent Features
+9.10 H8/300 Dependent Features
==============================
* Menu:
\1f
File: as.info, Node: H8/300 Options, Next: H8/300 Syntax, Up: H8/300-Dependent
-8.10.1 Options
+9.10.1 Options
--------------
-`as' has no additional command-line options for the Renesas (formerly
-Hitachi) H8/300 family.
+The Renesas H8/300 version of `as' has one machine-dependent option:
+
+`-h-tick-hex'
+ Support H'00 style hex constants in addition to 0x00 style.
+
\1f
File: as.info, Node: H8/300 Syntax, Next: H8/300 Floating Point, Prev: H8/300 Options, Up: H8/300-Dependent
-8.10.2 Syntax
+9.10.2 Syntax
-------------
* Menu:
\1f
File: as.info, Node: H8/300-Chars, Next: H8/300-Regs, Up: H8/300 Syntax
-8.10.2.1 Special Characters
+9.10.2.1 Special Characters
...........................
`;' is the line comment character.
\1f
File: as.info, Node: H8/300-Regs, Next: H8/300-Addressing, Prev: H8/300-Chars, Up: H8/300 Syntax
-8.10.2.2 Register Names
+9.10.2.2 Register Names
.......................
You can use predefined symbols of the form `rNh' and `rNl' to refer to
\1f
File: as.info, Node: H8/300-Addressing, Prev: H8/300-Regs, Up: H8/300 Syntax
-8.10.2.3 Addressing Modes
+9.10.2.3 Addressing Modes
.........................
as understands the following addressing modes for the H8/300:
\1f
File: as.info, Node: H8/300 Floating Point, Next: H8/300 Directives, Prev: H8/300 Syntax, Up: H8/300-Dependent
-8.10.3 Floating Point
+9.10.3 Floating Point
---------------------
The H8/300 family has no hardware floating point, but the `.float'
\1f
File: as.info, Node: H8/300 Directives, Next: H8/300 Opcodes, Prev: H8/300 Floating Point, Up: H8/300-Dependent
-8.10.4 H8/300 Machine Directives
+9.10.4 H8/300 Machine Directives
--------------------------------
`as' has the following machine-dependent directives for the H8/300:
\1f
File: as.info, Node: H8/300 Opcodes, Prev: H8/300 Directives, Up: H8/300-Dependent
-8.10.5 Opcodes
+9.10.5 Opcodes
--------------
For detailed information on the H8/300 machine instruction set, see
\1f
File: as.info, Node: HPPA-Dependent, Next: ESA/390-Dependent, Prev: H8/300-Dependent, Up: Machine Dependencies
-8.11 HPPA Dependent Features
+9.11 HPPA Dependent Features
============================
* Menu:
\1f
File: as.info, Node: HPPA Notes, Next: HPPA Options, Up: HPPA-Dependent
-8.11.1 Notes
+9.11.1 Notes
------------
As a back end for GNU CC `as' has been throughly tested and should work
\1f
File: as.info, Node: HPPA Options, Next: HPPA Syntax, Prev: HPPA Notes, Up: HPPA-Dependent
-8.11.2 Options
+9.11.2 Options
--------------
`as' has no machine-dependent command-line options for the HPPA.
\1f
File: as.info, Node: HPPA Syntax, Next: HPPA Floating Point, Prev: HPPA Options, Up: HPPA-Dependent
-8.11.3 Syntax
+9.11.3 Syntax
-------------
The assembler syntax closely follows the HPPA instruction set reference
\1f
File: as.info, Node: HPPA Floating Point, Next: HPPA Directives, Prev: HPPA Syntax, Up: HPPA-Dependent
-8.11.4 Floating Point
+9.11.4 Floating Point
---------------------
The HPPA family uses IEEE floating-point numbers.
\1f
File: as.info, Node: HPPA Directives, Next: HPPA Opcodes, Prev: HPPA Floating Point, Up: HPPA-Dependent
-8.11.5 HPPA Assembler Directives
+9.11.5 HPPA Assembler Directives
--------------------------------
`as' for the HPPA supports many additional directives for compatibility
\1f
File: as.info, Node: HPPA Opcodes, Prev: HPPA Directives, Up: HPPA-Dependent
-8.11.6 Opcodes
+9.11.6 Opcodes
--------------
For detailed information on the HPPA machine instruction set, see
\1f
File: as.info, Node: ESA/390-Dependent, Next: i386-Dependent, Prev: HPPA-Dependent, Up: Machine Dependencies
-8.12 ESA/390 Dependent Features
+9.12 ESA/390 Dependent Features
===============================
* Menu:
\1f
File: as.info, Node: ESA/390 Notes, Next: ESA/390 Options, Up: ESA/390-Dependent
-8.12.1 Notes
+9.12.1 Notes
------------
The ESA/390 `as' port is currently intended to be a back-end for the
\1f
File: as.info, Node: ESA/390 Options, Next: ESA/390 Syntax, Prev: ESA/390 Notes, Up: ESA/390-Dependent
-8.12.2 Options
+9.12.2 Options
--------------
`as' has no machine-dependent command-line options for the ESA/390.
\1f
File: as.info, Node: ESA/390 Syntax, Next: ESA/390 Floating Point, Prev: ESA/390 Options, Up: ESA/390-Dependent
-8.12.3 Syntax
+9.12.3 Syntax
-------------
The opcode/operand syntax follows the ESA/390 Principles of Operation
\1f
File: as.info, Node: ESA/390 Floating Point, Next: ESA/390 Directives, Prev: ESA/390 Syntax, Up: ESA/390-Dependent
-8.12.4 Floating Point
+9.12.4 Floating Point
---------------------
The assembler generates only IEEE floating-point numbers. The older
\1f
File: as.info, Node: ESA/390 Directives, Next: ESA/390 Opcodes, Prev: ESA/390 Floating Point, Up: ESA/390-Dependent
-8.12.5 ESA/390 Assembler Directives
+9.12.5 ESA/390 Assembler Directives
-----------------------------------
`as' for the ESA/390 supports all of the standard ELF/SVR4 assembler
\1f
File: as.info, Node: ESA/390 Opcodes, Prev: ESA/390 Directives, Up: ESA/390-Dependent
-8.12.6 Opcodes
+9.12.6 Opcodes
--------------
For detailed information on the ESA/390 machine instruction set, see
\1f
File: as.info, Node: i386-Dependent, Next: i860-Dependent, Prev: ESA/390-Dependent, Up: Machine Dependencies
-8.13 80386 Dependent Features
+9.13 80386 Dependent Features
=============================
The i386 version `as' supports both the original Intel 386
* Menu:
* i386-Options:: Options
+* i386-Directives:: X86 specific directives
* i386-Syntax:: AT&T Syntax versus Intel Syntax
* i386-Mnemonics:: Instruction Naming
* i386-Regs:: Register Naming
* i386-Notes:: Notes
\1f
-File: as.info, Node: i386-Options, Next: i386-Syntax, Up: i386-Dependent
+File: as.info, Node: i386-Options, Next: i386-Directives, Up: i386-Dependent
-8.13.1 Options
+9.13.1 Options
--------------
The i386 version of `as' has a few machine dependent options:
character. This does not disable `/' at the beginning of a line
starting a comment, or affect using `#' for starting a comment.
-`-march=CPU'
- This option specifies an instruction set architecture for
- generating instructions. The following architectures are
- recognized: `i8086', `i186', `i286', `i386', `i486', `i586',
- `i686', `pentium', `pentiumpro', `pentiumii', `pentiumiii',
- `pentium4', `prescott', `nocona', `core', `core2', `k6', `k6_2',
- `athlon', `sledgehammer', `opteron', `k8', `generic32' and
- `generic64'.
+`-march=CPU[+EXTENSION...]'
+ This option specifies the target processor. The assembler will
+ issue an error message if an attempt is made to assemble an
+ instruction which will not execute on the target processor. The
+ following processor names are recognized: `i8086', `i186', `i286',
+ `i386', `i486', `i586', `i686', `pentium', `pentiumpro',
+ `pentiumii', `pentiumiii', `pentium4', `prescott', `nocona',
+ `core', `core2', `corei7', `l1om', `k6', `k6_2', `athlon',
+ `opteron', `k8', `amdfam10', `generic32' and `generic64'.
- This option only affects instructions generated by the assembler.
- The `.arch' directive will take precedent.
+ In addition to the basic instruction set, the assembler can be
+ told to accept various extension mnemonics. For example,
+ `-march=i686+sse4+vmx' extends I686 with SSE4 and VMX. The
+ following extensions are currently supported: `8087', `287', `387',
+ `no87', `mmx', `nommx', `sse', `sse2', `sse3', `ssse3', `sse4.1',
+ `sse4.2', `sse4', `nosse', `avx', `noavx', `vmx', `smx', `xsave',
+ `aes', `pclmul', `fma', `movbe', `ept', `clflush', `syscall',
+ `rdtscp', `3dnow', `3dnowa', `sse4a', `sse5', `svme', `abm' and
+ `padlock'. Note that rather than extending a basic instruction
+ set, the extension mnemonics starting with `no' revoke the
+ respective functionality.
+
+ When the `.arch' directive is used with `-march', the `.arch'
+ directive will take precedent.
`-mtune=CPU'
This option specifies a processor to optimize for. When used in
conjunction with the `-march' option, only instructions of the
processor specified by the `-march' option will be generated.
- Valid CPU values are identical to `-march=CPU'.
+ Valid CPU values are identical to the processor list of
+ `-march=CPU'.
+
+`-msse2avx'
+ This option specifies that the assembler should encode SSE
+ instructions with VEX prefix.
+
+`-msse-check=NONE'
+
+`-msse-check=WARNING'
+
+`-msse-check=ERROR'
+ These options control if the assembler should check SSE
+ intructions. `-msse-check=NONE' will make the assembler not to
+ check SSE instructions, which is the default.
+ `-msse-check=WARNING' will make the assembler issue a warning for
+ any SSE intruction. `-msse-check=ERROR' will make the assembler
+ issue an error for any SSE intruction.
+
+`-mmnemonic=ATT'
+
+`-mmnemonic=INTEL'
+ This option specifies instruction mnemonic for matching
+ instructions. The `.att_mnemonic' and `.intel_mnemonic'
+ directives will take precedent.
+
+`-msyntax=ATT'
+
+`-msyntax=INTEL'
+ This option specifies instruction syntax when processing
+ instructions. The `.att_syntax' and `.intel_syntax' directives
+ will take precedent.
+
+`-mnaked-reg'
+ This opetion specifies that registers don't require a `%' prefix.
+ The `.att_syntax' and `.intel_syntax' directives will take
+ precedent.
+
+
+\1f
+File: as.info, Node: i386-Directives, Next: i386-Syntax, Prev: i386-Options, Up: i386-Dependent
+
+9.13.2 x86 specific Directives
+------------------------------
+
+`.lcomm SYMBOL , LENGTH[, ALIGNMENT]'
+ Reserve LENGTH (an absolute expression) bytes for a local common
+ denoted by SYMBOL. The section and value of SYMBOL are those of
+ the new local common. The addresses are allocated in the bss
+ section, so that at run-time the bytes start off zeroed. Since
+ SYMBOL is not declared global, it is normally not visible to `ld'.
+ The optional third parameter, ALIGNMENT, specifies the desired
+ alignment of the symbol in the bss section.
+
+ This directive is only available for COFF based x86 targets.
\1f
-File: as.info, Node: i386-Syntax, Next: i386-Mnemonics, Prev: i386-Options, Up: i386-Dependent
+File: as.info, Node: i386-Syntax, Next: i386-Mnemonics, Prev: i386-Directives, Up: i386-Dependent
-8.13.2 AT&T Syntax versus Intel Syntax
+9.13.3 AT&T Syntax versus Intel Syntax
--------------------------------------
`as' now supports assembly using Intel assembler syntax.
* AT&T and Intel syntax use the opposite order for source and
destination operands. Intel `add eax, 4' is `addl $4, %eax'. The
`source, dest' convention is maintained for compatibility with
- previous Unix assemblers. Note that instructions with more than
- one source operand, such as the `enter' instruction, do _not_ have
- reversed order. *Note i386-Bugs::.
+ previous Unix assemblers. Note that `bound', `invlpga', and
+ instructions with 2 immediate operands, such as the `enter'
+ instruction, do _not_ have reversed order. *Note i386-Bugs::.
* In AT&T syntax the size of memory operands is determined from the
last character of the instruction mnemonic. Mnemonic suffixes of
\1f
File: as.info, Node: i386-Mnemonics, Next: i386-Regs, Prev: i386-Syntax, Up: i386-Dependent
-8.13.3 Instruction Naming
+9.13.4 Instruction Naming
-------------------------
Instruction mnemonics are suffixed with one character modifiers which
long), `bq' (from byte to quadruple word), `wq' (from word to quadruple
word), and `lq' (from long to quadruple word).
+ Different encoding options can be specified via optional mnemonic
+suffix. `.s' suffix swaps 2 register operands in encoding when moving
+from one register to another.
+
The Intel-syntax conversion instructions
* `cbw' -- sign-extend byte in `%al' to word in `%ax',
Far call/jump instructions are `lcall' and `ljmp' in AT&T syntax,
but are `call far' and `jump far' in Intel convention.
+9.13.5 AT&T Mnemonic versus Intel Mnemonic
+------------------------------------------
+
+`as' supports assembly using Intel mnemonic. `.intel_mnemonic' selects
+Intel mnemonic with Intel syntax, and `.att_mnemonic' switches back to
+the usual AT&T mnemonic with AT&T syntax for compatibility with the
+output of `gcc'. Several x87 instructions, `fadd', `fdiv', `fdivp',
+`fdivr', `fdivrp', `fmul', `fsub', `fsubp', `fsubr' and `fsubrp', are
+implemented in AT&T System V/386 assembler with different mnemonics
+from those in Intel IA32 specification. `gcc' generates those
+instructions with AT&T mnemonic.
+
\1f
File: as.info, Node: i386-Regs, Next: i386-Prefixes, Prev: i386-Mnemonics, Up: i386-Dependent
-8.13.4 Register Naming
+9.13.6 Register Naming
----------------------
Register operands are always prefixed with `%'. The 80386 registers
\1f
File: as.info, Node: i386-Prefixes, Next: i386-Memory, Prev: i386-Regs, Up: i386-Dependent
-8.13.5 Instruction Prefixes
+9.13.7 Instruction Prefixes
---------------------------
Instruction prefixes are used to modify the following instruction. They
\1f
File: as.info, Node: i386-Memory, Next: i386-Jumps, Prev: i386-Prefixes, Up: i386-Dependent
-8.13.6 Memory References
+9.13.8 Memory References
------------------------
An Intel syntax indirect memory reference of the form
\1f
File: as.info, Node: i386-Jumps, Next: i386-Float, Prev: i386-Memory, Up: i386-Dependent
-8.13.7 Handling of Jump Instructions
+9.13.9 Handling of Jump Instructions
------------------------------------
Jump instructions are always optimized to use the smallest possible
\1f
File: as.info, Node: i386-Float, Next: i386-SIMD, Prev: i386-Jumps, Up: i386-Dependent
-8.13.8 Floating Point
----------------------
+9.13.10 Floating Point
+----------------------
All 80387 floating point types except packed BCD are supported. (BCD
support may be added without much difficulty). These data types are
\1f
File: as.info, Node: i386-SIMD, Next: i386-16bit, Prev: i386-Float, Up: i386-Dependent
-8.13.9 Intel's MMX and AMD's 3DNow! SIMD Operations
----------------------------------------------------
+9.13.11 Intel's MMX and AMD's 3DNow! SIMD Operations
+----------------------------------------------------
`as' supports Intel's MMX instruction set (SIMD instructions for
integer data), available on Intel's Pentium MMX processors and Pentium
\1f
File: as.info, Node: i386-16bit, Next: i386-Arch, Prev: i386-SIMD, Up: i386-Dependent
-8.13.10 Writing 16-bit Code
+9.13.12 Writing 16-bit Code
---------------------------
While `as' normally writes only "pure" 32-bit i386 code or 64-bit
\1f
File: as.info, Node: i386-Bugs, Next: i386-Notes, Prev: i386-Arch, Up: i386-Dependent
-8.13.11 AT&T Syntax bugs
+9.13.13 AT&T Syntax bugs
------------------------
The UnixWare assembler, and probably other AT&T derived ix86 Unix
\1f
File: as.info, Node: i386-Arch, Next: i386-Bugs, Prev: i386-16bit, Up: i386-Dependent
-8.13.12 Specifying CPU Architecture
+9.13.14 Specifying CPU Architecture
-----------------------------------
`as' may be told to assemble for a particular CPU (sub-)architecture
`i486' `i586' `i686' `pentium'
`pentiumpro' `pentiumii' `pentiumiii' `pentium4'
`prescott' `nocona' `core' `core2'
+`corei7' `l1om'
+`k6' `k6_2' `athlon' `k8'
`amdfam10'
-`k6' `athlon' `sledgehammer' `k8'
+`generic32' `generic64'
`.mmx' `.sse' `.sse2' `.sse3'
`.ssse3' `.sse4.1' `.sse4.2' `.sse4'
-`.sse4a' `.3dnow' `.3dnowa' `.padlock'
-`.pacifica' `.svme' `.abm'
+`.avx' `.vmx' `.smx' `.xsave'
+`.aes' `.pclmul' `.fma' `.movbe'
+`.ept' `.clflush'
+`.3dnow' `.3dnowa' `.sse4a' `.sse5'
+`.syscall' `.rdtscp' `.svme' `.abm'
+`.padlock'
Apart from the warning, there are only two other effects on `as'
operation; Firstly, if you specify a CPU other than `i486', then shift
\1f
File: as.info, Node: i386-Notes, Prev: i386-Bugs, Up: i386-Dependent
-8.13.13 Notes
+9.13.15 Notes
-------------
There is some trickery concerning the `mul' and `imul' instructions
\1f
File: as.info, Node: i860-Dependent, Next: i960-Dependent, Prev: i386-Dependent, Up: Machine Dependencies
-8.14 Intel i860 Dependent Features
+9.14 Intel i860 Dependent Features
==================================
* Menu:
\1f
File: as.info, Node: Notes-i860, Next: Options-i860, Up: i860-Dependent
-8.14.1 i860 Notes
+9.14.1 i860 Notes
-----------------
This is a fairly complete i860 assembler which is compatible with the
\1f
File: as.info, Node: Options-i860, Next: Directives-i860, Prev: Notes-i860, Up: i860-Dependent
-8.14.2 i860 Command-line Options
+9.14.2 i860 Command-line Options
--------------------------------
-8.14.2.1 SVR4 compatibility options
+9.14.2.1 SVR4 compatibility options
...................................
`-V'
`-Qn'
Ignored.
-8.14.2.2 Other options
+9.14.2.2 Other options
......................
`-EL'
\1f
File: as.info, Node: Directives-i860, Next: Opcodes for i860, Prev: Options-i860, Up: i860-Dependent
-8.14.3 i860 Machine Directives
+9.14.3 i860 Machine Directives
------------------------------
`.dual'
\1f
File: as.info, Node: Opcodes for i860, Prev: Directives-i860, Up: i860-Dependent
-8.14.4 i860 Opcodes
+9.14.4 i860 Opcodes
-------------------
All of the Intel i860XR and i860XP machine instructions are supported.
Please see either _i860 Microprocessor Programmer's Reference Manual_
or _i860 Microprocessor Architecture_ for more information.
-8.14.4.1 Other instruction support (pseudo-instructions)
+9.14.4.1 Other instruction support (pseudo-instructions)
........................................................
For compatibility with some other i860 assemblers, a number of
\1f
File: as.info, Node: i960-Dependent, Next: IA-64-Dependent, Prev: i860-Dependent, Up: Machine Dependencies
-8.15 Intel 80960 Dependent Features
+9.15 Intel 80960 Dependent Features
===================================
* Menu:
\1f
File: as.info, Node: Options-i960, Next: Floating Point-i960, Up: i960-Dependent
-8.15.1 i960 Command-line Options
+9.15.1 i960 Command-line Options
--------------------------------
`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC'
\1f
File: as.info, Node: Floating Point-i960, Next: Directives-i960, Prev: Options-i960, Up: i960-Dependent
-8.15.2 Floating Point
+9.15.2 Floating Point
---------------------
`as' generates IEEE floating-point numbers for the directives `.float',
\1f
File: as.info, Node: Directives-i960, Next: Opcodes for i960, Prev: Floating Point-i960, Up: i960-Dependent
-8.15.3 i960 Machine Directives
+9.15.3 i960 Machine Directives
------------------------------
`.bss SYMBOL, LENGTH, ALIGN'
\1f
File: as.info, Node: Opcodes for i960, Prev: Directives-i960, Up: i960-Dependent
-8.15.4 i960 Opcodes
+9.15.4 i960 Opcodes
-------------------
All Intel 960 machine instructions are supported; *note i960
\1f
File: as.info, Node: callj-i960, Next: Compare-and-branch-i960, Up: Opcodes for i960
-8.15.4.1 `callj'
+9.15.4.1 `callj'
................
You can write `callj' to have the assembler or the linker determine the
\1f
File: as.info, Node: Compare-and-branch-i960, Prev: callj-i960, Up: Opcodes for i960
-8.15.4.2 Compare-and-Branch
+9.15.4.2 Compare-and-Branch
...........................
The 960 architectures provide combined Compare-and-Branch instructions
\1f
File: as.info, Node: IA-64-Dependent, Next: IP2K-Dependent, Prev: i960-Dependent, Up: Machine Dependencies
-8.16 IA-64 Dependent Features
+9.16 IA-64 Dependent Features
=============================
* Menu:
\1f
File: as.info, Node: IA-64 Options, Next: IA-64 Syntax, Up: IA-64-Dependent
-8.16.1 Options
+9.16.1 Options
--------------
`-mconstant-gp'
\1f
File: as.info, Node: IA-64 Syntax, Next: IA-64 Opcodes, Prev: IA-64 Options, Up: IA-64-Dependent
-8.16.2 Syntax
+9.16.2 Syntax
-------------
The assembler syntax closely follows the IA-64 Assembly Language
\1f
File: as.info, Node: IA-64-Chars, Next: IA-64-Regs, Up: IA-64 Syntax
-8.16.2.1 Special Characters
+9.16.2.1 Special Characters
...........................
`//' is the line comment token.
\1f
File: as.info, Node: IA-64-Regs, Next: IA-64-Bits, Prev: IA-64-Chars, Up: IA-64 Syntax
-8.16.2.2 Register Names
+9.16.2.2 Register Names
.......................
The 128 integer registers are referred to as `rN'. The 128
\1f
File: as.info, Node: IA-64-Bits, Prev: IA-64-Regs, Up: IA-64 Syntax
-8.16.2.3 IA-64 Processor-Status-Register (PSR) Bit Names
+9.16.2.3 IA-64 Processor-Status-Register (PSR) Bit Names
........................................................
The assembler defines bit masks for each of the bits in the IA-64
\1f
File: as.info, Node: IA-64 Opcodes, Prev: IA-64 Syntax, Up: IA-64-Dependent
-8.16.3 Opcodes
+9.16.3 Opcodes
--------------
For detailed information on the IA-64 machine instruction set, see the
(http://developer.intel.com/design/itanium/arch_spec.htm).
\1f
-File: as.info, Node: IP2K-Dependent, Next: M32C-Dependent, Prev: IA-64-Dependent, Up: Machine Dependencies
+File: as.info, Node: IP2K-Dependent, Next: LM32-Dependent, Prev: IA-64-Dependent, Up: Machine Dependencies
-8.17 IP2K Dependent Features
+9.17 IP2K Dependent Features
============================
* Menu:
\1f
File: as.info, Node: IP2K-Opts, Up: IP2K-Dependent
-8.17.1 IP2K Options
+9.17.1 IP2K Options
-------------------
The Ubicom IP2K version of `as' has a few machine dependent options:
\1f
-File: as.info, Node: M32C-Dependent, Next: M32R-Dependent, Prev: IP2K-Dependent, Up: Machine Dependencies
+File: as.info, Node: LM32-Dependent, Next: M32C-Dependent, Prev: IP2K-Dependent, Up: Machine Dependencies
+
+9.18 LM32 Dependent Features
+============================
+
+* Menu:
+
+* LM32 Options:: Options
+* LM32 Syntax:: Syntax
+* LM32 Opcodes:: Opcodes
+
+\1f
+File: as.info, Node: LM32 Options, Next: LM32 Syntax, Up: LM32-Dependent
+
+9.18.1 Options
+--------------
+
+`-mmultiply-enabled'
+ Enable multiply instructions.
+
+`-mdivide-enabled'
+ Enable divide instructions.
+
+`-mbarrel-shift-enabled'
+ Enable barrel-shift instructions.
+
+`-msign-extend-enabled'
+ Enable sign extend instructions.
+
+`-muser-enabled'
+ Enable user defined instructions.
+
+`-micache-enabled'
+ Enable instruction cache related CSRs.
+
+`-mdcache-enabled'
+ Enable data cache related CSRs.
+
+`-mbreak-enabled'
+ Enable break instructions.
+
+`-mall-enabled'
+ Enable all instructions and CSRs.
+
+
+\1f
+File: as.info, Node: LM32 Syntax, Next: LM32 Opcodes, Prev: LM32 Options, Up: LM32-Dependent
+
+9.18.2 Syntax
+-------------
+
+* Menu:
+
+* LM32-Regs:: Register Names
+* LM32-Modifiers:: Relocatable Expression Modifiers
+
+\1f
+File: as.info, Node: LM32-Regs, Next: LM32-Modifiers, Up: LM32 Syntax
+
+9.18.2.1 Register Names
+.......................
+
+LM32 has 32 x 32-bit general purpose registers `r0', `r1', ... `r31'.
+
+ The following aliases are defined: `gp' - `r26', `fp' - `r27', `sp'
+- `r28', `ra' - `r29', `ea' - `r30', `ba' - `r31'.
+
+ LM32 has the following Control and Status Registers (CSRs).
+
+`IE'
+ Interrupt enable.
+
+`IM'
+ Interrupt mask.
+
+`IP'
+ Interrupt pending.
+
+`ICC'
+ Instruction cache control.
+
+`DCC'
+ Data cache control.
+
+`CC'
+ Cycle counter.
+
+`CFG'
+ Configuration.
+
+`EBA'
+ Exception base address.
+
+`DC'
+ Debug control.
+
+`DEBA'
+ Debug exception base address.
+
+`JTX'
+ JTAG transmit.
+
+`JRX'
+ JTAG receive.
+
+`BP0'
+ Breakpoint 0.
+
+`BP1'
+ Breakpoint 1.
+
+`BP2'
+ Breakpoint 2.
+
+`BP3'
+ Breakpoint 3.
+
+`WP0'
+ Watchpoint 0.
+
+`WP1'
+ Watchpoint 1.
+
+`WP2'
+ Watchpoint 2.
+
+`WP3'
+ Watchpoint 3.
+
+\1f
+File: as.info, Node: LM32-Modifiers, Prev: LM32-Regs, Up: LM32 Syntax
+
+9.18.2.2 Relocatable Expression Modifiers
+.........................................
+
+The assembler supports several modifiers when using relocatable
+addresses in LM32 instruction operands. The general syntax is the
+following:
+
+ modifier(relocatable-expression)
+
+`lo'
+ This modifier allows you to use bits 0 through 15 of an address
+ expression as 16 bit relocatable expression.
+
+`hi'
+ This modifier allows you to use bits 16 through 23 of an address
+ expression as 16 bit relocatable expression.
+
+ For example
+
+ ori r4, r4, lo(sym+10)
+ orhi r4, r4, hi(sym+10)
+
+`gp'
+ This modified creates a 16-bit relocatable expression that is the
+ offset of the symbol from the global pointer.
+
+ mva r4, gp(sym)
+
+`got'
+ This modifier places a symbol in the GOT and creates a 16-bit
+ relocatable expression that is the offset into the GOT of this
+ symbol.
+
+ lw r4, (gp+got(sym))
+
+`gotofflo16'
+ This modifier allows you to use the bits 0 through 15 of an
+ address which is an offset from the GOT.
+
+`gotoffhi16'
+ This modifier allows you to use the bits 16 through 31 of an
+ address which is an offset from the GOT.
+
+ orhi r4, r4, gotoffhi16(lsym)
+ addi r4, r4, gotofflo16(lsym)
+
+
+\1f
+File: as.info, Node: LM32 Opcodes, Prev: LM32 Syntax, Up: LM32-Dependent
+
+9.18.3 Opcodes
+--------------
+
+For detailed information on the LM32 machine instruction set, see
+`http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/'.
+
+ `as' implements all the standard LM32 opcodes.
+
+\1f
+File: as.info, Node: M32C-Dependent, Next: M32R-Dependent, Prev: LM32-Dependent, Up: Machine Dependencies
-8.18 M32C Dependent Features
+9.19 M32C Dependent Features
============================
`as' can assemble code for several different members of the Renesas
\1f
File: as.info, Node: M32C-Opts, Next: M32C-Modifiers, Up: M32C-Dependent
-8.18.1 M32C Options
+9.19.1 M32C Options
-------------------
-The Renesas M32C version of `as' has two machine-dependent options:
+The Renesas M32C version of `as' has these machine-dependent options:
`-m32c'
Assemble M32C instructions.
`-m16c'
Assemble M16C instructions (default).
+`-relax'
+ Enable support for link-time relaxations.
+
+`-h-tick-hex'
+ Support H'00 style hex constants in addition to 0x00 style.
+
\1f
File: as.info, Node: M32C-Modifiers, Prev: M32C-Opts, Up: M32C-Dependent
-8.18.2 Symbolic Operand Modifiers
+9.19.2 Symbolic Operand Modifiers
---------------------------------
The assembler supports several modifiers when using symbol addresses in
\1f
File: as.info, Node: M32R-Dependent, Next: M68K-Dependent, Prev: M32C-Dependent, Up: Machine Dependencies
-8.19 M32R Dependent Features
+9.20 M32R Dependent Features
============================
* Menu:
\1f
File: as.info, Node: M32R-Opts, Next: M32R-Directives, Up: M32R-Dependent
-8.19.1 M32R Options
+9.20.1 M32R Options
-------------------
The Renease M32R version of `as' has a few machine dependent options:
\1f
File: as.info, Node: M32R-Directives, Next: M32R-Warnings, Prev: M32R-Opts, Up: M32R-Dependent
-8.19.2 M32R Directives
+9.20.2 M32R Directives
----------------------
The Renease M32R version of `as' has a few architecture specific
\1f
File: as.info, Node: M32R-Warnings, Prev: M32R-Directives, Up: M32R-Dependent
-8.19.3 M32R Warnings
+9.20.3 M32R Warnings
--------------------
There are several warning and error messages that can be produced by
\1f
File: as.info, Node: M68K-Dependent, Next: M68HC11-Dependent, Prev: M32R-Dependent, Up: Machine Dependencies
-8.20 M680x0 Dependent Features
+9.21 M680x0 Dependent Features
==============================
* Menu:
\1f
File: as.info, Node: M68K-Opts, Next: M68K-Syntax, Up: M68K-Dependent
-8.20.1 M680x0 Options
+9.21.1 M680x0 Options
---------------------
The Motorola 680x0 version of `as' has a few machine dependent options:
\1f
File: as.info, Node: M68K-Syntax, Next: M68K-Moto-Syntax, Prev: M68K-Opts, Up: M68K-Dependent
-8.20.2 Syntax
+9.21.2 Syntax
-------------
This syntax for the Motorola 680x0 was developed at MIT.
\1f
File: as.info, Node: M68K-Moto-Syntax, Next: M68K-Float, Prev: M68K-Syntax, Up: M68K-Dependent
-8.20.3 Motorola Syntax
+9.21.3 Motorola Syntax
----------------------
The standard Motorola syntax for this chip differs from the syntax
\1f
File: as.info, Node: M68K-Float, Next: M68K-Directives, Prev: M68K-Moto-Syntax, Up: M68K-Dependent
-8.20.4 Floating Point
+9.21.4 Floating Point
---------------------
Packed decimal (P) format floating literals are not supported. Feel
\1f
File: as.info, Node: M68K-Directives, Next: M68K-opcodes, Prev: M68K-Float, Up: M68K-Dependent
-8.20.5 680x0 Machine Directives
+9.21.5 680x0 Machine Directives
-------------------------------
In order to be compatible with the Sun assembler the 680x0 assembler
\1f
File: as.info, Node: M68K-opcodes, Prev: M68K-Directives, Up: M68K-Dependent
-8.20.6 Opcodes
+9.21.6 Opcodes
--------------
* Menu:
\1f
File: as.info, Node: M68K-Branch, Next: M68K-Chars, Up: M68K-opcodes
-8.20.6.1 Branch Improvement
+9.21.6.1 Branch Improvement
...........................
Certain pseudo opcodes are permitted for branch instructions. They
\1f
File: as.info, Node: M68K-Chars, Prev: M68K-Branch, Up: M68K-opcodes
-8.20.6.2 Special Characters
+9.21.6.2 Special Characters
...........................
The immediate character is `#' for Sun compatibility. The line-comment
it looks like `# line file', in which case it is treated normally.
\1f
-File: as.info, Node: M68HC11-Dependent, Next: MIPS-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies
+File: as.info, Node: M68HC11-Dependent, Next: MicroBlaze-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies
-8.21 M68HC11 and M68HC12 Dependent Features
+9.22 M68HC11 and M68HC12 Dependent Features
===========================================
* Menu:
\1f
File: as.info, Node: M68HC11-Opts, Next: M68HC11-Syntax, Up: M68HC11-Dependent
-8.21.1 M68HC11 and M68HC12 Options
+9.22.1 M68HC11 and M68HC12 Options
----------------------------------
The Motorola 68HC11 and 68HC12 version of `as' have a few machine
\1f
File: as.info, Node: M68HC11-Syntax, Next: M68HC11-Modifiers, Prev: M68HC11-Opts, Up: M68HC11-Dependent
-8.21.2 Syntax
+9.22.2 Syntax
-------------
In the M68HC11 syntax, the instruction name comes first and it may be
\1f
File: as.info, Node: M68HC11-Modifiers, Next: M68HC11-Directives, Prev: M68HC11-Syntax, Up: M68HC11-Dependent
-8.21.3 Symbolic Operand Modifiers
+9.22.3 Symbolic Operand Modifiers
---------------------------------
The assembler supports several modifiers when using symbol addresses in
\1f
File: as.info, Node: M68HC11-Directives, Next: M68HC11-Float, Prev: M68HC11-Modifiers, Up: M68HC11-Dependent
-8.21.4 Assembler Directives
+9.22.4 Assembler Directives
---------------------------
The 68HC11 and 68HC12 version of `as' have the following specific
\1f
File: as.info, Node: M68HC11-Float, Next: M68HC11-opcodes, Prev: M68HC11-Directives, Up: M68HC11-Dependent
-8.21.5 Floating Point
+9.22.5 Floating Point
---------------------
Packed decimal (P) format floating literals are not supported. Feel
\1f
File: as.info, Node: M68HC11-opcodes, Prev: M68HC11-Float, Up: M68HC11-Dependent
-8.21.6 Opcodes
+9.22.6 Opcodes
--------------
* Menu:
\1f
File: as.info, Node: M68HC11-Branch, Up: M68HC11-opcodes
-8.21.6.1 Branch Improvement
+9.22.6.1 Branch Improvement
...........................
Certain pseudo opcodes are permitted for branch instructions. They
\1f
-File: as.info, Node: MIPS-Dependent, Next: MMIX-Dependent, Prev: M68HC11-Dependent, Up: Machine Dependencies
+File: as.info, Node: MicroBlaze-Dependent, Next: MIPS-Dependent, Prev: M68HC11-Dependent, Up: Machine Dependencies
+
+9.23 MicroBlaze Dependent Features
+==================================
+
+ The Xilinx MicroBlaze processor family includes several variants,
+all using the same core instruction set. This chapter covers features
+of the GNU assembler that are specific to the MicroBlaze architecture.
+For details about the MicroBlaze instruction set, please see the
+`MicroBlaze Processor Reference Guide (UG081)' available at
+www.xilinx.com.
+
+* Menu:
+
+* MicroBlaze Directives:: Directives for MicroBlaze Processors.
+
+\1f
+File: as.info, Node: MicroBlaze Directives, Up: MicroBlaze-Dependent
+
+9.23.1 Directives
+-----------------
+
+A number of assembler directives are available for MicroBlaze.
+
+`.data8 EXPRESSION,...'
+ This directive is an alias for `.byte'. Each expression is
+ assembled into an eight-bit value.
+
+`.data16 EXPRESSION,...'
+ This directive is an alias for `.hword'. Each expression is
+ assembled into an 16-bit value.
+
+`.data32 EXPRESSION,...'
+ This directive is an alias for `.word'. Each expression is
+ assembled into an 32-bit value.
+
+`.ent NAME[,LABEL]'
+ This directive is an alias for `.func' denoting the start of
+ function NAME at (optional) LABEL.
+
+`.end NAME[,LABEL]'
+ This directive is an alias for `.endfunc' denoting the end of
+ function NAME.
+
+`.gpword LABEL,...'
+ This directive is an alias for `.rva'. The resolved address of
+ LABEL is stored in the data section.
+
+`.weakext LABEL'
+ Declare that LABEL is a weak external symbol.
+
+`.rodata'
+ Switch to .rodata section. Equivalent to `.section .rodata'
+
+`.sdata2'
+ Switch to .sdata2 section. Equivalent to `.section .sdata2'
+
+`.sdata'
+ Switch to .sdata section. Equivalent to `.section .sdata'
+
+`.bss'
+ Switch to .bss section. Equivalent to `.section .bss'
+
+`.sbss'
+ Switch to .sbss section. Equivalent to `.section .sbss'
+
+\1f
+File: as.info, Node: MIPS-Dependent, Next: MMIX-Dependent, Prev: MicroBlaze-Dependent, Up: Machine Dependencies
-8.22 MIPS Dependent Features
+9.24 MIPS Dependent Features
============================
GNU `as' for MIPS architectures supports several different MIPS
* MIPS option stack:: Directives to save and restore options
* MIPS ASE instruction generation overrides:: Directives to control
generation of MIPS ASE instructions
+* MIPS floating-point:: Directives to override floating-point options
\1f
File: as.info, Node: MIPS Opts, Next: MIPS Object, Up: MIPS-Dependent
-8.22.1 Assembler options
+9.24.1 Assembler options
------------------------
The MIPS configurations of GNU `as' support these special options:
`-no-mfix-vr4130'
Insert nops to work around the VR4130 `mflo'/`mfhi' errata.
+`-mfix-24k'
+`-no-mfix-24k'
+ Insert nops to work around the 24K `eret'/`deret' errata.
+
`-m4010'
`-no-m4010'
Generate code for the LSI R4010 chip. This tells the assembler to
2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130,
vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231,
rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000,
- 10000, 12000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem, 4kep, 4ksd,
- m4k, m4kp, 24kc, 24kf2_1, 24kf, 24kf1_1, 24kec, 24kef2_1,
- 24kef, 24kef1_1, 34kc, 34kf2_1, 34kf, 34kf1_1, 74kc, 74kf2_1,
- 74kf, 74kf1_1, 74kf3_2, 5kc, 5kf, 20kc, 25kf, sb1, sb1a
+ 10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem,
+ 4kep, 4ksd, m4k, m4kp, 24kc, 24kf2_1, 24kf, 24kf1_1, 24kec,
+ 24kef2_1, 24kef, 24kef1_1, 34kc, 34kf2_1, 34kf, 34kf1_1, 74kc,
+ 74kf2_1, 74kf, 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf,
+ 1004kf1_1, 5kc, 5kf, 20kc, 25kf, sb1, sb1a, loongson2e,
+ loongson2f, octeon, xlr
For compatibility reasons, `Nx' and `Bfx' are accepted as synonyms
for `Nf1_1'. These values are deprecated.
`-nocpp', because the GNU assembler itself never runs the C
preprocessor.
+`-msoft-float'
+`-mhard-float'
+ Disable or enable floating-point instructions. Note that by
+ default floating-point instructions are always allowed even with
+ CPU targets that don't have support for these instructions.
+
+`-msingle-float'
+`-mdouble-float'
+ Disable or enable double-precision floating-point operations. Note
+ that by default double-precision floating-point operations are
+ always allowed even with CPU targets that don't have support for
+ these operations.
+
`--construct-floats'
`--no-construct-floats'
The `--no-construct-floats' option disables the construction of
\1f
File: as.info, Node: MIPS Object, Next: MIPS Stabs, Prev: MIPS Opts, Up: MIPS-Dependent
-8.22.2 MIPS ECOFF object code
+9.24.2 MIPS ECOFF object code
-----------------------------
Assembling for a MIPS ECOFF target supports some additional sections
\1f
File: as.info, Node: MIPS Stabs, Next: MIPS ISA, Prev: MIPS Object, Up: MIPS-Dependent
-8.22.3 Directives for debugging information
+9.24.3 Directives for debugging information
-------------------------------------------
MIPS ECOFF `as' supports several directives used for generating
\1f
File: as.info, Node: MIPS symbol sizes, Next: MIPS autoextend, Prev: MIPS ISA, Up: MIPS-Dependent
-8.22.4 Directives to override the size of symbols
+9.24.4 Directives to override the size of symbols
-------------------------------------------------
The n64 ABI allows symbols to have any 64-bit value. Although this
\1f
File: as.info, Node: MIPS ISA, Next: MIPS symbol sizes, Prev: MIPS Stabs, Up: MIPS-Dependent
-8.22.5 Directives to override the ISA level
+9.24.5 Directives to override the ISA level
-------------------------------------------
GNU `as' supports an additional directive to change the MIPS
\1f
File: as.info, Node: MIPS autoextend, Next: MIPS insn, Prev: MIPS symbol sizes, Up: MIPS-Dependent
-8.22.6 Directives for extending MIPS 16 bit instructions
+9.24.6 Directives for extending MIPS 16 bit instructions
--------------------------------------------------------
By default, MIPS 16 instructions are automatically extended to 32 bits
\1f
File: as.info, Node: MIPS insn, Next: MIPS option stack, Prev: MIPS autoextend, Up: MIPS-Dependent
-8.22.7 Directive to mark data as an instruction
+9.24.7 Directive to mark data as an instruction
-----------------------------------------------
The `.insn' directive tells `as' that the following data is actually
adds 1 to the value, so that jumping to the loaded address will do the
right thing.
+ The `.global' and `.globl' directives supported by `as' will by
+default mark the symbol as pointing to a region of data not code. This
+means that, for example, any instructions following such a symbol will
+not be disassembled by `objdump' as it will regard them as data. To
+change this behaviour an optional section name can be placed after the
+symbol name in the `.global' directive. If this section exists and is
+known to be a code section, then the symbol will be marked as poiting at
+code not data. Ie the syntax for the directive is:
+
+ `.global SYMBOL[ SECTION][, SYMBOL[ SECTION]] ...',
+
+ Here is a short example:
+
+ .global foo .text, bar, baz .data
+ foo:
+ nop
+ bar:
+ .word 0x0
+ baz:
+ .word 0x1
+
\1f
File: as.info, Node: MIPS option stack, Next: MIPS ASE instruction generation overrides, Prev: MIPS insn, Up: MIPS-Dependent
-8.22.8 Directives to save and restore options
+9.24.8 Directives to save and restore options
---------------------------------------------
The directives `.set push' and `.set pop' may be used to save and
Traditional MIPS assemblers do not support these directives.
\1f
-File: as.info, Node: MIPS ASE instruction generation overrides, Prev: MIPS option stack, Up: MIPS-Dependent
+File: as.info, Node: MIPS ASE instruction generation overrides, Next: MIPS floating-point, Prev: MIPS option stack, Up: MIPS-Dependent
-8.22.9 Directives to control generation of MIPS ASE instructions
+9.24.9 Directives to control generation of MIPS ASE instructions
----------------------------------------------------------------
The directive `.set mips3d' makes the assembler accept instructions
Traditional MIPS assemblers do not support these directives.
\1f
-File: as.info, Node: MMIX-Dependent, Next: MSP430-Dependent, Prev: MIPS-Dependent, Up: Machine Dependencies
+File: as.info, Node: MIPS floating-point, Prev: MIPS ASE instruction generation overrides, Up: MIPS-Dependent
-8.23 MMIX Dependent Features
+9.24.10 Directives to override floating-point options
+-----------------------------------------------------
+
+The directives `.set softfloat' and `.set hardfloat' provide finer
+control of disabling and enabling float-point instructions. These
+directives always override the default (that hard-float instructions
+are accepted) or the command-line options (`-msoft-float' and
+`-mhard-float').
+
+ The directives `.set singlefloat' and `.set doublefloat' provide
+finer control of disabling and enabling double-precision float-point
+operations. These directives always override the default (that
+double-precision operations are accepted) or the command-line options
+(`-msingle-float' and `-mdouble-float').
+
+ Traditional MIPS assemblers do not support these directives.
+
+\1f
+File: as.info, Node: MMIX-Dependent, Next: MSP430-Dependent, Prev: MIPS-Dependent, Up: Machine Dependencies
+
+9.25 MMIX Dependent Features
============================
* Menu:
\1f
File: as.info, Node: MMIX-Opts, Next: MMIX-Expand, Up: MMIX-Dependent
-8.23.1 Command-line Options
+9.25.1 Command-line Options
---------------------------
The MMIX version of `as' has some machine-dependent options.
\1f
File: as.info, Node: MMIX-Expand, Next: MMIX-Syntax, Prev: MMIX-Opts, Up: MMIX-Dependent
-8.23.2 Instruction expansion
+9.25.2 Instruction expansion
----------------------------
When `as' encounters an instruction with an operand that is either not
\1f
File: as.info, Node: MMIX-Syntax, Next: MMIX-mmixal, Prev: MMIX-Expand, Up: MMIX-Dependent
-8.23.3 Syntax
+9.25.3 Syntax
-------------
The assembly syntax is supposed to be upward compatible with that
\1f
File: as.info, Node: MMIX-Chars, Next: MMIX-Symbols, Up: MMIX-Syntax
-8.23.3.1 Special Characters
+9.25.3.1 Special Characters
...........................
The characters `*' and `#' are line comment characters; each start a
\1f
File: as.info, Node: MMIX-Symbols, Next: MMIX-Regs, Prev: MMIX-Chars, Up: MMIX-Syntax
-8.23.3.2 Symbols
+9.25.3.2 Symbols
................
The character `:' is permitted in identifiers. There are two
\1f
File: as.info, Node: MMIX-Regs, Next: MMIX-Pseudos, Prev: MMIX-Symbols, Up: MMIX-Syntax
-8.23.3.3 Register names
+9.25.3.3 Register names
.......................
Local and global registers are specified as `$0' to `$255'. The
\1f
File: as.info, Node: MMIX-Pseudos, Prev: MMIX-Regs, Up: MMIX-Syntax
-8.23.3.4 Assembler Directives
+9.25.3.4 Assembler Directives
.............................
`LOC'
\1f
File: as.info, Node: MMIX-mmixal, Prev: MMIX-Syntax, Up: MMIX-Dependent
-8.23.4 Differences to `mmixal'
+9.25.4 Differences to `mmixal'
------------------------------
The binutils `as' and `ld' combination has a few differences in
\1f
File: as.info, Node: MSP430-Dependent, Next: SH-Dependent, Prev: MMIX-Dependent, Up: Machine Dependencies
-8.24 MSP 430 Dependent Features
+9.26 MSP 430 Dependent Features
===============================
* Menu:
\1f
File: as.info, Node: MSP430 Options, Next: MSP430 Syntax, Up: MSP430-Dependent
-8.24.1 Options
+9.26.1 Options
--------------
`-m'
\1f
File: as.info, Node: MSP430 Syntax, Next: MSP430 Floating Point, Prev: MSP430 Options, Up: MSP430-Dependent
-8.24.2 Syntax
+9.26.2 Syntax
-------------
* Menu:
\1f
File: as.info, Node: MSP430-Macros, Next: MSP430-Chars, Up: MSP430 Syntax
-8.24.2.1 Macros
+9.26.2.1 Macros
...............
The macro syntax used on the MSP 430 is like that described in the MSP
\1f
File: as.info, Node: MSP430-Chars, Next: MSP430-Regs, Prev: MSP430-Macros, Up: MSP430 Syntax
-8.24.2.2 Special Characters
+9.26.2.2 Special Characters
...........................
`;' is the line comment character.
\1f
File: as.info, Node: MSP430-Regs, Next: MSP430-Ext, Prev: MSP430-Chars, Up: MSP430 Syntax
-8.24.2.3 Register Names
+9.26.2.3 Register Names
.......................
General-purpose registers are represented by predefined symbols of the
\1f
File: as.info, Node: MSP430-Ext, Prev: MSP430-Regs, Up: MSP430 Syntax
-8.24.2.4 Assembler Extensions
+9.26.2.4 Assembler Extensions
.............................
`@rN'
\1f
File: as.info, Node: MSP430 Floating Point, Next: MSP430 Directives, Prev: MSP430 Syntax, Up: MSP430-Dependent
-8.24.3 Floating Point
+9.26.3 Floating Point
---------------------
The MSP 430 family uses IEEE 32-bit floating-point numbers.
\1f
File: as.info, Node: MSP430 Directives, Next: MSP430 Opcodes, Prev: MSP430 Floating Point, Up: MSP430-Dependent
-8.24.4 MSP 430 Machine Directives
+9.26.4 MSP 430 Machine Directives
---------------------------------
`.file'
\1f
File: as.info, Node: MSP430 Opcodes, Next: MSP430 Profiling Capability, Prev: MSP430 Directives, Up: MSP430-Dependent
-8.24.5 Opcodes
+9.26.5 Opcodes
--------------
`as' implements all the standard MSP 430 opcodes. No additional
\1f
File: as.info, Node: MSP430 Profiling Capability, Prev: MSP430 Opcodes, Up: MSP430-Dependent
-8.24.6 Profiling Capability
+9.26.6 Profiling Capability
---------------------------
It is a performance hit to use gcc's profiling approach for this tiny
\1f
File: as.info, Node: PDP-11-Dependent, Next: PJ-Dependent, Prev: SH64-Dependent, Up: Machine Dependencies
-8.25 PDP-11 Dependent Features
+9.27 PDP-11 Dependent Features
==============================
* Menu:
\1f
File: as.info, Node: PDP-11-Options, Next: PDP-11-Pseudos, Up: PDP-11-Dependent
-8.25.1 Options
+9.27.1 Options
--------------
The PDP-11 version of `as' has a rich set of machine dependent options.
-8.25.1.1 Code Generation Options
+9.27.1.1 Code Generation Options
................................
`-mpic | -mno-pic'
The default is to generate position-independent code.
-8.25.1.2 Instruction Set Extension Options
+9.27.1.2 Instruction Set Extension Options
..........................................
These options enables or disables the use of extensions over the base
Enable (or disable) the use of the microcode instructions: `LDUB',
`MED', and `XFC'.
-8.25.1.3 CPU Model Options
+9.27.1.3 CPU Model Options
..........................
These options enable the instruction set extensions supported by a
T11 CPU. Enable limited extended instruction set, `MFPS', and
`MTPS'.
-8.25.1.4 Machine Model Options
+9.27.1.4 Machine Model Options
..............................
These options enable the instruction set extensions supported by a
\1f
File: as.info, Node: PDP-11-Pseudos, Next: PDP-11-Syntax, Prev: PDP-11-Options, Up: PDP-11-Dependent
-8.25.2 Assembler Directives
+9.27.2 Assembler Directives
---------------------------
The PDP-11 version of `as' has a few machine dependent assembler
\1f
File: as.info, Node: PDP-11-Syntax, Next: PDP-11-Mnemonics, Prev: PDP-11-Pseudos, Up: PDP-11-Dependent
-8.25.3 PDP-11 Assembly Language Syntax
+9.27.3 PDP-11 Assembly Language Syntax
--------------------------------------
`as' supports both DEC syntax and BSD syntax. The only difference is
\1f
File: as.info, Node: PDP-11-Mnemonics, Next: PDP-11-Synthetic, Prev: PDP-11-Syntax, Up: PDP-11-Dependent
-8.25.4 Instruction Naming
+9.27.4 Instruction Naming
-------------------------
Some instructions have alternative names.
\1f
File: as.info, Node: PDP-11-Synthetic, Prev: PDP-11-Mnemonics, Up: PDP-11-Dependent
-8.25.5 Synthetic Instructions
+9.27.5 Synthetic Instructions
-----------------------------
The `JBR' and `J'CC synthetic instructions are not supported yet.
\1f
File: as.info, Node: PJ-Dependent, Next: PPC-Dependent, Prev: PDP-11-Dependent, Up: Machine Dependencies
-8.26 picoJava Dependent Features
+9.28 picoJava Dependent Features
================================
* Menu:
\1f
File: as.info, Node: PJ Options, Up: PJ-Dependent
-8.26.1 Options
+9.28.1 Options
--------------
`as' has two additional command-line options for the picoJava
This option selects big endian data output.
\1f
-File: as.info, Node: PPC-Dependent, Next: Sparc-Dependent, Prev: PJ-Dependent, Up: Machine Dependencies
+File: as.info, Node: PPC-Dependent, Next: S/390-Dependent, Prev: PJ-Dependent, Up: Machine Dependencies
-8.27 PowerPC Dependent Features
+9.29 PowerPC Dependent Features
===============================
* Menu:
\1f
File: as.info, Node: PowerPC-Opts, Next: PowerPC-Pseudo, Up: PPC-Dependent
-8.27.1 Options
+9.29.1 Options
--------------
The PowerPC chip family includes several successive levels, using the
`-m440'
Generate code for PowerPC 440. BookE and some 405 instructions.
+`-m476'
+ Generate code for PowerPC 476.
+
`-m7400, -m7410, -m7450, -m7455'
Generate code for PowerPC 7400/7410/7450/7455.
-`-mppc64, -m620'
- Generate code for PowerPC 620/625/630.
+`-m750cl'
+ Generate code for PowerPC 750CL.
+
+`-mppc64, -m620'
+ Generate code for PowerPC 620/625/630.
+
+`-me500, -me500x2'
+ Generate code for Motorola e500 core complex.
+
+`-mspe'
+ Generate code for Motorola SPE instructions.
+
+`-mppc64bridge'
+ Generate code for PowerPC 64, including bridge insns.
+
+`-mbooke'
+ Generate code for 32-bit BookE.
+
+`-ma2'
+ Generate code for A2 architecture.
+
+`-me300'
+ Generate code for PowerPC e300 family.
+
+`-maltivec'
+ Generate code for processors with AltiVec instructions.
+
+`-mvsx'
+ Generate code for processors with Vector-Scalar (VSX) instructions.
+
+`-mpower4'
+ Generate code for Power4 architecture.
+
+`-mpower5'
+ Generate code for Power5 architecture.
+
+`-mpower6'
+ Generate code for Power6 architecture.
+
+`-mpower7'
+ Generate code for Power7 architecture.
+
+`-mcell'
+ Generate code for Cell Broadband Engine architecture.
+
+`-mcom'
+ Generate code Power/PowerPC common instructions.
+
+`-many'
+ Generate code for any architecture (PWR/PWRX/PPC).
+
+`-mregnames'
+ Allow symbolic names for registers.
+
+`-mno-regnames'
+ Do not allow symbolic names for registers.
+
+`-mrelocatable'
+ Support for GCC's -mrelocatable option.
+
+`-mrelocatable-lib'
+ Support for GCC's -mrelocatable-lib option.
+
+`-memb'
+ Set PPC_EMB bit in ELF flags.
+
+`-mlittle, -mlittle-endian'
+ Generate code for a little endian machine.
+
+`-mbig, -mbig-endian'
+ Generate code for a big endian machine.
+
+`-msolaris'
+ Generate code for Solaris.
+
+`-mno-solaris'
+ Do not generate code for Solaris.
+
+\1f
+File: as.info, Node: PowerPC-Pseudo, Prev: PowerPC-Opts, Up: PPC-Dependent
+
+9.29.2 PowerPC Assembler Directives
+-----------------------------------
+
+A number of assembler directives are available for PowerPC. The
+following table is far from complete.
+
+`.machine "string"'
+ This directive allows you to change the machine for which code is
+ generated. `"string"' may be any of the -m cpu selection options
+ (without the -m) enclosed in double quotes, `"push"', or `"pop"'.
+ `.machine "push"' saves the currently selected cpu, which may be
+ restored with `.machine "pop"'.
+
+\1f
+File: as.info, Node: S/390-Dependent, Next: SCORE-Dependent, Prev: PPC-Dependent, Up: Machine Dependencies
+
+9.30 IBM S/390 Dependent Features
+=================================
+
+ The s390 version of `as' supports two architectures modes and seven
+chip levels. The architecture modes are the Enterprise System
+Architecture (ESA) and the newer z/Architecture mode. The chip levels
+are g5, g6, z900, z990, z9-109, z9-ec and z10.
+
+* Menu:
+
+* s390 Options:: Command-line Options.
+* s390 Characters:: Special Characters.
+* s390 Syntax:: Assembler Instruction syntax.
+* s390 Directives:: Assembler Directives.
+* s390 Floating Point:: Floating Point.
+
+\1f
+File: as.info, Node: s390 Options, Next: s390 Characters, Up: S/390-Dependent
+
+9.30.1 Options
+--------------
+
+The following table lists all available s390 specific options:
+
+`-m31 | -m64'
+ Select 31- or 64-bit ABI implying a word size of 32- or 64-bit.
+
+ These options are only available with the ELF object file format,
+ and require that the necessary BFD support has been included (on a
+ 31-bit platform you must add -enable-64-bit-bfd on the call to the
+ configure script to enable 64-bit usage and use s390x as target
+ platform).
+
+`-mesa | -mzarch'
+ Select the architecture mode, either the Enterprise System
+ Architecture (esa) mode or the z/Architecture mode (zarch).
+
+ The 64-bit instructions are only available with the z/Architecture
+ mode. The combination of `-m64' and `-mesa' results in a warning
+ message.
+
+`-march=CPU'
+ This option specifies the target processor. The following
+ processor names are recognized: `g5', `g6', `z900', `z990',
+ `z9-109', `z9-ec' and `z10'. Assembling an instruction that is
+ not supported on the target processor results in an error message.
+ Do not specify `g5' or `g6' with `-mzarch'.
+
+`-mregnames'
+ Allow symbolic names for registers.
+
+`-mno-regnames'
+ Do not allow symbolic names for registers.
+
+`-mwarn-areg-zero'
+ Warn whenever the operand for a base or index register has been
+ specified but evaluates to zero. This can indicate the misuse of
+ general purpose register 0 as an address register.
+
+
+\1f
+File: as.info, Node: s390 Characters, Next: s390 Syntax, Prev: s390 Options, Up: S/390-Dependent
+
+9.30.2 Special Characters
+-------------------------
+
+`#' is the line comment character.
+
+\1f
+File: as.info, Node: s390 Syntax, Next: s390 Directives, Prev: s390 Characters, Up: S/390-Dependent
+
+9.30.3 Instruction syntax
+-------------------------
+
+The assembler syntax closely follows the syntax outlined in Enterprise
+Systems Architecture/390 Principles of Operation (SA22-7201) and the
+z/Architecture Principles of Operation (SA22-7832).
+
+ Each instruction has two major parts, the instruction mnemonic and
+the instruction operands. The instruction format varies.
+
+* Menu:
+
+* s390 Register:: Register Naming
+* s390 Mnemonics:: Instruction Mnemonics
+* s390 Operands:: Instruction Operands
+* s390 Formats:: Instruction Formats
+* s390 Aliases:: Instruction Aliases
+* s390 Operand Modifier:: Instruction Operand Modifier
+* s390 Instruction Marker:: Instruction Marker
+* s390 Literal Pool Entries:: Literal Pool Entries
+
+\1f
+File: as.info, Node: s390 Register, Next: s390 Mnemonics, Up: s390 Syntax
+
+9.30.3.1 Register naming
+........................
+
+The `as' recognizes a number of predefined symbols for the various
+processor registers. A register specification in one of the instruction
+formats is an unsigned integer between 0 and 15. The specific
+instruction and the position of the register in the instruction format
+denotes the type of the register. The register symbols are prefixed with
+`%':
+
+ %rN the 16 general purpose registers, 0 <= N <= 15
+ %fN the 16 floating point registers, 0 <= N <= 15
+ %aN the 16 access registers, 0 <= N <= 15
+ %cN the 16 control registers, 0 <= N <= 15
+ %lit an alias for the general purpose register %r13
+ %sp an alias for the general purpose register %r15
+
+\1f
+File: as.info, Node: s390 Mnemonics, Next: s390 Operands, Prev: s390 Register, Up: s390 Syntax
+
+9.30.3.2 Instruction Mnemonics
+..............................
+
+All instructions documented in the Principles of Operation are supported
+with the mnemonic and order of operands as described. The instruction
+mnemonic identifies the instruction format (*Note s390 Formats::) and
+the specific operation code for the instruction. For example, the `lr'
+mnemonic denotes the instruction format `RR' with the operation code
+`0x18'.
+
+ The definition of the various mnemonics follows a scheme, where the
+first character usually hint at the type of the instruction:
+
+ a add instruction, for example `al' for add logical 32-bit
+ b branch instruction, for example `bc' for branch on condition
+ c compare or convert instruction, for example `cr' for compare
+ register 32-bit
+ d divide instruction, for example `dlr' devide logical register
+ 64-bit to 32-bit
+ i insert instruction, for example `ic' insert character
+ l load instruction, for example `ltr' load and test register
+ mv move instruction, for example `mvc' move character
+ m multiply instruction, for example `mh' multiply halfword
+ n and instruction, for example `ni' and immediate
+ o or instruction, for example `oc' or character
+ sla, sll shift left single instruction
+ sra, srl shift right single instruction
+ st store instruction, for example `stm' store multiple
+ s subtract instruction, for example `slr' subtract
+ logical 32-bit
+ t test or translate instruction, of example `tm' test under mask
+ x exclusive or instruction, for example `xc' exclusive or
+ character
+
+ Certain characters at the end of the mnemonic may describe a property
+of the instruction:
+
+ c the instruction uses a 8-bit character operand
+ f the instruction extends a 32-bit operand to 64 bit
+ g the operands are treated as 64-bit values
+ h the operand uses a 16-bit halfword operand
+ i the instruction uses an immediate operand
+ l the instruction uses unsigned, logical operands
+ m the instruction uses a mask or operates on multiple values
+ r if r is the last character, the instruction operates on registers
+ y the instruction uses 20-bit displacements
+
+ There are many exceptions to the scheme outlined in the above lists,
+in particular for the priviledged instructions. For non-priviledged
+instruction it works quite well, for example the instruction `clgfr' c:
+compare instruction, l: unsigned operands, g: 64-bit operands, f: 32-
+to 64-bit extension, r: register operands. The instruction compares an
+64-bit value in a register with the zero extended 32-bit value from a
+second register. For a complete list of all mnemonics see appendix B
+in the Principles of Operation.
+
+\1f
+File: as.info, Node: s390 Operands, Next: s390 Formats, Prev: s390 Mnemonics, Up: s390 Syntax
+
+9.30.3.3 Instruction Operands
+.............................
+
+Instruction operands can be grouped into three classes, operands located
+in registers, immediate operands, and operands in storage.
+
+ A register operand can be located in general, floating-point, access,
+or control register. The register is identified by a four-bit field.
+The field containing the register operand is called the R field.
+
+ Immediate operands are contained within the instruction and can have
+8, 16 or 32 bits. The field containing the immediate operand is called
+the I field. Dependent on the instruction the I field is either signed
+or unsigned.
+
+ A storage operand consists of an address and a length. The address
+of a storage operands can be specified in any of these ways:
+
+ * The content of a single general R
+
+ * The sum of the content of a general register called the base
+ register B plus the content of a displacement field D
+
+ * The sum of the contents of two general registers called the index
+ register X and the base register B plus the content of a
+ displacement field
+
+ * The sum of the current instruction address and a 32-bit signed
+ immediate field multiplied by two.
+
+ The length of a storage operand can be:
+
+ * Implied by the instruction
+
+ * Specified by a bitmask
+
+ * Specified by a four-bit or eight-bit length field L
+
+ * Specified by the content of a general register
+
+ The notation for storage operand addresses formed from multiple
+fields is as follows:
+
+`Dn(Bn)'
+ the address for operand number n is formed from the content of
+ general register Bn called the base register and the displacement
+ field Dn.
+
+`Dn(Xn,Bn)'
+ the address for operand number n is formed from the content of
+ general register Xn called the index register, general register Bn
+ called the base register and the displacement field Dn.
+
+`Dn(Ln,Bn)'
+ the address for operand number n is formed from the content of
+ general regiser Bn called the base register and the displacement
+ field Dn. The length of the operand n is specified by the field
+ Ln.
+
+ The base registers Bn and the index registers Xn of a storage
+operand can be skipped. If Bn and Xn are skipped, a zero will be stored
+to the operand field. The notation changes as follows:
+
+ full notation short notation
+ ------------------------------------------
+ Dn(0,Bn) Dn(Bn)
+ Dn(0,0) Dn
+ Dn(0) Dn
+ Dn(Ln,0) Dn(Ln)
+
+\1f
+File: as.info, Node: s390 Formats, Next: s390 Aliases, Prev: s390 Operands, Up: s390 Syntax
+
+9.30.3.4 Instruction Formats
+............................
+
+The Principles of Operation manuals lists 26 instruction formats where
+some of the formats have multiple variants. For the `.insn' pseudo
+directive the assembler recognizes some of the formats. Typically, the
+most general variant of the instruction format is used by the `.insn'
+directive.
+
+ The following table lists the abbreviations used in the table of
+instruction formats:
+
+ OpCode / OpCd Part of the op code.
+ Bx Base register number for operand x.
+ Dx Displacement for operand x.
+ DLx Displacement lower 12 bits for operand x.
+ DHx Displacement higher 8-bits for operand x.
+ Rx Register number for operand x.
+ Xx Index register number for operand x.
+ Ix Signed immediate for operand x.
+ Ux Unsigned immediate for operand x.
+
+ An instruction is two, four, or six bytes in length and must be
+aligned on a 2 byte boundary. The first two bits of the instruction
+specify the length of the instruction, 00 indicates a two byte
+instruction, 01 and 10 indicates a four byte instruction, and 11
+indicates a six byte instruction.
+
+ The following table lists the s390 instruction formats that are
+available with the `.insn' pseudo directive:
+
+`E format'
+
+ +-------------+
+ | OpCode |
+ +-------------+
+ 0 15
+
+`RI format: <insn> R1,I2'
+
+ +--------+----+----+------------------+
+ | OpCode | R1 |OpCd| I2 |
+ +--------+----+----+------------------+
+ 0 8 12 16 31
+
+`RIE format: <insn> R1,R3,I2'
+
+ +--------+----+----+------------------+--------+--------+
+ | OpCode | R1 | R3 | I2 |////////| OpCode |
+ +--------+----+----+------------------+--------+--------+
+ 0 8 12 16 32 40 47
+
+`RIL format: <insn> R1,I2'
+
+ +--------+----+----+------------------------------------+
+ | OpCode | R1 |OpCd| I2 |
+ +--------+----+----+------------------------------------+
+ 0 8 12 16 47
+
+`RILU format: <insn> R1,U2'
+
+ +--------+----+----+------------------------------------+
+ | OpCode | R1 |OpCd| U2 |
+ +--------+----+----+------------------------------------+
+ 0 8 12 16 47
+
+`RIS format: <insn> R1,I2,M3,D4(B4)'
+
+ +--------+----+----+----+-------------+--------+--------+
+ | OpCode | R1 | M3 | B4 | D4 | I2 | Opcode |
+ +--------+----+----+----+-------------+--------+--------+
+ 0 8 12 16 20 32 36 47
+
+`RR format: <insn> R1,R2'
+
+ +--------+----+----+
+ | OpCode | R1 | R2 |
+ +--------+----+----+
+ 0 8 12 15
+
+`RRE format: <insn> R1,R2'
+
+ +------------------+--------+----+----+
+ | OpCode |////////| R1 | R2 |
+ +------------------+--------+----+----+
+ 0 16 24 28 31
+
+`RRF format: <insn> R1,R2,R3,M4'
+
+ +------------------+----+----+----+----+
+ | OpCode | R3 | M4 | R1 | R2 |
+ +------------------+----+----+----+----+
+ 0 16 20 24 28 31
+
+`RRS format: <insn> R1,R2,M3,D4(B4)'
+
+ +--------+----+----+----+-------------+----+----+--------+
+ | OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode |
+ +--------+----+----+----+-------------+----+----+--------+
+ 0 8 12 16 20 32 36 40 47
+
+`RS format: <insn> R1,R3,D2(B2)'
+
+ +--------+----+----+----+-------------+
+ | OpCode | R1 | R3 | B2 | D2 |
+ +--------+----+----+----+-------------+
+ 0 8 12 16 20 31
+
+`RSE format: <insn> R1,R3,D2(B2)'
+
+ +--------+----+----+----+-------------+--------+--------+
+ | OpCode | R1 | R3 | B2 | D2 |////////| OpCode |
+ +--------+----+----+----+-------------+--------+--------+
+ 0 8 12 16 20 32 40 47
+
+`RSI format: <insn> R1,R3,I2'
+
+ +--------+----+----+------------------------------------+
+ | OpCode | R1 | R3 | I2 |
+ +--------+----+----+------------------------------------+
+ 0 8 12 16 47
+
+`RSY format: <insn> R1,R3,D2(B2)'
+
+ +--------+----+----+----+-------------+--------+--------+
+ | OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode |
+ +--------+----+----+----+-------------+--------+--------+
+ 0 8 12 16 20 32 40 47
+
+`RX format: <insn> R1,D2(X2,B2)'
+
+ +--------+----+----+----+-------------+
+ | OpCode | R1 | X2 | B2 | D2 |
+ +--------+----+----+----+-------------+
+ 0 8 12 16 20 31
+
+`RXE format: <insn> R1,D2(X2,B2)'
+
+ +--------+----+----+----+-------------+--------+--------+
+ | OpCode | R1 | X2 | B2 | D2 |////////| OpCode |
+ +--------+----+----+----+-------------+--------+--------+
+ 0 8 12 16 20 32 40 47
+
+`RXF format: <insn> R1,R3,D2(X2,B2)'
+
+ +--------+----+----+----+-------------+----+---+--------+
+ | OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode |
+ +--------+----+----+----+-------------+----+---+--------+
+ 0 8 12 16 20 32 36 40 47
+
+`RXY format: <insn> R1,D2(X2,B2)'
+
+ +--------+----+----+----+-------------+--------+--------+
+ | OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode |
+ +--------+----+----+----+-------------+--------+--------+
+ 0 8 12 16 20 32 36 40 47
+
+`S format: <insn> D2(B2)'
+
+ +------------------+----+-------------+
+ | OpCode | B2 | D2 |
+ +------------------+----+-------------+
+ 0 16 20 31
+
+`SI format: <insn> D1(B1),I2'
+
+ +--------+---------+----+-------------+
+ | OpCode | I2 | B1 | D1 |
+ +--------+---------+----+-------------+
+ 0 8 16 20 31
+
+`SIY format: <insn> D1(B1),U2'
+
+ +--------+---------+----+-------------+--------+--------+
+ | OpCode | I2 | B1 | DL1 | DH1 | OpCode |
+ +--------+---------+----+-------------+--------+--------+
+ 0 8 16 20 32 36 40 47
+
+`SIL format: <insn> D1(B1),I2'
+
+ +------------------+----+-------------+-----------------+
+ | OpCode | B1 | D1 | I2 |
+ +------------------+----+-------------+-----------------+
+ 0 16 20 32 47
+
+`SS format: <insn> D1(R1,B1),D2(B3),R3'
+
+ +--------+----+----+----+-------------+----+------------+
+ | OpCode | R1 | R3 | B1 | D1 | B2 | D2 |
+ +--------+----+----+----+-------------+----+------------+
+ 0 8 12 16 20 32 36 47
+
+`SSE format: <insn> D1(B1),D2(B2)'
+
+ +------------------+----+-------------+----+------------+
+ | OpCode | B1 | D1 | B2 | D2 |
+ +------------------+----+-------------+----+------------+
+ 0 8 12 16 20 32 36 47
+
+`SSF format: <insn> D1(B1),D2(B2),R3'
+
+ +--------+----+----+----+-------------+----+------------+
+ | OpCode | R3 |OpCd| B1 | D1 | B2 | D2 |
+ +--------+----+----+----+-------------+----+------------+
+ 0 8 12 16 20 32 36 47
+
+
+ For the complete list of all instruction format variants see the
+Principles of Operation manuals.
+
+\1f
+File: as.info, Node: s390 Aliases, Next: s390 Operand Modifier, Prev: s390 Formats, Up: s390 Syntax
+
+9.30.3.5 Instruction Aliases
+............................
+
+A specific bit pattern can have multiple mnemonics, for example the bit
+pattern `0xa7000000' has the mnemonics `tmh' and `tmlh'. In addition,
+there are a number of mnemonics recognized by `as' that are not present
+in the Principles of Operation. These are the short forms of the
+branch instructions, where the condition code mask operand is encoded
+in the mnemonic. This is relevant for the branch instructions, the
+compare and branch instructions, and the compare and trap instructions.
+
+ For the branch instructions there are 20 condition code strings that
+can be used as part of the mnemonic in place of a mask operand in the
+instruction format:
+
+ instruction short form
+ ------------------------------------------
+ bcr M1,R2 b<m>r R2
+ bc M1,D2(X2,B2) b<m> D2(X2,B2)
+ brc M1,I2 j<m> I2
+ brcl M1,I2 jg<m> I2
+
+ In the mnemonic for a branch instruction the condition code string
+<m> can be any of the following:
+
+ o jump on overflow / if ones
+ h jump on A high
+ p jump on plus
+ nle jump on not low or equal
+ l jump on A low
+ m jump on minus
+ nhe jump on not high or equal
+ lh jump on low or high
+ ne jump on A not equal B
+ nz jump on not zero / if not zeros
+ e jump on A equal B
+ z jump on zero / if zeroes
+ nlh jump on not low or high
+ he jump on high or equal
+ nl jump on A not low
+ nm jump on not minus / if not mixed
+ le jump on low or equal
+ nh jump on A not high
+ np jump on not plus
+ no jump on not overflow / if not ones
+
+ For the compare and branch, and compare and trap instructions there
+are 12 condition code strings that can be used as part of the mnemonic
+in place of a mask operand in the instruction format:
+
+ instruction short form
+ --------------------------------------------------------
+ crb R1,R2,M3,D4(B4) crb<m> R1,R2,D4(B4)
+ cgrb R1,R2,M3,D4(B4) cgrb<m> R1,R2,D4(B4)
+ crj R1,R2,M3,I4 crj<m> R1,R2,I4
+ cgrj R1,R2,M3,I4 cgrj<m> R1,R2,I4
+ cib R1,I2,M3,D4(B4) cib<m> R1,I2,D4(B4)
+ cgib R1,I2,M3,D4(B4) cgib<m> R1,I2,D4(B4)
+ cij R1,I2,M3,I4 cij<m> R1,I2,I4
+ cgij R1,I2,M3,I4 cgij<m> R1,I2,I4
+ crt R1,R2,M3 crt<m> R1,R2
+ cgrt R1,R2,M3 cgrt<m> R1,R2
+ cit R1,I2,M3 cit<m> R1,I2
+ cgit R1,I2,M3 cgit<m> R1,I2
+ clrb R1,R2,M3,D4(B4) clrb<m> R1,R2,D4(B4)
+ clgrb R1,R2,M3,D4(B4) clgrb<m> R1,R2,D4(B4)
+ clrj R1,R2,M3,I4 clrj<m> R1,R2,I4
+ clgrj R1,R2,M3,I4 clgrj<m> R1,R2,I4
+ clib R1,I2,M3,D4(B4) clib<m> R1,I2,D4(B4)
+ clgib R1,I2,M3,D4(B4) clgib<m> R1,I2,D4(B4)
+ clij R1,I2,M3,I4 clij<m> R1,I2,I4
+ clgij R1,I2,M3,I4 clgij<m> R1,I2,I4
+ clrt R1,R2,M3 clrt<m> R1,R2
+ clgrt R1,R2,M3 clgrt<m> R1,R2
+ clfit R1,I2,M3 clfit<m> R1,I2
+ clgit R1,I2,M3 clgit<m> R1,I2
+
+ In the mnemonic for a compare and branch and compare and trap
+instruction the condition code string <m> can be any of the following:
+
+ h jump on A high
+ nle jump on not low or equal
+ l jump on A low
+ nhe jump on not high or equal
+ ne jump on A not equal B
+ lh jump on low or high
+ e jump on A equal B
+ nlh jump on not low or high
+ nl jump on A not low
+ he jump on high or equal
+ nh jump on A not high
+ le jump on low or equal
+
+\1f
+File: as.info, Node: s390 Operand Modifier, Next: s390 Instruction Marker, Prev: s390 Aliases, Up: s390 Syntax
+
+9.30.3.6 Instruction Operand Modifier
+.....................................
+
+If a symbol modifier is attached to a symbol in an expression for an
+instruction operand field, the symbol term is replaced with a reference
+to an object in the global offset table (GOT) or the procedure linkage
+table (PLT). The following expressions are allowed: `symbol@modifier +
+constant', `symbol@modifier + label + constant', and `symbol@modifier -
+label + constant'. The term `symbol' is the symbol that will be
+entered into the GOT or PLT, `label' is a local label, and `constant'
+is an arbitrary expression that the assembler can evaluate to a
+constant value.
+
+ The term `(symbol + constant1)@modifier +/- label + constant2' is
+also accepted but a warning message is printed and the term is
+converted to `symbol@modifier +/- label + constant1 + constant2'.
+
+`@got'
+`@got12'
+ The @got modifier can be used for displacement fields, 16-bit
+ immediate fields and 32-bit pc-relative immediate fields. The
+ @got12 modifier is synonym to @got. The symbol is added to the
+ GOT. For displacement fields and 16-bit immediate fields the
+ symbol term is replaced with the offset from the start of the GOT
+ to the GOT slot for the symbol. For a 32-bit pc-relative field
+ the pc-relative offset to the GOT slot from the current
+ instruction address is used.
+
+`@gotent'
+ The @gotent modifier can be used for 32-bit pc-relative immediate
+ fields. The symbol is added to the GOT and the symbol term is
+ replaced with the pc-relative offset from the current instruction
+ to the GOT slot for the symbol.
+
+`@gotoff'
+ The @gotoff modifier can be used for 16-bit immediate fields. The
+ symbol term is replaced with the offset from the start of the GOT
+ to the address of the symbol.
+
+`@gotplt'
+ The @gotplt modifier can be used for displacement fields, 16-bit
+ immediate fields, and 32-bit pc-relative immediate fields. A
+ procedure linkage table entry is generated for the symbol and a
+ jump slot for the symbol is added to the GOT. For displacement
+ fields and 16-bit immediate fields the symbol term is replaced
+ with the offset from the start of the GOT to the jump slot for the
+ symbol. For a 32-bit pc-relative field the pc-relative offset to
+ the jump slot from the current instruction address is used.
+
+`@plt'
+ The @plt modifier can be used for 16-bit and 32-bit pc-relative
+ immediate fields. A procedure linkage table entry is generated for
+ the symbol. The symbol term is replaced with the relative offset
+ from the current instruction to the PLT entry for the symbol.
+
+`@pltoff'
+ The @pltoff modifier can be used for 16-bit immediate fields. The
+ symbol term is replaced with the offset from the start of the PLT
+ to the address of the symbol.
+
+`@gotntpoff'
+ The @gotntpoff modifier can be used for displacement fields. The
+ symbol is added to the static TLS block and the negated offset to
+ the symbol in the static TLS block is added to the GOT. The symbol
+ term is replaced with the offset to the GOT slot from the start of
+ the GOT.
+
+`@indntpoff'
+ The @indntpoff modifier can be used for 32-bit pc-relative
+ immediate fields. The symbol is added to the static TLS block and
+ the negated offset to the symbol in the static TLS block is added
+ to the GOT. The symbol term is replaced with the pc-relative
+ offset to the GOT slot from the current instruction address.
+
+ For more information about the thread local storage modifiers
+`gotntpoff' and `indntpoff' see the ELF extension documentation `ELF
+Handling For Thread-Local Storage'.
+
+\1f
+File: as.info, Node: s390 Instruction Marker, Next: s390 Literal Pool Entries, Prev: s390 Operand Modifier, Up: s390 Syntax
+
+9.30.3.7 Instruction Marker
+...........................
+
+The thread local storage instruction markers are used by the linker to
+perform code optimization.
+
+`:tls_load'
+ The :tls_load marker is used to flag the load instruction in the
+ initial exec TLS model that retrieves the offset from the thread
+ pointer to a thread local storage variable from the GOT.
+
+`:tls_gdcall'
+ The :tls_gdcall marker is used to flag the branch-and-save
+ instruction to the __tls_get_offset function in the global dynamic
+ TLS model.
+
+`:tls_ldcall'
+ The :tls_ldcall marker is used to flag the branch-and-save
+ instruction to the __tls_get_offset function in the local dynamic
+ TLS model.
+
+ For more information about the thread local storage instruction
+marker and the linker optimizations see the ELF extension documentation
+`ELF Handling For Thread-Local Storage'.
+
+\1f
+File: as.info, Node: s390 Literal Pool Entries, Prev: s390 Instruction Marker, Up: s390 Syntax
+
+9.30.3.8 Literal Pool Entries
+.............................
+
+A literal pool is a collection of values. To access the values a pointer
+to the literal pool is loaded to a register, the literal pool register.
+Usually, register %r13 is used as the literal pool register (*Note s390
+Register::). Literal pool entries are created by adding the suffix
+:lit1, :lit2, :lit4, or :lit8 to the end of an expression for an
+instruction operand. The expression is added to the literal pool and the
+operand is replaced with the offset to the literal in the literal pool.
+
+`:lit1'
+ The literal pool entry is created as an 8-bit value. An operand
+ modifier must not be used for the original expression.
+
+`:lit2'
+ The literal pool entry is created as a 16 bit value. The operand
+ modifier @got may be used in the original expression. The term
+ `x@got:lit2' will put the got offset for the global symbol x to
+ the literal pool as 16 bit value.
+
+`:lit4'
+ The literal pool entry is created as a 32-bit value. The operand
+ modifier @got and @plt may be used in the original expression. The
+ term `x@got:lit4' will put the got offset for the global symbol x
+ to the literal pool as a 32-bit value. The term `x@plt:lit4' will
+ put the plt offset for the global symbol x to the literal pool as
+ a 32-bit value.
+
+`:lit8'
+ The literal pool entry is created as a 64-bit value. The operand
+ modifier @got and @plt may be used in the original expression. The
+ term `x@got:lit8' will put the got offset for the global symbol x
+ to the literal pool as a 64-bit value. The term `x@plt:lit8' will
+ put the plt offset for the global symbol x to the literal pool as
+ a 64-bit value.
+
+ The assembler directive `.ltorg' is used to emit all literal pool
+entries to the current position.
+
+\1f
+File: as.info, Node: s390 Directives, Next: s390 Floating Point, Prev: s390 Syntax, Up: S/390-Dependent
+
+9.30.4 Assembler Directives
+---------------------------
+
+`as' for s390 supports all of the standard ELF assembler directives as
+outlined in the main part of this document. Some directives have been
+extended and there are some additional directives, which are only
+available for the s390 `as'.
+
+`.insn'
+ This directive permits the numeric representation of an
+ instructions and makes the assembler insert the operands according
+ to one of the instructions formats for `.insn' (*Note s390
+ Formats::). For example, the instruction `l %r1,24(%r15)' could
+ be written as `.insn rx,0x58000000,%r1,24(%r15)'.
+
+`.short'
+`.long'
+`.quad'
+ This directive places one or more 16-bit (.short), 32-bit (.long),
+ or 64-bit (.quad) values into the current section. If an ELF or
+ TLS modifier is used only the following expressions are allowed:
+ `symbol@modifier + constant', `symbol@modifier + label +
+ constant', and `symbol@modifier - label + constant'. The
+ following modifiers are available:
+ `@got'
+ `@got12'
+ The @got modifier can be used for .short, .long and .quad.
+ The @got12 modifier is synonym to @got. The symbol is added
+ to the GOT. The symbol term is replaced with offset from the
+ start of the GOT to the GOT slot for the symbol.
+
+ `@gotoff'
+ The @gotoff modifier can be used for .short, .long and .quad.
+ The symbol term is replaced with the offset from the start of
+ the GOT to the address of the symbol.
+
+ `@gotplt'
+ The @gotplt modifier can be used for .long and .quad. A
+ procedure linkage table entry is generated for the symbol and
+ a jump slot for the symbol is added to the GOT. The symbol
+ term is replaced with the offset from the start of the GOT to
+ the jump slot for the symbol.
+
+ `@plt'
+ The @plt modifier can be used for .long and .quad. A
+ procedure linkage table entry us generated for the symbol.
+ The symbol term is replaced with the address of the PLT entry
+ for the symbol.
+
+ `@pltoff'
+ The @pltoff modifier can be used for .short, .long and .quad.
+ The symbol term is replaced with the offset from the start of
+ the PLT to the address of the symbol.
+
+ `@tlsgd'
+ `@tlsldm'
+ The @tlsgd and @tlsldm modifier can be used for .long and
+ .quad. A tls_index structure for the symbol is added to the
+ GOT. The symbol term is replaced with the offset from the
+ start of the GOT to the tls_index structure.
+
+ `@gotntpoff'
+ `@indntpoff'
+ The @gotntpoff and @indntpoff modifier can be used for .long
+ and .quad. The symbol is added to the static TLS block and
+ the negated offset to the symbol in the static TLS block is
+ added to the GOT. For @gotntpoff the symbol term is replaced
+ with the offset from the start of the GOT to the GOT slot,
+ for @indntpoff the symbol term is replaced with the address
+ of the GOT slot.
+
+ `@dtpoff'
+ The @dtpoff modifier can be used for .long and .quad. The
+ symbol term is replaced with the offset of the symbol
+ relative to the start of the TLS block it is contained in.
+
+ `@ntpoff'
+ The @ntpoff modifier can be used for .long and .quad. The
+ symbol term is replaced with the offset of the symbol
+ relative to the TCB pointer.
+
+ For more information about the thread local storage modifiers see
+ the ELF extension documentation `ELF Handling For Thread-Local
+ Storage'.
+
+`.ltorg'
+ This directive causes the current contents of the literal pool to
+ be dumped to the current location (*Note s390 Literal Pool
+ Entries::).
+
+\1f
+File: as.info, Node: s390 Floating Point, Prev: s390 Directives, Up: S/390-Dependent
+
+9.30.5 Floating Point
+---------------------
+
+The assembler recognizes both the IEEE floating-point instruction and
+the hexadecimal floating-point instructions. The floating-point
+constructors `.float', `.single', and `.double' always emit the IEEE
+format. To assemble hexadecimal floating-point constants the `.long'
+and `.quad' directives must be used.
+
+\1f
+File: as.info, Node: SCORE-Dependent, Next: Sparc-Dependent, Prev: S/390-Dependent, Up: Machine Dependencies
+
+9.31 SCORE Dependent Features
+=============================
+
+* Menu:
+
+* SCORE-Opts:: Assembler options
+* SCORE-Pseudo:: SCORE Assembler Directives
+
+\1f
+File: as.info, Node: SCORE-Opts, Next: SCORE-Pseudo, Up: SCORE-Dependent
+
+9.31.1 Options
+--------------
+
+The following table lists all available SCORE options.
+
+`-G NUM'
+ This option sets the largest size of an object that can be
+ referenced implicitly with the `gp' register. The default value is
+ 8.
+
+`-EB'
+ Assemble code for a big-endian cpu
+
+`-EL'
+ Assemble code for a little-endian cpu
+
+`-FIXDD'
+ Assemble code for fix data dependency
+
+`-NWARN'
+ Assemble code for no warning message for fix data dependency
-`-me500, -me500x2'
- Generate code for Motorola e500 core complex.
+`-SCORE5'
+ Assemble code for target is SCORE5
-`-mspe'
- Generate code for Motorola SPE instructions.
+`-SCORE5U'
+ Assemble code for target is SCORE5U
-`-mppc64bridge'
- Generate code for PowerPC 64, including bridge insns.
+`-SCORE7'
+ Assemble code for target is SCORE7, this is default setting
-`-mbooke64'
- Generate code for 64-bit BookE.
+`-SCORE3'
+ Assemble code for target is SCORE3
-`-mbooke, mbooke32'
- Generate code for 32-bit BookE.
+`-march=score7'
+ Assemble code for target is SCORE7, this is default setting
-`-me300'
- Generate code for PowerPC e300 family.
+`-march=score3'
+ Assemble code for target is SCORE3
-`-maltivec'
- Generate code for processors with AltiVec instructions.
+`-USE_R1'
+ Assemble code for no warning message when using temp register r1
-`-mpower4'
- Generate code for Power4 architecture.
+`-KPIC'
+ Generate code for PIC. This option tells the assembler to generate
+ score position-independent macro expansions. It also tells the
+ assembler to mark the output file as PIC.
-`-mpower5'
- Generate code for Power5 architecture.
+`-O0'
+ Assembler will not perform any optimizations
-`-mpower6'
- Generate code for Power6 architecture.
+`-V'
+ Sunplus release version
-`-mcell'
- Generate code for Cell Broadband Engine architecture.
-`-mcom'
- Generate code Power/PowerPC common instructions.
+\1f
+File: as.info, Node: SCORE-Pseudo, Prev: SCORE-Opts, Up: SCORE-Dependent
-`-many'
- Generate code for any architecture (PWR/PWRX/PPC).
+9.31.2 SCORE Assembler Directives
+---------------------------------
-`-mregnames'
- Allow symbolic names for registers.
+A number of assembler directives are available for SCORE. The
+following table is far from complete.
-`-mno-regnames'
- Do not allow symbolic names for registers.
+`.set nwarn'
+ Let the assembler not to generate warnings if the source machine
+ language instructions happen data dependency.
-`-mrelocatable'
- Support for GCC's -mrelocatable option.
+`.set fixdd'
+ Let the assembler to insert bubbles (32 bit nop instruction / 16
+ bit nop! Instruction) if the source machine language instructions
+ happen data dependency.
-`-mrelocatable-lib'
- Support for GCC's -mrelocatable-lib option.
+`.set nofixdd'
+ Let the assembler to generate warnings if the source machine
+ language instructions happen data dependency. (Default)
-`-memb'
- Set PPC_EMB bit in ELF flags.
+`.set r1'
+ Let the assembler not to generate warnings if the source program
+ uses r1. allow user to use r1
-`-mlittle, -mlittle-endian'
- Generate code for a little endian machine.
+`set nor1'
+ Let the assembler to generate warnings if the source program uses
+ r1. (Default)
-`-mbig, -mbig-endian'
- Generate code for a big endian machine.
+`.sdata'
+ Tell the assembler to add subsequent data into the sdata section
-`-msolaris'
- Generate code for Solaris.
+`.rdata'
+ Tell the assembler to add subsequent data into the rdata section
-`-mno-solaris'
- Do not generate code for Solaris.
+`.frame "frame-register", "offset", "return-pc-register"'
+ Describe a stack frame. "frame-register" is the frame register,
+ "offset" is the distance from the frame register to the virtual
+ frame pointer, "return-pc-register" is the return program register.
+ You must use ".ent" before ".frame" and only one ".frame" can be
+ used per ".ent".
-\1f
-File: as.info, Node: PowerPC-Pseudo, Prev: PowerPC-Opts, Up: PPC-Dependent
+`.mask "bitmask", "frameoffset"'
+ Indicate which of the integer registers are saved in the current
+ function's stack frame, this is for the debugger to explain the
+ frame chain.
-8.27.2 PowerPC Assembler Directives
------------------------------------
+`.ent "proc-name"'
+ Set the beginning of the procedure "proc_name". Use this directive
+ when you want to generate information for the debugger.
-A number of assembler directives are available for PowerPC. The
-following table is far from complete.
+`.end proc-name'
+ Set the end of a procedure. Use this directive to generate
+ information for the debugger.
+
+`.bss'
+ Switch the destination of following statements into the bss
+ section, which is used for data that is uninitialized anywhere.
-`.machine "string"'
- This directive allows you to change the machine for which code is
- generated. `"string"' may be any of the -m cpu selection options
- (without the -m) enclosed in double quotes, `"push"', or `"pop"'.
- `.machine "push"' saves the currently selected cpu, which may be
- restored with `.machine "pop"'.
\1f
File: as.info, Node: SH-Dependent, Next: SH64-Dependent, Prev: MSP430-Dependent, Up: Machine Dependencies
-8.28 Renesas / SuperH SH Dependent Features
+9.32 Renesas / SuperH SH Dependent Features
===========================================
* Menu:
\1f
File: as.info, Node: SH Options, Next: SH Syntax, Up: SH-Dependent
-8.28.1 Options
+9.32.1 Options
--------------
`as' has following command-line options for the Renesas (formerly
`--isa=all'
Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
+`-h-tick-hex'
+ Support H'00 style hex constants in addition to 0x00 style.
+
\1f
File: as.info, Node: SH Syntax, Next: SH Floating Point, Prev: SH Options, Up: SH-Dependent
-8.28.2 Syntax
+9.32.2 Syntax
-------------
* Menu:
\1f
File: as.info, Node: SH-Chars, Next: SH-Regs, Up: SH Syntax
-8.28.2.1 Special Characters
+9.32.2.1 Special Characters
...........................
`!' is the line comment character.
\1f
File: as.info, Node: SH-Regs, Next: SH-Addressing, Prev: SH-Chars, Up: SH Syntax
-8.28.2.2 Register Names
+9.32.2.2 Register Names
.......................
You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', `r5',
\1f
File: as.info, Node: SH-Addressing, Prev: SH-Regs, Up: SH Syntax
-8.28.2.3 Addressing Modes
+9.32.2.3 Addressing Modes
.........................
`as' understands the following addressing modes for the SH. `RN' in
\1f
File: as.info, Node: SH Floating Point, Next: SH Directives, Prev: SH Syntax, Up: SH-Dependent
-8.28.3 Floating Point
+9.32.3 Floating Point
---------------------
SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
\1f
File: as.info, Node: SH Directives, Next: SH Opcodes, Prev: SH Floating Point, Up: SH-Dependent
-8.28.4 SH Machine Directives
+9.32.4 SH Machine Directives
----------------------------
`uaword'
\1f
File: as.info, Node: SH Opcodes, Prev: SH Directives, Up: SH-Dependent
-8.28.5 Opcodes
+9.32.5 Opcodes
--------------
For detailed information on the SH machine instruction set, see
\1f
File: as.info, Node: SH64-Dependent, Next: PDP-11-Dependent, Prev: SH-Dependent, Up: Machine Dependencies
-8.29 SuperH SH64 Dependent Features
+9.33 SuperH SH64 Dependent Features
===================================
* Menu:
\1f
File: as.info, Node: SH64 Options, Next: SH64 Syntax, Up: SH64-Dependent
-8.29.1 Options
+9.33.1 Options
--------------
`-isa=sh4 | sh4a'
`-expand-pt32'
With -abi=64, expand PT, PTA and PTB instructions to 32 bits only.
+`-h-tick-hex'
+ Support H'00 style hex constants in addition to 0x00 style.
+
\1f
File: as.info, Node: SH64 Syntax, Next: SH64 Directives, Prev: SH64 Options, Up: SH64-Dependent
-8.29.2 Syntax
+9.33.2 Syntax
-------------
* Menu:
\1f
File: as.info, Node: SH64-Chars, Next: SH64-Regs, Up: SH64 Syntax
-8.29.2.1 Special Characters
+9.33.2.1 Special Characters
...........................
`!' is the line comment character.
\1f
File: as.info, Node: SH64-Regs, Next: SH64-Addressing, Prev: SH64-Chars, Up: SH64 Syntax
-8.29.2.2 Register Names
+9.33.2.2 Register Names
.......................
You can use the predefined symbols `r0' through `r63' to refer to the
\1f
File: as.info, Node: SH64-Addressing, Prev: SH64-Regs, Up: SH64 Syntax
-8.29.2.3 Addressing Modes
+9.33.2.3 Addressing Modes
.........................
SH64 operands consist of either a register or immediate value. The
\1f
File: as.info, Node: SH64 Directives, Next: SH64 Opcodes, Prev: SH64 Syntax, Up: SH64-Dependent
-8.29.3 SH64 Machine Directives
+9.33.3 SH64 Machine Directives
------------------------------
In addition to the SH directives, the SH64 provides the following
\1f
File: as.info, Node: SH64 Opcodes, Prev: SH64 Directives, Up: SH64-Dependent
-8.29.4 Opcodes
+9.33.4 Opcodes
--------------
For detailed information on the SH64 machine instruction set, see
\1f
-File: as.info, Node: Sparc-Dependent, Next: TIC54X-Dependent, Prev: PPC-Dependent, Up: Machine Dependencies
+File: as.info, Node: Sparc-Dependent, Next: TIC54X-Dependent, Prev: SCORE-Dependent, Up: Machine Dependencies
-8.30 SPARC Dependent Features
+9.34 SPARC Dependent Features
=============================
* Menu:
* Sparc-Opts:: Options
* Sparc-Aligned-Data:: Option to enforce aligned data
+* Sparc-Syntax:: Syntax
* Sparc-Float:: Floating Point
* Sparc-Directives:: Sparc Machine Directives
\1f
File: as.info, Node: Sparc-Opts, Next: Sparc-Aligned-Data, Up: Sparc-Dependent
-8.30.1 Options
+9.34.1 Options
--------------
-The SPARC chip family includes several successive levels, using the same
-core instruction set, but including a few additional instructions at
-each level. There are exceptions to this however. For details on what
-instructions each variant supports, please see the chip's architecture
-reference manual.
+The SPARC chip family includes several successive versions, using the
+same core instruction set, but including a few additional instructions
+at each version. There are exceptions to this however. For details on
+what instructions each variant supports, please see the chip's
+architecture reference manual.
By default, `as' assumes the core instruction set (SPARC v6), but
"bumps" the architecture level as needed: it switches to successively
the higher levels.
If not configured for SPARC v9 (`sparc64-*-*') GAS will not bump
-passed sparclite by default, an option must be passed to enable the v9
+past sparclite by default, an option must be passed to enable the v9
instructions.
GAS treats sparclite as being compatible with v8, unless an
UltraSPARC extensions.
`-xarch=v8plus | -xarch=v8plusa'
- For compatibility with the Solaris v9 assembler. These options are
+ For compatibility with the SunOS v9 assembler. These options are
equivalent to -Av8plus and -Av8plusa, respectively.
`-bump'
that the necessary BFD support has been included.
\1f
-File: as.info, Node: Sparc-Aligned-Data, Next: Sparc-Float, Prev: Sparc-Opts, Up: Sparc-Dependent
+File: as.info, Node: Sparc-Aligned-Data, Next: Sparc-Syntax, Prev: Sparc-Opts, Up: Sparc-Dependent
-8.30.2 Enforcing aligned data
+9.34.2 Enforcing aligned data
-----------------------------
SPARC GAS normally permits data to be misaligned. For example, it
permits the `.long' pseudo-op to be used on a byte boundary. However,
-the native SunOS and Solaris assemblers issue an error when they see
-misaligned data.
+the native SunOS assemblers issue an error when they see misaligned
+data.
You can use the `--enforce-aligned-data' option to make SPARC GAS
-also issue an error about misaligned data, just as the SunOS and Solaris
-assemblers do.
+also issue an error about misaligned data, just as the SunOS assemblers
+do.
The `--enforce-aligned-data' option is not the default because gcc
issues misaligned data pseudo-ops when it initializes certain packed
structures in your own code.
\1f
-File: as.info, Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Aligned-Data, Up: Sparc-Dependent
+File: as.info, Node: Sparc-Syntax, Next: Sparc-Float, Prev: Sparc-Aligned-Data, Up: Sparc-Dependent
+
+9.34.3 Sparc Syntax
+-------------------
+
+The assembler syntax closely follows The Sparc Architecture Manual,
+versions 8 and 9, as well as most extensions defined by Sun for their
+UltraSPARC and Niagara line of processors.
+
+* Menu:
+
+* Sparc-Chars:: Special Characters
+* Sparc-Regs:: Register Names
+* Sparc-Constants:: Constant Names
+* Sparc-Relocs:: Relocations
+* Sparc-Size-Translations:: Size Translations
+
+\1f
+File: as.info, Node: Sparc-Chars, Next: Sparc-Regs, Up: Sparc-Syntax
+
+9.34.3.1 Special Characters
+...........................
+
+`#' is the line comment character.
+
+ `;' can be used instead of a newline to separate statements.
+
+\1f
+File: as.info, Node: Sparc-Regs, Next: Sparc-Constants, Prev: Sparc-Chars, Up: Sparc-Syntax
+
+9.34.3.2 Register Names
+.......................
+
+The Sparc integer register file is broken down into global, outgoing,
+local, and incoming.
+
+ * The 8 global registers are referred to as `%gN'.
+
+ * The 8 outgoing registers are referred to as `%oN'.
+
+ * The 8 local registers are referred to as `%lN'.
+
+ * The 8 incoming registers are referred to as `%iN'.
+
+ * The frame pointer register `%i6' can be referenced using the alias
+ `%fp'.
+
+ * The stack pointer register `%o6' can be referenced using the alias
+ `%sp'.
+
+ Floating point registers are simply referred to as `%fN'. When
+assembling for pre-V9, only 32 floating point registers are available.
+For V9 and later there are 64, but there are restrictions when
+referencing the upper 32 registers. They can only be accessed as
+double or quad, and thus only even or quad numbered accesses are
+allowed. For example, `%f34' is a legal floating point register, but
+`%f35' is not.
+
+ Certain V9 instructions allow access to ancillary state registers.
+Most simply they can be referred to as `%asrN' where N can be from 16
+to 31. However, there are some aliases defined to reference ASR
+registers defined for various UltraSPARC processors:
+
+ * The tick compare register is referred to as `%tick_cmpr'.
+
+ * The system tick register is referred to as `%stick'. An alias,
+ `%sys_tick', exists but is deprecated and should not be used by
+ new software.
+
+ * The system tick compare register is referred to as `%stick_cmpr'.
+ An alias, `%sys_tick_cmpr', exists but is deprecated and should
+ not be used by new software.
+
+ * The software interrupt register is referred to as `%softint'.
+
+ * The set software interrupt register is referred to as
+ `%set_softint'. The mnemonic `%softint_set' is provided as an
+ alias.
+
+ * The clear software interrupt register is referred to as
+ `%clear_softint'. The mnemonic `%softint_clear' is provided as an
+ alias.
+
+ * The performance instrumentation counters register is referred to as
+ `%pic'.
+
+ * The performance control register is referred to as `%pcr'.
+
+ * The graphics status register is referred to as `%gsr'.
+
+ * The V9 dispatch control register is referred to as `%dcr'.
+
+ Various V9 branch and conditional move instructions allow
+specification of which set of integer condition codes to test. These
+are referred to as `%xcc' and `%icc'.
+
+ In V9, there are 4 sets of floating point condition codes which are
+referred to as `%fccN'.
+
+ Several special privileged and non-privileged registers exist:
+
+ * The V9 address space identifier register is referred to as `%asi'.
+
+ * The V9 restorable windows register is referred to as `%canrestore'.
+
+ * The V9 savable windows register is referred to as `%cansave'.
+
+ * The V9 clean windows register is referred to as `%cleanwin'.
+
+ * The V9 current window pointer register is referred to as `%cwp'.
+
+ * The floating-point queue register is referred to as `%fq'.
+
+ * The V8 co-processor queue register is referred to as `%cq'.
+
+ * The floating point status register is referred to as `%fsr'.
+
+ * The other windows register is referred to as `%otherwin'.
+
+ * The V9 program counter register is referred to as `%pc'.
+
+ * The V9 next program counter register is referred to as `%npc'.
+
+ * The V9 processor interrupt level register is referred to as `%pil'.
+
+ * The V9 processor state register is referred to as `%pstate'.
+
+ * The trap base address register is referred to as `%tba'.
+
+ * The V9 tick register is referred to as `%tick'.
+
+ * The V9 trap level is referred to as `%tl'.
+
+ * The V9 trap program counter is referred to as `%tpc'.
+
+ * The V9 trap next program counter is referred to as `%tnpc'.
+
+ * The V9 trap state is referred to as `%tstate'.
+
+ * The V9 trap type is referred to as `%tt'.
+
+ * The V9 condition codes is referred to as `%ccr'.
+
+ * The V9 floating-point registers state is referred to as `%fprs'.
+
+ * The V9 version register is referred to as `%ver'.
+
+ * The V9 window state register is referred to as `%wstate'.
+
+ * The Y register is referred to as `%y'.
+
+ * The V8 window invalid mask register is referred to as `%wim'.
+
+ * The V8 processor state register is referred to as `%psr'.
+
+ * The V9 global register level register is referred to as `%gl'.
+
+ Several special register names exist for hypervisor mode code:
+
+ * The hyperprivileged processor state register is referred to as
+ `%hpstate'.
+
+ * The hyperprivileged trap state register is referred to as
+ `%htstate'.
+
+ * The hyperprivileged interrupt pending register is referred to as
+ `%hintp'.
+
+ * The hyperprivileged trap base address register is referred to as
+ `%htba'.
+
+ * The hyperprivileged implementation version register is referred to
+ as `%hver'.
+
+ * The hyperprivileged system tick compare register is referred to as
+ `%hstick_cmpr'. Note that there is no `%hstick' register, the
+ normal `%stick' is used.
+
+\1f
+File: as.info, Node: Sparc-Constants, Next: Sparc-Relocs, Prev: Sparc-Regs, Up: Sparc-Syntax
+
+9.34.3.3 Constants
+..................
+
+Several Sparc instructions take an immediate operand field for which
+mnemonic names exist. Two such examples are `membar' and `prefetch'.
+Another example are the set of V9 memory access instruction that allow
+specification of an address space identifier.
+
+ The `membar' instruction specifies a memory barrier that is the
+defined by the operand which is a bitmask. The supported mask
+mnemonics are:
+
+ * `#Sync' requests that all operations (including nonmemory
+ reference operations) appearing prior to the `membar' must have
+ been performed and the effects of any exceptions become visible
+ before any instructions after the `membar' may be initiated. This
+ corresponds to `membar' cmask field bit 2.
+
+ * `#MemIssue' requests that all memory reference operations
+ appearing prior to the `membar' must have been performed before
+ any memory operation after the `membar' may be initiated. This
+ corresponds to `membar' cmask field bit 1.
+
+ * `#Lookaside' requests that a store appearing prior to the `membar'
+ must complete before any load following the `membar' referencing
+ the same address can be initiated. This corresponds to `membar'
+ cmask field bit 0.
+
+ * `#StoreStore' defines that the effects of all stores appearing
+ prior to the `membar' instruction must be visible to all
+ processors before the effect of any stores following the `membar'.
+ Equivalent to the deprecated `stbar' instruction. This
+ corresponds to `membar' mmask field bit 3.
+
+ * `#LoadStore' defines all loads appearing prior to the `membar'
+ instruction must have been performed before the effect of any
+ stores following the `membar' is visible to any other processor.
+ This corresponds to `membar' mmask field bit 2.
+
+ * `#StoreLoad' defines that the effects of all stores appearing
+ prior to the `membar' instruction must be visible to all
+ processors before loads following the `membar' may be performed.
+ This corresponds to `membar' mmask field bit 1.
+
+ * `#LoadLoad' defines that all loads appearing prior to the `membar'
+ instruction must have been performed before any loads following
+ the `membar' may be performed. This corresponds to `membar' mmask
+ field bit 0.
+
+
+ These values can be ored together, for example:
+
+ membar #Sync
+ membar #StoreLoad | #LoadLoad
+ membar #StoreLoad | #StoreStore
+
+ The `prefetch' and `prefetcha' instructions take a prefetch function
+code. The following prefetch function code constant mnemonics are
+available:
+
+ * `#n_reads' requests a prefetch for several reads, and corresponds
+ to a prefetch function code of 0.
+
+ `#one_read' requests a prefetch for one read, and corresponds to a
+ prefetch function code of 1.
+
+ `#n_writes' requests a prefetch for several writes (and possibly
+ reads), and corresponds to a prefetch function code of 2.
+
+ `#one_write' requests a prefetch for one write, and corresponds to
+ a prefetch function code of 3.
+
+ `#page' requests a prefetch page, and corresponds to a prefetch
+ function code of 4.
+
+ `#invalidate' requests a prefetch invalidate, and corresponds to a
+ prefetch function code of 16.
+
+ `#unified' requests a prefetch to the nearest unified cache, and
+ corresponds to a prefetch function code of 17.
+
+ `#n_reads_strong' requests a strong prefetch for several reads,
+ and corresponds to a prefetch function code of 20.
+
+ `#one_read_strong' requests a strong prefetch for one read, and
+ corresponds to a prefetch function code of 21.
+
+ `#n_writes_strong' requests a strong prefetch for several writes,
+ and corresponds to a prefetch function code of 22.
+
+ `#one_write_strong' requests a strong prefetch for one write, and
+ corresponds to a prefetch function code of 23.
+
+ Onle one prefetch code may be specified. Here are some examples:
+
+ prefetch [%l0 + %l2], #one_read
+ prefetch [%g2 + 8], #n_writes
+ prefetcha [%g1] 0x8, #unified
+ prefetcha [%o0 + 0x10] %asi, #n_reads
+
+ The actual behavior of a given prefetch function code is processor
+ specific. If a processor does not implement a given prefetch
+ function code, it will treat the prefetch instruction as a nop.
+
+ For instructions that accept an immediate address space identifier,
+ `as' provides many mnemonics corresponding to V9 defined as well
+ as UltraSPARC and Niagara extended values. For example, `#ASI_P'
+ and `#ASI_BLK_INIT_QUAD_LDD_AIUS'. See the V9 and processor
+ specific manuals for details.
+
+
+\1f
+File: as.info, Node: Sparc-Relocs, Next: Sparc-Size-Translations, Prev: Sparc-Constants, Up: Sparc-Syntax
+
+9.34.3.4 Relocations
+....................
+
+ELF relocations are available as defined in the 32-bit and 64-bit Sparc
+ELF specifications.
+
+ `R_SPARC_HI22' is obtained using `%hi' and `R_SPARC_LO10' is
+obtained using `%lo'. Likewise `R_SPARC_HIX22' is obtained from `%hix'
+and `R_SPARC_LOX10' is obtained using `%lox'. For example:
+
+ sethi %hi(symbol), %g1
+ or %g1, %lo(symbol), %g1
+
+ sethi %hix(symbol), %g1
+ xor %g1, %lox(symbol), %g1
+
+ These "high" mnemonics extract bits 31:10 of their operand, and the
+"low" mnemonics extract bits 9:0 of their operand.
+
+ V9 code model relocations can be requested as follows:
+
+ * `R_SPARC_HH22' is requested using `%hh'. It can also be generated
+ using `%uhi'.
+
+ * `R_SPARC_HM10' is requested using `%hm'. It can also be generated
+ using `%ulo'.
+
+ * `R_SPARC_LM22' is requested using `%lm'.
+
+ * `R_SPARC_H44' is requested using `%h44'.
+
+ * `R_SPARC_M44' is requested using `%m44'.
+
+ * `R_SPARC_L44' is requested using `%l44'.
+
+ The PC relative relocation `R_SPARC_PC22' can be obtained by
+enclosing an operand inside of `%pc22'. Likewise, the `R_SPARC_PC10'
+relocation can be obtained using `%pc10'. These are mostly used when
+assembling PIC code. For example, the standard PIC sequence on Sparc
+to get the base of the global offset table, PC relative, into a
+register, can be performed as:
+
+ sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7
+ add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7
+
+ Several relocations exist to allow the link editor to potentially
+optimize GOT data references. The `R_SPARC_GOTDATA_OP_HIX22'
+relocation can obtained by enclosing an operand inside of
+`%gdop_hix22'. The `R_SPARC_GOTDATA_OP_LOX10' relocation can obtained
+by enclosing an operand inside of `%gdop_lox10'. Likewise,
+`R_SPARC_GOTDATA_OP' can be obtained by enclosing an operand inside of
+`%gdop'. For example, assuming the GOT base is in register `%l7':
+
+ sethi %gdop_hix22(symbol), %l1
+ xor %l1, %gdop_lox10(symbol), %l1
+ ld [%l7 + %l1], %l2, %gdop(symbol)
+
+ There are many relocations that can be requested for access to
+thread local storage variables. All of the Sparc TLS mnemonics are
+supported:
+
+ * `R_SPARC_TLS_GD_HI22' is requested using `%tgd_hi22'.
+
+ * `R_SPARC_TLS_GD_LO10' is requested using `%tgd_lo10'.
+
+ * `R_SPARC_TLS_GD_ADD' is requested using `%tgd_add'.
+
+ * `R_SPARC_TLS_GD_CALL' is requested using `%tgd_call'.
+
+ * `R_SPARC_TLS_LDM_HI22' is requested using `%tldm_hi22'.
+
+ * `R_SPARC_TLS_LDM_LO10' is requested using `%tldm_lo10'.
+
+ * `R_SPARC_TLS_LDM_ADD' is requested using `%tldm_add'.
+
+ * `R_SPARC_TLS_LDM_CALL' is requested using `%tldm_call'.
+
+ * `R_SPARC_TLS_LDO_HIX22' is requested using `%tldo_hix22'.
+
+ * `R_SPARC_TLS_LDO_LOX10' is requested using `%tldo_lox10'.
+
+ * `R_SPARC_TLS_LDO_ADD' is requested using `%tldo_add'.
+
+ * `R_SPARC_TLS_IE_HI22' is requested using `%tie_hi22'.
+
+ * `R_SPARC_TLS_IE_LO10' is requested using `%tie_lo10'.
+
+ * `R_SPARC_TLS_IE_LD' is requested using `%tie_ld'.
+
+ * `R_SPARC_TLS_IE_LDX' is requested using `%tie_ldx'.
+
+ * `R_SPARC_TLS_IE_ADD' is requested using `%tie_add'.
+
+ * `R_SPARC_TLS_LE_HIX22' is requested using `%tle_hix22'.
+
+ * `R_SPARC_TLS_LE_LOX10' is requested using `%tle_lox10'.
+
+ Here are some example TLS model sequences.
+
+ First, General Dynamic:
+
+ sethi %tgd_hi22(symbol), %l1
+ add %l1, %tgd_lo10(symbol), %l1
+ add %l7, %l1, %o0, %tgd_add(symbol)
+ call __tls_get_addr, %tgd_call(symbol)
+ nop
+
+ Local Dynamic:
+
+ sethi %tldm_hi22(symbol), %l1
+ add %l1, %tldm_lo10(symbol), %l1
+ add %l7, %l1, %o0, %tldm_add(symbol)
+ call __tls_get_addr, %tldm_call(symbol)
+ nop
+
+ sethi %tldo_hix22(symbol), %l1
+ xor %l1, %tldo_lox10(symbol), %l1
+ add %o0, %l1, %l1, %tldo_add(symbol)
+
+ Initial Exec:
+
+ sethi %tie_hi22(symbol), %l1
+ add %l1, %tie_lo10(symbol), %l1
+ ld [%l7 + %l1], %o0, %tie_ld(symbol)
+ add %g7, %o0, %o0, %tie_add(symbol)
+
+ sethi %tie_hi22(symbol), %l1
+ add %l1, %tie_lo10(symbol), %l1
+ ldx [%l7 + %l1], %o0, %tie_ldx(symbol)
+ add %g7, %o0, %o0, %tie_add(symbol)
+
+ And finally, Local Exec:
+
+ sethi %tle_hix22(symbol), %l1
+ add %l1, %tle_lox10(symbol), %l1
+ add %g7, %l1, %l1
+
+ When assembling for 64-bit, and a secondary constant addend is
+specified in an address expression that would normally generate an
+`R_SPARC_LO10' relocation, the assembler will emit an `R_SPARC_OLO10'
+instead.
+
+\1f
+File: as.info, Node: Sparc-Size-Translations, Prev: Sparc-Relocs, Up: Sparc-Syntax
+
+9.34.3.5 Size Translations
+..........................
-8.30.3 Floating Point
+Often it is desirable to write code in an operand size agnostic manner.
+`as' provides support for this via operand size opcode translations.
+Translations are supported for loads, stores, shifts, compare-and-swap
+atomics, and the `clr' synthetic instruction.
+
+ If generating 32-bit code, `as' will generate the 32-bit opcode.
+Whereas if 64-bit code is being generated, the 64-bit opcode will be
+emitted. For example `ldn' will be transformed into `ld' for 32-bit
+code and `ldx' for 64-bit code.
+
+ Here is an example meant to demonstrate all the supported opcode
+translations:
+
+ ldn [%o0], %o1
+ ldna [%o0] %asi, %o2
+ stn %o1, [%o0]
+ stna %o2, [%o0] %asi
+ slln %o3, 3, %o3
+ srln %o4, 8, %o4
+ sran %o5, 12, %o5
+ casn [%o0], %o1, %o2
+ casna [%o0] %asi, %o1, %o2
+ clrn %g1
+
+ In 32-bit mode `as' will emit:
+
+ ld [%o0], %o1
+ lda [%o0] %asi, %o2
+ st %o1, [%o0]
+ sta %o2, [%o0] %asi
+ sll %o3, 3, %o3
+ srl %o4, 8, %o4
+ sra %o5, 12, %o5
+ cas [%o0], %o1, %o2
+ casa [%o0] %asi, %o1, %o2
+ clr %g1
+
+ And in 64-bit mode `as' will emit:
+
+ ldx [%o0], %o1
+ ldxa [%o0] %asi, %o2
+ stx %o1, [%o0]
+ stxa %o2, [%o0] %asi
+ sllx %o3, 3, %o3
+ srlx %o4, 8, %o4
+ srax %o5, 12, %o5
+ casx [%o0], %o1, %o2
+ casxa [%o0] %asi, %o1, %o2
+ clrx %g1
+
+ Finally, the `.nword' translating directive is supported as well.
+It is documented in the section on Sparc machine directives.
+
+\1f
+File: as.info, Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Syntax, Up: Sparc-Dependent
+
+9.34.4 Floating Point
---------------------
The Sparc uses IEEE floating-point numbers.
\1f
File: as.info, Node: Sparc-Directives, Prev: Sparc-Float, Up: Sparc-Dependent
-8.30.4 Sparc Machine Directives
+9.34.5 Sparc Machine Directives
-------------------------------
The Sparc version of `as' supports the following additional machine
\1f
File: as.info, Node: TIC54X-Dependent, Next: V850-Dependent, Prev: Sparc-Dependent, Up: Machine Dependencies
-8.31 TIC54X Dependent Features
+9.35 TIC54X Dependent Features
==============================
* Menu:
\1f
File: as.info, Node: TIC54X-Opts, Next: TIC54X-Block, Up: TIC54X-Dependent
-8.31.1 Options
+9.35.1 Options
--------------
The TMS320C54X version of `as' has a few machine-dependent options.
\1f
File: as.info, Node: TIC54X-Block, Next: TIC54X-Env, Prev: TIC54X-Opts, Up: TIC54X-Dependent
-8.31.2 Blocking
+9.35.2 Blocking
---------------
A blocked section or memory block is guaranteed not to cross the
\1f
File: as.info, Node: TIC54X-Env, Next: TIC54X-Constants, Prev: TIC54X-Block, Up: TIC54X-Dependent
-8.31.3 Environment Settings
+9.35.3 Environment Settings
---------------------------
`C54XDSP_DIR' and `A_DIR' are semicolon-separated paths which are added
\1f
File: as.info, Node: TIC54X-Constants, Next: TIC54X-Subsyms, Prev: TIC54X-Env, Up: TIC54X-Dependent
-8.31.4 Constants Syntax
+9.35.4 Constants Syntax
-----------------------
The TIC54X version of `as' allows the following additional constant
\1f
File: as.info, Node: TIC54X-Subsyms, Next: TIC54X-Locals, Prev: TIC54X-Constants, Up: TIC54X-Dependent
-8.31.5 String Substitution
+9.35.5 String Substitution
--------------------------
A subset of allowable symbols (which we'll call subsyms) may be assigned
\1f
File: as.info, Node: TIC54X-Locals, Next: TIC54X-Builtins, Prev: TIC54X-Subsyms, Up: TIC54X-Dependent
-8.31.6 Local Labels
+9.35.6 Local Labels
-------------------
Local labels may be defined in two ways:
\1f
File: as.info, Node: TIC54X-Builtins, Next: TIC54X-Ext, Prev: TIC54X-Locals, Up: TIC54X-Dependent
-8.31.7 Math Builtins
+9.35.7 Math Builtins
--------------------
The following built-in functions may be used to generate a
\1f
File: as.info, Node: TIC54X-Ext, Next: TIC54X-Directives, Prev: TIC54X-Builtins, Up: TIC54X-Dependent
-8.31.8 Extended Addressing
+9.35.8 Extended Addressing
--------------------------
The `LDX' pseudo-op is provided for loading the extended addressing bits
\1f
File: as.info, Node: TIC54X-Directives, Next: TIC54X-Macros, Prev: TIC54X-Ext, Up: TIC54X-Dependent
-8.31.9 Directives
+9.35.9 Directives
-----------------
`.align [SIZE]'
\1f
File: as.info, Node: TIC54X-Macros, Next: TIC54X-MMRegs, Prev: TIC54X-Directives, Up: TIC54X-Dependent
-8.31.10 Macros
+9.35.10 Macros
--------------
Macros do not require explicit dereferencing of arguments (i.e., \ARG).
\1f
File: as.info, Node: TIC54X-MMRegs, Prev: TIC54X-Macros, Up: TIC54X-Dependent
-8.31.11 Memory-mapped Registers
+9.35.11 Memory-mapped Registers
-------------------------------
The following symbols are recognized as memory-mapped registers:
\1f
File: as.info, Node: Z80-Dependent, Next: Z8000-Dependent, Prev: Xtensa-Dependent, Up: Machine Dependencies
-8.32 Z80 Dependent Features
+9.36 Z80 Dependent Features
===========================
* Menu:
\1f
File: as.info, Node: Z80 Options, Next: Z80 Syntax, Up: Z80-Dependent
-8.32.1 Options
+9.36.1 Options
--------------
The Zilog Z80 and Ascii R800 version of `as' have a few machine
\1f
File: as.info, Node: Z80 Syntax, Next: Z80 Floating Point, Prev: Z80 Options, Up: Z80-Dependent
-8.32.2 Syntax
+9.36.2 Syntax
-------------
The assembler syntax closely follows the 'Z80 family CPU User Manual' by
\1f
File: as.info, Node: Z80-Chars, Next: Z80-Regs, Up: Z80 Syntax
-8.32.2.1 Special Characters
+9.36.2.1 Special Characters
...........................
The semicolon `;' is the line comment character;
\1f
File: as.info, Node: Z80-Regs, Next: Z80-Case, Prev: Z80-Chars, Up: Z80 Syntax
-8.32.2.2 Register Names
+9.36.2.2 Register Names
.......................
The registers are referred to with the letters assigned to them by
\1f
File: as.info, Node: Z80-Case, Prev: Z80-Regs, Up: Z80 Syntax
-8.32.2.3 Case Sensitivity
+9.36.2.3 Case Sensitivity
.........................
Upper and lower case are equivalent in register names, opcodes,
\1f
File: as.info, Node: Z80 Floating Point, Next: Z80 Directives, Prev: Z80 Syntax, Up: Z80-Dependent
-8.32.3 Floating Point
+9.36.3 Floating Point
---------------------
Floating-point numbers are not supported.
\1f
File: as.info, Node: Z80 Directives, Next: Z80 Opcodes, Prev: Z80 Floating Point, Up: Z80-Dependent
-8.32.4 Z80 Assembler Directives
+9.36.4 Z80 Assembler Directives
-------------------------------
`as' for the Z80 supports some additional directives for compatibility
\1f
File: as.info, Node: Z80 Opcodes, Prev: Z80 Directives, Up: Z80-Dependent
-8.32.5 Opcodes
+9.36.5 Opcodes
--------------
In line with common practice, Z80 mnemonics are used for both the Z80
\1f
File: as.info, Node: Z8000-Dependent, Next: Vax-Dependent, Prev: Z80-Dependent, Up: Machine Dependencies
-8.33 Z8000 Dependent Features
+9.37 Z8000 Dependent Features
=============================
The Z8000 as supports both members of the Z8000 family: the
\1f
File: as.info, Node: Z8000 Options, Next: Z8000 Syntax, Up: Z8000-Dependent
-8.33.1 Options
+9.37.1 Options
--------------
`-z8001'
\1f
File: as.info, Node: Z8000 Syntax, Next: Z8000 Directives, Prev: Z8000 Options, Up: Z8000-Dependent
-8.33.2 Syntax
+9.37.2 Syntax
-------------
* Menu:
\1f
File: as.info, Node: Z8000-Chars, Next: Z8000-Regs, Up: Z8000 Syntax
-8.33.2.1 Special Characters
+9.37.2.1 Special Characters
...........................
`!' is the line comment character.
\1f
File: as.info, Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, Up: Z8000 Syntax
-8.33.2.2 Register Names
+9.37.2.2 Register Names
.......................
The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer
\1f
File: as.info, Node: Z8000-Addressing, Prev: Z8000-Regs, Up: Z8000 Syntax
-8.33.2.3 Addressing Modes
+9.37.2.3 Addressing Modes
.........................
as understands the following addressing modes for the Z8000:
\1f
File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent
-8.33.3 Assembler Directives for the Z8000
+9.37.3 Assembler Directives for the Z8000
-----------------------------------------
The Z8000 port of as includes additional assembler directives, for
\1f
File: as.info, Node: Z8000 Opcodes, Prev: Z8000 Directives, Up: Z8000-Dependent
-8.33.4 Opcodes
+9.37.4 Opcodes
--------------
For detailed information on the Z8000 machine instruction set, see
\1f
File: as.info, Node: Vax-Dependent, Prev: Z8000-Dependent, Up: Machine Dependencies
-8.34 VAX Dependent Features
+9.38 VAX Dependent Features
===========================
* Menu:
\1f
File: as.info, Node: VAX-Opts, Next: VAX-float, Up: Vax-Dependent
-8.34.1 VAX Command-Line Options
+9.38.1 VAX Command-Line Options
-------------------------------
The Vax version of `as' accepts any of the following options, gives a
\1f
File: as.info, Node: VAX-float, Next: VAX-directives, Prev: VAX-Opts, Up: Vax-Dependent
-8.34.2 VAX Floating Point
+9.38.2 VAX Floating Point
-------------------------
Conversion of flonums to floating point is correct, and compatible with
\1f
File: as.info, Node: VAX-directives, Next: VAX-opcodes, Prev: VAX-float, Up: Vax-Dependent
-8.34.3 Vax Machine Directives
+9.38.3 Vax Machine Directives
-----------------------------
The Vax version of the assembler supports four directives for
\1f
File: as.info, Node: VAX-opcodes, Next: VAX-branch, Prev: VAX-directives, Up: Vax-Dependent
-8.34.4 VAX Opcodes
+9.38.4 VAX Opcodes
------------------
All DEC mnemonics are supported. Beware that `case...' instructions
\1f
File: as.info, Node: VAX-branch, Next: VAX-operands, Prev: VAX-opcodes, Up: Vax-Dependent
-8.34.5 VAX Branch Improvement
+9.38.5 VAX Branch Improvement
-----------------------------
Certain pseudo opcodes are permitted. They are for branch
\1f
File: as.info, Node: VAX-operands, Next: VAX-no, Prev: VAX-branch, Up: Vax-Dependent
-8.34.6 VAX Operands
+9.38.6 VAX Operands
-------------------
The immediate character is `$' for Unix compatibility, not `#' as DEC
\1f
File: as.info, Node: VAX-no, Prev: VAX-operands, Up: Vax-Dependent
-8.34.7 Not Supported on VAX
+9.38.7 Not Supported on VAX
---------------------------
Vax bit fields can not be assembled with `as'. Someone can add the
\1f
File: as.info, Node: V850-Dependent, Next: Xtensa-Dependent, Prev: TIC54X-Dependent, Up: Machine Dependencies
-8.35 v850 Dependent Features
+9.39 v850 Dependent Features
============================
* Menu:
\1f
File: as.info, Node: V850 Options, Next: V850 Syntax, Up: V850-Dependent
-8.35.1 Options
+9.39.1 Options
--------------
`as' supports the following additional command-line options for the
\1f
File: as.info, Node: V850 Syntax, Next: V850 Floating Point, Prev: V850 Options, Up: V850-Dependent
-8.35.2 Syntax
+9.39.2 Syntax
-------------
* Menu:
\1f
File: as.info, Node: V850-Chars, Next: V850-Regs, Up: V850 Syntax
-8.35.2.1 Special Characters
+9.39.2.1 Special Characters
...........................
`#' is the line comment character.
\1f
File: as.info, Node: V850-Regs, Prev: V850-Chars, Up: V850 Syntax
-8.35.2.2 Register Names
+9.39.2.2 Register Names
.......................
`as' supports the following names for registers:
\1f
File: as.info, Node: V850 Floating Point, Next: V850 Directives, Prev: V850 Syntax, Up: V850-Dependent
-8.35.3 Floating Point
+9.39.3 Floating Point
---------------------
The V850 family uses IEEE floating-point numbers.
\1f
File: as.info, Node: V850 Directives, Next: V850 Opcodes, Prev: V850 Floating Point, Up: V850-Dependent
-8.35.4 V850 Machine Directives
+9.39.4 V850 Machine Directives
------------------------------
`.offset <EXPRESSION>'
\1f
File: as.info, Node: V850 Opcodes, Prev: V850 Directives, Up: V850-Dependent
-8.35.5 Opcodes
+9.39.5 Opcodes
--------------
`as' implements all the standard V850 opcodes.
\1f
File: as.info, Node: Xtensa-Dependent, Next: Z80-Dependent, Prev: V850-Dependent, Up: Machine Dependencies
-8.36 Xtensa Dependent Features
+9.40 Xtensa Dependent Features
==============================
This chapter covers features of the GNU assembler that are specific
\1f
File: as.info, Node: Xtensa Options, Next: Xtensa Syntax, Up: Xtensa-Dependent
-8.36.1 Command Line Options
+9.40.1 Command Line Options
---------------------------
The Xtensa version of the GNU assembler supports these special options:
\1f
File: as.info, Node: Xtensa Syntax, Next: Xtensa Optimizations, Prev: Xtensa Options, Up: Xtensa-Dependent
-8.36.2 Assembler Syntax
+9.40.2 Assembler Syntax
-----------------------
Block comments are delimited by `/*' and `*/'. End of line comments
{ [FORMAT;] OPCODE0 [OPERANDS]; OPCODE1 [OPERANDS]; OPCODE2 [OPERANDS]; ... }
- The assembler can automatically bundle opcodes into FLIX
-instructions. It encodes the opcodes in order, one at a time, choosing
-the smallest format where each opcode can be encoded and filling unused
+ If an opcode can only be encoded in a FLIX instruction but is not
+specified as part of a FLIX bundle, the assembler will choose the
+smallest format where the opcode can be encoded and will fill unused
instruction slots with no-ops.
* Menu:
\1f
File: as.info, Node: Xtensa Opcodes, Next: Xtensa Registers, Up: Xtensa Syntax
-8.36.2.1 Opcode Names
+9.40.2.1 Opcode Names
.....................
See the `Xtensa Instruction Set Architecture (ISA) Reference Manual'
\1f
File: as.info, Node: Xtensa Registers, Prev: Xtensa Opcodes, Up: Xtensa Syntax
-8.36.2.2 Register Names
+9.40.2.2 Register Names
.......................
The assembly syntax for a register file entry is the "short" name for a
\1f
File: as.info, Node: Xtensa Optimizations, Next: Xtensa Relaxation, Prev: Xtensa Syntax, Up: Xtensa-Dependent
-8.36.3 Xtensa Optimizations
+9.40.3 Xtensa Optimizations
---------------------------
The optimizations currently supported by `as' are generation of density
\1f
File: as.info, Node: Density Instructions, Next: Xtensa Automatic Alignment, Up: Xtensa Optimizations
-8.36.3.1 Using Density Instructions
+9.40.3.1 Using Density Instructions
...................................
The Xtensa instruction set has a code density option that provides
\1f
File: as.info, Node: Xtensa Automatic Alignment, Prev: Density Instructions, Up: Xtensa Optimizations
-8.36.3.2 Automatic Instruction Alignment
+9.40.3.2 Automatic Instruction Alignment
........................................
The Xtensa assembler will automatically align certain instructions, both
instruction fetch widths.) An instruction immediately following a call
is treated as a branch target in this context, because it will be the
target of a return from the call. This alignment has the potential to
-reduce branch penalties at some expense in code size. The assembler
-will not attempt to align labels with the prefixes `.Ln' and `.LM',
-since these labels are used for debugging information and are not
-typically branch targets. This optimization is enabled by default.
-You can disable it with the `--no-target-align' command-line option
-(*note Command Line Options: Xtensa Options.).
+reduce branch penalties at some expense in code size. This
+optimization is enabled by default. You can disable it with the
+`--no-target-align' command-line option (*note Command Line Options:
+Xtensa Options.).
The target alignment optimization is done without adding instructions
that could increase the execution time of the program. If there are
\1f
File: as.info, Node: Xtensa Relaxation, Next: Xtensa Directives, Prev: Xtensa Optimizations, Up: Xtensa-Dependent
-8.36.4 Xtensa Relaxation
+9.40.4 Xtensa Relaxation
------------------------
When an instruction operand is outside the range allowed for that
\1f
File: as.info, Node: Xtensa Branch Relaxation, Next: Xtensa Call Relaxation, Up: Xtensa Relaxation
-8.36.4.1 Conditional Branch Relaxation
+9.40.4.1 Conditional Branch Relaxation
......................................
When the target of a branch is too far away from the branch itself,
\1f
File: as.info, Node: Xtensa Call Relaxation, Next: Xtensa Immediate Relaxation, Prev: Xtensa Branch Relaxation, Up: Xtensa Relaxation
-8.36.4.2 Function Call Relaxation
+9.40.4.2 Function Call Relaxation
.................................
Function calls may require relaxation because the Xtensa immediate call
\1f
File: as.info, Node: Xtensa Immediate Relaxation, Prev: Xtensa Call Relaxation, Up: Xtensa Relaxation
-8.36.4.3 Other Immediate Field Relaxation
+9.40.4.3 Other Immediate Field Relaxation
.........................................
The assembler normally performs the following other relaxations. They
.literal .L1, 2040
l32r a1, .L1
- addi a1, a0, a1
+ add a1, a0, a1
l32i a1, a1, 0
If the load destination and source address register are the same, an
\1f
File: as.info, Node: Xtensa Directives, Prev: Xtensa Relaxation, Up: Xtensa-Dependent
-8.36.5 Directives
+9.40.5 Directives
-----------------
The Xtensa assembler supports a region-based directive syntax:
\1f
File: as.info, Node: Schedule Directive, Next: Longcalls Directive, Up: Xtensa Directives
-8.36.5.1 schedule
+9.40.5.1 schedule
.................
The `schedule' directive is recognized only for compatibility with
\1f
File: as.info, Node: Longcalls Directive, Next: Transform Directive, Prev: Schedule Directive, Up: Xtensa Directives
-8.36.5.2 longcalls
+9.40.5.2 longcalls
..................
The `longcalls' directive enables or disables function call relaxation.
\1f
File: as.info, Node: Transform Directive, Next: Literal Directive, Prev: Longcalls Directive, Up: Xtensa Directives
-8.36.5.3 transform
+9.40.5.3 transform
..................
This directive enables or disables all assembler transformation,
\1f
File: as.info, Node: Literal Directive, Next: Literal Position Directive, Prev: Transform Directive, Up: Xtensa Directives
-8.36.5.4 literal
+9.40.5.4 literal
................
The `.literal' directive is used to define literal pool data, i.e.,
\1f
File: as.info, Node: Literal Position Directive, Next: Literal Prefix Directive, Prev: Literal Directive, Up: Xtensa Directives
-8.36.5.5 literal_position
+9.40.5.5 literal_position
.........................
When using `--text-section-literals' to place literals inline in the
\1f
File: as.info, Node: Literal Prefix Directive, Next: Absolute Literals Directive, Prev: Literal Position Directive, Up: Xtensa Directives
-8.36.5.6 literal_prefix
+9.40.5.6 literal_prefix
.......................
The `literal_prefix' directive allows you to override the default
\1f
File: as.info, Node: Absolute Literals Directive, Prev: Literal Prefix Directive, Up: Xtensa Directives
-8.36.5.7 absolute-literals
+9.40.5.7 absolute-literals
..........................
The `absolute-literals' and `no-absolute-literals' directives control
\1f
File: as.info, Node: Reporting Bugs, Next: Acknowledgements, Prev: Machine Dependencies, Up: Top
-9 Reporting Bugs
-****************
+10 Reporting Bugs
+*****************
Your bug reports play an essential role in making `as' reliable.
\1f
File: as.info, Node: Bug Criteria, Next: Bug Reporting, Up: Reporting Bugs
-9.1 Have You Found a Bug?
-=========================
+10.1 Have You Found a Bug?
+==========================
If you are not sure whether you have found a bug, here are some
guidelines:
\1f
File: as.info, Node: Bug Reporting, Prev: Bug Criteria, Up: Reporting Bugs
-9.2 How to Report Bugs
-======================
+10.2 How to Report Bugs
+=======================
A number of companies and individuals offer support for GNU products.
If you obtained `as' from a support organization, we recommend you
\1f
File: as.info, Node: Acknowledgements, Next: GNU Free Documentation License, Prev: Reporting Bugs, Up: Top
-10 Acknowledgements
+11 Acknowledgements
*******************
If you have contributed to GAS and your name isn't listed here, it is
Several engineers at Cygnus Support have also provided many small
bug fixes and configuration enhancements.
+ Jon Beniston added support for the Lattice Mico32 architecture.
+
Many others have contributed large or small bugfixes and
enhancements. If you have contributed significant work and are not
mentioned on this list, and want to be, let us know. Some of the
Appendix A GNU Free Documentation License
*****************************************
- Version 1.1, March 2000
+ Version 1.3, 3 November 2008
- Copyright (C) 2000, 2003 Free Software Foundation, Inc.
- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ Copyright (C) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc.
+ `http://fsf.org/'
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
-
0. PREAMBLE
The purpose of this License is to make a manual, textbook, or other
- written document "free" in the sense of freedom: to assure everyone
- the effective freedom to copy and redistribute it, with or without
- modifying it, either commercially or noncommercially. Secondarily,
- this License preserves for the author and publisher a way to get
- credit for their work, while not being considered responsible for
- modifications made by others.
+ functional and useful document "free" in the sense of freedom: to
+ assure everyone the effective freedom to copy and redistribute it,
+ with or without modifying it, either commercially or
+ noncommercially. Secondarily, this License preserves for the
+ author and publisher a way to get credit for their work, while not
+ being considered responsible for modifications made by others.
This License is a kind of "copyleft", which means that derivative
works of the document must themselves be free in the same sense.
We recommend this License principally for works whose purpose is
instruction or reference.
-
1. APPLICABILITY AND DEFINITIONS
- This License applies to any manual or other work that contains a
- notice placed by the copyright holder saying it can be distributed
- under the terms of this License. The "Document", below, refers to
- any such manual or work. Any member of the public is a licensee,
- and is addressed as "you."
+ This License applies to any manual or other work, in any medium,
+ that contains a notice placed by the copyright holder saying it
+ can be distributed under the terms of this License. Such a notice
+ grants a world-wide, royalty-free license, unlimited in duration,
+ to use that work under the conditions stated herein. The
+ "Document", below, refers to any such manual or work. Any member
+ of the public is a licensee, and is addressed as "you". You
+ accept the license if you copy, modify or distribute the work in a
+ way requiring permission under copyright law.
A "Modified Version" of the Document means any work containing the
Document or a portion of it, either copied verbatim, or with
modifications and/or translated into another language.
- A "Secondary Section" is a named appendix or a front-matter
- section of the Document that deals exclusively with the
- relationship of the publishers or authors of the Document to the
- Document's overall subject (or to related matters) and contains
- nothing that could fall directly within that overall subject.
- (For example, if the Document is in part a textbook of
- mathematics, a Secondary Section may not explain any mathematics.)
- The relationship could be a matter of historical connection with
- the subject or with related matters, or of legal, commercial,
- philosophical, ethical or political position regarding them.
+ A "Secondary Section" is a named appendix or a front-matter section
+ of the Document that deals exclusively with the relationship of the
+ publishers or authors of the Document to the Document's overall
+ subject (or to related matters) and contains nothing that could
+ fall directly within that overall subject. (Thus, if the Document
+ is in part a textbook of mathematics, a Secondary Section may not
+ explain any mathematics.) The relationship could be a matter of
+ historical connection with the subject or with related matters, or
+ of legal, commercial, philosophical, ethical or political position
+ regarding them.
The "Invariant Sections" are certain Secondary Sections whose
titles are designated, as being those of Invariant Sections, in
the notice that says that the Document is released under this
- License.
+ License. If a section does not fit the above definition of
+ Secondary then it is not allowed to be designated as Invariant.
+ The Document may contain zero Invariant Sections. If the Document
+ does not identify any Invariant Sections then there are none.
The "Cover Texts" are certain short passages of text that are
listed, as Front-Cover Texts or Back-Cover Texts, in the notice
- that says that the Document is released under this License.
+ that says that the Document is released under this License. A
+ Front-Cover Text may be at most 5 words, and a Back-Cover Text may
+ be at most 25 words.
A "Transparent" copy of the Document means a machine-readable copy,
represented in a format whose specification is available to the
- general public, whose contents can be viewed and edited directly
- and straightforwardly with generic text editors or (for images
+ general public, that is suitable for revising the document
+ straightforwardly with generic text editors or (for images
composed of pixels) generic paint programs or (for drawings) some
widely available drawing editor, and that is suitable for input to
text formatters or for automatic translation to a variety of
formats suitable for input to text formatters. A copy made in an
- otherwise Transparent file format whose markup has been designed
- to thwart or discourage subsequent modification by readers is not
- Transparent. A copy that is not "Transparent" is called "Opaque."
+ otherwise Transparent file format whose markup, or absence of
+ markup, has been arranged to thwart or discourage subsequent
+ modification by readers is not Transparent. An image format is
+ not Transparent if used for any substantial amount of text. A
+ copy that is not "Transparent" is called "Opaque".
Examples of suitable formats for Transparent copies include plain
ASCII without markup, Texinfo input format, LaTeX input format,
SGML or XML using a publicly available DTD, and
- standard-conforming simple HTML designed for human modification.
- Opaque formats include PostScript, PDF, proprietary formats that
- can be read and edited only by proprietary word processors, SGML
- or XML for which the DTD and/or processing tools are not generally
- available, and the machine-generated HTML produced by some word
- processors for output purposes only.
+ standard-conforming simple HTML, PostScript or PDF designed for
+ human modification. Examples of transparent image formats include
+ PNG, XCF and JPG. Opaque formats include proprietary formats that
+ can be read and edited only by proprietary word processors, SGML or
+ XML for which the DTD and/or processing tools are not generally
+ available, and the machine-generated HTML, PostScript or PDF
+ produced by some word processors for output purposes only.
The "Title Page" means, for a printed book, the title page itself,
plus such following pages as are needed to hold, legibly, the
Page" means the text near the most prominent appearance of the
work's title, preceding the beginning of the body of the text.
+ The "publisher" means any person or entity that distributes copies
+ of the Document to the public.
+
+ A section "Entitled XYZ" means a named subunit of the Document
+ whose title either is precisely XYZ or contains XYZ in parentheses
+ following text that translates XYZ in another language. (Here XYZ
+ stands for a specific section name mentioned below, such as
+ "Acknowledgements", "Dedications", "Endorsements", or "History".)
+ To "Preserve the Title" of such a section when you modify the
+ Document means that it remains a section "Entitled XYZ" according
+ to this definition.
+
+ The Document may include Warranty Disclaimers next to the notice
+ which states that this License applies to the Document. These
+ Warranty Disclaimers are considered to be included by reference in
+ this License, but only as regards disclaiming warranties: any other
+ implication that these Warranty Disclaimers may have is void and
+ has no effect on the meaning of this License.
+
2. VERBATIM COPYING
You may copy and distribute the Document in any medium, either
3. COPYING IN QUANTITY
- If you publish printed copies of the Document numbering more than
- 100, and the Document's license notice requires Cover Texts, you
- must enclose the copies in covers that carry, clearly and legibly,
- all these Cover Texts: Front-Cover Texts on the front cover, and
+ If you publish printed copies (or copies in media that commonly
+ have printed covers) of the Document, numbering more than 100, and
+ the Document's license notice requires Cover Texts, you must
+ enclose the copies in covers that carry, clearly and legibly, all
+ these Cover Texts: Front-Cover Texts on the front cover, and
Back-Cover Texts on the back cover. Both covers must also clearly
and legibly identify you as the publisher of these copies. The
front cover must present the full title with all words of the
If you publish or distribute Opaque copies of the Document
numbering more than 100, you must either include a
machine-readable Transparent copy along with each Opaque copy, or
- state in or with each Opaque copy a publicly-accessible
- computer-network location containing a complete Transparent copy
- of the Document, free of added material, which the general
- network-using public has access to download anonymously at no
- charge using public-standard network protocols. If you use the
+ state in or with each Opaque copy a computer-network location from
+ which the general network-using public has access to download
+ using public-standard network protocols a complete Transparent
+ copy of the Document, free of added material. If you use the
latter option, you must take reasonably prudent steps, when you
begin distribution of Opaque copies in quantity, to ensure that
this Transparent copy will remain thus accessible at the stated
whoever possesses a copy of it. In addition, you must do these
things in the Modified Version:
- A. Use in the Title Page (and on the covers, if any) a title
- distinct from that of the Document, and from those of previous
- versions (which should, if there were any, be listed in the
- History section of the Document). You may use the same title
- as a previous version if the original publisher of that version
- gives permission.
- B. List on the Title Page, as authors, one or more persons or
- entities responsible for authorship of the modifications in the
- Modified Version, together with at least five of the principal
- authors of the Document (all of its principal authors, if it
- has less than five).
- C. State on the Title page the name of the publisher of the
- Modified Version, as the publisher.
- D. Preserve all the copyright notices of the Document.
- E. Add an appropriate copyright notice for your modifications
- adjacent to the other copyright notices.
- F. Include, immediately after the copyright notices, a license
- notice giving the public permission to use the Modified Version
- under the terms of this License, in the form shown in the
- Addendum below.
- G. Preserve in that license notice the full lists of Invariant
- Sections and required Cover Texts given in the Document's
- license notice.
- H. Include an unaltered copy of this License.
- I. Preserve the section entitled "History", and its title, and add
- to it an item stating at least the title, year, new authors, and
- publisher of the Modified Version as given on the Title Page.
- If there is no section entitled "History" in the Document,
- create one stating the title, year, authors, and publisher of
- the Document as given on its Title Page, then add an item
- describing the Modified Version as stated in the previous
- sentence.
- J. Preserve the network location, if any, given in the Document for
- public access to a Transparent copy of the Document, and
- likewise the network locations given in the Document for
- previous versions it was based on. These may be placed in the
- "History" section. You may omit a network location for a work
- that was published at least four years before the Document
- itself, or if the original publisher of the version it refers
- to gives permission.
- K. In any section entitled "Acknowledgements" or "Dedications",
- preserve the section's title, and preserve in the section all the
- substance and tone of each of the contributor acknowledgements
- and/or dedications given therein.
- L. Preserve all the Invariant Sections of the Document,
- unaltered in their text and in their titles. Section numbers
- or the equivalent are not considered part of the section titles.
- M. Delete any section entitled "Endorsements." Such a section
- may not be included in the Modified Version.
- N. Do not retitle any existing section as "Endorsements" or to
- conflict in title with any Invariant Section.
+ A. Use in the Title Page (and on the covers, if any) a title
+ distinct from that of the Document, and from those of
+ previous versions (which should, if there were any, be listed
+ in the History section of the Document). You may use the
+ same title as a previous version if the original publisher of
+ that version gives permission.
+
+ B. List on the Title Page, as authors, one or more persons or
+ entities responsible for authorship of the modifications in
+ the Modified Version, together with at least five of the
+ principal authors of the Document (all of its principal
+ authors, if it has fewer than five), unless they release you
+ from this requirement.
+
+ C. State on the Title page the name of the publisher of the
+ Modified Version, as the publisher.
+
+ D. Preserve all the copyright notices of the Document.
+
+ E. Add an appropriate copyright notice for your modifications
+ adjacent to the other copyright notices.
+
+ F. Include, immediately after the copyright notices, a license
+ notice giving the public permission to use the Modified
+ Version under the terms of this License, in the form shown in
+ the Addendum below.
+
+ G. Preserve in that license notice the full lists of Invariant
+ Sections and required Cover Texts given in the Document's
+ license notice.
+
+ H. Include an unaltered copy of this License.
+
+ I. Preserve the section Entitled "History", Preserve its Title,
+ and add to it an item stating at least the title, year, new
+ authors, and publisher of the Modified Version as given on
+ the Title Page. If there is no section Entitled "History" in
+ the Document, create one stating the title, year, authors,
+ and publisher of the Document as given on its Title Page,
+ then add an item describing the Modified Version as stated in
+ the previous sentence.
+
+ J. Preserve the network location, if any, given in the Document
+ for public access to a Transparent copy of the Document, and
+ likewise the network locations given in the Document for
+ previous versions it was based on. These may be placed in
+ the "History" section. You may omit a network location for a
+ work that was published at least four years before the
+ Document itself, or if the original publisher of the version
+ it refers to gives permission.
+
+ K. For any section Entitled "Acknowledgements" or "Dedications",
+ Preserve the Title of the section, and preserve in the
+ section all the substance and tone of each of the contributor
+ acknowledgements and/or dedications given therein.
+
+ L. Preserve all the Invariant Sections of the Document,
+ unaltered in their text and in their titles. Section numbers
+ or the equivalent are not considered part of the section
+ titles.
+
+ M. Delete any section Entitled "Endorsements". Such a section
+ may not be included in the Modified Version.
+
+ N. Do not retitle any existing section to be Entitled
+ "Endorsements" or to conflict in title with any Invariant
+ Section.
+
+ O. Preserve any Warranty Disclaimers.
If the Modified Version includes new front-matter sections or
appendices that qualify as Secondary Sections and contain no
Version's license notice. These titles must be distinct from any
other section titles.
- You may add a section entitled "Endorsements", provided it contains
+ You may add a section Entitled "Endorsements", provided it contains
nothing but endorsements of your Modified Version by various
- parties-for example, statements of peer review or that the text has
- been approved by an organization as the authoritative definition
- of a standard.
+ parties--for example, statements of peer review or that the text
+ has been approved by an organization as the authoritative
+ definition of a standard.
You may add a passage of up to five words as a Front-Cover Text,
and a passage of up to 25 words as a Back-Cover Text, to the end
modified versions, provided that you include in the combination
all of the Invariant Sections of all of the original documents,
unmodified, and list them all as Invariant Sections of your
- combined work in its license notice.
+ combined work in its license notice, and that you preserve all
+ their Warranty Disclaimers.
The combined work need only contain one copy of this License, and
multiple identical Invariant Sections may be replaced with a single
the list of Invariant Sections in the license notice of the
combined work.
- In the combination, you must combine any sections entitled
+ In the combination, you must combine any sections Entitled
"History" in the various original documents, forming one section
- entitled "History"; likewise combine any sections entitled
- "Acknowledgements", and any sections entitled "Dedications." You
- must delete all sections entitled "Endorsements."
+ Entitled "History"; likewise combine any sections Entitled
+ "Acknowledgements", and any sections Entitled "Dedications". You
+ must delete all sections Entitled "Endorsements."
6. COLLECTIONS OF DOCUMENTS
A compilation of the Document or its derivatives with other
separate and independent documents or works, in or on a volume of
- a storage or distribution medium, does not as a whole count as a
- Modified Version of the Document, provided no compilation
- copyright is claimed for the compilation. Such a compilation is
- called an "aggregate", and this License does not apply to the
- other self-contained works thus compiled with the Document, on
- account of their being thus compiled, if they are not themselves
- derivative works of the Document.
+ a storage or distribution medium, is called an "aggregate" if the
+ copyright resulting from the compilation is not used to limit the
+ legal rights of the compilation's users beyond what the individual
+ works permit. When the Document is included in an aggregate, this
+ License does not apply to the other works in the aggregate which
+ are not themselves derivative works of the Document.
If the Cover Text requirement of section 3 is applicable to these
- copies of the Document, then if the Document is less than one
- quarter of the entire aggregate, the Document's Cover Texts may be
- placed on covers that surround only the Document within the
- aggregate. Otherwise they must appear on covers around the whole
- aggregate.
+ copies of the Document, then if the Document is less than one half
+ of the entire aggregate, the Document's Cover Texts may be placed
+ on covers that bracket the Document within the aggregate, or the
+ electronic equivalent of covers if the Document is in electronic
+ form. Otherwise they must appear on printed covers that bracket
+ the whole aggregate.
8. TRANSLATION
permission from their copyright holders, but you may include
translations of some or all Invariant Sections in addition to the
original versions of these Invariant Sections. You may include a
- translation of this License provided that you also include the
- original English version of this License. In case of a
- disagreement between the translation and the original English
- version of this License, the original English version will prevail.
+ translation of this License, and all the license notices in the
+ Document, and any Warranty Disclaimers, provided that you also
+ include the original English version of this License and the
+ original versions of those notices and disclaimers. In case of a
+ disagreement between the translation and the original version of
+ this License or a notice or disclaimer, the original version will
+ prevail.
+
+ If a section in the Document is Entitled "Acknowledgements",
+ "Dedications", or "History", the requirement (section 4) to
+ Preserve its Title (section 1) will typically require changing the
+ actual title.
9. TERMINATION
You may not copy, modify, sublicense, or distribute the Document
- except as expressly provided for under this License. Any other
- attempt to copy, modify, sublicense or distribute the Document is
- void, and will automatically terminate your rights under this
- License. However, parties who have received copies, or rights,
- from you under this License will not have their licenses
- terminated so long as such parties remain in full compliance.
+ except as expressly provided under this License. Any attempt
+ otherwise to copy, modify, sublicense, or distribute it is void,
+ and will automatically terminate your rights under this License.
+
+ However, if you cease all violation of this License, then your
+ license from a particular copyright holder is reinstated (a)
+ provisionally, unless and until the copyright holder explicitly
+ and finally terminates your license, and (b) permanently, if the
+ copyright holder fails to notify you of the violation by some
+ reasonable means prior to 60 days after the cessation.
+
+ Moreover, your license from a particular copyright holder is
+ reinstated permanently if the copyright holder notifies you of the
+ violation by some reasonable means, this is the first time you have
+ received notice of violation of this License (for any work) from
+ that copyright holder, and you cure the violation prior to 30 days
+ after your receipt of the notice.
+
+ Termination of your rights under this section does not terminate
+ the licenses of parties who have received copies or rights from
+ you under this License. If your rights have been terminated and
+ not permanently reinstated, receipt of a copy of some or all of
+ the same material does not give you any rights to use it.
10. FUTURE REVISIONS OF THIS LICENSE
the GNU Free Documentation License from time to time. Such new
versions will be similar in spirit to the present version, but may
differ in detail to address new problems or concerns. See
- http://www.gnu.org/copyleft/.
+ `http://www.gnu.org/copyleft/'.
Each version of the License is given a distinguishing version
number. If the Document specifies that a particular numbered
published (not as a draft) by the Free Software Foundation. If
the Document does not specify a version number of this License,
you may choose any version ever published (not as a draft) by the
- Free Software Foundation.
+ Free Software Foundation. If the Document specifies that a proxy
+ can decide which future versions of this License can be used, that
+ proxy's public statement of acceptance of a version permanently
+ authorizes you to choose that version for the Document.
+
+ 11. RELICENSING
+
+ "Massive Multiauthor Collaboration Site" (or "MMC Site") means any
+ World Wide Web server that publishes copyrightable works and also
+ provides prominent facilities for anybody to edit those works. A
+ public wiki that anybody can edit is an example of such a server.
+ A "Massive Multiauthor Collaboration" (or "MMC") contained in the
+ site means any set of copyrightable works thus published on the MMC
+ site.
+
+ "CC-BY-SA" means the Creative Commons Attribution-Share Alike 3.0
+ license published by Creative Commons Corporation, a not-for-profit
+ corporation with a principal place of business in San Francisco,
+ California, as well as future copyleft versions of that license
+ published by that same organization.
+
+ "Incorporate" means to publish or republish a Document, in whole or
+ in part, as part of another Document.
+
+ An MMC is "eligible for relicensing" if it is licensed under this
+ License, and if all works that were first published under this
+ License somewhere other than this MMC, and subsequently
+ incorporated in whole or in part into the MMC, (1) had no cover
+ texts or invariant sections, and (2) were thus incorporated prior
+ to November 1, 2008.
+
+ The operator of an MMC Site may republish an MMC contained in the
+ site under CC-BY-SA on the same site at any time before August 1,
+ 2009, provided the MMC is eligible for relicensing.
ADDENDUM: How to use this License for your documents
the License in the document and put the following copyright and license
notices just after the title page:
- Copyright (C) YEAR YOUR NAME.
- Permission is granted to copy, distribute and/or modify this document
- under the terms of the GNU Free Documentation License, Version 1.1
- or any later version published by the Free Software Foundation;
- with the Invariant Sections being LIST THEIR TITLES, with the
- Front-Cover Texts being LIST, and with the Back-Cover Texts being LIST.
- A copy of the license is included in the section entitled "GNU
- Free Documentation License."
+ Copyright (C) YEAR YOUR NAME.
+ Permission is granted to copy, distribute and/or modify this document
+ under the terms of the GNU Free Documentation License, Version 1.3
+ or any later version published by the Free Software Foundation;
+ with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
+ Texts. A copy of the license is included in the section entitled ``GNU
+ Free Documentation License''.
+
+ If you have Invariant Sections, Front-Cover Texts and Back-Cover
+Texts, replace the "with...Texts." line with this:
- If you have no Invariant Sections, write "with no Invariant Sections"
-instead of saying which ones are invariant. If you have no Front-Cover
-Texts, write "no Front-Cover Texts" instead of "Front-Cover Texts being
-LIST"; likewise for Back-Cover Texts.
+ with the Invariant Sections being LIST THEIR TITLES, with
+ the Front-Cover Texts being LIST, and with the Back-Cover Texts
+ being LIST.
+
+ If you have Invariant Sections without Cover Texts, or some other
+combination of the three, merge those two alternatives to suit the
+situation.
If your document contains nontrivial examples of program code, we
recommend releasing these examples in parallel under your choice of
\0\b[index\0\b]
* Menu:
-* #: Comments. (line 38)
+* #: Comments. (line 39)
* #APP: Preprocessing. (line 27)
* #NO_APP: Preprocessing. (line 27)
-* $ in symbol names <1>: SH64-Chars. (line 10)
-* $ in symbol names <2>: SH-Chars. (line 10)
-* $ in symbol names <3>: D30V-Chars. (line 63)
-* $ in symbol names: D10V-Chars. (line 46)
+* $ in symbol names <1>: D30V-Chars. (line 63)
+* $ in symbol names <2>: SH64-Chars. (line 10)
+* $ in symbol names <3>: D10V-Chars. (line 46)
+* $ in symbol names: SH-Chars. (line 10)
* $a: ARM Mapping Symbols. (line 9)
* $acos math builtin, TIC54X: TIC54X-Builtins. (line 10)
* $asin math builtin, TIC54X: TIC54X-Builtins. (line 13)
* --emulation=criself command line option, CRIS: CRIS-Opts. (line 9)
* --enforce-aligned-data: Sparc-Aligned-Data. (line 11)
* --fatal-warnings: W. (line 16)
+* --fix-v4bx command line option, ARM: ARM Options. (line 143)
* --fixed-special-register-names command line option, MMIX: MMIX-Opts.
(line 8)
* --force-long-branches: M68HC11-Opts. (line 69)
* --generate-example: M68HC11-Opts. (line 86)
* --globalize-symbols command line option, MMIX: MMIX-Opts. (line 12)
* --gnu-syntax command line option, MMIX: MMIX-Opts. (line 16)
-* --hash-size=NUMBER: Overview. (line 307)
+* --hash-size=NUMBER: Overview. (line 326)
* --linker-allocated-gregs command line option, MMIX: MMIX-Opts.
(line 67)
* --listing-cont-lines: listing. (line 34)
* --underscore command line option, CRIS: CRIS-Opts. (line 15)
* --warn: W. (line 19)
* -1 option, VAX/VMS: VAX-Opts. (line 77)
-* -32addr command line option, Alpha: Alpha Options. (line 50)
+* -32addr command line option, Alpha: Alpha Options. (line 58)
* -a: a. (line 6)
* -A options, i960: Options-i960. (line 6)
* -ac: a. (line 6)
* -ad: a. (line 6)
+* -ag: a. (line 6)
* -ah: a. (line 6)
* -al: a. (line 6)
* -an: a. (line 6)
* -Av9a: Sparc-Opts. (line 25)
* -b option, i960: Options-i960. (line 22)
* -big option, M32R: M32R-Opts. (line 35)
-* -construct-floats: MIPS Opts. (line 195)
* -D: D. (line 6)
* -D, ignored on VAX: VAX-Opts. (line 11)
* -d, VAX option: VAX-Opts. (line 16)
-* -eabi= command line option, ARM: ARM Options. (line 107)
+* -eabi= command line option, ARM: ARM Options. (line 126)
* -EB command line option, ARC: ARC Options. (line 31)
-* -EB command line option, ARM: ARM Options. (line 112)
+* -EB command line option, ARM: ARM Options. (line 131)
* -EB option (MIPS): MIPS Opts. (line 13)
* -EB option, M32R: M32R-Opts. (line 39)
* -EL command line option, ARC: ARC Options. (line 35)
-* -EL command line option, ARM: ARM Options. (line 116)
+* -EL command line option, ARM: ARM Options. (line 135)
* -EL option (MIPS): MIPS Opts. (line 13)
* -EL option, M32R: M32R-Opts. (line 32)
* -f: f. (line 6)
-* -F command line option, Alpha: Alpha Options. (line 50)
-* -G command line option, Alpha: Alpha Options. (line 46)
-* -g command line option, Alpha: Alpha Options. (line 40)
+* -F command line option, Alpha: Alpha Options. (line 58)
+* -G command line option, Alpha: Alpha Options. (line 54)
+* -g command line option, Alpha: Alpha Options. (line 48)
* -G option (MIPS): MIPS Opts. (line 8)
* -H option, VAX/VMS: VAX-Opts. (line 81)
* -h option, VAX/VMS: VAX-Opts. (line 45)
* -Ip option, M32RX: M32R-Opts. (line 97)
* -J, ignored on VAX: VAX-Opts. (line 27)
* -K: K. (line 6)
-* -k command line option, ARM: ARM Options. (line 120)
+* -k command line option, ARM: ARM Options. (line 139)
* -KPIC option, M32R: M32R-Opts. (line 42)
* -KPIC option, MIPS: MIPS Opts. (line 21)
* -L: L. (line 6)
* -m11/93: PDP-11-Options. (line 173)
* -m11/94: PDP-11-Options. (line 173)
* -m16c option, M16C: M32C-Opts. (line 12)
+* -m31 option, s390: s390 Options. (line 8)
* -m32c option, M32C: M32C-Opts. (line 9)
* -m32r option, M32R: M32R-Opts. (line 21)
* -m32rx option, M32R2: M32R-Opts. (line 17)
* -m32rx option, M32RX: M32R-Opts. (line 9)
+* -m64 option, s390: s390 Options. (line 8)
* -m68000 and related options: M68K-Opts. (line 104)
* -m68hc11: M68HC11-Opts. (line 9)
* -m68hc12: M68HC11-Opts. (line 14)
* -m[no-]mac command line option, M680x0: M68K-Opts. (line 21)
* -m[no-]usp command line option, M680x0: M68K-Opts. (line 21)
* -mall: PDP-11-Options. (line 26)
+* -mall-enabled command line option, LM32: LM32 Options. (line 30)
* -mall-extensions: PDP-11-Options. (line 26)
-* -mall-opcodes command line option, AVR: AVR Options. (line 43)
-* -mapcs command line option, ARM: ARM Options. (line 80)
-* -mapcs-float command line option, ARM: ARM Options. (line 93)
-* -mapcs-reentrant command line option, ARM: ARM Options. (line 98)
+* -mall-opcodes command line option, AVR: AVR Options. (line 62)
+* -mapcs command line option, ARM: ARM Options. (line 99)
+* -mapcs-float command line option, ARM: ARM Options. (line 112)
+* -mapcs-reentrant command line option, ARM: ARM Options. (line 117)
* -marc[5|6|7|8] command line option, ARC: ARC Options. (line 6)
-* -march= command line option, ARM: ARM Options. (line 37)
+* -march= command line option, ARM: ARM Options. (line 40)
* -march= command line option, M680x0: M68K-Opts. (line 8)
* -march= option, i386: i386-Options. (line 31)
+* -march= option, s390: s390 Options. (line 25)
* -march= option, x86-64: i386-Options. (line 31)
-* -matpcs command line option, ARM: ARM Options. (line 85)
+* -matpcs command line option, ARM: ARM Options. (line 104)
+* -mbarrel-shift-enabled command line option, LM32: LM32 Options.
+ (line 12)
+* -mbreak-enabled command line option, LM32: LM32 Options. (line 27)
* -mcis: PDP-11-Options. (line 32)
* -mconstant-gp command line option, IA-64: IA-64 Options. (line 6)
* -mCPU command line option, Alpha: Alpha Options. (line 6)
* -mcpu option, cpu: TIC54X-Opts. (line 15)
* -mcpu= command line option, ARM: ARM Options. (line 6)
+* -mcpu= command line option, Blackfin: Blackfin Options. (line 6)
* -mcpu= command line option, M680x0: M68K-Opts. (line 14)
* -mcsm: PDP-11-Options. (line 43)
+* -mdcache-enabled command line option, LM32: LM32 Options. (line 24)
* -mdebug command line option, Alpha: Alpha Options. (line 25)
+* -mdivide-enabled command line option, LM32: LM32 Options. (line 9)
* -me option, stderr redirect: TIC54X-Opts. (line 20)
* -meis: PDP-11-Options. (line 46)
* -merrors-to-file option, stderr redirect: TIC54X-Opts. (line 20)
+* -mesa option, s390: s390 Options. (line 17)
* -mf option, far-mode: TIC54X-Opts. (line 8)
* -mf11: PDP-11-Options. (line 122)
* -mfar-mode option, far-mode: TIC54X-Opts. (line 8)
* -mfis: PDP-11-Options. (line 51)
-* -mfloat-abi= command line option, ARM: ARM Options. (line 102)
+* -mfloat-abi= command line option, ARM: ARM Options. (line 121)
* -mfp-11: PDP-11-Options. (line 56)
* -mfpp: PDP-11-Options. (line 56)
* -mfpu: PDP-11-Options. (line 56)
-* -mfpu= command line option, ARM: ARM Options. (line 52)
+* -mfpu= command line option, ARM: ARM Options. (line 55)
+* -micache-enabled command line option, LM32: LM32 Options. (line 21)
+* -mimplicit-it command line option, ARM: ARM Options. (line 83)
* -mip2022 option, IP2K: IP2K-Opts. (line 14)
* -mip2022ext option, IP2022: IP2K-Opts. (line 9)
* -mj11: PDP-11-Options. (line 126)
* -mmcu= command line option, AVR: AVR Options. (line 6)
* -mmfpt: PDP-11-Options. (line 70)
* -mmicrocode: PDP-11-Options. (line 83)
+* -mmnemonic= option, i386: i386-Options. (line 80)
+* -mmnemonic= option, x86-64: i386-Options. (line 80)
+* -mmultiply-enabled command line option, LM32: LM32 Options. (line 6)
* -mmutiproc: PDP-11-Options. (line 73)
* -mmxps: PDP-11-Options. (line 77)
+* -mnaked-reg option, i386: i386-Options. (line 94)
+* -mnaked-reg option, x86-64: i386-Options. (line 94)
* -mno-cis: PDP-11-Options. (line 32)
* -mno-csm: PDP-11-Options. (line 43)
* -mno-eis: PDP-11-Options. (line 46)
* -mno-mutiproc: PDP-11-Options. (line 73)
* -mno-mxps: PDP-11-Options. (line 77)
* -mno-pic: PDP-11-Options. (line 11)
-* -mno-skip-bug command line option, AVR: AVR Options. (line 46)
+* -mno-regnames option, s390: s390 Options. (line 35)
+* -mno-skip-bug command line option, AVR: AVR Options. (line 65)
* -mno-spl: PDP-11-Options. (line 80)
-* -mno-sym32: MIPS Opts. (line 183)
-* -mno-wrap command line option, AVR: AVR Options. (line 49)
+* -mno-sym32: MIPS Opts. (line 189)
+* -mno-wrap command line option, AVR: AVR Options. (line 68)
* -mpic: PDP-11-Options. (line 11)
+* -mregnames option, s390: s390 Options. (line 32)
* -mrelax command line option, V850: V850 Options. (line 51)
* -mshort: M68HC11-Opts. (line 27)
* -mshort-double: M68HC11-Opts. (line 36)
+* -msign-extend-enabled command line option, LM32: LM32 Options.
+ (line 15)
* -mspl: PDP-11-Options. (line 80)
-* -msym32: MIPS Opts. (line 183)
+* -msse-check= option, i386: i386-Options. (line 68)
+* -msse-check= option, x86-64: i386-Options. (line 68)
+* -msse2avx option, i386: i386-Options. (line 64)
+* -msse2avx option, x86-64: i386-Options. (line 64)
+* -msym32: MIPS Opts. (line 189)
+* -msyntax= option, i386: i386-Options. (line 87)
+* -msyntax= option, x86-64: i386-Options. (line 87)
* -mt11: PDP-11-Options. (line 130)
-* -mthumb command line option, ARM: ARM Options. (line 71)
-* -mthumb-interwork command line option, ARM: ARM Options. (line 76)
-* -mtune= option, i386: i386-Options. (line 43)
-* -mtune= option, x86-64: i386-Options. (line 43)
+* -mthumb command line option, ARM: ARM Options. (line 74)
+* -mthumb-interwork command line option, ARM: ARM Options. (line 79)
+* -mtune= option, i386: i386-Options. (line 56)
+* -mtune= option, x86-64: i386-Options. (line 56)
+* -muser-enabled command line option, LM32: LM32 Options. (line 18)
* -mv850 command line option, V850: V850 Options. (line 23)
* -mv850any command line option, V850: V850 Options. (line 41)
* -mv850e command line option, V850: V850 Options. (line 29)
* -mv850e1 command line option, V850: V850 Options. (line 35)
* -mvxworks-pic option, MIPS: MIPS Opts. (line 26)
+* -mwarn-areg-zero option, s390: s390 Options. (line 38)
+* -mwarn-deprecated command line option, ARM: ARM Options. (line 147)
+* -mzarch option, s390: s390 Options. (line 17)
* -N command line option, CRIS: CRIS-Opts. (line 57)
* -nIp option, M32RX: M32R-Opts. (line 101)
* -no-bitinst, M32R2: M32R-Opts. (line 54)
-* -no-construct-floats: MIPS Opts. (line 195)
* -no-ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 93)
* -no-mdebug command line option, Alpha: Alpha Options. (line 25)
* -no-parallel option, M32RX: M32R-Opts. (line 51)
* -no-warn-explicit-parallel-conflicts option, M32RX: M32R-Opts.
(line 79)
* -no-warn-unmatched-high option, M32R: M32R-Opts. (line 111)
-* -nocpp ignored (MIPS): MIPS Opts. (line 186)
+* -nocpp ignored (MIPS): MIPS Opts. (line 192)
+* -noreplace command line option, Alpha: Alpha Options. (line 40)
* -o: o. (line 6)
* -O option, M32RX: M32R-Opts. (line 59)
* -parallel option, M32RX: M32R-Opts. (line 46)
* -R: R. (line 6)
* -r800 command line option, Z80: Z80 Options. (line 41)
* -relax command line option, Alpha: Alpha Options. (line 32)
+* -replace command line option, Alpha: Alpha Options. (line 40)
* -S, ignored on VAX: VAX-Opts. (line 11)
* -t, ignored on VAX: VAX-Opts. (line 36)
* -T, ignored on VAX: VAX-Opts. (line 11)
* -z8001 command line option, Z8000: Z8000 Options. (line 6)
* -z8002 command line option, Z8000: Z8000 Options. (line 9)
* . (symbol): Dot. (line 6)
-* .arch directive, ARM: ARM Directives. (line 210)
+* .2byte directive, ARM: ARM Directives. (line 6)
+* .4byte directive, ARM: ARM Directives. (line 6)
+* .8byte directive, ARM: ARM Directives. (line 6)
+* .align directive, ARM: ARM Directives. (line 11)
+* .arch directive, ARM: ARM Directives. (line 18)
+* .arm directive, ARM: ARM Directives. (line 22)
* .big directive, M32RX: M32R-Directives. (line 88)
-* .cantunwind directive, ARM: ARM Directives. (line 114)
-* .cpu directive, ARM: ARM Directives. (line 206)
-* .eabi_attribute directive, ARM: ARM Directives. (line 224)
-* .fnend directive, ARM: ARM Directives. (line 105)
-* .fnstart directive, ARM: ARM Directives. (line 102)
-* .fpu directive, ARM: ARM Directives. (line 220)
-* .handlerdata directive, ARM: ARM Directives. (line 125)
+* .bss directive, ARM: ARM Directives. (line 30)
+* .cantunwind directive, ARM: ARM Directives. (line 33)
+* .code directive, ARM: ARM Directives. (line 37)
+* .cpu directive, ARM: ARM Directives. (line 41)
+* .dn and .qn directives, ARM: ARM Directives. (line 45)
+* .eabi_attribute directive, ARM: ARM Directives. (line 69)
+* .even directive, ARM: ARM Directives. (line 93)
+* .extend directive, ARM: ARM Directives. (line 96)
+* .fnend directive, ARM: ARM Directives. (line 102)
+* .fnstart directive, ARM: ARM Directives. (line 111)
+* .force_thumb directive, ARM: ARM Directives. (line 114)
+* .fpu directive, ARM: ARM Directives. (line 118)
+* .global: MIPS insn. (line 12)
+* .handlerdata directive, ARM: ARM Directives. (line 122)
* .insn: MIPS insn. (line 6)
+* .insn directive, s390: s390 Directives. (line 11)
+* .inst directive, ARM: ARM Directives. (line 131)
+* .ldouble directive, ARM: ARM Directives. (line 96)
* .little directive, M32RX: M32R-Directives. (line 82)
-* .ltorg directive, ARM: ARM Directives. (line 85)
+* .long directive, s390: s390 Directives. (line 16)
+* .ltorg directive, ARM: ARM Directives. (line 143)
+* .ltorg directive, s390: s390 Directives. (line 88)
* .m32r directive, M32R: M32R-Directives. (line 66)
* .m32r2 directive, M32R2: M32R-Directives. (line 77)
* .m32rx directive, M32RX: M32R-Directives. (line 72)
-* .movsp directive, ARM: ARM Directives. (line 180)
+* .movsp directive, ARM: ARM Directives. (line 157)
* .o: Object. (line 6)
-* .object_arch directive, ARM: ARM Directives. (line 214)
-* .pad directive, ARM: ARM Directives. (line 175)
+* .object_arch directive, ARM: ARM Directives. (line 162)
+* .packed directive, ARM: ARM Directives. (line 168)
+* .pad directive, ARM: ARM Directives. (line 25)
* .param on HPPA: HPPA Directives. (line 19)
-* .personality directive, ARM: ARM Directives. (line 118)
-* .personalityindex directive, ARM: ARM Directives. (line 121)
-* .pool directive, ARM: ARM Directives. (line 99)
-* .save directive, ARM: ARM Directives. (line 134)
+* .personality directive, ARM: ARM Directives. (line 178)
+* .personalityindex directive, ARM: ARM Directives. (line 181)
+* .pool directive, ARM: ARM Directives. (line 185)
+* .quad directive, s390: s390 Directives. (line 16)
+* .req directive, ARM: ARM Directives. (line 188)
+* .save directive, ARM: ARM Directives. (line 193)
+* .secrel32 directive, ARM: ARM Directives. (line 231)
* .set arch=CPU: MIPS ISA. (line 18)
* .set autoextend: MIPS autoextend. (line 6)
+* .set doublefloat: MIPS floating-point. (line 12)
* .set dsp: MIPS ASE instruction generation overrides.
(line 21)
* .set dspr2: MIPS ASE instruction generation overrides.
(line 26)
+* .set hardfloat: MIPS floating-point. (line 6)
* .set mdmx: MIPS ASE instruction generation overrides.
(line 16)
* .set mips3d: MIPS ASE instruction generation overrides.
* .set nosym32: MIPS symbol sizes. (line 6)
* .set pop: MIPS option stack. (line 6)
* .set push: MIPS option stack. (line 6)
+* .set singlefloat: MIPS floating-point. (line 12)
* .set smartmips: MIPS ASE instruction generation overrides.
(line 11)
+* .set softfloat: MIPS floating-point. (line 6)
* .set sym32: MIPS symbol sizes. (line 6)
-* .setfp directive, ARM: ARM Directives. (line 185)
-* .unwind_raw directive, ARM: ARM Directives. (line 199)
+* .setfp directive, ARM: ARM Directives. (line 217)
+* .short directive, s390: s390 Directives. (line 16)
+* .syntax directive, ARM: ARM Directives. (line 236)
+* .thumb directive, ARM: ARM Directives. (line 240)
+* .thumb_func directive, ARM: ARM Directives. (line 243)
+* .thumb_set directive, ARM: ARM Directives. (line 254)
+* .unreq directive, ARM: ARM Directives. (line 261)
+* .unwind_raw directive, ARM: ARM Directives. (line 272)
* .v850 directive, V850: V850 Directives. (line 14)
* .v850e directive, V850: V850 Directives. (line 20)
* .v850e1 directive, V850: V850 Directives. (line 26)
-* .vsave directive, ARM: ARM Directives. (line 158)
+* .vsave directive, ARM: ARM Directives. (line 279)
* .z8001: Z8000 Directives. (line 11)
* .z8002: Z8000 Directives. (line 15)
* 16-bit code, i386: i386-16bit. (line 6)
* a.out symbol attributes: a.out Symbols. (line 6)
* A_DIR environment variable, TIC54X: TIC54X-Env. (line 6)
* ABI options, SH64: SH64 Options. (line 29)
-* ABORT directive: ABORT (COFF). (line 6)
* abort directive: Abort. (line 6)
+* ABORT directive: ABORT (COFF). (line 6)
* absolute section: Ld Sections. (line 29)
* absolute-literals directive: Absolute Literals Directive.
(line 6)
* ADRL reg,<label> pseudo op, ARM: ARM Opcodes. (line 35)
* advancing location counter: Org. (line 6)
* align directive: Align. (line 6)
-* align directive, ARM: ARM Directives. (line 6)
* align directive, SPARC: Sparc-Directives. (line 9)
* align directive, TIC54X: TIC54X-Directives. (line 6)
* alignment of branch targets: Xtensa Automatic Alignment.
* Alpha registers: Alpha-Regs. (line 6)
* Alpha relocations: Alpha-Relocs. (line 6)
* Alpha support: Alpha-Dependent. (line 6)
-* Alpha Syntax: Alpha Options. (line 54)
+* Alpha Syntax: Alpha Options. (line 62)
* Alpha-only directives: Alpha Directives. (line 10)
* altered difference tables: Word. (line 12)
* alternate syntax for the 680x0: M68K-Moto-Syntax. (line 6)
* architecture options, M680x0: M68K-Opts. (line 104)
* Architecture variant option, CRIS: CRIS-Opts. (line 33)
* architectures, PowerPC: PowerPC-Opts. (line 6)
+* architectures, SCORE: SCORE-Opts. (line 6)
* architectures, SPARC: Sparc-Opts. (line 6)
* arguments for addition: Infix Ops. (line 44)
* arguments for subtraction: Infix Ops. (line 49)
* arithmetic functions: Operators. (line 6)
* arithmetic operands: Arguments. (line 6)
* ARM data relocations: ARM-Relocations. (line 6)
-* arm directive, ARM: ARM Directives. (line 60)
* ARM floating point (IEEE): ARM Floating Point. (line 6)
* ARM identifiers: ARM-Chars. (line 15)
* ARM immediate character: ARM-Chars. (line 13)
* assembler version: v. (line 6)
* assembler, and linker: Secs Background. (line 10)
* assembly listings, enabling: a. (line 6)
-* assigning values to symbols <1>: Equ. (line 6)
-* assigning values to symbols: Setting Symbols. (line 6)
+* assigning values to symbols <1>: Setting Symbols. (line 6)
+* assigning values to symbols: Equ. (line 6)
* atmp directive, i860: Directives-i860. (line 16)
* att_syntax pseudo op, i386: i386-Syntax. (line 6)
* att_syntax pseudo op, x86-64: i386-Syntax. (line 6)
* balignl directive: Balign. (line 27)
* balignw directive: Balign. (line 27)
* bes directive, TIC54X: TIC54X-Directives. (line 197)
-* BFIN directives: BFIN Directives. (line 6)
-* BFIN syntax: BFIN Syntax. (line 6)
-* big endian output, MIPS: Overview. (line 616)
-* big endian output, PJ: Overview. (line 523)
+* big endian output, MIPS: Overview. (line 641)
+* big endian output, PJ: Overview. (line 548)
* big-endian output, MIPS: MIPS Opts. (line 13)
* bignums: Bignums. (line 6)
* binary constants, TIC54X: TIC54X-Constants. (line 8)
* binary integers: Integers. (line 6)
* bit names, IA-64: IA-64-Bits. (line 6)
* bitfields, not supported on VAX: VAX-no. (line 6)
-* Blackfin support: BFIN-Dependent. (line 6)
+* Blackfin directives: Blackfin Directives. (line 6)
+* Blackfin options (none): Blackfin Options. (line 6)
+* Blackfin support: Blackfin-Dependent. (line 6)
+* Blackfin syntax: Blackfin Syntax. (line 6)
* block: Z8000 Directives. (line 55)
* branch improvement, M680x0: M68K-Branch. (line 6)
* branch improvement, M68HC11: M68HC11-Branch. (line 6)
* byte directive, TIC54X: TIC54X-Directives. (line 36)
* C54XDSP_DIR environment variable, TIC54X: TIC54X-Env. (line 6)
* c_mode directive, TIC54X: TIC54X-Directives. (line 51)
-* call instructions, i386: i386-Mnemonics. (line 51)
+* call instructions, i386: i386-Mnemonics. (line 55)
* call instructions, relaxation: Xtensa Call Relaxation.
(line 6)
-* call instructions, x86-64: i386-Mnemonics. (line 51)
+* call instructions, x86-64: i386-Mnemonics. (line 55)
* callj, i960 pseudo-opcode: callj-i960. (line 6)
* carriage return (\r): Strings. (line 24)
* case sensitivity, Z80: Z80-Case. (line 6)
-* cfi_endproc directive: CFI directives. (line 16)
+* cfi_endproc directive: CFI directives. (line 26)
+* cfi_sections directive: CFI directives. (line 13)
* cfi_startproc directive: CFI directives. (line 6)
* char directive, TIC54X: TIC54X-Directives. (line 36)
* character constant, Z80: Z80-Chars. (line 13)
* character, single: Chars. (line 6)
* characters used in symbols: Symbol Intro. (line 6)
* clink directive, TIC54X: TIC54X-Directives. (line 45)
-* code directive, ARM: ARM Directives. (line 53)
* code16 directive, i386: i386-16bit. (line 6)
* code16gcc directive, i386: i386-16bit. (line 6)
* code32 directive, i386: i386-16bit. (line 6)
* constants, floating point: Flonums. (line 6)
* constants, integer: Integers. (line 6)
* constants, number: Numbers. (line 6)
+* constants, Sparc: Sparc-Constants. (line 6)
* constants, string: Strings. (line 6)
* constants, TIC54X: TIC54X-Constants. (line 6)
-* conversion instructions, i386: i386-Mnemonics. (line 32)
-* conversion instructions, x86-64: i386-Mnemonics. (line 32)
+* conversion instructions, i386: i386-Mnemonics. (line 36)
+* conversion instructions, x86-64: i386-Mnemonics. (line 36)
* coprocessor wait, i386: i386-Prefixes. (line 40)
* copy directive, TIC54X: TIC54X-Directives. (line 54)
* cpu directive, M680x0: M68K-Directives. (line 30)
* D10V floating point: D10V-Float. (line 6)
* D10V line comment character: D10V-Chars. (line 6)
* D10V opcode summary: D10V-Opcodes. (line 6)
-* D10V optimization: Overview. (line 401)
+* D10V optimization: Overview. (line 420)
* D10V options: D10V-Opts. (line 6)
* D10V registers: D10V-Regs. (line 6)
* D10V size modifiers: D10V-Size. (line 6)
* D30V floating point: D30V-Float. (line 6)
* D30V Guarded Execution: D30V-Guarded. (line 6)
* D30V line comment character: D30V-Chars. (line 6)
-* D30V nops: Overview. (line 409)
-* D30V nops after 32-bit multiply: Overview. (line 412)
+* D30V nops: Overview. (line 428)
+* D30V nops after 32-bit multiply: Overview. (line 431)
* D30V opcode summary: D30V-Opcodes. (line 6)
-* D30V optimization: Overview. (line 406)
+* D30V optimization: Overview. (line 425)
* D30V options: D30V-Opts. (line 6)
* D30V registers: D30V-Regs. (line 6)
* D30V size modifiers: D30V-Size. (line 6)
* dim directive: Dim. (line 6)
* directives and instructions: Statements. (line 19)
* directives for PowerPC: PowerPC-Pseudo. (line 6)
-* directives, BFIN: BFIN Directives. (line 6)
+* directives for SCORE: SCORE-Pseudo. (line 6)
+* directives, Blackfin: Blackfin Directives. (line 6)
* directives, M32R: M32R-Directives. (line 6)
* directives, M680x0: M68K-Directives. (line 6)
* directives, machine independent: Pseudo Ops. (line 6)
* directives, Xtensa: Xtensa Directives. (line 6)
* directives, Z8000: Z8000 Directives. (line 6)
+* Disable floating-point instructions: MIPS floating-point. (line 6)
+* Disable single-precision floating-point operations: MIPS floating-point.
+ (line 12)
* displacement sizing character, VAX: VAX-operands. (line 12)
-* dn and qn directives, ARM: ARM Directives. (line 29)
* dollar local symbols: Symbol Names. (line 105)
* dot (symbol): Dot. (line 6)
* double directive: Double. (line 6)
* elseif directive: Elseif. (line 6)
* empty expressions: Empty Exprs. (line 6)
* emsg directive, TIC54X: TIC54X-Directives. (line 77)
-* emulation: Overview. (line 719)
+* emulation: Overview. (line 744)
+* encoding options, i386: i386-Mnemonics. (line 32)
+* encoding options, x86-64: i386-Mnemonics. (line 32)
* end directive: End. (line 6)
* enddual directive, i860: Directives-i860. (line 11)
* endef directive: Endef. (line 6)
* endfunc directive: Endfunc. (line 6)
-* endianness, MIPS: Overview. (line 616)
-* endianness, PJ: Overview. (line 523)
+* endianness, MIPS: Overview. (line 641)
+* endianness, PJ: Overview. (line 548)
* endif directive: Endif. (line 6)
* endloop directive, TIC54X: TIC54X-Directives. (line 143)
* endm directive: Macro. (line 138)
* fepsw register, V850: V850-Regs. (line 110)
* ffloat directive, VAX: VAX-directives. (line 14)
* field directive, TIC54X: TIC54X-Directives. (line 91)
-* file directive <1>: File. (line 6)
-* file directive: LNS directives. (line 6)
+* file directive: File. (line 6)
* file directive, MSP 430: MSP430 Directives. (line 6)
-* file name, logical: File. (line 6)
+* file name, logical: File. (line 13)
* files, including: Include. (line 6)
* files, input: Input Files. (line 6)
* fill directive: Fill. (line 6)
-* filling memory <1>: Space. (line 6)
-* filling memory: Skip. (line 6)
+* filling memory <1>: Skip. (line 6)
+* filling memory: Space. (line 6)
* FLIX syntax: Xtensa Syntax. (line 6)
* float directive: Float. (line 6)
* float directive, i386: i386-Float. (line 14)
* float directive, x86-64: i386-Float. (line 14)
* floating point numbers: Flonums. (line 6)
* floating point numbers (double): Double. (line 6)
-* floating point numbers (single) <1>: Single. (line 6)
-* floating point numbers (single): Float. (line 6)
+* floating point numbers (single) <1>: Float. (line 6)
+* floating point numbers (single): Single. (line 6)
* floating point, Alpha (IEEE): Alpha Floating Point.
(line 6)
* floating point, ARC (IEEE): ARC Floating Point. (line 6)
* floating point, M68HC11: M68HC11-Float. (line 6)
* floating point, MSP 430 (IEEE): MSP430 Floating Point.
(line 6)
+* floating point, s390: s390 Floating Point. (line 6)
* floating point, SH (IEEE): SH Floating Point. (line 6)
* floating point, SPARC (IEEE): Sparc-Float. (line 6)
* floating point, V850 (IEEE): V850 Floating Point. (line 6)
* floating point, x86-64: i386-Float. (line 6)
* floating point, Z80: Z80 Floating Point. (line 6)
* flonums: Flonums. (line 6)
-* force_thumb directive, ARM: ARM Directives. (line 63)
* format of error messages: Errors. (line 24)
* format of warning messages: Errors. (line 12)
* formfeed (\f): Strings. (line 18)
* H8/300 line separator: H8/300-Chars. (line 8)
* H8/300 machine directives (none): H8/300 Directives. (line 6)
* H8/300 opcode summary: H8/300 Opcodes. (line 6)
-* H8/300 options (none): H8/300 Options. (line 6)
+* H8/300 options: H8/300 Options. (line 6)
* H8/300 registers: H8/300-Regs. (line 6)
* H8/300 size suffixes: H8/300 Opcodes. (line 163)
* H8/300 support: H8/300-Dependent. (line 6)
* i386 16-bit code: i386-16bit. (line 6)
* i386 arch directive: i386-Arch. (line 6)
* i386 att_syntax pseudo op: i386-Syntax. (line 6)
-* i386 conversion instructions: i386-Mnemonics. (line 32)
+* i386 conversion instructions: i386-Mnemonics. (line 36)
* i386 floating point: i386-Float. (line 6)
* i386 immediate operands: i386-Syntax. (line 15)
* i386 instruction naming: i386-Mnemonics. (line 6)
* i386 jump, call, return: i386-Syntax. (line 38)
* i386 jump/call operands: i386-Syntax. (line 15)
* i386 memory references: i386-Memory. (line 6)
+* i386 mnemonic compatibility: i386-Mnemonics. (line 61)
* i386 mul, imul instructions: i386-Notes. (line 6)
* i386 options: i386-Options. (line 6)
* i386 register operands: i386-Syntax. (line 15)
* i386 source, destination operands: i386-Syntax. (line 22)
* i386 support: i386-Dependent. (line 6)
* i386 syntax compatibility: i386-Syntax. (line 6)
-* i80306 support: i386-Dependent. (line 6)
+* i80386 support: i386-Dependent. (line 6)
* i860 machine directives: Directives-i860. (line 6)
* i860 opcodes: Opcodes for i860. (line 6)
* i860 support: i860-Dependent. (line 6)
* inhibiting interrupts, i386: i386-Prefixes. (line 36)
* input: Input Files. (line 6)
* input file linenumbers: Input Files. (line 35)
+* instruction aliases, s390: s390 Aliases. (line 6)
* instruction expansion, CRIS: CRIS-Expand. (line 6)
* instruction expansion, MMIX: MMIX-Expand. (line 6)
+* instruction formats, s390: s390 Formats. (line 6)
+* instruction marker, s390: s390 Instruction Marker.
+ (line 6)
+* instruction mnemonics, s390: s390 Mnemonics. (line 6)
* instruction naming, i386: i386-Mnemonics. (line 6)
* instruction naming, x86-64: i386-Mnemonics. (line 6)
+* instruction operand modifier, s390: s390 Operand Modifier.
+ (line 6)
+* instruction operands, s390: s390 Operands. (line 6)
* instruction prefixes, i386: i386-Prefixes. (line 6)
* instruction set, M680x0: M68K-opcodes. (line 6)
* instruction set, M68HC11: M68HC11-opcodes. (line 6)
* instruction summary, D10V: D10V-Opcodes. (line 6)
* instruction summary, D30V: D30V-Opcodes. (line 6)
* instruction summary, H8/300: H8/300 Opcodes. (line 6)
+* instruction summary, LM32: LM32 Opcodes. (line 6)
* instruction summary, SH: SH Opcodes. (line 6)
* instruction summary, SH64: SH64 Opcodes. (line 6)
* instruction summary, Z8000: Z8000 Opcodes. (line 6)
+* instruction syntax, s390: s390 Syntax. (line 6)
* instructions and directives: Statements. (line 19)
* int directive: Int. (line 6)
* int directive, H8/300: H8/300 Directives. (line 6)
* internal directive: Internal. (line 6)
* invalid input: Bug Criteria. (line 14)
* invocation summary: Overview. (line 6)
-* IP2K architecture options: IP2K-Opts. (line 9)
+* IP2K architecture options: IP2K-Opts. (line 14)
* IP2K options: IP2K-Opts. (line 6)
* IP2K support: IP2K-Dependent. (line 6)
* irp directive: Irp. (line 6)
* irpc directive: Irpc. (line 6)
* ISA options, SH64: SH64 Options. (line 6)
* joining text and data sections: R. (line 6)
-* jump instructions, i386: i386-Mnemonics. (line 51)
-* jump instructions, x86-64: i386-Mnemonics. (line 51)
+* jump instructions, i386: i386-Mnemonics. (line 55)
+* jump instructions, x86-64: i386-Mnemonics. (line 55)
* jump optimization, i386: i386-Jumps. (line 6)
* jump optimization, x86-64: i386-Jumps. (line 6)
* jump/call operands, i386: i386-Syntax. (line 15)
* label directive, TIC54X: TIC54X-Directives. (line 123)
* labels: Labels. (line 6)
* lcomm directive: Lcomm. (line 6)
+* lcomm directive, COFF: i386-Directives. (line 6)
* ld: Object. (line 15)
* ldouble directive M680x0: M68K-Float. (line 17)
* ldouble directive M68HC11: M68HC11-Float. (line 17)
* line comment character, IA-64: IA-64-Chars. (line 6)
* line comment character, M680x0: M68K-Chars. (line 6)
* line comment character, MSP 430: MSP430-Chars. (line 6)
+* line comment character, s390: s390 Characters. (line 6)
* line comment character, SH: SH-Chars. (line 6)
* line comment character, SH64: SH64-Chars. (line 6)
+* line comment character, Sparc: Sparc-Chars. (line 6)
* line comment character, V850: V850-Chars. (line 6)
* line comment character, Z80: Z80-Chars. (line 6)
* line comment character, Z8000: Z8000-Chars. (line 6)
* line separator, IA-64: IA-64-Chars. (line 8)
* line separator, SH: SH-Chars. (line 8)
* line separator, SH64: SH64-Chars. (line 8)
+* line separator, Sparc: Sparc-Chars. (line 8)
* line separator, Z8000: Z8000-Chars. (line 8)
-* lines starting with #: Comments. (line 38)
+* lines starting with #: Comments. (line 39)
* linker: Object. (line 15)
* linker, and assembler: Secs Background. (line 10)
* linkonce directive: Linkonce. (line 6)
* listing control: title line: Title. (line 6)
* listings, enabling: a. (line 6)
* literal directive: Literal Directive. (line 6)
+* literal pool entries, s390: s390 Literal Pool Entries.
+ (line 6)
* literal_position directive: Literal Position Directive.
(line 6)
* literal_prefix directive: Literal Prefix Directive.
(line 6)
-* little endian output, MIPS: Overview. (line 619)
-* little endian output, PJ: Overview. (line 526)
+* little endian output, MIPS: Overview. (line 644)
+* little endian output, PJ: Overview. (line 551)
* little-endian output, MIPS: MIPS Opts. (line 13)
+* LM32 modifiers: LM32-Modifiers. (line 6)
+* LM32 opcode summary: LM32 Opcodes. (line 6)
+* LM32 options (none): LM32 Options. (line 6)
+* LM32 register names: LM32-Regs. (line 6)
+* LM32 support: LM32-Dependent. (line 6)
* ln directive: Ln. (line 6)
* lo pseudo-op, V850: V850 Opcodes. (line 22)
-* loc directive: LNS directives. (line 19)
-* loc_mark_blocks directive: LNS directives. (line 50)
+* loc directive: Loc. (line 6)
+* loc_mark_labels directive: Loc_mark_labels. (line 6)
* local common symbols: Lcomm. (line 6)
+* local directive: Local. (line 6)
* local labels: Symbol Names. (line 35)
* local symbol names: Symbol Names. (line 22)
* local symbols, retaining in output: L. (line 6)
* location counter: Dot. (line 6)
* location counter, advancing: Org. (line 6)
* location counter, Z80: Z80-Chars. (line 8)
-* logical file name: File. (line 6)
+* logical file name: File. (line 13)
* logical line number: Line. (line 6)
-* logical line numbers: Comments. (line 38)
+* logical line numbers: Comments. (line 39)
* long directive: Long. (line 6)
* long directive, ARC: ARC Directives. (line 159)
* long directive, i386: i386-Float. (line 21)
* machine directives, TIC54X: TIC54X-Directives. (line 6)
* machine directives, V850: V850 Directives. (line 6)
* machine directives, VAX: VAX-directives. (line 6)
+* machine directives, x86: i386-Directives. (line 6)
* machine independent directives: Pseudo Ops. (line 6)
* machine instructions (not covered): Manual. (line 14)
* machine-independent syntax: Syntax. (line 6)
* memory-mapped registers, TIC54X: TIC54X-MMRegs. (line 6)
* merging text and data sections: R. (line 6)
* messages from assembler: Errors. (line 6)
+* MicroBlaze architectures: MicroBlaze-Dependent.
+ (line 6)
+* MicroBlaze directives: MicroBlaze Directives.
+ (line 6)
+* MicroBlaze support: MicroBlaze-Dependent.
+ (line 13)
* minus, permitted arguments: Infix Ops. (line 49)
* MIPS architecture options: MIPS Opts. (line 29)
* MIPS big-endian output: MIPS Opts. (line 13)
* MIPS DSP Release 2 instruction generation override: MIPS ASE instruction generation overrides.
(line 26)
* MIPS ECOFF sections: MIPS Object. (line 6)
-* MIPS endianness: Overview. (line 616)
-* MIPS ISA: Overview. (line 622)
+* MIPS endianness: Overview. (line 641)
+* MIPS ISA: Overview. (line 647)
* MIPS ISA override: MIPS ISA. (line 6)
* MIPS little-endian output: MIPS Opts. (line 13)
* MIPS MDMX instruction generation override: MIPS ASE instruction generation overrides.
* mmsg directive, TIC54X: TIC54X-Directives. (line 77)
* MMX, i386: i386-SIMD. (line 6)
* MMX, x86-64: i386-SIMD. (line 6)
+* mnemonic compatibility, i386: i386-Mnemonics. (line 61)
* mnemonic suffixes, i386: i386-Syntax. (line 29)
* mnemonic suffixes, x86-64: i386-Syntax. (line 29)
* mnemonics for opcodes, VAX: VAX-opcodes. (line 6)
* mnemonics, D10V: D10V-Opcodes. (line 6)
* mnemonics, D30V: D30V-Opcodes. (line 6)
* mnemonics, H8/300: H8/300 Opcodes. (line 6)
+* mnemonics, LM32: LM32 Opcodes. (line 6)
* mnemonics, SH: SH Opcodes. (line 6)
* mnemonics, SH64: SH64 Opcodes. (line 6)
* mnemonics, Z8000: Z8000 Opcodes. (line 6)
* numbers, 16-bit: hword. (line 6)
* numeric values: Expressions. (line 6)
* nword directive, SPARC: Sparc-Directives. (line 20)
+* object attributes: Object Attributes. (line 6)
* object file: Object. (line 6)
* object file format: Object Formats. (line 6)
* object file name: o. (line 6)
* opcode summary, D10V: D10V-Opcodes. (line 6)
* opcode summary, D30V: D30V-Opcodes. (line 6)
* opcode summary, H8/300: H8/300 Opcodes. (line 6)
+* opcode summary, LM32: LM32 Opcodes. (line 6)
* opcode summary, SH: SH Opcodes. (line 6)
* opcode summary, SH64: SH64 Opcodes. (line 6)
* opcode summary, Z8000: Z8000 Opcodes. (line 6)
* operator precedence: Infix Ops. (line 11)
* operators, in expressions: Operators. (line 6)
* operators, permitted arguments: Infix Ops. (line 6)
-* optimization, D10V: Overview. (line 401)
-* optimization, D30V: Overview. (line 406)
+* optimization, D10V: Overview. (line 420)
+* optimization, D30V: Overview. (line 425)
* optimizations: Xtensa Optimizations.
(line 6)
* option directive, ARC: ARC Directives. (line 162)
* options for ARC (none): ARC Options. (line 6)
* options for ARM (none): ARM Options. (line 6)
* options for AVR (none): AVR Options. (line 6)
+* options for Blackfin (none): Blackfin Options. (line 6)
* options for i386: i386-Options. (line 6)
* options for IA-64: IA-64 Options. (line 6)
+* options for LM32 (none): LM32 Options. (line 6)
* options for MSP430 (none): MSP430 Options. (line 6)
* options for PDP-11: PDP-11-Options. (line 6)
* options for PowerPC: PowerPC-Opts. (line 6)
+* options for s390: s390 Options. (line 6)
+* options for SCORE: SCORE-Opts. (line 6)
* options for SPARC: Sparc-Opts. (line 6)
* options for V850 (none): V850 Options. (line 6)
* options for VAX/VMS: VAX-Opts. (line 42)
* options, CRIS: CRIS-Opts. (line 6)
* options, D10V: D10V-Opts. (line 6)
* options, D30V: D30V-Opts. (line 6)
-* options, H8/300 (none): H8/300 Options. (line 6)
+* options, H8/300: H8/300 Options. (line 6)
* options, i960: Options-i960. (line 6)
* options, IP2K: IP2K-Opts. (line 6)
* options, M32C: M32C-Opts. (line 6)
* PDP-11 instruction naming: PDP-11-Mnemonics. (line 6)
* PDP-11 support: PDP-11-Dependent. (line 6)
* PDP-11 syntax: PDP-11-Syntax. (line 6)
-* PIC code generation for ARM: ARM Options. (line 120)
+* PIC code generation for ARM: ARM Options. (line 139)
* PIC code generation for M32R: M32R-Opts. (line 42)
* PIC selection, MIPS: MIPS Opts. (line 21)
-* PJ endianness: Overview. (line 523)
+* PJ endianness: Overview. (line 548)
* PJ options: PJ Options. (line 6)
* PJ support: PJ-Dependent. (line 6)
* plus, permitted arguments: Infix Ops. (line 44)
* register names, CRIS: CRIS-Regs. (line 6)
* register names, H8/300: H8/300-Regs. (line 6)
* register names, IA-64: IA-64-Regs. (line 6)
+* register names, LM32: LM32-Regs. (line 6)
* register names, MMIX: MMIX-Regs. (line 6)
* register names, MSP 430: MSP430-Regs. (line 6)
+* register names, Sparc: Sparc-Regs. (line 6)
* register names, V850: V850-Regs. (line 6)
* register names, VAX: VAX-operands. (line 17)
* register names, Xtensa: Xtensa Registers. (line 6)
* register names, Z80: Z80-Regs. (line 6)
+* register naming, s390: s390 Register. (line 6)
* register operands, i386: i386-Syntax. (line 15)
* register operands, x86-64: i386-Syntax. (line 15)
* registers, D10V: D10V-Regs. (line 6)
* relocation: Sections. (line 6)
* relocation example: Ld Sections. (line 40)
* relocations, Alpha: Alpha-Relocs. (line 6)
+* relocations, Sparc: Sparc-Relocs. (line 6)
* repeat prefixes, i386: i386-Prefixes. (line 44)
* reporting bugs in assembler: Reporting Bugs. (line 6)
* rept directive: Rept. (line 6)
-* req directive, ARM: ARM Directives. (line 13)
* reserve directive, SPARC: Sparc-Directives. (line 39)
* return instructions, i386: i386-Syntax. (line 38)
* return instructions, x86-64: i386-Syntax. (line 38)
* REX prefixes, i386: i386-Prefixes. (line 46)
* rsect: Z8000 Directives. (line 52)
+* s390 floating point: s390 Floating Point. (line 6)
+* s390 instruction aliases: s390 Aliases. (line 6)
+* s390 instruction formats: s390 Formats. (line 6)
+* s390 instruction marker: s390 Instruction Marker.
+ (line 6)
+* s390 instruction mnemonics: s390 Mnemonics. (line 6)
+* s390 instruction operand modifier: s390 Operand Modifier.
+ (line 6)
+* s390 instruction operands: s390 Operands. (line 6)
+* s390 instruction syntax: s390 Syntax. (line 6)
+* s390 line comment character: s390 Characters. (line 6)
+* s390 literal pool entries: s390 Literal Pool Entries.
+ (line 6)
+* s390 options: s390 Options. (line 6)
+* s390 register naming: s390 Register. (line 6)
+* s390 support: S/390-Dependent. (line 6)
* sblock directive, TIC54X: TIC54X-Directives. (line 183)
* sbttl directive: Sbttl. (line 6)
* schedule directive: Schedule Directive. (line 6)
* scl directive: Scl. (line 6)
+* SCORE architectures: SCORE-Opts. (line 6)
+* SCORE directives: SCORE-Pseudo. (line 6)
+* SCORE options: SCORE-Opts. (line 6)
+* SCORE processor: SCORE-Dependent. (line 6)
* sdaoff pseudo-op, V850: V850 Opcodes. (line 65)
* search path for .include: I. (line 6)
* sect directive, MSP 430: MSP430 Directives. (line 18)
* sect directive, TIC54X: TIC54X-Directives. (line 189)
* section directive (COFF version): Section. (line 16)
-* section directive (ELF version): Section. (line 67)
+* section directive (ELF version): Section. (line 70)
* section directive, V850: V850 Directives. (line 9)
* section override prefixes, i386: i386-Prefixes. (line 23)
-* Section Stack <1>: SubSection. (line 6)
-* Section Stack <2>: Section. (line 62)
-* Section Stack <3>: PushSection. (line 6)
-* Section Stack <4>: PopSection. (line 6)
+* Section Stack <1>: Section. (line 65)
+* Section Stack <2>: SubSection. (line 6)
+* Section Stack <3>: PopSection. (line 6)
+* Section Stack <4>: PushSection. (line 6)
* Section Stack: Previous. (line 6)
* section-relative addressing: Secs Background. (line 68)
* sections: Sections. (line 6)
* size modifiers, M680x0: M68K-Syntax. (line 8)
* size prefixes, i386: i386-Prefixes. (line 27)
* size suffixes, H8/300: H8/300 Opcodes. (line 163)
+* size, translations, Sparc: Sparc-Size-Translations.
+ (line 6)
* sizes operands, i386: i386-Syntax. (line 29)
* sizes operands, x86-64: i386-Syntax. (line 29)
* skip directive: Skip. (line 6)
* space directive, TIC54X: TIC54X-Directives. (line 197)
* space used, maximum for assembly: statistics. (line 6)
* SPARC architectures: Sparc-Opts. (line 6)
+* Sparc constants: Sparc-Constants. (line 6)
* SPARC data alignment: Sparc-Aligned-Data. (line 6)
* SPARC floating point (IEEE): Sparc-Float. (line 6)
+* Sparc line comment character: Sparc-Chars. (line 6)
+* Sparc line separator: Sparc-Chars. (line 8)
* SPARC machine directives: Sparc-Directives. (line 6)
* SPARC options: Sparc-Opts. (line 6)
+* Sparc registers: Sparc-Regs. (line 6)
+* Sparc relocations: Sparc-Relocs. (line 6)
+* Sparc size translations: Sparc-Size-Translations.
+ (line 6)
* SPARC support: Sparc-Dependent. (line 6)
+* SPARC syntax: Sparc-Aligned-Data. (line 21)
* special characters, ARC: ARC-Chars. (line 6)
* special characters, M680x0: M68K-Chars. (line 6)
* special purpose registers, MSP 430: MSP430-Regs. (line 11)
* statement separator, IA-64: IA-64-Chars. (line 8)
* statement separator, SH: SH-Chars. (line 8)
* statement separator, SH64: SH64-Chars. (line 8)
+* statement separator, Sparc: Sparc-Chars. (line 8)
* statement separator, Z8000: Z8000-Chars. (line 8)
* statements, structure of: Statements. (line 6)
* statistics, about assembly: statistics. (line 6)
* stopping the assembly: Abort. (line 6)
* string constants: Strings. (line 6)
-* string directive: String. (line 6)
+* string directive: String. (line 8)
* string directive on HPPA: HPPA Directives. (line 137)
* string directive, TIC54X: TIC54X-Directives. (line 209)
* string literals: Ascii. (line 6)
-* string, copying to object file: String. (line 6)
+* string, copying to object file: String. (line 8)
+* string16 directive: String. (line 8)
+* string16, copying to object file: String. (line 8)
+* string32 directive: String. (line 8)
+* string32, copying to object file: String. (line 8)
+* string64 directive: String. (line 8)
+* string64, copying to object file: String. (line 8)
+* string8 directive: String. (line 8)
+* string8, copying to object file: String. (line 8)
* struct directive: Struct. (line 6)
* struct directive, TIC54X: TIC54X-Directives. (line 217)
* structure debugging, COFF: Tag. (line 6)
* symbol attributes, COFF: COFF Symbols. (line 6)
* symbol attributes, SOM: SOM Symbols. (line 6)
* symbol descriptor, COFF: Desc. (line 6)
-* symbol modifiers <1>: M68HC11-Modifiers. (line 12)
-* symbol modifiers <2>: M32C-Modifiers. (line 11)
-* symbol modifiers: AVR-Modifiers. (line 12)
+* symbol modifiers <1>: AVR-Modifiers. (line 12)
+* symbol modifiers <2>: LM32-Modifiers. (line 12)
+* symbol modifiers <3>: M32C-Modifiers. (line 11)
+* symbol modifiers: M68HC11-Modifiers. (line 12)
* symbol names: Symbol Names. (line 6)
-* symbol names, $ in <1>: SH64-Chars. (line 10)
-* symbol names, $ in <2>: SH-Chars. (line 10)
+* symbol names, $ in <1>: SH-Chars. (line 10)
+* symbol names, $ in <2>: SH64-Chars. (line 10)
* symbol names, $ in <3>: D30V-Chars. (line 63)
* symbol names, $ in: D10V-Chars. (line 46)
* symbol names, local: Symbol Names. (line 22)
* syntax compatibility, i386: i386-Syntax. (line 6)
* syntax compatibility, x86-64: i386-Syntax. (line 6)
* syntax, AVR: AVR-Modifiers. (line 6)
-* syntax, BFIN: BFIN Syntax. (line 6)
+* syntax, Blackfin: Blackfin Syntax. (line 6)
* syntax, D10V: D10V-Syntax. (line 6)
* syntax, D30V: D30V-Syntax. (line 6)
+* syntax, LM32: LM32-Modifiers. (line 6)
* syntax, M32C: M32C-Modifiers. (line 6)
* syntax, M680x0: M68K-Syntax. (line 8)
* syntax, M68HC11 <1>: M68HC11-Modifiers. (line 6)
* syntax, M68HC11: M68HC11-Syntax. (line 6)
* syntax, machine-independent: Syntax. (line 6)
+* syntax, SPARC: Sparc-Aligned-Data. (line 21)
* syntax, Xtensa assembler: Xtensa Syntax. (line 6)
* sysproc directive, i960: Directives-i960. (line 37)
* tab (\t): Strings. (line 27)
* tab directive, TIC54X: TIC54X-Directives. (line 248)
* tag directive: Tag. (line 6)
-* tag directive, TIC54X: TIC54X-Directives. (line 217)
+* tag directive, TIC54X: TIC54X-Directives. (line 251)
* tdaoff pseudo-op, V850: V850 Opcodes. (line 81)
* temporary symbol names: Symbol Names. (line 35)
* text and data sections, joining: R. (line 6)
* text section: Ld Sections. (line 9)
* tfloat directive, i386: i386-Float. (line 14)
* tfloat directive, x86-64: i386-Float. (line 14)
-* thumb directive, ARM: ARM Directives. (line 57)
* Thumb support: ARM-Dependent. (line 6)
-* thumb_func directive, ARM: ARM Directives. (line 67)
-* thumb_set directive, ARM: ARM Directives. (line 78)
* TIC54X builtin math functions: TIC54X-Builtins. (line 6)
* TIC54X machine directives: TIC54X-Directives. (line 6)
* TIC54X memory-mapped registers: TIC54X-MMRegs. (line 6)
* ulong directive, TIC54X: TIC54X-Directives. (line 135)
* undefined section: Ld Sections. (line 36)
* union directive, TIC54X: TIC54X-Directives. (line 251)
-* unreq directive, ARM: ARM Directives. (line 18)
* unsegm: Z8000 Directives. (line 14)
* usect directive, TIC54X: TIC54X-Directives. (line 263)
* ushort directive, TIC54X: TIC54X-Directives. (line 111)
* version directive, TIC54X: TIC54X-Directives. (line 277)
* version of assembler: v. (line 6)
* versions of symbols: Symver. (line 6)
-* visibility <1>: Protected. (line 6)
-* visibility <2>: Internal. (line 6)
+* visibility <1>: Internal. (line 6)
+* visibility <2>: Protected. (line 6)
* visibility: Hidden. (line 6)
* VMS (VAX) options: VAX-Opts. (line 42)
* vtable_entry directive: VTableEntry. (line 6)
* word directive, x86-64: i386-Float. (line 21)
* writing patterns in memory: Fill. (line 6)
* wval: Z8000 Directives. (line 24)
+* x86 machine directives: i386-Directives. (line 6)
* x86-64 arch directive: i386-Arch. (line 6)
* x86-64 att_syntax pseudo op: i386-Syntax. (line 6)
-* x86-64 conversion instructions: i386-Mnemonics. (line 32)
+* x86-64 conversion instructions: i386-Mnemonics. (line 36)
* x86-64 floating point: i386-Float. (line 6)
* x86-64 immediate operands: i386-Syntax. (line 15)
* x86-64 instruction naming: i386-Mnemonics. (line 6)
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projects / msp430-binutils.git / blobdiff