Merge commit 'upstream/2.20'

[msp430-binutils.git] / gas / testsuite / gas / bfin / control_code2.s

diff --git a/gas/testsuite/gas/bfin/control_code2.s b/gas/testsuite/gas/bfin/control_code2.s
index 4633bcc281da9d4cc23f5ed0d9f27bb64843877c..50648cc1f1dd8dad2d79e0301f1cf169478f63a8 100755 (executable)
--- a/gas/testsuite/gas/bfin/control_code2.s
+++ b/gas/testsuite/gas/bfin/control_code2.s
@@ -1,257 +1,257 @@
-\r
-.EXTERN MY_LABEL2;\r
-.section .text;\r
-\r
-//\r
-//6 CONTROL CODE BIT MANAGEMENT\r
-//\r
-\r
-//CC = Dreg == Dreg ; /* equal, register, signed (a) */\r
-CC = R7 == R0;\r
-CC = R6 == R1;\r
-CC = R0 == R7;\r
-\r
-//CC = Dreg == imm3 ; /* equal, immediate, signed (a) */\r
-CC = R7 == -4;\r
-CC = R7 == 3;\r
-CC = R0 == -4;\r
-CC = R0 == 3;\r
-\r
-//CC = Dreg < Dreg ; /* less than, register, signed (a) */\r
-CC = R7 < R0;\r
-CC = R6 < R0;\r
-CC = R7 < R1;\r
-CC = R1 < R7;\r
-CC = R0 < R6;\r
-\r
-//CC = Dreg < imm3 ; /* less than, immediate, signed (a) */\r
-CC = R7 < -4;\r
-CC = R6 < -4;\r
-CC = R7 < 3;\r
-CC = R1 < 3;\r
-\r
-//CC = Dreg <= Dreg ; /* less than or equal, register, signed (a) */\r
-CC = R7 <= R0;\r
-CC = R6 <= R0;\r
-CC = R7 <= R1;\r
-CC = R1 <= R7;\r
-CC = R0 <= R6;\r
-\r
-//CC = Dreg <= imm3 ; /* less than or equal, immediate, signed (a) */\r
-CC = R7 <= -4;\r
-CC = R6 <= -4;\r
-CC = R7 <= 3;\r
-CC = R1 <= 3;\r
-\r
-//CC = Dreg < Dreg (IU) ; /* less than, register, unsigned (a) */\r
-CC = R7 < R0(IU);\r
-CC = R6 < R0(IU);\r
-CC = R7 < R1(IU);\r
-CC = R1 < R7(IU);\r
-CC = R0 < R6(IU);\r
-\r
-//CC = Dreg < uimm3 (IU) ; /* less than, immediate, unsigned (a) */\r
-CC = R7 < 0(IU);\r
-CC = R6 < 0(IU);\r
-CC = R7 < 7(IU);\r
-CC = R1 < 7(IU);\r
-//CC = Dreg <= Dreg (IU) ; /* less than or equal, register, unsigned (a) */\r
-CC = R7 <= R0(IU);\r
-CC = R6 <= R0(IU);\r
-CC = R7 <= R1(IU);\r
-CC = R1 <= R7(IU);\r
-CC = R0 <= R6(IU);\r
-\r
-\r
-//CC = Dreg <= uimm3 (IU) ; /* less than or equal, immediate unsigned (a) */\r
-CC = R7 <= 0(IU);\r
-CC = R6 <= 0(IU);\r
-CC = R7 <= 7(IU);\r
-CC = R1 <= 7(IU);\r
-\r
-//CC = Preg == Preg ; /* equal, register, signed (a) */\r
-CC = P5 == P0;\r
-CC = P5 == P1;\r
-CC = P0 == P2;\r
-CC = P3 == P5;\r
-\r
-//CC = Preg == imm3 ; /* equal, immediate, signed (a) */\r
-CC = P5 == -4;\r
-CC = P5 == 0;\r
-CC = P5 == 3;\r
-CC = P2 == -4;\r
-CC = P2 == 0;\r
-CC = P2 == 3;\r
-\r
-//CC = Preg < Preg ; /* less than, register, signed (a) */\r
-CC = P5 < P0;\r
-CC = P5 < P1;\r
-CC = P0 < P2;\r
-CC = P3 < P5;\r
-\r
-//CC = Preg < imm3 ; /* less than, immediate, signed (a) */\r
-CC = P5 < -4;\r
-CC = P5 < 0;\r
-CC = P5 < 3;\r
-CC = P2 < -4;\r
-CC = P2 < 0;\r
-CC = P2 < 3;\r
-\r
-\r
-//CC = Preg <= Preg ; /* less than or equal, register, signed (a) */\r
-CC = P5 <= P0;\r
-CC = P5 <= P1;\r
-CC = P0 <= P2;\r
-CC = P3 <= P5;\r
-\r
-//CC = Preg <= imm3 ; /* less than or equal, immediate, signed (a) */\r
-CC = P5 <= -4;\r
-CC = P5 <= 0;\r
-CC = P5 <= 3;\r
-CC = P2 <= -4;\r
-CC = P2 <= 0;\r
-CC = P2 <= 3;\r
-\r
-//CC = Preg < Preg (IU) ; /* less than, register, unsigned (a) */\r
-CC = P5 < P0(IU);\r
-CC = P5 < P1(IU);\r
-CC = P0 < P2(IU);\r
-CC = P3 < P5(IU);\r
-\r
-//CC = Preg < uimm3 (IU) ; /* less than, immediate, unsigned (a) */\r
-CC = P5 < 0(IU);\r
-CC = P5 < 7(IU);\r
-CC = P2 < 0(IU);\r
-CC = P2 < 7(IU);\r
-\r
-//CC = Preg <= Preg (IU) ; /* less than or equal, register, unsigned (a) */\r
-CC = P5 <= P0(IU);\r
-CC = P5 <= P1(IU);\r
-CC = P0 <= P2(IU);\r
-CC = P3 <= P5(IU);\r
-\r
-//CC = Preg <= uimm3 (IU) ; /* less than or equal, immediate unsigned (a) */\r
-CC = P5 <= 0(IU);\r
-CC = P5 <= 7(IU);\r
-CC = P2 <= 0(IU);\r
-CC = P2 <= 7(IU);\r
-\r
-CC = A0 == A1 ; /* equal, signed (a) */\r
-CC = A0 < A1 ; /* less than, Accumulator, signed (a) */\r
-CC = A0 <= A1 ; /* less than or equal, Accumulator, signed (a) */\r
-\r
-//Dreg = CC ; /* CC into 32-bit data register, zero-extended (a) */\r
-R7 = CC;\r
-R0 = CC;\r
-\r
-//statbit = CC ; /* status bit equals CC (a) */\r
-AZ = CC;\r
-AN = CC;\r
-AC0= CC;\r
-AC1= CC;\r
-//V  = CC;\r
-VS = CC; \r
-AV0= CC;\r
-AV0S= CC; \r
-AV1 = CC; \r
-AV1S= CC; \r
-AQ  = CC;\r
-//statbit |= CC ; /* status bit equals status bit OR CC (a) */\r
-AZ |= CC;\r
-AN |= CC;\r
-AC0|= CC;\r
-AC1|= CC;\r
-//V  |= CC;\r
-VS |= CC; \r
-AV0|= CC;\r
-AV0S|= CC; \r
-AV1 |= CC; \r
-AV1S|= CC; \r
-AQ  |= CC;\r
-\r
-//statbit &= CC ; /* status bit equals status bit AND CC (a) */\r
-AZ &= CC;\r
-AN &= CC;\r
-AC0&= CC;\r
-AC1&= CC;\r
-//V  &= CC;\r
-VS &= CC; \r
-AV0&= CC;\r
-AV0S&= CC; \r
-AV1 &= CC; \r
-AV1S&= CC; \r
-AQ  &= CC;\r
-\r
-//statbit ^= CC ; /* status bit equals status bit XOR CC (a) */\r
-\r
-AZ ^= CC;\r
-AN ^= CC;\r
-AC0^= CC;\r
-AC1^= CC;\r
-//V  ^= CC;\r
-VS ^= CC; \r
-AV0^= CC;\r
-AV0S^= CC; \r
-AV1 ^= CC; \r
-AV1S^= CC; \r
-AQ  ^= CC;\r
-//CC = Dreg ; /* CC set if the register is non-zero (a) */\r
-CC = R7;\r
-CC = R6;\r
-CC = R1;\r
-CC = R0;\r
-\r
-\r
-//CC = statbit ; /* CC equals status bit (a) */\r
-CC = AZ;\r
-CC = AN;\r
-CC = AC0;\r
-CC = AC1;\r
-//CC = V;\r
-CC = VS; \r
-CC = AV0;\r
-CC = AV0S; \r
-CC = AV1; \r
-CC = AV1S; \r
-CC = AQ;\r
-\r
-//CC |= statbit ; /* CC equals CC OR status bit (a) */\r
-CC |= AZ;\r
-CC |= AN;\r
-CC |= AC0;\r
-CC |= AC1;\r
-//CC |= V;\r
-CC |= VS; \r
-CC |= AV0;\r
-CC |= AV0S; \r
-CC |= AV1; \r
-CC |= AV1S; \r
-CC |= AQ;\r
-\r
-//CC &= statbit ; /* CC equals CC AND status bit (a) */\r
-CC &= AZ;\r
-CC &= AN;\r
-CC &= AC0;\r
-CC &= AC1;\r
-//CC &= V;\r
-CC &= VS; \r
-CC &= AV0;\r
-CC &= AV0S; \r
-CC &= AV1; \r
-CC &= AV1S; \r
-CC &= AQ;\r
-\r
-//CC ^= statbit ; /* CC equals CC XOR status bit (a) */\r
-CC ^= AZ;\r
-CC ^= AN;\r
-CC ^= AC0;\r
-CC ^= AC1;\r
-//CC ^= V;\r
-CC ^= VS; \r
-CC ^= AV0;\r
-CC ^= AV0S; \r
-CC ^= AV1; \r
-CC ^= AV1S; \r
-CC ^= AQ;\r
-\r
-CC = ! CC ; /* (a) */\r
+
+.EXTERN MY_LABEL2;
+.section .text;
+
+//
+//6 CONTROL CODE BIT MANAGEMENT
+//
+
+//CC = Dreg == Dreg ; /* equal, register, signed (a) */
+CC = R7 == R0;
+CC = R6 == R1;
+CC = R0 == R7;
+
+//CC = Dreg == imm3 ; /* equal, immediate, signed (a) */
+CC = R7 == -4;
+CC = R7 == 3;
+CC = R0 == -4;
+CC = R0 == 3;
+
+//CC = Dreg < Dreg ; /* less than, register, signed (a) */
+CC = R7 < R0;
+CC = R6 < R0;
+CC = R7 < R1;
+CC = R1 < R7;
+CC = R0 < R6;
+
+//CC = Dreg < imm3 ; /* less than, immediate, signed (a) */
+CC = R7 < -4;
+CC = R6 < -4;
+CC = R7 < 3;
+CC = R1 < 3;
+
+//CC = Dreg <= Dreg ; /* less than or equal, register, signed (a) */
+CC = R7 <= R0;
+CC = R6 <= R0;
+CC = R7 <= R1;
+CC = R1 <= R7;
+CC = R0 <= R6;
+
+//CC = Dreg <= imm3 ; /* less than or equal, immediate, signed (a) */
+CC = R7 <= -4;
+CC = R6 <= -4;
+CC = R7 <= 3;
+CC = R1 <= 3;
+
+//CC = Dreg < Dreg (IU) ; /* less than, register, unsigned (a) */
+CC = R7 < R0(IU);
+CC = R6 < R0(IU);
+CC = R7 < R1(IU);
+CC = R1 < R7(IU);
+CC = R0 < R6(IU);
+
+//CC = Dreg < uimm3 (IU) ; /* less than, immediate, unsigned (a) */
+CC = R7 < 0(IU);
+CC = R6 < 0(IU);
+CC = R7 < 7(IU);
+CC = R1 < 7(IU);
+//CC = Dreg <= Dreg (IU) ; /* less than or equal, register, unsigned (a) */
+CC = R7 <= R0(IU);
+CC = R6 <= R0(IU);
+CC = R7 <= R1(IU);
+CC = R1 <= R7(IU);
+CC = R0 <= R6(IU);
+
+
+//CC = Dreg <= uimm3 (IU) ; /* less than or equal, immediate unsigned (a) */
+CC = R7 <= 0(IU);
+CC = R6 <= 0(IU);
+CC = R7 <= 7(IU);
+CC = R1 <= 7(IU);
+
+//CC = Preg == Preg ; /* equal, register, signed (a) */
+CC = P5 == P0;
+CC = P5 == P1;
+CC = P0 == P2;
+CC = P3 == P5;
+
+//CC = Preg == imm3 ; /* equal, immediate, signed (a) */
+CC = P5 == -4;
+CC = P5 == 0;
+CC = P5 == 3;
+CC = P2 == -4;
+CC = P2 == 0;
+CC = P2 == 3;
+
+//CC = Preg < Preg ; /* less than, register, signed (a) */
+CC = P5 < P0;
+CC = P5 < P1;
+CC = P0 < P2;
+CC = P3 < P5;
+
+//CC = Preg < imm3 ; /* less than, immediate, signed (a) */
+CC = P5 < -4;
+CC = P5 < 0;
+CC = P5 < 3;
+CC = P2 < -4;
+CC = P2 < 0;
+CC = P2 < 3;
+
+
+//CC = Preg <= Preg ; /* less than or equal, register, signed (a) */
+CC = P5 <= P0;
+CC = P5 <= P1;
+CC = P0 <= P2;
+CC = P3 <= P5;
+
+//CC = Preg <= imm3 ; /* less than or equal, immediate, signed (a) */
+CC = P5 <= -4;
+CC = P5 <= 0;
+CC = P5 <= 3;
+CC = P2 <= -4;
+CC = P2 <= 0;
+CC = P2 <= 3;
+
+//CC = Preg < Preg (IU) ; /* less than, register, unsigned (a) */
+CC = P5 < P0(IU);
+CC = P5 < P1(IU);
+CC = P0 < P2(IU);
+CC = P3 < P5(IU);
+
+//CC = Preg < uimm3 (IU) ; /* less than, immediate, unsigned (a) */
+CC = P5 < 0(IU);
+CC = P5 < 7(IU);
+CC = P2 < 0(IU);
+CC = P2 < 7(IU);
+
+//CC = Preg <= Preg (IU) ; /* less than or equal, register, unsigned (a) */
+CC = P5 <= P0(IU);
+CC = P5 <= P1(IU);
+CC = P0 <= P2(IU);
+CC = P3 <= P5(IU);
+
+//CC = Preg <= uimm3 (IU) ; /* less than or equal, immediate unsigned (a) */
+CC = P5 <= 0(IU);
+CC = P5 <= 7(IU);
+CC = P2 <= 0(IU);
+CC = P2 <= 7(IU);
+
+CC = A0 == A1 ; /* equal, signed (a) */
+CC = A0 < A1 ; /* less than, Accumulator, signed (a) */
+CC = A0 <= A1 ; /* less than or equal, Accumulator, signed (a) */
+
+//Dreg = CC ; /* CC into 32-bit data register, zero-extended (a) */
+R7 = CC;
+R0 = CC;
+
+//statbit = CC ; /* status bit equals CC (a) */
+AZ = CC;
+AN = CC;
+AC0= CC;
+AC1= CC;
+//V  = CC;
+VS = CC; 
+AV0= CC;
+AV0S= CC; 
+AV1 = CC; 
+AV1S= CC; 
+AQ  = CC;
+//statbit |= CC ; /* status bit equals status bit OR CC (a) */
+AZ |= CC;
+AN |= CC;
+AC0|= CC;
+AC1|= CC;
+//V  |= CC;
+VS |= CC; 
+AV0|= CC;
+AV0S|= CC; 
+AV1 |= CC; 
+AV1S|= CC; 
+AQ  |= CC;
+
+//statbit &= CC ; /* status bit equals status bit AND CC (a) */
+AZ &= CC;
+AN &= CC;
+AC0&= CC;
+AC1&= CC;
+//V  &= CC;
+VS &= CC; 
+AV0&= CC;
+AV0S&= CC; 
+AV1 &= CC; 
+AV1S&= CC; 
+AQ  &= CC;
+
+//statbit ^= CC ; /* status bit equals status bit XOR CC (a) */
+
+AZ ^= CC;
+AN ^= CC;
+AC0^= CC;
+AC1^= CC;
+//V  ^= CC;
+VS ^= CC; 
+AV0^= CC;
+AV0S^= CC; 
+AV1 ^= CC; 
+AV1S^= CC; 
+AQ  ^= CC;
+//CC = Dreg ; /* CC set if the register is non-zero (a) */
+CC = R7;
+CC = R6;
+CC = R1;
+CC = R0;
+
+
+//CC = statbit ; /* CC equals status bit (a) */
+CC = AZ;
+CC = AN;
+CC = AC0;
+CC = AC1;
+//CC = V;
+CC = VS; 
+CC = AV0;
+CC = AV0S; 
+CC = AV1; 
+CC = AV1S; 
+CC = AQ;
+
+//CC |= statbit ; /* CC equals CC OR status bit (a) */
+CC |= AZ;
+CC |= AN;
+CC |= AC0;
+CC |= AC1;
+//CC |= V;
+CC |= VS; 
+CC |= AV0;
+CC |= AV0S; 
+CC |= AV1; 
+CC |= AV1S; 
+CC |= AQ;
+
+//CC &= statbit ; /* CC equals CC AND status bit (a) */
+CC &= AZ;
+CC &= AN;
+CC &= AC0;
+CC &= AC1;
+//CC &= V;
+CC &= VS; 
+CC &= AV0;
+CC &= AV0S; 
+CC &= AV1; 
+CC &= AV1S; 
+CC &= AQ;
+
+//CC ^= statbit ; /* CC equals CC XOR status bit (a) */
+CC ^= AZ;
+CC ^= AN;
+CC ^= AC0;
+CC ^= AC1;
+//CC ^= V;
+CC ^= VS; 
+CC ^= AV0;
+CC ^= AV0S; 
+CC ^= AV1; 
+CC ^= AV1S; 
+CC ^= AQ;
+
+CC = ! CC ; /* (a) */