Merge commit 'upstream/2.20'

[msp430-binutils.git] / gas / testsuite / gas / bfin / stack2.s

diff --git a/gas/testsuite/gas/bfin/stack2.s b/gas/testsuite/gas/bfin/stack2.s
index 5d7f2c23334232a341e5b576847d5e504c37f8d1..adb4288e4f8ea4c23b841be6633c7f4e51bfaa7d 100755 (executable)
--- a/gas/testsuite/gas/bfin/stack2.s
+++ b/gas/testsuite/gas/bfin/stack2.s
@@ -1,125 +1,127 @@
-\r
-.EXTERN MY_LABEL2;\r
-.section .text;\r
-\r
-//\r
-//5 STACK CONTROL\r
-//\r
-\r
-//[ -- SP ] = allreg ; /* predecrement SP (a) */\r
-\r
-[--SP ] =  R0;\r
-[--SP ] =  R6;\r
-\r
-[--SP ] =  P0;\r
-[--SP ] =  P4;\r
-\r
-[--SP ] =  I0;\r
-[--SP ] =  I1;\r
-\r
-[--SP ] =  M0;\r
-[--SP ] =  M1;\r
-\r
-[--SP ] =  L0;\r
-[--SP ] =  L1;\r
-\r
-[--SP ] =  B0;\r
-[--SP ] =  B1;\r
-\r
-[--SP ] =  A0.X;\r
-[--SP ] =  A1.X;\r
-\r
-[--SP ] =  A0.W;\r
-[--SP ] =  A1.W;\r
-\r
-[--SP ] =  ASTAT;\r
-[--SP ] =  RETS;\r
-[--SP ] =  RETI;\r
-[--SP ] =  RETX;\r
-[--SP ] =  RETN;\r
-[--SP ] =  RETE;\r
-[--SP ] =  LC0;\r
-[--SP ] =  LC1;\r
-[--SP ] =  LT0;\r
-[--SP ] =  LT1;\r
-[--SP ] =  LB0;\r
-[--SP ] =  LB1;\r
-[--SP ] =  CYCLES;\r
-[--SP ] =  CYCLES2;\r
-//[--SP ] =  EMUDAT;\r
-[--SP ] =  USP;\r
-[--SP ] =  SEQSTAT;\r
-[--SP ] =  SYSCFG;\r
-\r
-\r
-//[ -- SP ] = ( R7 : Dreglim , P5 : Preglim ) ; /* Dregs and indexed Pregs (a) */\r
-[--SP ] = ( R7:0, P5:0);\r
-\r
-\r
-//[ -- SP ] = ( R7 : Dreglim ) ; /* Dregs, only (a) */\r
-[--SP ] = ( R7:0);\r
-\r
-//[ -- SP ] = ( P5 : Preglim ) ; /* indexed Pregs, only (a) */\r
-[--SP ] = (P5:0);\r
-\r
-\r
-//mostreg = [ SP ++ ] ; /* post-increment SP; does not apply to Data Registers and Pointer Registers (a) */\r
-\r
-R0= [ SP ++ ] ;      \r
-R6= [ SP ++ ] ;      \r
-         \r
-P0= [ SP ++ ] ;      \r
-P4= [ SP ++ ] ;      \r
-         \r
-I0= [ SP ++ ] ;      \r
-I1= [ SP ++ ] ;      \r
-         \r
-M0= [ SP ++ ] ;      \r
-M1= [ SP ++ ] ;      \r
-         \r
-L0= [ SP ++ ] ;      \r
-L1= [ SP ++ ] ;      \r
-         \r
-B0= [ SP ++ ] ;      \r
-B1= [ SP ++ ] ;      \r
-         \r
-A0.X= [ SP ++ ] ;    \r
-A1.X= [ SP ++ ] ;    \r
-         \r
-A0.W= [ SP ++ ] ;    \r
-A1.W= [ SP ++ ] ;    \r
-         \r
-ASTAT= [ SP ++ ] ;   \r
-RETS= [ SP ++ ] ;    \r
-RETI= [ SP ++ ] ;    \r
-RETX= [ SP ++ ] ;    \r
-RETN= [ SP ++ ] ;    \r
-RETE= [ SP ++ ] ;    \r
-LC0= [ SP ++ ] ;     \r
-LC1= [ SP ++ ] ;     \r
-LT0= [ SP ++ ] ;     \r
-LT1= [ SP ++ ] ;     \r
-LB0= [ SP ++ ] ;     \r
-LB1= [ SP ++ ] ;     \r
-CYCLES= [ SP ++ ] ;  \r
-CYCLES2= [ SP ++ ] ; \r
-//EMUDAT= [ SP ++ ] ;  \r
-USP= [ SP ++ ] ;     \r
-SEQSTAT= [ SP ++ ] ; \r
-SYSCFG= [ SP ++ ] ;  \r
-\r
-//( R7 : Dreglim, P5 : Preglim ) = [ SP ++ ] ; /* Dregs and indexed Pregs (a) */\r
-( R7:0, P5:0) = [ SP++ ];\r
-\r
-//( R7 : Dreglim ) = [ SP ++ ] ; /* Dregs, only (a) */\r
-( R7:0) = [ SP++ ];\r
-\r
-//( P5 : Preglim ) = [ SP ++ ] ; /* indexed Pregs, only (a) */\r
-( P5:0) = [ SP++ ];\r
-\r
-//LINK uimm18m4 ; /* allocate a stack frame of specified size (b) */\r
-LINK 0X0;\r
-LINK 0X8;\r
-LINK 0x3FFFC;\r
-\r
-UNLINK ; /* de-allocate the stack frame (b)*/\r
+
+.EXTERN MY_LABEL2;
+.section .text;
+
+//
+//5 STACK CONTROL
+//
+
+//[ -- SP ] = allreg ; /* predecrement SP (a) */
+
+[--SP ] =  R0;
+[--SP ] =  R6;
+
+[--SP ] =  P0;
+[--SP ] =  P4;
+
+[--SP ] =  I0;
+[--SP ] =  I1;
+
+[--SP ] =  M0;
+[--SP ] =  M1;
+
+[--SP ] =  L0;
+[--SP ] =  L1;
+
+[--SP ] =  B0;
+[--SP ] =  B1;
+
+[--SP ] =  A0.X;
+[--SP ] =  A1.X;
+
+[--SP ] =  A0.W;
+[--SP ] =  A1.W;
+
+[--SP ] =  ASTAT;
+[--SP ] =  RETS;
+[--SP ] =  RETI;
+[--SP ] =  RETX;
+[--SP ] =  RETN;
+[--SP ] =  RETE;
+[--SP ] =  LC0;
+[--SP ] =  LC1;
+[--SP ] =  LT0;
+[--SP ] =  LT1;
+[--SP ] =  LB0;
+[--SP ] =  LB1;
+[--SP ] =  CYCLES;
+[--SP ] =  CYCLES2;
+//[--SP ] =  EMUDAT;
+[--SP ] =  USP;
+[--SP ] =  SEQSTAT;
+[--SP ] =  SYSCFG;
+
+
+//[ -- SP ] = ( R7 : Dreglim , P5 : Preglim ) ; /* Dregs and indexed Pregs (a) */
+[--SP ] = ( R7:0, P5:0);
+
+
+//[ -- SP ] = ( R7 : Dreglim ) ; /* Dregs, only (a) */
+[--SP ] = ( R7:0);
+
+//[ -- SP ] = ( P5 : Preglim ) ; /* indexed Pregs, only (a) */
+[--SP ] = (P5:0);
+
+
+//mostreg = [ SP ++ ] ; /* post-increment SP; does not apply to Data Registers and Pointer Registers (a) */
+
+R0= [ SP ++ ] ;      
+R6= [ SP ++ ] ;      
+         
+P0= [ SP ++ ] ;      
+P4= [ SP ++ ] ;      
+         
+I0= [ SP ++ ] ;      
+I1= [ SP ++ ] ;      
+         
+M0= [ SP ++ ] ;      
+M1= [ SP ++ ] ;      
+         
+L0= [ SP ++ ] ;      
+L1= [ SP ++ ] ;      
+         
+B0= [ SP ++ ] ;      
+B1= [ SP ++ ] ;      
+         
+A0.X= [ SP ++ ] ;    
+A1.X= [ SP ++ ] ;    
+         
+A0.W= [ SP ++ ] ;    
+A1.W= [ SP ++ ] ;    
+         
+ASTAT= [ SP ++ ] ;   
+RETS= [ SP ++ ] ;    
+RETI= [ SP ++ ] ;    
+RETX= [ SP ++ ] ;    
+RETN= [ SP ++ ] ;    
+RETE= [ SP ++ ] ;    
+LC0= [ SP ++ ] ;     
+LC1= [ SP ++ ] ;     
+LT0= [ SP ++ ] ;     
+LT1= [ SP ++ ] ;     
+LB0= [ SP ++ ] ;     
+LB1= [ SP ++ ] ;     
+CYCLES= [ SP ++ ] ;  
+CYCLES2= [ SP ++ ] ; 
+//EMUDAT= [ SP ++ ] ;  
+USP= [ SP ++ ] ;     
+SEQSTAT= [ SP ++ ] ; 
+SYSCFG= [ SP ++ ] ;  
+
+//( R7 : Dreglim, P5 : Preglim ) = [ SP ++ ] ; /* Dregs and indexed Pregs (a) */
+( R7:0, P5:0) = [ SP++ ];
+
+//( R7 : Dreglim ) = [ SP ++ ] ; /* Dregs, only (a) */
+( R7:0) = [ SP++ ];
+
+//( P5 : Preglim ) = [ SP ++ ] ; /* indexed Pregs, only (a) */
+( P5:0) = [ SP++ ];
+
+//LINK uimm18m4 ; /* allocate a stack frame of specified size (b) */
+LINK 0X0;
+LINK 0X8;
+LINK 0x3FFFC;
+
+UNLINK ; /* de-allocate the stack frame (b)*/
+
+L$L$foo:  (R7:6,P5:3) = [SP++]; /* Pop multiple on the same line with a label */