Merge commit 'upstream/2.20'

[msp430-binutils.git] / include / opcode / mips.h

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 71822a41bd38754a3bfc6698d89c90bfacbbf325..27d10e61a842a201b6d7623839f396deffb75ca2 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1,6 +1,6 @@
 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,

-   2003, 2004, 2005
+   2003, 2004, 2005, 2008, 2009

    Free Software Foundation, Inc.
    Contributed by Ralph Campbell and OSF
    Commented and modified by Ian Lance Taylor, Cygnus Support
    Free Software Foundation, Inc.
    Contributed by Ralph Campbell and OSF
    Commented and modified by Ian Lance Taylor, Cygnus Support


@@ -215,6 +215,16 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
 #define OP_SH_UDI4             6
 #define OP_MASK_UDI4           0xfffff
 
 #define OP_SH_UDI4             6
 #define OP_MASK_UDI4           0xfffff
 

+/* Octeon */
+#define OP_SH_BBITIND          16
+#define OP_MASK_BBITIND                0x1f
+#define OP_SH_CINSPOS          6
+#define OP_MASK_CINSPOS                0x1f
+#define OP_SH_CINSLM1          11
+#define OP_MASK_CINSLM1                0x1f
+#define OP_SH_SEQI             6
+#define OP_MASK_SEQI           0x3ff
+

 /* This structure holds information for a particular instruction.  */
 
 struct mips_opcode
 /* This structure holds information for a particular instruction.  */
 
 struct mips_opcode


@@ -252,6 +262,7 @@ struct mips_opcode
 
    Each of these characters corresponds to a mask field defined above.
 
 
    Each of these characters corresponds to a mask field defined above.
 

+   "1" 5 bit sync type (OP_*_SHAMT)

    "<" 5 bit shift amount (OP_*_SHAMT)
    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
    "a" 26 bit target address (OP_*_TARGET)
    "<" 5 bit shift amount (OP_*_SHAMT)
    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
    "a" 26 bit target address (OP_*_TARGET)


@@ -370,6 +381,20 @@ struct mips_opcode
    "+3" UDI immediate bits 6-20
    "+4" UDI immediate bits 6-25
 
    "+3" UDI immediate bits 6-20
    "+4" UDI immediate bits 6-25
 

+   Octeon:
+   "+x" Bit index field of bbit.  Enforces: 0 <= index < 32.
+   "+X" Bit index field of bbit aliasing bbit32.  Matches if 32 <= index < 64,
+       otherwise skips to next candidate.
+   "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
+   "+P" Position field of cins/exts aliasing cins32/exts32.  Matches if
+       32 <= pos < 64, otherwise skips to next candidate.
+   "+Q" Immediate field of seqi/snei.  Enforces -512 <= imm < 512.
+   "+s" Length-minus-one field of cins/exts.  Enforces: 0 <= lenm1 < 32.
+   "+S" Length-minus-one field of cins32/exts32 or cins/exts aliasing
+       cint32/exts32.  Enforces non-negative value and that
+       pos + lenm1 < 32 or pos + lenm1 < 64 depending whether previous
+       position field is "+p" or "+P".
+

    Other:
    "()" parens surrounding optional value
    ","  separates operands
    Other:
    "()" parens surrounding optional value
    ","  separates operands


@@ -377,7 +402,7 @@ struct mips_opcode
    "+"  Start of extension sequence.
 
    Characters used so far, for quick reference when adding more:
    "+"  Start of extension sequence.
 
    Characters used so far, for quick reference when adding more:

-   "234567890"
+   "1234567890"

    "%[]<>(),+:'@!$*&"
    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
    "abcdefghijklopqrstuvwxz"
    "%[]<>(),+:'@!$*&"
    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
    "abcdefghijklopqrstuvwxz"


@@ -385,8 +410,8 @@ struct mips_opcode
    Extension character sequences used so far ("+" followed by the
    following), for quick reference when adding more:
    "1234"
    Extension character sequences used so far ("+" followed by the
    following), for quick reference when adding more:
    "1234"

-   "ABCDEFGHIT"
-   "t"
+   "ABCDEFGHIPQSTX"
+   "pstx"

 */
 
 /* These are the bits which may be set in the pinfo field of an
 */
 
 /* These are the bits which may be set in the pinfo field of an


@@ -456,6 +481,9 @@ struct mips_opcode
 #define INSN_MULT                   0x40000000
 /* Instruction synchronize shared memory.  */
 #define INSN_SYNC                  0x80000000
 #define INSN_MULT                   0x40000000
 /* Instruction synchronize shared memory.  */
 #define INSN_SYNC                  0x80000000

+/* Instruction is actually a macro.  It should be ignored by the
+   disassembler, and requires special treatment by the assembler.  */
+#define INSN_MACRO                  0xffffffff

 
 /* These are the bits which may be set in the pinfo2 field of an
    instruction. */
 
 /* These are the bits which may be set in the pinfo2 field of an
    instruction. */


@@ -466,26 +494,59 @@ struct mips_opcode
 #define INSN2_READ_MDMX_ACC        0x00000002
 /* Instruction writes MDMX accumulator. */
 #define INSN2_WRITE_MDMX_ACC       0x00000004
 #define INSN2_READ_MDMX_ACC        0x00000002
 /* Instruction writes MDMX accumulator. */
 #define INSN2_WRITE_MDMX_ACC       0x00000004

-
-/* Instruction is actually a macro.  It should be ignored by the
-   disassembler, and requires special treatment by the assembler.  */
-#define INSN_MACRO                  0xffffffff
+/* Macro uses single-precision floating-point instructions.  This should
+   only be set for macros.  For instructions, FP_S in pinfo carries the
+   same information.  */
+#define INSN2_M_FP_S               0x00000008
+/* Macro uses double-precision floating-point instructions.  This should
+   only be set for macros.  For instructions, FP_D in pinfo carries the
+   same information.  */
+#define INSN2_M_FP_D               0x00000010

 
 /* Masks used to mark instructions to indicate which MIPS ISA level
 
 /* Masks used to mark instructions to indicate which MIPS ISA level

-   they were introduced in.  ISAs, as defined below, are logical
-   ORs of these bits, indicating that they support the instructions
-   defined at the given level.  */
-
-#define INSN_ISA_MASK            0x00000fff
-#define INSN_ISA1                 0x00000001
-#define INSN_ISA2                 0x00000002
-#define INSN_ISA3                 0x00000004
-#define INSN_ISA4                 0x00000008
-#define INSN_ISA5                 0x00000010
-#define INSN_ISA32                0x00000020
-#define INSN_ISA64                0x00000040
-#define INSN_ISA32R2              0x00000080
-#define INSN_ISA64R2              0x00000100
+   they were introduced in.  INSN_ISA_MASK masks an enumeration that
+   specifies the base ISA level(s).  The remainder of a 32-bit
+   word constructed using these macros is a bitmask of the remaining
+   INSN_* values below.  */
+
+#define INSN_ISA_MASK            0x0000000ful
+
+/* We cannot start at zero due to ISA_UNKNOWN below.  */
+#define INSN_ISA1                 1
+#define INSN_ISA2                 2
+#define INSN_ISA3                 3
+#define INSN_ISA4                 4
+#define INSN_ISA5                 5
+#define INSN_ISA32                6
+#define INSN_ISA32R2              7
+#define INSN_ISA64                8
+#define INSN_ISA64R2              9
+/* Below this point the INSN_* values correspond to combinations of ISAs.
+   They are only for use in the opcodes table to indicate membership of
+   a combination of ISAs that cannot be expressed using the usual inclusion
+   ordering on the above INSN_* values.  */
+#define INSN_ISA3_32              10
+#define INSN_ISA3_32R2            11
+#define INSN_ISA4_32              12
+#define INSN_ISA4_32R2            13
+#define INSN_ISA5_32R2            14
+
+/* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
+   INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
+   this table describes whether at least one of the ISAs described by X
+   is/are implemented by ISA Y.  (Think of Y as the ISA level supported by
+   a particular core and X as the ISA level(s) at which a certain instruction
+   is defined.)  The ISA(s) described by X is/are implemented by Y iff
+   (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
+   is non-zero.  */
+static const unsigned int mips_isa_table[] =
+  { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
+
+/* Masks used for Chip specific instructions.  */
+#define INSN_CHIP_MASK           0xc3ff0820
+
+/* Cavium Networks Octeon instructions.  */
+#define INSN_OCTEON              0x00000800

 
 /* Masks used for MIPS-defined ASEs.  */
 #define INSN_ASE_MASK            0x3c00f000
 
 /* Masks used for MIPS-defined ASEs.  */
 #define INSN_ASE_MASK            0x3c00f000


@@ -498,8 +559,6 @@ struct mips_opcode
 /* MIPS-3D ASE */
 #define INSN_MIPS3D               0x00008000
 
 /* MIPS-3D ASE */
 #define INSN_MIPS3D               0x00008000
 

-/* Chip specific instructions.  These are bitmasks.  */
-

 /* MIPS R4650 instruction.  */
 #define INSN_4650                 0x00010000
 /* LSI R4010 instruction.  */
 /* MIPS R4650 instruction.  */
 #define INSN_4650                 0x00010000
 /* LSI R4010 instruction.  */


@@ -529,21 +588,27 @@ struct mips_opcode
 #define INSN_SMARTMIPS            0x10000000
 /* DSP R2 ASE  */
 #define INSN_DSPR2                0x20000000
 #define INSN_SMARTMIPS            0x10000000
 /* DSP R2 ASE  */
 #define INSN_DSPR2                0x20000000

+/* ST Microelectronics Loongson 2E.  */
+#define INSN_LOONGSON_2E          0x40000000
+/* ST Microelectronics Loongson 2F.  */
+#define INSN_LOONGSON_2F          0x80000000
+/* RMI Xlr instruction */
+#define INSN_XLR                 0x00000020

 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
 #define       ISA_UNKNOWN     0               /* Gas internal use.  */
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
 #define       ISA_UNKNOWN     0               /* Gas internal use.  */

-#define       ISA_MIPS1       (INSN_ISA1)
-#define       ISA_MIPS2       (ISA_MIPS1 | INSN_ISA2)
-#define       ISA_MIPS3       (ISA_MIPS2 | INSN_ISA3)
-#define       ISA_MIPS4       (ISA_MIPS3 | INSN_ISA4)
-#define       ISA_MIPS5       (ISA_MIPS4 | INSN_ISA5)
+#define       ISA_MIPS1       INSN_ISA1
+#define       ISA_MIPS2       INSN_ISA2
+#define       ISA_MIPS3       INSN_ISA3
+#define       ISA_MIPS4       INSN_ISA4
+#define       ISA_MIPS5       INSN_ISA5

 
 

-#define       ISA_MIPS32      (ISA_MIPS2 | INSN_ISA32)
-#define       ISA_MIPS64      (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
+#define       ISA_MIPS32      INSN_ISA32
+#define       ISA_MIPS64      INSN_ISA64

 
 

-#define       ISA_MIPS32R2    (ISA_MIPS32 | INSN_ISA32R2)
-#define       ISA_MIPS64R2    (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
+#define       ISA_MIPS32R2    INSN_ISA32R2
+#define       ISA_MIPS64R2    INSN_ISA64R2

 
 
 /* CPU defines, use instead of hardcoding processor number. Keep this
 
 
 /* CPU defines, use instead of hardcoding processor number. Keep this


@@ -569,6 +634,8 @@ struct mips_opcode
 #define CPU_RM9000     9000
 #define CPU_R10000     10000
 #define CPU_R12000     12000
 #define CPU_RM9000     9000
 #define CPU_R10000     10000
 #define CPU_R12000     12000

+#define CPU_R14000     14000
+#define CPU_R16000     16000

 #define CPU_MIPS16     16
 #define CPU_MIPS32     32
 #define CPU_MIPS32R2   33
 #define CPU_MIPS16     16
 #define CPU_MIPS32     32
 #define CPU_MIPS32R2   33


@@ -576,6 +643,10 @@ struct mips_opcode
 #define CPU_MIPS64      64
 #define CPU_MIPS64R2   65
 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
 #define CPU_MIPS64      64
 #define CPU_MIPS64R2   65
 #define CPU_SB1         12310201        /* octal 'SB', 01.  */

+#define CPU_LOONGSON_2E 3001
+#define CPU_LOONGSON_2F 3002
+#define CPU_OCTEON     6501
+#define CPU_XLR        887682          /* decimal 'XLR'   */

 
 /* Test for membership in an ISA including chip specific ISAs.  INSN
    is pointer to an element of the opcode table; ISA is the specified
 
 /* Test for membership in an ISA including chip specific ISAs.  INSN
    is pointer to an element of the opcode table; ISA is the specified


@@ -583,20 +654,33 @@ struct mips_opcode
    test, or zero if no CPU specific ISA test is desired.  */
 
 #define OPCODE_IS_MEMBER(insn, isa, cpu)                               \
    test, or zero if no CPU specific ISA test is desired.  */
 
 #define OPCODE_IS_MEMBER(insn, isa, cpu)                               \

-    (((insn)->membership & isa) != 0                                   \
+    (((isa & INSN_ISA_MASK) != 0                                        \
+      && ((insn)->membership & INSN_ISA_MASK) != 0                      \
+      && ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >>                \
+           (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0)       \
+     || ((isa & ~INSN_ISA_MASK)                                         \
+          & ((insn)->membership & ~INSN_ISA_MASK)) != 0                 \

      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)    \
      || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0)   \
      || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0)   \
      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)    \
      || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)   \
      || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)    \
      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)    \
      || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0)   \
      || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0)   \
      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)    \
      || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)   \
      || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)    \

-     || ((cpu == CPU_R10000 || cpu == CPU_R12000)                      \
+     || ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000  \
+         || cpu == CPU_R16000)                                         \

         && ((insn)->membership & INSN_10000) != 0)                     \
      || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)       \
      || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)    \
      || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)   \
      || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)   \
      || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)   \
         && ((insn)->membership & INSN_10000) != 0)                     \
      || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)       \
      || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)    \
      || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)   \
      || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)   \
      || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)   \

+     || (cpu == CPU_LOONGSON_2E                                         \
+         && ((insn)->membership & INSN_LOONGSON_2E) != 0)               \
+     || (cpu == CPU_LOONGSON_2F                                         \
+         && ((insn)->membership & INSN_LOONGSON_2F) != 0)               \
+     || (cpu == CPU_OCTEON                                             \
+        && ((insn)->membership & INSN_OCTEON) != 0)                    \
+     || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0)        \

      || 0)     /* Please keep this term for easier source merging.  */
 
 /* This is a list of macro expanded instructions.
      || 0)     /* Please keep this term for easier source merging.  */
 
 /* This is a list of macro expanded instructions.


@@ -729,6 +813,11 @@ enum
   M_LWR_A,
   M_LWR_AB,
   M_LWU_AB,
   M_LWR_A,
   M_LWR_AB,
   M_LWU_AB,

+  M_MSGSND,
+  M_MSGLD,
+  M_MSGLD_T,
+  M_MSGWAIT,
+  M_MSGWAIT_T,

   M_MOVE,
   M_MUL,
   M_MUL_I,
   M_MOVE,
   M_MUL,
   M_MUL_I,


@@ -910,11 +999,10 @@ extern int bfd_mips_num_opcodes;
 #define MIPS16OP_MASK_IMM6     0x3f
 #define MIPS16OP_SH_IMM6       5
 
 #define MIPS16OP_MASK_IMM6     0x3f
 #define MIPS16OP_SH_IMM6       5
 

-/* These are the characters which may appears in the args field of an
-   instruction.  They appear in the order in which the fields appear
-   when the instruction is used.  Commas and parentheses in the args
-   string are ignored when assembling, and written into the output
-   when disassembling.
+/* These are the characters which may appears in the args field of a MIPS16
+   instruction.  They appear in the order in which the fields appear when the
+   instruction is used.  Commas and parentheses in the args string are ignored
+   when assembling, and written into the output when disassembling.

 
    "y" 3 bit register (MIPS16OP_*_RY)
    "x" 3 bit register (MIPS16OP_*_RX)
 
    "y" 3 bit register (MIPS16OP_*_RY)
    "x" 3 bit register (MIPS16OP_*_RX)