Merge commit 'upstream/2.20'

[msp430-binutils.git] / ld / testsuite / ld-powerpc / aix-glink-2-32.dd

diff --git a/ld/testsuite/ld-powerpc/aix-glink-2-32.dd b/ld/testsuite/ld-powerpc/aix-glink-2-32.dd
new file mode 100644 (file)
index 0000000..2c91d23
--- /dev/null
+++ b/ld/testsuite/ld-powerpc/aix-glink-2-32.dd
@@ -0,0 +1,69 @@
+
+tmpdir/aix-glink-2:     file format aixcoff-rs6000
+
+
+Disassembly of section \.text:
+
+10000000 <\.b1>:
+10000000:      60 00 00 00     oril    r0,r0,0
+
+10000004 <\.b2>:
+10000004:      60 00 00 00     oril    r0,r0,0
+
+10000008 <\.b3>:
+10000008:      60 00 00 00     oril    r0,r0,0
+
+1000000c <\.main>:
+1000000c:      48 00 f1 03     bla     f100 <.*>
+10000010:      48 00 00 21     bl      10000030 <\.a2>
+10000014:      48 00 00 41     bl      10000054 <\.a3>
+10000018:      4b ff ff e9     bl      10000000 <\.b1>
+1000001c:      4b ff ff e9     bl      10000004 <\.b2>
+10000020:      4b ff ff e9     bl      10000008 <\.b3>
+10000024:      48 00 f5 03     bla     f500 <.*>
+10000028:      48 00 00 51     bl      10000078 <\.c2>
+1000002c:      48 00 00 71     bl      1000009c <\.c3>
+
+10000030 <\.a2>:
+10000030:      81 82 00 00     l       r12,0\(r2\)
+10000034:      90 41 00 14     st      r2,20\(r1\)
+10000038:      80 0c 00 00     l       r0,0\(r12\)
+1000003c:      80 4c 00 04     l       r2,4\(r12\)
+10000040:      7c 09 03 a6     mtctr   r0
+10000044:      4e 80 04 20     bctr
+10000048:      00 00 00 00     \.long 0x0
+1000004c:      00 0c 80 00     \.long 0xc8000
+10000050:      00 00 00 00     \.long 0x0
+
+10000054 <\.a3>:
+10000054:      81 82 00 04     l       r12,4\(r2\)
+10000058:      90 41 00 14     st      r2,20\(r1\)
+1000005c:      80 0c 00 00     l       r0,0\(r12\)
+10000060:      80 4c 00 04     l       r2,4\(r12\)
+10000064:      7c 09 03 a6     mtctr   r0
+10000068:      4e 80 04 20     bctr
+1000006c:      00 00 00 00     \.long 0x0
+10000070:      00 0c 80 00     \.long 0xc8000
+10000074:      00 00 00 00     \.long 0x0
+
+10000078 <\.c2>:
+10000078:      81 82 00 08     l       r12,8\(r2\)
+1000007c:      90 41 00 14     st      r2,20\(r1\)
+10000080:      80 0c 00 00     l       r0,0\(r12\)
+10000084:      80 4c 00 04     l       r2,4\(r12\)
+10000088:      7c 09 03 a6     mtctr   r0
+1000008c:      4e 80 04 20     bctr
+10000090:      00 00 00 00     \.long 0x0
+10000094:      00 0c 80 00     \.long 0xc8000
+10000098:      00 00 00 00     \.long 0x0
+
+1000009c <\.c3>:
+1000009c:      81 82 00 0c     l       r12,12\(r2\)
+100000a0:      90 41 00 14     st      r2,20\(r1\)
+100000a4:      80 0c 00 00     l       r0,0\(r12\)
+100000a8:      80 4c 00 04     l       r2,4\(r12\)
+100000ac:      7c 09 03 a6     mtctr   r0
+100000b0:      4e 80 04 20     bctr
+100000b4:      00 00 00 00     \.long 0x0
+100000b8:      00 0c 80 00     \.long 0xc8000
+100000bc:      00 00 00 00     \.long 0x0