Imported binutils-2.20

[msp430-binutils.git] / ld / testsuite / ld-powerpc / tlsso.d

diff --git a/ld/testsuite/ld-powerpc/tlsso.d b/ld/testsuite/ld-powerpc/tlsso.d
index 3fa4029d5a91bedfd17a6cb0af7ad27a9c7bf011..4a3b04557d4e201ef1ea272854aa9992521bab1b 100644 (file)
--- a/ld/testsuite/ld-powerpc/tlsso.d
+++ b/ld/testsuite/ld-powerpc/tlsso.d
@@ -8,7 +8,7 @@
 
 Disassembly of section \.text:
 
-.* <\.__tls_get_addr>:
+.* <00000010\.plt_call\.__tls_get_addr(|_opt)\+0>:
 .*     f8 41 00 28     std     r2,40\(r1\)
 .*     e9 62 80 78     ld      r11,-32648\(r2\)
 .*     7d 69 03 a6     mtctr   r11
@@ -17,46 +17,47 @@ Disassembly of section \.text:
 .*     4e 80 04 20     bctr
 
 .* <_start>:
-.*     38 62 80 30     addi    r3,r2,-32720
-.*     4b ff ff e5     bl      .* <\.__tls_get_addr>
+.*     38 62 80 20     addi    r3,r2,-32736
+.*     4b ff ff e5     bl      .*
 .*     e8 41 00 28     ld      r2,40\(r1\)
-.*     38 62 80 08     addi    r3,r2,-32760
-.*     4b ff ff d9     bl      .* <\.__tls_get_addr>
+.*     38 62 80 50     addi    r3,r2,-32688
+.*     4b ff ff d9     bl      .*
 .*     e8 41 00 28     ld      r2,40\(r1\)
-.*     38 62 80 48     addi    r3,r2,-32696
-.*     4b ff ff cd     bl      .* <\.__tls_get_addr>
+.*     38 62 80 38     addi    r3,r2,-32712
+.*     4b ff ff cd     bl      .*
 .*     e8 41 00 28     ld      r2,40\(r1\)
-.*     38 62 80 08     addi    r3,r2,-32760
-.*     4b ff ff c1     bl      .* <\.__tls_get_addr>
+.*     38 62 80 50     addi    r3,r2,-32688
+.*     4b ff ff c1     bl      .*
 .*     e8 41 00 28     ld      r2,40\(r1\)
 .*     39 23 80 40     addi    r9,r3,-32704
 .*     3d 23 00 00     addis   r9,r3,0
 .*     81 49 80 48     lwz     r10,-32696\(r9\)
-.*     e9 22 80 40     ld      r9,-32704\(r2\)
+.*     e9 22 80 30     ld      r9,-32720\(r2\)
 .*     7d 49 18 2a     ldx     r10,r9,r3
-.*     e9 22 80 58     ld      r9,-32680\(r2\)
+.*     e9 22 80 48     ld      r9,-32696\(r2\)
 .*     7d 49 6a 2e     lhzx    r10,r9,r13
 .*     89 4d 00 00     lbz     r10,0\(r13\)
 .*     3d 2d 00 00     addis   r9,r13,0
 .*     99 49 00 00     stb     r10,0\(r9\)
-.*     38 62 80 18     addi    r3,r2,-32744
-.*     4b ff ff 8d     bl      .* <\.__tls_get_addr>
-.*     e8 41 00 28     ld      r2,40\(r1\)
 .*     38 62 80 08     addi    r3,r2,-32760
-.*     4b ff ff 81     bl      .* <\.__tls_get_addr>
+.*     4b ff ff 8d     bl      .*
+.*     e8 41 00 28     ld      r2,40\(r1\)
+.*     38 62 80 50     addi    r3,r2,-32688
+.*     4b ff ff 81     bl      .*
 .*     e8 41 00 28     ld      r2,40\(r1\)
 .*     f9 43 80 08     std     r10,-32760\(r3\)
 .*     3d 23 00 00     addis   r9,r3,0
 .*     91 49 80 10     stw     r10,-32752\(r9\)
-.*     e9 22 80 28     ld      r9,-32728\(r2\)
+.*     e9 22 80 18     ld      r9,-32744\(r2\)
 .*     7d 49 19 2a     stdx    r10,r9,r3
-.*     e9 22 80 58     ld      r9,-32680\(r2\)
+.*     e9 22 80 48     ld      r9,-32696\(r2\)
 .*     7d 49 6b 2e     sthx    r10,r9,r13
 .*     e9 4d 00 02     lwa     r10,0\(r13\)
 .*     3d 2d 00 00     addis   r9,r13,0
 .*     a9 49 00 00     lha     r10,0\(r9\)
 .*     00 00 00 00 .*
 .*     00 01 02 20 .*
+.* <__glink_PLTresolve>:
 .*     7d 88 02 a6     mflr    r12
 .*     42 9f 00 05     bcl-    20,4\*cr7\+so,.*
 .*     7d 68 02 a6     mflr    r11