+typedef struct initializer
+{
+ const char *name;
+ const char *init;
+} initializer;
+
+static initializer cpu_flag_init[] =
+{
+ { "CPU_UNKNOWN_FLAGS",
+ "~CpuL1OM" },
+ { "CPU_GENERIC32_FLAGS",
+ "Cpu186|Cpu286|Cpu386" },
+ { "CPU_GENERIC64_FLAGS",
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuClflush|Cpu387|Cpu687|CpuMMX|CpuSSE|CpuSSE2|CpuLM" },
+ { "CPU_NONE_FLAGS",
+ "0" },
+ { "CPU_I186_FLAGS",
+ "Cpu186" },
+ { "CPU_I286_FLAGS",
+ "Cpu186|Cpu286" },
+ { "CPU_I386_FLAGS",
+ "Cpu186|Cpu286|Cpu386" },
+ { "CPU_I486_FLAGS",
+ "Cpu186|Cpu286|Cpu386|Cpu486" },
+ { "CPU_I586_FLAGS",
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu387" },
+ { "CPU_I686_FLAGS",
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|Cpu387|Cpu687" },
+ { "CPU_P2_FLAGS",
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|Cpu387|Cpu687|CpuMMX" },
+ { "CPU_P3_FLAGS",
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|Cpu387|Cpu687|CpuMMX|CpuSSE" },
+ { "CPU_P4_FLAGS",
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuClflush|Cpu387|Cpu687|CpuMMX|CpuSSE|CpuSSE2" },
+ { "CPU_NOCONA_FLAGS",
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuClflush|Cpu387|Cpu687|CpuFISTTP|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuLM" },
+ { "CPU_CORE_FLAGS",
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuClflush|Cpu387|Cpu687|CpuFISTTP|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3" },
+ { "CPU_CORE2_FLAGS",
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuClflush|Cpu387|Cpu687|CpuFISTTP|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuLM" },
+ { "CPU_COREI7_FLAGS",
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuClflush|Cpu387|Cpu687|CpuFISTTP|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuRdtscp|CpuLM" },
+ { "CPU_K6_FLAGS",
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuSYSCALL|Cpu387|CpuMMX" },
+ { "CPU_K6_2_FLAGS",
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuSYSCALL|Cpu387|CpuMMX|Cpu3dnow" },
+ { "CPU_ATHLON_FLAGS",
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|Cpu387|Cpu687|CpuMMX|Cpu3dnow|Cpu3dnowA" },
+ { "CPU_K8_FLAGS",
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuMMX|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuLM" },
+ { "CPU_AMDFAM10_FLAGS",
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuFISTTP|CpuMMX|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM" },
+ { "CPU_8087_FLAGS",
+ "Cpu8087" },
+ { "CPU_287_FLAGS",
+ "Cpu287" },
+ { "CPU_387_FLAGS",
+ "Cpu387" },
+ { "CPU_ANY87_FLAGS",
+ "Cpu8087|Cpu287|Cpu387|Cpu687|CpuFISTTP" },
+ { "CPU_CLFLUSH_FLAGS",
+ "CpuClflush" },
+ { "CPU_SYSCALL_FLAGS",
+ "CpuSYSCALL" },
+ { "CPU_MMX_FLAGS",
+ "CpuMMX" },
+ { "CPU_SSE_FLAGS",
+ "CpuMMX|CpuSSE" },
+ { "CPU_SSE2_FLAGS",
+ "CpuMMX|CpuSSE|CpuSSE2" },
+ { "CPU_SSE3_FLAGS",
+ "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3" },
+ { "CPU_SSSE3_FLAGS",
+ "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3" },
+ { "CPU_SSE4_1_FLAGS",
+ "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1" },
+ { "CPU_SSE4_2_FLAGS",
+ "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2" },
+ { "CPU_ANY_SSE_FLAGS",
+ "CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuAVX" },
+ { "CPU_VMX_FLAGS",
+ "CpuVMX" },
+ { "CPU_SMX_FLAGS",
+ "CpuSMX" },
+ { "CPU_XSAVE_FLAGS",
+ "CpuXsave" },
+ { "CPU_AES_FLAGS",
+ "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAES" },
+ { "CPU_PCLMUL_FLAGS",
+ "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuPCLMUL" },
+ { "CPU_FMA_FLAGS",
+ "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA" },
+ { "CPU_FMA4_FLAGS",
+ "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA4" },
+ { "CPU_MOVBE_FLAGS",
+ "CpuMovbe" },
+ { "CPU_RDTSCP_FLAGS",
+ "CpuRdtscp" },
+ { "CPU_EPT_FLAGS",
+ "CpuEPT" },
+ { "CPU_3DNOW_FLAGS",
+ "CpuMMX|Cpu3dnow" },
+ { "CPU_3DNOWA_FLAGS",
+ "CpuMMX|Cpu3dnow|Cpu3dnowA" },
+ { "CPU_PADLOCK_FLAGS",
+ "CpuPadLock" },
+ { "CPU_SVME_FLAGS",
+ "CpuSVME" },
+ { "CPU_SSE4A_FLAGS",
+ "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a" },
+ { "CPU_ABM_FLAGS",
+ "CpuABM" },
+ { "CPU_AVX_FLAGS",
+ "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX" },
+ { "CPU_ANY_AVX_FLAGS",
+ "CpuAVX" },
+ { "CPU_L1OM_FLAGS",
+ "unknown" },
+};
+
+static initializer operand_type_init[] =
+{
+ { "OPERAND_TYPE_NONE",
+ "0" },
+ { "OPERAND_TYPE_REG8",
+ "Reg8" },
+ { "OPERAND_TYPE_REG16",
+ "Reg16" },
+ { "OPERAND_TYPE_REG32",
+ "Reg32" },
+ { "OPERAND_TYPE_REG64",
+ "Reg64" },
+ { "OPERAND_TYPE_IMM1",
+ "Imm1" },
+ { "OPERAND_TYPE_IMM8",
+ "Imm8" },
+ { "OPERAND_TYPE_IMM8S",
+ "Imm8S" },
+ { "OPERAND_TYPE_IMM16",
+ "Imm16" },
+ { "OPERAND_TYPE_IMM32",
+ "Imm32" },
+ { "OPERAND_TYPE_IMM32S",
+ "Imm32S" },
+ { "OPERAND_TYPE_IMM64",
+ "Imm64" },
+ { "OPERAND_TYPE_BASEINDEX",
+ "BaseIndex" },
+ { "OPERAND_TYPE_DISP8",
+ "Disp8" },
+ { "OPERAND_TYPE_DISP16",
+ "Disp16" },
+ { "OPERAND_TYPE_DISP32",
+ "Disp32" },
+ { "OPERAND_TYPE_DISP32S",
+ "Disp32S" },
+ { "OPERAND_TYPE_DISP64",
+ "Disp64" },
+ { "OPERAND_TYPE_INOUTPORTREG",
+ "InOutPortReg" },
+ { "OPERAND_TYPE_SHIFTCOUNT",
+ "ShiftCount" },
+ { "OPERAND_TYPE_CONTROL",
+ "Control" },
+ { "OPERAND_TYPE_TEST",
+ "Test" },
+ { "OPERAND_TYPE_DEBUG",
+ "FloatReg" },
+ { "OPERAND_TYPE_FLOATREG",
+ "FloatReg" },
+ { "OPERAND_TYPE_FLOATACC",
+ "FloatAcc" },
+ { "OPERAND_TYPE_SREG2",
+ "SReg2" },
+ { "OPERAND_TYPE_SREG3",
+ "SReg3" },
+ { "OPERAND_TYPE_ACC",
+ "Acc" },
+ { "OPERAND_TYPE_JUMPABSOLUTE",
+ "JumpAbsolute" },
+ { "OPERAND_TYPE_REGMMX",
+ "RegMMX" },
+ { "OPERAND_TYPE_REGXMM",
+ "RegXMM" },
+ { "OPERAND_TYPE_REGYMM",
+ "RegYMM" },
+ { "OPERAND_TYPE_ESSEG",
+ "EsSeg" },
+ { "OPERAND_TYPE_ACC32",
+ "Reg32|Acc|Dword" },
+ { "OPERAND_TYPE_ACC64",
+ "Reg64|Acc|Qword" },
+ { "OPERAND_TYPE_INOUTPORTREG",
+ "InOutPortReg" },
+ { "OPERAND_TYPE_REG16_INOUTPORTREG",
+ "Reg16|InOutPortReg" },
+ { "OPERAND_TYPE_DISP16_32",
+ "Disp16|Disp32" },
+ { "OPERAND_TYPE_ANYDISP",
+ "Disp8|Disp16|Disp32|Disp32S|Disp64" },
+ { "OPERAND_TYPE_IMM16_32",
+ "Imm16|Imm32" },
+ { "OPERAND_TYPE_IMM16_32S",
+ "Imm16|Imm32S" },
+ { "OPERAND_TYPE_IMM16_32_32S",
+ "Imm16|Imm32|Imm32S" },
+ { "OPERAND_TYPE_IMM32_32S_DISP32",
+ "Imm32|Imm32S|Disp32" },
+ { "OPERAND_TYPE_IMM64_DISP64",
+ "Imm64|Disp64" },
+ { "OPERAND_TYPE_IMM32_32S_64_DISP32",
+ "Imm32|Imm32S|Imm64|Disp32" },
+ { "OPERAND_TYPE_IMM32_32S_64_DISP32_64",
+ "Imm32|Imm32S|Imm64|Disp32|Disp64" },
+};
+
+typedef struct bitfield
+{
+ int position;
+ int value;
+ const char *name;
+} bitfield;
+
+#define BITFIELD(n) { n, 0, #n }
+
+static bitfield cpu_flags[] =
+{
+ BITFIELD (Cpu186),
+ BITFIELD (Cpu286),
+ BITFIELD (Cpu386),
+ BITFIELD (Cpu486),
+ BITFIELD (Cpu586),
+ BITFIELD (Cpu686),
+ BITFIELD (CpuClflush),
+ BITFIELD (CpuSYSCALL),
+ BITFIELD (Cpu8087),
+ BITFIELD (Cpu287),
+ BITFIELD (Cpu387),
+ BITFIELD (Cpu687),
+ BITFIELD (CpuFISTTP),
+ BITFIELD (CpuMMX),
+ BITFIELD (CpuSSE),
+ BITFIELD (CpuSSE2),
+ BITFIELD (CpuSSE3),
+ BITFIELD (CpuSSSE3),
+ BITFIELD (CpuSSE4_1),
+ BITFIELD (CpuSSE4_2),
+ BITFIELD (CpuAVX),
+ BITFIELD (CpuL1OM),
+ BITFIELD (CpuSSE4a),
+ BITFIELD (Cpu3dnow),
+ BITFIELD (Cpu3dnowA),
+ BITFIELD (CpuPadLock),
+ BITFIELD (CpuSVME),
+ BITFIELD (CpuVMX),
+ BITFIELD (CpuSMX),
+ BITFIELD (CpuABM),
+ BITFIELD (CpuXsave),
+ BITFIELD (CpuAES),
+ BITFIELD (CpuPCLMUL),
+ BITFIELD (CpuFMA),
+ BITFIELD (CpuFMA4),
+ BITFIELD (CpuLM),
+ BITFIELD (CpuMovbe),
+ BITFIELD (CpuEPT),
+ BITFIELD (CpuRdtscp),
+ BITFIELD (Cpu64),
+ BITFIELD (CpuNo64),
+#ifdef CpuUnused
+ BITFIELD (CpuUnused),
+#endif
+};
+
+static bitfield opcode_modifiers[] =
+{
+ BITFIELD (D),
+ BITFIELD (W),
+ BITFIELD (S),
+ BITFIELD (Modrm),
+ BITFIELD (ShortForm),
+ BITFIELD (Jump),
+ BITFIELD (JumpDword),
+ BITFIELD (JumpByte),
+ BITFIELD (JumpInterSegment),
+ BITFIELD (FloatMF),
+ BITFIELD (FloatR),
+ BITFIELD (FloatD),
+ BITFIELD (Size16),
+ BITFIELD (Size32),
+ BITFIELD (Size64),
+ BITFIELD (IgnoreSize),
+ BITFIELD (DefaultSize),
+ BITFIELD (No_bSuf),
+ BITFIELD (No_wSuf),
+ BITFIELD (No_lSuf),
+ BITFIELD (No_sSuf),
+ BITFIELD (No_qSuf),
+ BITFIELD (No_ldSuf),
+ BITFIELD (FWait),
+ BITFIELD (IsString),
+ BITFIELD (RegKludge),
+ BITFIELD (FirstXmm0),
+ BITFIELD (Implicit1stXmm0),
+ BITFIELD (ByteOkIntel),
+ BITFIELD (ToDword),
+ BITFIELD (ToQword),
+ BITFIELD (AddrPrefixOp0),
+ BITFIELD (IsPrefix),
+ BITFIELD (ImmExt),
+ BITFIELD (NoRex64),
+ BITFIELD (Rex64),
+ BITFIELD (Ugh),
+ BITFIELD (Vex),
+ BITFIELD (Vex256),
+ BITFIELD (VexNDS),
+ BITFIELD (VexNDD),
+ BITFIELD (VexW0),
+ BITFIELD (VexW1),
+ BITFIELD (Vex0F),
+ BITFIELD (Vex0F38),
+ BITFIELD (Vex0F3A),
+ BITFIELD (Vex3Sources),
+ BITFIELD (VexImmExt),
+ BITFIELD (SSE2AVX),
+ BITFIELD (NoAVX),
+ BITFIELD (OldGcc),
+ BITFIELD (ATTMnemonic),
+ BITFIELD (ATTSyntax),
+ BITFIELD (IntelSyntax),
+};
+
+static bitfield operand_types[] =
+{
+ BITFIELD (Reg8),
+ BITFIELD (Reg16),
+ BITFIELD (Reg32),
+ BITFIELD (Reg64),
+ BITFIELD (FloatReg),
+ BITFIELD (RegMMX),
+ BITFIELD (RegXMM),
+ BITFIELD (RegYMM),
+ BITFIELD (Imm8),
+ BITFIELD (Imm8S),
+ BITFIELD (Imm16),
+ BITFIELD (Imm32),
+ BITFIELD (Imm32S),
+ BITFIELD (Imm64),
+ BITFIELD (Imm1),
+ BITFIELD (BaseIndex),
+ BITFIELD (Disp8),
+ BITFIELD (Disp16),
+ BITFIELD (Disp32),
+ BITFIELD (Disp32S),
+ BITFIELD (Disp64),
+ BITFIELD (InOutPortReg),
+ BITFIELD (ShiftCount),
+ BITFIELD (Control),
+ BITFIELD (Debug),
+ BITFIELD (Test),
+ BITFIELD (SReg2),
+ BITFIELD (SReg3),
+ BITFIELD (Acc),
+ BITFIELD (FloatAcc),
+ BITFIELD (JumpAbsolute),
+ BITFIELD (EsSeg),
+ BITFIELD (RegMem),
+ BITFIELD (Mem),
+ BITFIELD (Byte),
+ BITFIELD (Word),
+ BITFIELD (Dword),
+ BITFIELD (Fword),
+ BITFIELD (Qword),
+ BITFIELD (Tbyte),
+ BITFIELD (Xmmword),
+ BITFIELD (Ymmword),
+ BITFIELD (Unspecified),
+ BITFIELD (Anysize),
+#ifdef OTUnused
+ BITFIELD (OTUnused),
+#endif
+};
+
+static const char *filename;
+
+static int
+compare (const void *x, const void *y)
+{
+ const bitfield *xp = (const bitfield *) x;
+ const bitfield *yp = (const bitfield *) y;
+ return xp->position - yp->position;
+}
+