+mm0, RegMMX, 0, 0, 29, 41
+mm1, RegMMX, 0, 1, 30, 42
+mm2, RegMMX, 0, 2, 31, 43
+mm3, RegMMX, 0, 3, 32, 44
+mm4, RegMMX, 0, 4, 33, 45
+mm5, RegMMX, 0, 5, 34, 46
+mm6, RegMMX, 0, 6, 35, 47
+mm7, RegMMX, 0, 7, 36, 48
+xmm0, RegXMM, 0, 0, 21, 17
+xmm1, RegXMM, 0, 1, 22, 18
+xmm2, RegXMM, 0, 2, 23, 19
+xmm3, RegXMM, 0, 3, 24, 20
+xmm4, RegXMM, 0, 4, 25, 21
+xmm5, RegXMM, 0, 5, 26, 22
+xmm6, RegXMM, 0, 6, 27, 23
+xmm7, RegXMM, 0, 7, 28, 24
+xmm8, RegXMM, RegRex, 0, Dw2Inval, 25
+xmm9, RegXMM, RegRex, 1, Dw2Inval, 26
+xmm10, RegXMM, RegRex, 2, Dw2Inval, 27
+xmm11, RegXMM, RegRex, 3, Dw2Inval, 28
+xmm12, RegXMM, RegRex, 4, Dw2Inval, 29
+xmm13, RegXMM, RegRex, 5, Dw2Inval, 30
+xmm14, RegXMM, RegRex, 6, Dw2Inval, 31
+xmm15, RegXMM, RegRex, 7, Dw2Inval, 32
+// AVX registers.
+ymm0, RegYMM, 0, 0, Dw2Inval, Dw2Inval
+ymm1, RegYMM, 0, 1, Dw2Inval, Dw2Inval
+ymm2, RegYMM, 0, 2, Dw2Inval, Dw2Inval
+ymm3, RegYMM, 0, 3, Dw2Inval, Dw2Inval
+ymm4, RegYMM, 0, 4, Dw2Inval, Dw2Inval
+ymm5, RegYMM, 0, 5, Dw2Inval, Dw2Inval
+ymm6, RegYMM, 0, 6, Dw2Inval, Dw2Inval
+ymm7, RegYMM, 0, 7, Dw2Inval, Dw2Inval
+ymm8, RegYMM, RegRex, 0, Dw2Inval, Dw2Inval
+ymm9, RegYMM, RegRex, 1, Dw2Inval, Dw2Inval
+ymm10, RegYMM, RegRex, 2, Dw2Inval, Dw2Inval
+ymm11, RegYMM, RegRex, 3, Dw2Inval, Dw2Inval
+ymm12, RegYMM, RegRex, 4, Dw2Inval, Dw2Inval
+ymm13, RegYMM, RegRex, 5, Dw2Inval, Dw2Inval
+ymm14, RegYMM, RegRex, 6, Dw2Inval, Dw2Inval
+ymm15, RegYMM, RegRex, 7, Dw2Inval, Dw2Inval
+// No type will make these registers rejected for all purposes except
+// for addressing. This saves creating one extra type for RIP/EIP.
+rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16
+eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval
+// No type will make these registers rejected for all purposes except
+// for addressing.
+eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval
+riz, BaseIndex, 0, RegRiz, Dw2Inval, Dw2Inval