Imported binutils-2.20

[msp430-binutils.git] / opcodes / m88k-dis.c

diff --git a/opcodes/m88k-dis.c b/opcodes/m88k-dis.c
index edecb4ba638a6ef4a1a1a45cecdddf9e42b5ac90..181ae3076c2bbb49697bd833ecb9f2e713cf797b 100644 (file)
--- a/opcodes/m88k-dis.c
+++ b/opcodes/m88k-dis.c
@@ -1,6 +1,6 @@
 /* Print instructions for the Motorola 88000, for GDB and GNU Binutils.
    Copyright 1986, 1987, 1988, 1989, 1990, 1991, 1993, 1998, 2000, 2001,
 /* Print instructions for the Motorola 88000, for GDB and GNU Binutils.
    Copyright 1986, 1987, 1988, 1989, 1990, 1991, 1993, 1998, 2000, 2001,

-   2002, 2005, 2007  Free Software Foundation, Inc.
+   2002, 2005, 2007, 2008  Free Software Foundation, Inc.

    Contributed by Data General Corporation, November 1989.
    Partially derived from an earlier printcmd.c.
 
    Contributed by Data General Corporation, November 1989.
    Partially derived from an earlier printcmd.c.
 


@@ -276,15 +276,15 @@ const INSTAB  instructions[] =
   {0x8400bc20,"fcmpu.sxs   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
   {0x8400bd20,"fcmpu.sxx   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
 
   {0x8400bc20,"fcmpu.sxs   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
   {0x8400bd20,"fcmpu.sxx   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
 

-  {0x84000820,"fcvt.sd     ",{21,5,REG} ,{0,5,REG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
-  {0x84000880,"fcvt.ds     ",{21,5,REG} ,{0,5,REG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
+  {0x84000820,"fcvt.ds     ",{21,5,REG} ,{0,5,REG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
+  {0x84000880,"fcvt.sd     ",{21,5,REG} ,{0,5,REG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },

 
 

-  {0x84008880,"fcvt.ds     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
-  {0x840088c0,"fcvt.dx     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
-  {0x84008820,"fcvt.sd     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
-  {0x84008840,"fcvt.sx     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
-  {0x84008920,"fcvt.xd     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
-  {0x84008900,"fcvt.xs     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
+  {0x84008880,"fcvt.sd     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
+  {0x840088c0,"fcvt.xd     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
+  {0x84008820,"fcvt.ds     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
+  {0x84008840,"fcvt.xs     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
+  {0x84008920,"fcvt.dx     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
+  {0x84008900,"fcvt.sx     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },

 
   {0x8400f2a0,"fdiv.ddd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
   {0x8400f280,"fdiv.dds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
 
   {0x8400f2a0,"fdiv.ddd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
   {0x8400f280,"fdiv.dds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },


@@ -696,7 +696,7 @@ m88kdis (bfd_vma pc,
   unsigned int opcode;
   const HASHTAB *entry_ptr;
   int opmask;
   unsigned int opcode;
   const HASHTAB *entry_ptr;
   int opmask;

-  unsigned int class;
+  unsigned int in_class;

 
   if (! ihashtab_initialized)
     {
 
   if (! ihashtab_initialized)
     {


@@ -706,17 +706,17 @@ m88kdis (bfd_vma pc,
 
   /* Create the appropriate mask to isolate the opcode.  */
   opmask = DEFMASK;
 
   /* Create the appropriate mask to isolate the opcode.  */
   opmask = DEFMASK;

-  class = instruction & DEFMASK;
-  if ((class >= SFU0) && (class <= SFU7))
+  in_class = instruction & DEFMASK;
+  if ((in_class >= SFU0) && (in_class <= SFU7))

     {
       if (instruction < SFU1)
        opmask = CTRLMASK;
       else
        opmask = SFUMASK;
     }
     {
       if (instruction < SFU1)
        opmask = CTRLMASK;
       else
        opmask = SFUMASK;
     }

-  else if (class == RRR)
+  else if (in_class == RRR)

     opmask = RRRMASK;
     opmask = RRRMASK;

-  else if (class == RRI10)
+  else if (in_class == RRI10)

     opmask = RRI10MASK;
 
   /* Isolate the opcode.  */
     opmask = RRI10MASK;
 
   /* Isolate the opcode.  */