]> oss.titaniummirror.com Git - msp430-binutils.git/blobdiff - opcodes/mips-opc.c
Merge commit 'upstream/2.20'
[msp430-binutils.git] / opcodes / mips-opc.c
index 7c2ef2bd316375915ad8616e54f78c4704c2054a..6278a2056617bcefea60bafc39b3e5e4afb63936 100644 (file)
@@ -1,6 +1,6 @@
 /* mips-opc.c -- MIPS opcode list.
    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
-   2003, 2004, 2005, 2007  Free Software Foundation, Inc.
+   2003, 2004, 2005, 2006, 2007, 2008, 2009  Free Software Foundation, Inc.
    Contributed by Ralph Campbell and OSF
    Commented and modified by Ian Lance Taylor, Cygnus Support
    Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
@@ -62,6 +62,7 @@
 #define WR_C1  INSN_COP
 #define WR_C2   INSN_COP
 #define WR_C3   INSN_COP
+#define CP     INSN_COP
 
 #define WR_HI  INSN_WRITE_HI
 #define RD_HI  INSN_READ_HI
 #define I64     INSN_ISA64
 #define I33    INSN_ISA32R2
 #define I65    INSN_ISA64R2
+#define I3_32   INSN_ISA3_32
+#define I3_33   INSN_ISA3_32R2
+#define I4_32   INSN_ISA4_32
+#define I4_33   INSN_ISA4_32R2
+#define I5_33   INSN_ISA5_32R2
 
 /* MIPS16 ASE support.  */
 #define I16     INSN_MIPS16
 /* MIPS64 MDMX ASE support.  */
 #define MX      INSN_MDMX
 
+#define IL2E    (INSN_LOONGSON_2E)
+#define IL2F    (INSN_LOONGSON_2F)
+
 #define P3     INSN_4650
 #define L1     INSN_4010
 #define V1     (INSN_4100 | INSN_4111 | INSN_4120)
 #define N5     (INSN_5400 | INSN_5500)
 #define N54    INSN_5400
 #define N55    INSN_5500
+#define IOCT   INSN_OCTEON
+#define XLR     INSN_XLR
 
 #define G1      (T3             \
                  )
@@ -174,8 +185,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
    them first.  The assemblers uses a hash table based on the
    instruction name anyhow.  */
 /* name,    args,      match,      mask,       pinfo,                  pinfo2,         membership */
-{"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                  0,              I4|I32|G3       },
-{"prefx",   "h,t(b)",  0x4c00000f, 0xfc0007ff, RD_b|RD_t,              0,              I4|I33  },
+{"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                  0,              I4_32|G3        },
+{"prefx",   "h,t(b)",  0x4c00000f, 0xfc0007ff, RD_b|RD_t|FP_S,         0,              I4_33   },
 {"nop",     "",         0x00000000, 0xffffffff, 0,                     INSN2_ALIAS,    I1      }, /* sll */
 {"ssnop",   "",         0x00000040, 0xffffffff, 0,                     INSN2_ALIAS,    I32|N55 }, /* sll */
 {"ehb",     "",         0x000000c0, 0xffffffff, 0,                     INSN2_ALIAS,    I33     }, /* sll */
@@ -193,16 +204,20 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"abs",     "d,v",     0,    (int) M_ABS,      INSN_MACRO,             0,              I1      },
 {"abs.s",   "D,V",     0x46000005, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
 {"abs.d",   "D,V",     0x46200005, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
-{"abs.ps",  "D,V",     0x46c00005, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5|I33  },
+{"abs.ps",  "D,V",     0x46c00005, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5_33|IL2F      },
+{"abs.ps",  "D,V",     0x45600005, 0xffff003f, WR_D|RD_S|FP_D,         0,              IL2E    },
 {"add",     "d,v,t",   0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"add",     "t,r,I",   0,    (int) M_ADD_I,    INSN_MACRO,             0,              I1      },
+{"add",        "D,S,T",        0x45c00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2E    },
+{"add",        "D,S,T",        0x4b40000c,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2F    },
 {"add.s",   "D,V,T",   0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
 {"add.d",   "D,V,T",   0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
 {"add.ob",  "X,Y,Q",   0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
 {"add.ob",  "D,S,T",   0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"add.ob",  "D,S,T[e]",        0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"add.ob",  "D,S,k",   0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
-{"add.ps",  "D,V,T",   0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
+{"add.ps",  "D,V,T",   0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5_33|IL2F      },
+{"add.ps",  "D,V,T",   0x45600000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              IL2E    },
 {"add.qh",  "X,Y,Q",   0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
 {"adda.ob", "Y,Q",     0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
 {"adda.qh", "Y,Q",     0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
@@ -213,35 +228,46 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"addr.ps", "D,S,T",   0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
 {"addu",    "d,v,t",   0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"addu",    "t,r,I",   0,    (int) M_ADDU_I,   INSN_MACRO,             0,              I1      },
+{"addu",       "D,S,T",        0x45800000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2E    },
+{"addu",       "D,S,T",        0x4b00000c,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2F    },
 {"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
 {"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
-{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
+{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D,    0,              I5_33   },
 {"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,            MX|SB1  },
 {"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,            MX      },
 {"and",     "d,v,t",   0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"and",     "t,r,I",   0,    (int) M_AND_I,    INSN_MACRO,             0,              I1      },
+{"and",        "D,S,T",        0x47c00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"and",        "D,S,T",        0x4bc00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"and.ob",  "X,Y,Q",   0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
 {"and.ob",  "D,S,T",   0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"and.ob",  "D,S,T[e]",        0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"and.ob",  "D,S,k",   0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"and.qh",  "X,Y,Q",   0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
 {"andi",    "t,r,i",   0x30000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
+{"baddu",   "d,v,t",   0x70000028, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              IOCT    },
 /* b is at the top of the table.  */
 /* bal is at the top of the table.  */
+{"bbit032", "s,+x,p",  0xd8000000, 0xfc000000, RD_s|CBD,               0,              IOCT    },
+{"bbit0",   "s,+X,p",  0xd8000000, 0xfc000000, RD_s|CBD,               0,              IOCT    }, /* bbit032 */
+{"bbit0",   "s,+x,p",  0xc8000000, 0xfc000000, RD_s|CBD,               0,              IOCT    },
+{"bbit132", "s,+x,p",  0xf8000000, 0xfc000000, RD_s|CBD,               0,              IOCT    },
+{"bbit1",   "s,+X,p",  0xf8000000, 0xfc000000, RD_s|CBD,               0,              IOCT    }, /* bbit132 */
+{"bbit1",   "s,+x,p",  0xe8000000, 0xfc000000, RD_s|CBD,               0,              IOCT    },
 /* bc0[tf]l? are at the bottom of the table.  */
 {"bc1any2f", "N,p",    0x45200000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
 {"bc1any2t", "N,p",    0x45210000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
 {"bc1any4f", "N,p",    0x45400000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
 {"bc1any4t", "N,p",    0x45410000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
 {"bc1f",    "p",       0x45000000, 0xffff0000, CBD|RD_CC|FP_S,         0,              I1      },
-{"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S,        0,              I4|I32  },
+{"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S,        0,              I4_32   },
 {"bc1fl",   "p",       0x45020000, 0xffff0000, CBL|RD_CC|FP_S,         0,              I2|T3   },
-{"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S,        0,              I4|I32  },
+{"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S,        0,              I4_32   },
 {"bc1t",    "p",       0x45010000, 0xffff0000, CBD|RD_CC|FP_S,         0,              I1      },
-{"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S,        0,              I4|I32  },
+{"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S,        0,              I4_32   },
 {"bc1tl",   "p",       0x45030000, 0xffff0000, CBL|RD_CC|FP_S,         0,              I2|T3   },
-{"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S,        0,              I4|I32  },
+{"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S,        0,              I4_32   },
 /* bc2* are at the bottom of the table.  */
 /* bc3* are at the bottom of the table.  */
 {"beqz",    "s,p",     0x10000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
@@ -304,116 +330,132 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"break",   "c",       0x0000000d, 0xfc00ffff, TRAP,                   0,              I1      },
 {"break",   "c,q",     0x0000000d, 0xfc00003f, TRAP,                   0,              I1      },
 {"c.f.d",   "S,T",     0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
-{"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4|I32  },
+{"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
-{"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4|I32  },
-{"c.f.ps",  "S,T",     0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
-{"c.f.ps",  "M,S,T",   0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
+{"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
+{"c.f.ps",  "S,T",     0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.f.ps",  "S,T",     0x45600030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
+{"c.f.ps",  "M,S,T",   0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.un.d",  "S,T",     0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
-{"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4|I32  },
+{"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
-{"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4|I32  },
-{"c.un.ps", "S,T",     0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
-{"c.un.ps", "M,S,T",   0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
+{"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
+{"c.un.ps", "S,T",     0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.un.ps", "S,T",     0x45600031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
+{"c.un.ps", "M,S,T",   0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.eq.d",  "S,T",     0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
-{"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4|I32  },
+{"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
-{"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4|I32  },
+{"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
 {"c.eq.ob", "Y,Q",     0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
 {"c.eq.ob", "S,T",     0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"c.eq.ob", "S,T[e]",  0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"c.eq.ob", "S,k",     0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
-{"c.eq.ps", "S,T",     0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
-{"c.eq.ps", "M,S,T",   0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
+{"c.eq.ps", "S,T",     0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.eq.ps", "S,T",     0x45600032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
+{"c.eq.ps", "M,S,T",   0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.eq.qh", "Y,Q",     0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
 {"c.ueq.d", "S,T",     0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
-{"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4|I32  },
+{"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
-{"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4|I32  },
-{"c.ueq.ps","S,T",     0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
-{"c.ueq.ps","M,S,T",   0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
+{"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
+{"c.ueq.ps","S,T",     0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.ueq.ps","S,T",     0x45600033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
+{"c.ueq.ps","M,S,T",   0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,             I1      },
-{"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4|I32  },
+{"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.olt.s", "S,T",     0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
-{"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4|I32  },
-{"c.olt.ps","S,T",     0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
-{"c.olt.ps","M,S,T",   0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
+{"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
+{"c.olt.ps","S,T",     0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.olt.ps","S,T",     0x45600034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
+{"c.olt.ps","M,S,T",   0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.ult.d", "S,T",     0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
-{"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4|I32  },
+{"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
-{"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4|I32  },
-{"c.ult.ps","S,T",     0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
-{"c.ult.ps","M,S,T",   0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
+{"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
+{"c.ult.ps","S,T",     0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.ult.ps","S,T",     0x45600035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
+{"c.ult.ps","M,S,T",   0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,             I1      },
-{"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4|I32  },
+{"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
-{"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4|I32  },
-{"c.ole.ps","S,T",     0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
-{"c.ole.ps","M,S,T",   0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
+{"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
+{"c.ole.ps","S,T",     0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.ole.ps","S,T",     0x45600036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
+{"c.ole.ps","M,S,T",   0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.ule.d", "S,T",     0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
-{"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4|I32  },
+{"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
-{"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4|I32  },
-{"c.ule.ps","S,T",     0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
-{"c.ule.ps","M,S,T",   0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
+{"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
+{"c.ule.ps","S,T",     0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.ule.ps","S,T",     0x45600037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
+{"c.ule.ps","M,S,T",   0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.sf.d",  "S,T",     0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
-{"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4|I32  },
+{"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
-{"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4|I32  },
-{"c.sf.ps", "S,T",     0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
-{"c.sf.ps", "M,S,T",   0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
+{"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
+{"c.sf.ps", "S,T",     0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.sf.ps", "S,T",     0x45600038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
+{"c.sf.ps", "M,S,T",   0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.ngle.d","S,T",     0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
-{"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4|I32  },
+{"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
-{"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4|I32  },
-{"c.ngle.ps","S,T",    0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
-{"c.ngle.ps","M,S,T",  0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
+{"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
+{"c.ngle.ps","S,T",    0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.ngle.ps","S,T",    0x45600039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
+{"c.ngle.ps","M,S,T",  0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.seq.d", "S,T",     0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
-{"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4|I32  },
+{"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
-{"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4|I32  },
-{"c.seq.ps","S,T",     0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
-{"c.seq.ps","M,S,T",   0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
+{"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
+{"c.seq.ps","S,T",     0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.seq.ps","S,T",     0x4560003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
+{"c.seq.ps","M,S,T",   0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.ngl.d", "S,T",     0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
-{"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4|I32  },
+{"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
-{"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4|I32  },
-{"c.ngl.ps","S,T",     0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
-{"c.ngl.ps","M,S,T",   0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
+{"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
+{"c.ngl.ps","S,T",     0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.ngl.ps","S,T",     0x4560003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
+{"c.ngl.ps","M,S,T",   0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.lt.d",  "S,T",     0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
-{"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4|I32  },
+{"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.lt.s",  "S,T",     0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
-{"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4|I32  },
+{"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
 {"c.lt.ob", "Y,Q",     0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
 {"c.lt.ob", "S,T",     0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"c.lt.ob", "S,T[e]",  0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"c.lt.ob", "S,k",     0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
-{"c.lt.ps", "S,T",     0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
-{"c.lt.ps", "M,S,T",   0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
+{"c.lt.ps", "S,T",     0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.lt.ps", "S,T",     0x4560003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
+{"c.lt.ps", "M,S,T",   0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.lt.qh", "Y,Q",     0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
 {"c.nge.d", "S,T",     0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
-{"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4|I32  },
+{"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
-{"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4|I32  },
-{"c.nge.ps","S,T",     0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
-{"c.nge.ps","M,S,T",   0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
+{"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
+{"c.nge.ps","S,T",     0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.nge.ps","S,T",     0x4560003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
+{"c.nge.ps","M,S,T",   0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.le.d",  "S,T",     0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
-{"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4|I32  },
+{"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.le.s",  "S,T",     0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
-{"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4|I32  },
+{"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
 {"c.le.ob", "Y,Q",     0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
 {"c.le.ob", "S,T",     0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"c.le.ob", "S,T[e]",  0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"c.le.ob", "S,k",     0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
-{"c.le.ps", "S,T",     0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
-{"c.le.ps", "M,S,T",   0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
+{"c.le.ps", "S,T",     0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.le.ps", "S,T",     0x4560003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
+{"c.le.ps", "M,S,T",   0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.le.qh", "Y,Q",     0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
 {"c.ngt.d", "S,T",     0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
-{"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4|I32  },
+{"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
-{"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4|I32  },
-{"c.ngt.ps","S,T",     0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
-{"c.ngt.ps","M,S,T",   0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
+{"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
+{"c.ngt.ps","S,T",     0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.ngt.ps","S,T",     0x4560003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
+{"c.ngt.ps","M,S,T",   0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"cabs.eq.d",  "M,S,T",        0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
 {"cabs.eq.ps", "M,S,T",        0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
 {"cabs.eq.s",  "M,S,T",        0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
@@ -467,10 +509,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"flushd",  "",                0xbc020000, 0xffffffff, 0,                      0,              L1      },
 {"flushid", "",                0xbc030000, 0xffffffff, 0,                      0,              L1      },
 {"wb",             "o(b)",     0xbc040000, 0xfc1f0000, SM|RD_b,                0,              L1      },
-{"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,                  0,              I3|I32|T3},
-{"cache",   "k,A(b)",  0,    (int) M_CACHE_AB, INSN_MACRO,             0,              I3|I32|T3},
-{"ceil.l.d", "D,S",    0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
-{"ceil.l.s", "D,S",    0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
+{"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,                  0,              I3_32|T3},
+{"cache",   "k,A(b)",  0,    (int) M_CACHE_AB, INSN_MACRO,             0,              I3_32|T3},
+{"ceil.l.d", "D,S",    0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3_33   },
+{"ceil.l.s", "D,S",    0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3_33   },
 {"ceil.w.d", "D,S",    0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
 {"ceil.w.s", "D,S",    0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
 {"cfc0",    "t,G",     0x40400000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1      },
@@ -481,6 +523,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"cftc1",   "d,E",     0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,            MT32    },
 {"cftc1",   "d,T",     0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,            MT32    },
 {"cftc2",   "d,E",     0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
+{"cins32",  "t,r,+p,+S",0x70000033, 0xfc00003f, WR_t|RD_s,             0,              IOCT    },
+{"cins",    "t,r,+P,+S",0x70000033, 0xfc00003f, WR_t|RD_s,             0,              IOCT    }, /* cins32 */
+{"cins",    "t,r,+p,+s",0x70000032, 0xfc00003f, WR_t|RD_s,             0,              IOCT    },
 {"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s,        0,              I32|N55 },
 {"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s,        0,              I32|N55 },
 {"ctc0",    "t,G",     0x40c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
@@ -491,28 +536,31 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"cttc1",   "t,g",     0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            MT32    },
 {"cttc1",   "t,S",     0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            MT32    },
 {"cttc2",   "t,g",     0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC,    0,              MT32    },
-{"cvt.d.l", "D,S",     0x46a00021, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
+{"cvt.d.l", "D,S",     0x46a00021, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3_33   },
 {"cvt.d.s", "D,S",     0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
 {"cvt.d.w", "D,S",     0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
-{"cvt.l.d", "D,S",     0x46200025, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
-{"cvt.l.s", "D,S",     0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
-{"cvt.s.l", "D,S",     0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
+{"cvt.l.d", "D,S",     0x46200025, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3_33   },
+{"cvt.l.s", "D,S",     0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3_33   },
+{"cvt.s.l", "D,S",     0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3_33   },
 {"cvt.s.d", "D,S",     0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
 {"cvt.s.w", "D,S",     0x46800020, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
-{"cvt.s.pl","D,S",     0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I5|I33  },
-{"cvt.s.pu","D,S",     0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I5|I33  },
+{"cvt.s.pl","D,S",     0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I5_33   },
+{"cvt.s.pu","D,S",     0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I5_33   },
 {"cvt.w.d", "D,S",     0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
 {"cvt.w.s", "D,S",     0x46000024, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
 {"cvt.ps.pw", "D,S",   0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              M3D     },
-{"cvt.ps.s","D,V,T",   0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0,            I5|I33  },
+{"cvt.ps.s","D,V,T",   0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0,            I5_33   },
 {"cvt.pw.ps", "D,S",   0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              M3D     },
 {"dabs",    "d,v",     0,    (int) M_DABS,     INSN_MACRO,             0,              I3      },
 {"dadd",    "d,v,t",   0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
 {"dadd",    "t,r,I",   0,    (int) M_DADD_I,   INSN_MACRO,             0,              I3      },
+{"dadd",       "D,S,T",        0x45e00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"dadd",       "D,S,T",        0x4b60000c,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"daddi",   "t,r,j",   0x60000000, 0xfc000000, WR_t|RD_s,              0,              I3      },
 {"daddiu",  "t,r,j",   0x64000000, 0xfc000000, WR_t|RD_s,              0,              I3      },
 {"daddu",   "d,v,t",   0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
 {"daddu",   "t,r,I",   0,    (int) M_DADDU_I,  INSN_MACRO,             0,              I3      },
+{"daddwc",  "d,s,t",   0x70000038, 0xfc0007ff, WR_d|RD_s|RD_t|WR_C0|RD_C0,     0,      XLR     },
 {"dbreak",  "",                0x7000003f, 0xffffffff, 0,                      0,              N5      },
 {"dclo",    "U,s",      0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t,        0,              I64|N55 },
 {"dclz",    "U,s",      0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t,        0,              I64|N55 },
@@ -532,8 +580,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             I3      },
 {"ddivu",   "d,v,t",   0,    (int) M_DDIVU_3,  INSN_MACRO,             0,              I3      },
 {"ddivu",   "d,v,I",   0,    (int) M_DDIVU_3I, INSN_MACRO,             0,              I3      },
-{"di",      "",                0x41606000, 0xffffffff, WR_t|WR_C0,             0,              I33     },
-{"di",      "t",       0x41606000, 0xffe0ffff, WR_t|WR_C0,             0,              I33     },
+{"di",      "",                0x41606000, 0xffffffff, WR_t|WR_C0,             0,              I33|IOCT},
+{"di",      "t",       0x41606000, 0xffe0ffff, WR_t|WR_C0,             0,              I33|IOCT},
 {"dins",    "t,r,I,+I",        0,    (int) M_DINS,     INSN_MACRO,             0,              I65     },
 {"dins",    "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s,                    0,              I65     },
 {"dinsm",   "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s,                    0,              I65     },
@@ -568,14 +616,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dmaccu",  "d,s,t",   0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
 {"dmaccus", "d,s,t",   0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
 {"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO,       0,             N411    },
-{"dmfc0",   "t,G",     0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I3      },
-{"dmfc0",   "t,+D",     0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,        0,              I64     },
-{"dmfc0",   "t,G,H",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,        0,              I64     },
+{"dmfc0",   "t,G",     0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I3|IOCT },
+{"dmfc0",   "t,+D",     0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,        0,              I64|IOCT},
+{"dmfc0",   "t,G,H",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,        0,              I64|IOCT},
 {"dmt",     "",                0x41600bc1, 0xffffffff, TRAP,                   0,              MT32    },
 {"dmt",     "t",       0x41600bc1, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
-{"dmtc0",   "t,G",     0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I3      },
-{"dmtc0",   "t,+D",     0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I64     },
-{"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I64     },
+{"dmtc0",   "t,G",     0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I3|IOCT },
+{"dmtc0",   "t,+D",     0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I64|IOCT},
+{"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I64|IOCT},
 {"dmfc1",   "t,S",     0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I3      },
 {"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,             I3      },
 {"dmtc1",   "t,S",     0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I3      },
@@ -584,6 +632,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* dmtc2 is at the bottom of the table.  */
 /* dmfc3 is at the bottom of the table.  */
 /* dmtc3 is at the bottom of the table.  */
+{"dmul",    "d,v,t",   0x70000003, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              IOCT    },
 {"dmul",    "d,v,t",   0,    (int) M_DMUL,     INSN_MACRO,             0,              I3      },
 {"dmul",    "d,v,I",   0,    (int) M_DMUL_I,   INSN_MACRO,             0,              I3      },
 {"dmulo",   "d,v,t",   0,    (int) M_DMULO,    INSN_MACRO,             0,              I3      },
@@ -594,12 +643,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             I3      },
 {"dneg",    "d,w",     0x0000002e, 0xffe007ff, WR_d|RD_t,              0,              I3      }, /* dsub 0 */
 {"dnegu",   "d,w",     0x0000002f, 0xffe007ff, WR_d|RD_t,              0,              I3      }, /* dsubu 0*/
+{"dpop",    "d,v",     0x7000002d, 0xfc1f07ff, WR_d|RD_s,              0,              IOCT    },
 {"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             I3      },
-{"drem",    "d,v,t",   3,    (int) M_DREM_3,   INSN_MACRO,             0,              I3      },
-{"drem",    "d,v,I",   3,    (int) M_DREM_3I,  INSN_MACRO,             0,              I3      },
+{"drem",    "d,v,t",   0,    (int) M_DREM_3,   INSN_MACRO,             0,              I3      },
+{"drem",    "d,v,I",   0,    (int) M_DREM_3I,  INSN_MACRO,             0,              I3      },
 {"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             I3      },
-{"dremu",   "d,v,t",   3,    (int) M_DREMU_3,  INSN_MACRO,             0,              I3      },
-{"dremu",   "d,v,I",   3,    (int) M_DREMU_3I, INSN_MACRO,             0,              I3      },
+{"dremu",   "d,v,t",   0,    (int) M_DREMU_3,  INSN_MACRO,             0,              I3      },
+{"dremu",   "d,v,I",   0,    (int) M_DREMU_3I, INSN_MACRO,             0,              I3      },
 {"dret",    "",                0x7000003e, 0xffffffff, 0,                      0,              N5      },
 {"drol",    "d,v,t",   0,    (int) M_DROL,     INSN_MACRO,             0,              I3      },
 {"drol",    "d,v,I",   0,    (int) M_DROL_I,   INSN_MACRO,             0,              I3      },
@@ -621,32 +671,43 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dsll",    "d,w,s",   0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsllv */
 {"dsll",    "d,w,>",   0x0000003c, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsll32 */
 {"dsll",    "d,w,<",   0x00000038, 0xffe0003f, WR_d|RD_t,              0,              I3      },
+{"dsll",       "D,S,T",        0x45a00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"dsll",       "D,S,T",        0x4b20000e,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"dsrav",   "d,t,s",   0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
 {"dsra32",  "d,w,<",   0x0000003f, 0xffe0003f, WR_d|RD_t,              0,              I3      },
 {"dsra",    "d,w,s",   0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsrav */
 {"dsra",    "d,w,>",   0x0000003f, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsra32 */
 {"dsra",    "d,w,<",   0x0000003b, 0xffe0003f, WR_d|RD_t,              0,              I3      },
+{"dsra",       "D,S,T",        0x45e00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"dsra",       "D,S,T",        0x4b60000f,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"dsrlv",   "d,t,s",   0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
 {"dsrl32",  "d,w,<",   0x0000003e, 0xffe0003f, WR_d|RD_t,              0,              I3      },
 {"dsrl",    "d,w,s",   0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsrlv */
 {"dsrl",    "d,w,>",   0x0000003e, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsrl32 */
 {"dsrl",    "d,w,<",   0x0000003a, 0xffe0003f, WR_d|RD_t,              0,              I3      },
+{"dsrl",       "D,S,T",        0x45a00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"dsrl",       "D,S,T",        0x4b20000f,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"dsub",    "d,v,t",   0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
 {"dsub",    "d,v,I",   0,    (int) M_DSUB_I,   INSN_MACRO,             0,              I3      },
+{"dsub",       "D,S,T",        0x45e00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"dsub",       "D,S,T",        0x4b60000d,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"dsubu",   "d,v,t",   0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
 {"dsubu",   "d,v,I",   0,    (int) M_DSUBU_I,  INSN_MACRO,             0,              I3      },
 {"dvpe",    "",                0x41600001, 0xffffffff, TRAP,                   0,              MT32    },
 {"dvpe",    "t",       0x41600001, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
-{"ei",      "",                0x41606020, 0xffffffff, WR_t|WR_C0,             0,              I33     },
-{"ei",      "t",       0x41606020, 0xffe0ffff, WR_t|WR_C0,             0,              I33     },
+{"ei",      "",                0x41606020, 0xffffffff, WR_t|WR_C0,             0,              I33|IOCT},
+{"ei",      "t",       0x41606020, 0xffe0ffff, WR_t|WR_C0,             0,              I33|IOCT},
 {"emt",     "",                0x41600be1, 0xffffffff, TRAP,                   0,              MT32    },
 {"emt",     "t",       0x41600be1, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
-{"eret",    "",         0x42000018, 0xffffffff, 0,                     0,              I3|I32  },
+{"eret",    "",         0x42000018, 0xffffffff, 0,                     0,              I3_32   },
 {"evpe",    "",                0x41600021, 0xffffffff, TRAP,                   0,              MT32    },
 {"evpe",    "t",       0x41600021, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
 {"ext",     "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s,                    0,              I33     },
-{"floor.l.d", "D,S",   0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
-{"floor.l.s", "D,S",   0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
+{"exts32",  "t,r,+p,+S",0x7000003b, 0xfc00003f, WR_t|RD_s,             0,              IOCT    },
+{"exts",    "t,r,+P,+S",0x7000003b, 0xfc00003f, WR_t|RD_s,             0,              IOCT    }, /* exts32 */
+{"exts",    "t,r,+p,+s",0x7000003a, 0xfc00003f, WR_t|RD_s,             0,              IOCT    },
+{"floor.l.d", "D,S",   0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3_33   },
+{"floor.l.s", "D,S",   0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3_33   },
 {"floor.w.d", "D,S",   0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
 {"floor.w.s", "D,S",   0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
 {"hibernate","",        0x42000023, 0xffffffff,        0,                      0,              V1      },
@@ -688,13 +749,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ld",     "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b,              0,              I3      },
 {"ld",      "t,o(b)",  0,    (int) M_LD_OB,    INSN_MACRO,             0,              I1      },
 {"ld",      "t,A(b)",  0,    (int) M_LD_AB,    INSN_MACRO,             0,              I1      },
+{"ldaddw",  "t,b",     0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b,      0,              XLR     },
+{"ldaddwu", "t,b",     0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b,      0,              XLR     },
+{"ldaddd",  "t,b",     0x70000012, 0xfc00ffff, SM|RD_t|WR_t|RD_b,      0,              XLR     },
 {"ldc1",    "T,o(b)",  0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      },
 {"ldc1",    "E,o(b)",  0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      },
-{"ldc1",    "T,A(b)",  0,    (int) M_LDC1_AB,  INSN_MACRO,             0,              I2      },
-{"ldc1",    "E,A(b)",  0,    (int) M_LDC1_AB,  INSN_MACRO,             0,              I2      },
+{"ldc1",    "T,A(b)",  0,    (int) M_LDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I2      },
+{"ldc1",    "E,A(b)",  0,    (int) M_LDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I2      },
 {"l.d",     "T,o(b)",  0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      }, /* ldc1 */
-{"l.d",     "T,o(b)",  0,    (int) M_L_DOB,    INSN_MACRO,             0,              I1      },
-{"l.d",     "T,A(b)",  0,    (int) M_L_DAB,    INSN_MACRO,             0,              I1      },
+{"l.d",     "T,o(b)",  0,    (int) M_L_DOB,    INSN_MACRO,             INSN2_M_FP_D,   I1      },
+{"l.d",     "T,A(b)",  0,    (int) M_L_DAB,    INSN_MACRO,             INSN2_M_FP_D,   I1      },
 {"ldc2",    "E,o(b)",  0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2      },
 {"ldc2",    "E,A(b)",  0,    (int) M_LDC2_AB,  INSN_MACRO,             0,              I2      },
 {"ldc3",    "E,o(b)",  0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2      },
@@ -703,32 +767,32 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ldl",            "t,A(b)",   0,    (int) M_LDL_AB,   INSN_MACRO,             0,              I3      },
 {"ldr",            "t,o(b)",   0x6c000000, 0xfc000000, LDD|WR_t|RD_b,          0,              I3      },
 {"ldr",     "t,A(b)",  0,    (int) M_LDR_AB,   INSN_MACRO,             0,              I3      },
-{"ldxc1",   "D,t(b)",  0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I4|I33  },
+{"ldxc1",   "D,t(b)",  0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I4_33   },
 {"lh",      "t,o(b)",  0x84000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
 {"lh",      "t,A(b)",  0,    (int) M_LH_AB,    INSN_MACRO,             0,              I1      },
 {"lhu",     "t,o(b)",  0x94000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
 {"lhu",     "t,A(b)",  0,    (int) M_LHU_AB,   INSN_MACRO,             0,              I1      },
 /* li is at the start of the table.  */
-{"li.d",    "t,F",     0,    (int) M_LI_D,     INSN_MACRO,             0,              I1      },
-{"li.d",    "T,L",     0,    (int) M_LI_DD,    INSN_MACRO,             0,              I1      },
-{"li.s",    "t,f",     0,    (int) M_LI_S,     INSN_MACRO,             0,              I1      },
-{"li.s",    "T,l",     0,    (int) M_LI_SS,    INSN_MACRO,             0,              I1      },
+{"li.d",    "t,F",     0,    (int) M_LI_D,     INSN_MACRO,             INSN2_M_FP_D,   I1      },
+{"li.d",    "T,L",     0,    (int) M_LI_DD,    INSN_MACRO,             INSN2_M_FP_D,   I1      },
+{"li.s",    "t,f",     0,    (int) M_LI_S,     INSN_MACRO,             INSN2_M_FP_S,   I1      },
+{"li.s",    "T,l",     0,    (int) M_LI_SS,    INSN_MACRO,             INSN2_M_FP_S,   I1      },
 {"ll",     "t,o(b)",   0xc0000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      },
 {"ll",     "t,A(b)",   0,    (int) M_LL_AB,    INSN_MACRO,             0,              I2      },
 {"lld",            "t,o(b)",   0xd0000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I3      },
 {"lld",     "t,A(b)",  0,    (int) M_LLD_AB,   INSN_MACRO,             0,              I3      },
 {"lui",     "t,u",     0x3c000000, 0xffe00000, WR_t,                   0,              I1      },
-{"luxc1",   "D,t(b)",  0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I5|I33|N55},
+{"luxc1",   "D,t(b)",  0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I5_33|N55},
 {"lw",      "t,o(b)",  0x8c000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
 {"lw",      "t,A(b)",  0,    (int) M_LW_AB,    INSN_MACRO,             0,              I1      },
 {"lwc0",    "E,o(b)",  0xc0000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
 {"lwc0",    "E,A(b)",  0,    (int) M_LWC0_AB,  INSN_MACRO,             0,              I1      },
 {"lwc1",    "T,o(b)",  0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      },
 {"lwc1",    "E,o(b)",  0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      },
-{"lwc1",    "T,A(b)",  0,    (int) M_LWC1_AB,  INSN_MACRO,             0,              I1      },
-{"lwc1",    "E,A(b)",  0,    (int) M_LWC1_AB,  INSN_MACRO,             0,              I1      },
+{"lwc1",    "T,A(b)",  0,    (int) M_LWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1      },
+{"lwc1",    "E,A(b)",  0,    (int) M_LWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1      },
 {"l.s",     "T,o(b)",  0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      }, /* lwc1 */
-{"l.s",     "T,A(b)",  0,    (int) M_LWC1_AB,  INSN_MACRO,             0,              I1      },
+{"l.s",     "T,A(b)",  0,    (int) M_LWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1      },
 {"lwc2",    "E,o(b)",  0xc8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
 {"lwc2",    "E,A(b)",  0,    (int) M_LWC2_AB,  INSN_MACRO,             0,              I1      },
 {"lwc3",    "E,o(b)",  0xcc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
@@ -744,7 +808,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"fork",    "d,s,t",   0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t,    0,              MT32    },
 {"lwu",     "t,o(b)",  0x9c000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I3      },
 {"lwu",     "t,A(b)",  0,    (int) M_LWU_AB,   INSN_MACRO,             0,              I3      },
-{"lwxc1",   "D,t(b)",  0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I4|I33  },
+{"lwxc1",   "D,t(b)",  0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_S, 0,             I4_33   },
 {"lwxs",    "d,t(b)",  0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d,     0,              SMT     },
 {"macc",    "d,s,t",   0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
 {"macc",    "d,s,t",   0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
@@ -760,9 +824,15 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"maccus",  "d,s,t",   0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
 {"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,             P3      },
 {"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,             P3      },
-{"madd.d",  "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,         I4|I33  },
-{"madd.s",  "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    0,         I4|I33  },
-{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,         I5|I33  },
+{"madd.d",  "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,         I4_33   },
+{"madd.d",     "D,S,T",        0x46200018,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"madd.d",     "D,S,T",        0x72200018,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"madd.s",  "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    0,         I4_33   },
+{"madd.s",     "D,S,T",        0x46000018,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2E    },
+{"madd.s",     "D,S,T",        0x72000018,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2F    },
+{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,         I5_33   },
+{"madd.ps",    "D,S,T",        0x45600018,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"madd.ps",    "D,S,T",        0x71600018,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,                L1      },
 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,                I32|N55 },
 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,                G1      },
@@ -800,9 +870,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mftlo",   "d",       0x41000021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
 {"mftlo",   "d,*",     0x41000021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
 {"mftr",    "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d,            0,              MT32    },
-{"mfc0",    "t,G",     0x40000000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1      },
-{"mfc0",    "t,+D",     0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,        0,              I32     },
-{"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,        0,              I32     },
+{"mfc0",    "t,G",     0x40000000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1|IOCT },
+{"mfc0",    "t,+D",     0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,        0,              I32|IOCT},
+{"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,        0,              I32|IOCT},
 {"mfc1",    "t,S",     0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
 {"mfc1",    "t,G",     0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
 {"mfhc1",   "t,S",     0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I33     },
@@ -816,6 +886,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mflo",    "d",       0x00000012, 0xffff07ff, WR_d|RD_LO,             0,              I1      },
 {"mflo",    "d,9",     0x00000012, 0xff9f07ff, WR_d|RD_LO,             0,              D32     },
 {"mflhxu",  "d",       0x00000052, 0xffff07ff, WR_d|MOD_HILO,          0,              SMT     },
+{"mfcr",    "t,s",     0x70000018, 0xfc00ffff, WR_t,                   0,              XLR     },
 {"min.ob",  "X,Y,Q",   0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
 {"min.ob",  "D,S,T",   0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"min.ob",  "D,S,T[e]",        0x48000006, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
@@ -823,42 +894,55 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"min.qh",  "X,Y,Q",   0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
 {"mov.d",   "D,S",     0x46200006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
 {"mov.s",   "D,S",     0x46000006, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
-{"mov.ps",  "D,S",     0x46c00006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5|I33  },
-{"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,          I4|I32  },
-{"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,             I4|I32  },
+{"mov.ps",  "D,S",     0x46c00006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5_33|IL2F      },
+{"mov.ps",  "D,S",     0x45600006, 0xffff003f, WR_D|RD_S|FP_D,         0,              IL2E    },
+{"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,          I4_32  },
+{"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,             I4_32   },
 {"movf.l",  "D,S,N",   0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
 {"movf.l",  "X,Y,N",   0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
-{"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,             I4|I32  },
-{"movf.ps", "D,S,N",   0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I5|I33  },
-{"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              I4|I32  },
+{"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,             I4_32   },
+{"movf.ps", "D,S,N",   0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I5_33   },
+{"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              I4_32|IL2E|IL2F },
+{"movnz",   "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              IL2E|IL2F       },
 {"ffc",     "d,v",     0x0000000b, 0xfc1f07ff, WR_d|RD_s,              0,              L1      },
-{"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             I4|I32  },
+{"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             I4_32   },
 {"movn.l",  "D,S,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             MX|SB1  },
 {"movn.l",  "X,Y,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             MX|SB1  },
-{"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,             I4|I32  },
-{"movn.ps", "D,S,t",    0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             I5|I33  },
-{"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,          I4|I32  },
-{"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,             I4|I32  },
+{"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,             I4_32   },
+{"movn.ps", "D,S,t",    0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             I5_33   },
+{"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,          I4_32   },
+{"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,             I4_32   },
 {"movt.l",  "D,S,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,             MX|SB1  },
 {"movt.l",  "X,Y,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,             MX|SB1  },
-{"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,             I4|I32  },
-{"movt.ps", "D,S,N",   0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I5|I33  },
-{"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              I4|I32  },
+{"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,             I4_32   },
+{"movt.ps", "D,S,N",   0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I5_33   },
+{"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              I4_32|IL2E|IL2F },
 {"ffs",     "d,v",     0x0000000a, 0xfc1f07ff, WR_d|RD_s,              0,              L1      },
-{"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             I4|I32  },
+{"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             I4_32   },
 {"movz.l",  "D,S,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             MX|SB1  },
 {"movz.l",  "X,Y,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             MX|SB1  },
-{"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,             I4|I32  },
-{"movz.ps", "D,S,t",    0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             I5|I33  },
+{"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,             I4_32   },
+{"movz.ps", "D,S,t",    0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             I5_33   },
 {"msac",    "d,s,t",   0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
 {"msacu",   "d,s,t",   0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
 {"msachi",  "d,s,t",   0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
 {"msachiu", "d,s,t",   0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
 /* move is at the top of the table.  */
 {"msgn.qh", "X,Y,Q",   0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
-{"msub.d",  "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
-{"msub.s",  "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
-{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5|I33  },
+{"msgsnd",  "t",       0,    (int) M_MSGSND,   INSN_MACRO,             0,             XLR      },
+{"msgld",   "",        0,    (int) M_MSGLD,    INSN_MACRO,             0,             XLR      },
+{"msgld",   "t",       0,    (int) M_MSGLD_T,  INSN_MACRO,             0,             XLR      },
+{"msgwait", "",        0,    (int) M_MSGWAIT,  INSN_MACRO,             0,             XLR      },
+{"msgwait", "t",       0,    (int) M_MSGWAIT_T,INSN_MACRO,             0,             XLR      },
+{"msub.d",  "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4_33   },
+{"msub.d",     "D,S,T",        0x46200019,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"msub.d",     "D,S,T",        0x72200019,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"msub.s",  "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4_33   },
+{"msub.s",     "D,S,T",        0x46000019,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2E    },
+{"msub.s",     "D,S,T",        0x72000019,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2F    },
+{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5_33   },
+{"msub.ps",    "D,S,T",        0x45600019,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"msub.ps",    "D,S,T",        0x71600019,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,     0,              L1      },
 {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,             I32|N55 },
 {"msub",    "7,s,t",   0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
@@ -867,9 +951,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"msubu",   "7,s,t",   0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
 {"mtpc",    "t,P",     0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0,         0,              M1|N5   },
 {"mtps",    "t,P",     0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0,         0,              M1|N5   },
-{"mtc0",    "t,G",     0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I1      },
-{"mtc0",    "t,+D",     0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I32     },
-{"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I32     },
+{"mtc0",    "t,G",     0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I1|IOCT },
+{"mtc0",    "t,+D",     0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I32|IOCT},
+{"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I32|IOCT},
 {"mtc1",    "t,S",     0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
 {"mtc1",    "t,G",     0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
 {"mthc1",   "t,S",     0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I33     },
@@ -883,6 +967,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtlo",    "s",       0x00000013, 0xfc1fffff, RD_s|WR_LO,             0,              I1      },
 {"mtlo",    "s,7",     0x00000013, 0xfc1fe7ff, RD_s|WR_LO,             0,              D32     },
 {"mtlhx",   "s",       0x00000053, 0xfc1fffff, RD_s|MOD_HILO,          0,              SMT     },
+{"mtcr",    "t,s",      0x70000019, 0xfc00ffff, RD_t,                  0,              XLR     },
+{"mtm0",    "s",       0x70000008, 0xfc1fffff, RD_s,                   0,              IOCT    },
+{"mtm1",    "s",       0x7000000c, 0xfc1fffff, RD_s,                   0,              IOCT    },
+{"mtm2",    "s",       0x7000000d, 0xfc1fffff, RD_s,                   0,              IOCT    },
+{"mtp0",    "s",       0x70000009, 0xfc1fffff, RD_s,                   0,              IOCT    },
+{"mtp1",    "s",       0x7000000a, 0xfc1fffff, RD_s,                   0,              IOCT    },
+{"mtp2",    "s",       0x7000000b, 0xfc1fffff, RD_s,                   0,              IOCT    },
 {"mttc0",   "t,G",     0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
 {"mttc0",   "t,+D",    0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
 {"mttc0",   "t,G,H",   0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
@@ -907,7 +998,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mul.ob",  "D,S,T",   0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"mul.ob",  "D,S,T[e]",        0x48000030, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"mul.ob",  "D,S,k",   0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
-{"mul.ps",  "D,V,T",   0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
+{"mul.ps",  "D,V,T",   0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5_33|IL2F      },
+{"mul.ps",  "D,V,T",   0x45600002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              IL2E    },
 {"mul.qh",  "X,Y,Q",   0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
 {"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,             I32|P3|N55},
 {"mul",     "d,s,t",   0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N54     },
@@ -956,16 +1048,31 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"negu",    "d,w",     0x00000023, 0xffe007ff, WR_d|RD_t,              0,              I1      }, /* subu 0 */
 {"neg.d",   "D,V",     0x46200007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
 {"neg.s",   "D,V",     0x46000007, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
-{"neg.ps",  "D,V",     0x46c00007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5|I33  },
-{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
-{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
-{"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5|I33  },
-{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
-{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
-{"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5|I33  },
+{"neg.ps",  "D,V",     0x46c00007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5_33|IL2F      },
+{"neg.ps",  "D,V",     0x45600007, 0xffff003f, WR_D|RD_S|FP_D,         0,              IL2E    },
+{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4_33   },
+{"nmadd.d",    "D,S,T",        0x4620001a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"nmadd.d",    "D,S,T",        0x7220001a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4_33   },
+{"nmadd.s",    "D,S,T",        0x4600001a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2E    },
+{"nmadd.s",    "D,S,T",        0x7200001a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2F    },
+{"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5_33   },
+{"nmadd.ps",   "D,S,T",        0x4560001a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"nmadd.ps",   "D,S,T",        0x7160001a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4_33   },
+{"nmsub.d",    "D,S,T",        0x4620001b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"nmsub.d",    "D,S,T",        0x7220001b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4_33   },
+{"nmsub.s",    "D,S,T",        0x4600001b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2E    },
+{"nmsub.s",    "D,S,T",        0x7200001b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2F    },
+{"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5_33   },
+{"nmsub.ps",   "D,S,T",        0x4560001b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"nmsub.ps",   "D,S,T",        0x7160001b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 /* nop is at the start of the table.  */
 {"nor",     "d,v,t",   0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"nor",     "t,r,I",   0,    (int) M_NOR_I,    INSN_MACRO,             0,              I1      },
+{"nor",        "D,S,T",        0x47a00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"nor",        "D,S,T",        0x4ba00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"nor.ob",  "X,Y,Q",   0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
 {"nor.ob",  "D,S,T",   0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"nor.ob",  "D,S,T[e]",        0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
@@ -974,6 +1081,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"not",     "d,v",     0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t,         0,              I1      },/*nor d,s,0*/
 {"or",      "d,v,t",   0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"or",      "t,r,I",   0,    (int) M_OR_I,     INSN_MACRO,             0,              I1      },
+{"or", "D,S,T",        0x45a00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"or", "D,S,T",        0x4b20000c,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"or.ob",   "X,Y,Q",   0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
 {"or.ob",   "D,S,T",   0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"or.ob",   "D,S,T[e]",        0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
@@ -993,11 +1102,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f,        WR_D|RD_S|RD_T,         0,              N54     },
 {"pickt.ob", "D,S,k",  0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"pickt.qh", "X,Y,Q",  0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
-{"pll.ps",  "D,V,T",   0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
-{"plu.ps",  "D,V,T",   0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
+{"pll.ps",  "D,V,T",   0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5_33   },
+{"plu.ps",  "D,V,T",   0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5_33   },
+{"pop",     "d,v",     0x7000002c, 0xfc1f07ff, WR_d|RD_s,              0,              IOCT    },
   /* pref and prefx are at the start of the table.  */
-{"pul.ps",  "D,V,T",   0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
-{"puu.ps",  "D,V,T",   0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
+{"pul.ps",  "D,V,T",   0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5_33   },
+{"puu.ps",  "D,V,T",   0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5_33   },
 {"pperm",   "s,t",     0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t,     0,              SMT     },
 {"rach.ob", "X",       0x7a00003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
 {"rach.ob", "D",       0x4a00003f, 0xfffff83f, WR_D,                   0,              N54     },
@@ -1008,9 +1118,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"racm.ob", "X",       0x7900003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
 {"racm.ob", "D",       0x4900003f, 0xfffff83f, WR_D,                   0,              N54     },
 {"racm.qh", "X",       0x7920003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
-{"recip.d", "D,S",     0x46200015, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4|I33  },
+{"recip.d", "D,S",     0x46200015, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4_33   },
 {"recip.ps","D,S",     0x46c00015, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
-{"recip.s", "D,S",     0x46000015, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4|I33  },
+{"recip.s", "D,S",     0x46000015, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4_33   },
 {"recip1.d",  "D,S",   0x4620001d, 0xffff003f, WR_D|RD_S|FP_D,         0,              M3D     },
 {"recip1.ps", "D,S",   0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
 {"recip1.s",  "D,S",   0x4600001d, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
@@ -1043,13 +1153,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"rotr",    "d,v,t",   0,    (int) M_ROR,      INSN_MACRO,             0,              I33|SMT },
 {"rotr",    "d,v,I",   0,    (int) M_ROR_I,    INSN_MACRO,             0,              I33|SMT },
 {"rotrv",   "d,t,s",   0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              I33|SMT },
-{"round.l.d", "D,S",   0x46200008, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
-{"round.l.s", "D,S",   0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
+{"round.l.d", "D,S",   0x46200008, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3_33   },
+{"round.l.s", "D,S",   0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3_33   },
 {"round.w.d", "D,S",   0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
 {"round.w.s", "D,S",   0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
-{"rsqrt.d", "D,S",     0x46200016, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4|I33  },
+{"rsqrt.d", "D,S",     0x46200016, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4_33   },
 {"rsqrt.ps","D,S",     0x46c00016, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
-{"rsqrt.s", "D,S",     0x46000016, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4|I33  },
+{"rsqrt.s", "D,S",     0x46000016, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4_33   },
 {"rsqrt1.d",  "D,S",   0x4620001e, 0xffff003f, WR_D|RD_S|FP_D,         0,              M3D     },
 {"rsqrt1.ps", "D,S",   0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
 {"rsqrt1.s",  "D,S",   0x4600001e, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
@@ -1076,26 +1186,30 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,                  0,              I32     },
 {"sdc1",    "T,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
 {"sdc1",    "E,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
-{"sdc1",    "T,A(b)",  0,    (int) M_SDC1_AB,  INSN_MACRO,             0,              I2      },
-{"sdc1",    "E,A(b)",  0,    (int) M_SDC1_AB,  INSN_MACRO,             0,              I2      },
+{"sdc1",    "T,A(b)",  0,    (int) M_SDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I2      },
+{"sdc1",    "E,A(b)",  0,    (int) M_SDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I2      },
 {"sdc2",    "E,o(b)",  0xf8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I2      },
 {"sdc2",    "E,A(b)",  0,    (int) M_SDC2_AB,  INSN_MACRO,             0,              I2      },
 {"sdc3",    "E,o(b)",  0xfc000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I2      },
 {"sdc3",    "E,A(b)",  0,    (int) M_SDC3_AB,  INSN_MACRO,             0,              I2      },
 {"s.d",     "T,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
-{"s.d",     "T,o(b)",  0,    (int) M_S_DOB,    INSN_MACRO,             0,              I1      },
-{"s.d",     "T,A(b)",  0,    (int) M_S_DAB,    INSN_MACRO,             0,              I1      },
+{"s.d",     "T,o(b)",  0,    (int) M_S_DOB,    INSN_MACRO,             INSN2_M_FP_D,   I1      },
+{"s.d",     "T,A(b)",  0,    (int) M_S_DAB,    INSN_MACRO,             INSN2_M_FP_D,   I1      },
 {"sdl",     "t,o(b)",  0xb0000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
 {"sdl",     "t,A(b)",  0,    (int) M_SDL_AB,   INSN_MACRO,             0,              I3      },
 {"sdr",     "t,o(b)",  0xb4000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
 {"sdr",     "t,A(b)",  0,    (int) M_SDR_AB,   INSN_MACRO,             0,              I3      },
-{"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D,        0,              I4|I33  },
+{"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D,        0,              I4_33   },
 {"seb",     "d,w",     0x7c000420, 0xffe007ff, WR_d|RD_t,              0,              I33     },
 {"seh",     "d,w",     0x7c000620, 0xffe007ff, WR_d|RD_t,              0,              I33     },
 {"selsl",   "d,v,t",   0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              L1      },
 {"selsr",   "d,v,t",   0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              L1      },
+{"seq",            "d,v,t",    0x7000002a, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              IOCT    },
 {"seq",     "d,v,t",   0,    (int) M_SEQ,      INSN_MACRO,             0,              I1      },
 {"seq",     "d,v,I",   0,    (int) M_SEQ_I,    INSN_MACRO,             0,              I1      },
+{"seq",        "S,T",          0x46a00032,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2E    },
+{"seq",        "S,T",          0x4ba0000c,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2F    },
+{"seqi",    "t,r,+Q",  0x7000002e, 0xfc00003f, WR_t|RD_s,              0,              IOCT    },
 {"sge",     "d,v,t",   0,    (int) M_SGE,      INSN_MACRO,             0,              I1      },
 {"sge",     "d,v,I",   0,    (int) M_SGE_I,    INSN_MACRO,             0,              I1      },
 {"sgeu",    "d,v,t",   0,    (int) M_SGEU,     INSN_MACRO,             0,              I1      },
@@ -1122,33 +1236,49 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              MX|SB1  },
 {"sle",     "d,v,t",   0,    (int) M_SLE,      INSN_MACRO,             0,              I1      },
 {"sle",     "d,v,I",   0,    (int) M_SLE_I,    INSN_MACRO,             0,              I1      },
+{"sle",        "S,T",          0x46a0003e,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2E    },
+{"sle",        "S,T",          0x4ba0000e,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2F    },
 {"sleu",    "d,v,t",   0,    (int) M_SLEU,     INSN_MACRO,             0,              I1      },
 {"sleu",    "d,v,I",   0,    (int) M_SLEU_I,   INSN_MACRO,             0,              I1      },
+{"sleu",       "S,T",          0x4680003e,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2E    },
+{"sleu",       "S,T",          0x4b80000e,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2F    },
 {"sllv",    "d,t,s",   0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
 {"sll",     "d,w,s",   0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* sllv */
 {"sll",     "d,w,<",   0x00000000, 0xffe0003f, WR_d|RD_t,              0,              I1      },
+{"sll",        "D,S,T",        0x45800002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"sll",        "D,S,T",        0x4b00000e,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"sll.ob",  "X,Y,Q",   0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
 {"sll.ob",  "D,S,T[e]",        0x48000010, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"sll.ob",  "D,S,k",   0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"sll.qh",  "X,Y,Q",   0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
 {"slt",     "d,v,t",   0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"slt",     "d,v,I",   0,    (int) M_SLT_I,    INSN_MACRO,             0,              I1      },
+{"slt",        "S,T",          0x46a0003c,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2E    },
+{"slt",        "S,T",          0x4ba0000d,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2F    },
 {"slti",    "t,r,j",   0x28000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
 {"sltiu",   "t,r,j",   0x2c000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
 {"sltu",    "d,v,t",   0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"sltu",    "d,v,I",   0,    (int) M_SLTU_I,   INSN_MACRO,             0,              I1      },
+{"sltu",       "S,T",          0x4680003c,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2E    },
+{"sltu",       "S,T",          0x4b80000d,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2F    },
+{"sne",            "d,v,t",    0x7000002b, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              IOCT    },
 {"sne",     "d,v,t",   0,    (int) M_SNE,      INSN_MACRO,             0,              I1      },
 {"sne",     "d,v,I",   0,    (int) M_SNE_I,    INSN_MACRO,             0,              I1      },
+{"snei",    "t,r,+Q",  0x7000002f, 0xfc00003f, WR_t|RD_s,              0,              IOCT    },
 {"sqrt.d",  "D,S",     0x46200004, 0xffff003f, WR_D|RD_S|FP_D,         0,              I2      },
 {"sqrt.s",  "D,S",     0x46000004, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
 {"sqrt.ps", "D,S",     0x46c00004, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
 {"srav",    "d,t,s",   0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
 {"sra",     "d,w,s",   0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* srav */
 {"sra",     "d,w,<",   0x00000003, 0xffe0003f, WR_d|RD_t,              0,              I1      },
+{"sra",        "D,S,T",        0x45c00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"sra",        "D,S,T",        0x4b40000f,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"sra.qh",  "X,Y,Q",   0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
 {"srlv",    "d,t,s",   0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
 {"srl",     "d,w,s",   0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* srlv */
 {"srl",     "d,w,<",   0x00000002, 0xffe0003f, WR_d|RD_t,              0,              I1      },
+{"srl",        "D,S,T",        0x45800003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"srl",        "D,S,T",        0x4b00000f,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"srl.ob",  "X,Y,Q",   0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
 {"srl.ob",  "D,S,T[e]",        0x48000012, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"srl.ob",  "D,S,k",   0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
@@ -1157,13 +1287,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"standby", "",         0x42000021, 0xffffffff,        0,                      0,              V1      },
 {"sub",     "d,v,t",   0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"sub",     "d,v,I",   0,    (int) M_SUB_I,    INSN_MACRO,             0,              I1      },
+{"sub",        "D,S,T",        0x45c00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2E    },
+{"sub",        "D,S,T",        0x4b40000d,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2F    },
 {"sub.d",   "D,V,T",   0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
 {"sub.s",   "D,V,T",   0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
 {"sub.ob",  "X,Y,Q",   0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
 {"sub.ob",  "D,S,T",   0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"sub.ob",  "D,S,T[e]",        0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"sub.ob",  "D,S,k",   0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
-{"sub.ps",  "D,V,T",   0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
+{"sub.ps",  "D,V,T",   0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5_33|IL2F      },
+{"sub.ps",  "D,V,T",   0x45600001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              IL2E    },
 {"sub.qh",  "X,Y,Q",   0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
 {"suba.ob", "Y,Q",     0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
 {"suba.qh", "Y,Q",     0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
@@ -1171,18 +1304,23 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"subl.qh", "Y,Q",     0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
 {"subu",    "d,v,t",   0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"subu",    "d,v,I",   0,    (int) M_SUBU_I,   INSN_MACRO,             0,              I1      },
+{"subu",       "D,S,T",        0x45800001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2E    },
+{"subu",       "D,S,T",        0x4b00000d,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2F    },
 {"suspend", "",         0x42000022, 0xffffffff,        0,                      0,              V1      },
-{"suxc1",   "S,t(b)",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b,     0,              I5|I33|N55},
+{"suxc1",   "S,t(b)",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D,        0,              I5_33|N55},
 {"sw",      "t,o(b)",  0xac000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
 {"sw",      "t,A(b)",  0,    (int) M_SW_AB,    INSN_MACRO,             0,              I1      },
+{"swapw",   "t,b",     0x70000014, 0xfc00ffff, SM|RD_t|WR_t|RD_b,      0,              XLR     },
+{"swapwu",  "t,b",     0x70000015, 0xfc00ffff, SM|RD_t|WR_t|RD_b,      0,              XLR     },
+{"swapd",   "t,b",     0x70000016, 0xfc00ffff, SM|RD_t|WR_t|RD_b,      0,              XLR     },
 {"swc0",    "E,o(b)",  0xe0000000, 0xfc000000, SM|RD_C0|RD_b,          0,              I1      },
 {"swc0",    "E,A(b)",  0,    (int) M_SWC0_AB,  INSN_MACRO,             0,              I1      },
 {"swc1",    "T,o(b)",  0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      },
 {"swc1",    "E,o(b)",  0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      },
-{"swc1",    "T,A(b)",  0,    (int) M_SWC1_AB,  INSN_MACRO,             0,              I1      },
-{"swc1",    "E,A(b)",  0,    (int) M_SWC1_AB,  INSN_MACRO,             0,              I1      },
+{"swc1",    "T,A(b)",  0,    (int) M_SWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1      },
+{"swc1",    "E,A(b)",  0,    (int) M_SWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1      },
 {"s.s",     "T,o(b)",  0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      }, /* swc1 */
-{"s.s",     "T,A(b)",  0,    (int) M_SWC1_AB,  INSN_MACRO,             0,              I1      },
+{"s.s",     "T,A(b)",  0,    (int) M_SWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1      },
 {"swc2",    "E,o(b)",  0xe8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I1      },
 {"swc2",    "E,A(b)",  0,    (int) M_SWC2_AB,  INSN_MACRO,             0,              I1      },
 {"swc3",    "E,o(b)",  0xec000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I1      },
@@ -1195,8 +1333,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"swr",     "t,A(b)",  0,    (int) M_SWR_AB,   INSN_MACRO,             0,              I1      },
 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000,        RD_t|RD_b,              0,              I2      }, /* same */
 {"invalidate", "t,A(b)",0,    (int) M_SWR_AB,  INSN_MACRO,             0,              I2      }, /* as swr */
-{"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S,        0,              I4|I33  },
+{"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S,        0,              I4_33   },
+{"synciobdma", "",     0x0000008f, 0xffffffff, INSN_SYNC,              0,              IOCT    },
+{"syncs",   "",                0x0000018f, 0xffffffff, INSN_SYNC,              0,              IOCT    },
+{"syncw",   "",                0x0000010f, 0xffffffff, INSN_SYNC,              0,              IOCT    },
+{"syncws",  "",                0x0000014f, 0xffffffff, INSN_SYNC,              0,              IOCT    },
 {"sync",    "",                0x0000000f, 0xffffffff, INSN_SYNC,              0,              I2|G1   },
+{"sync",    "1",       0x0000000f, 0xfffff83f, INSN_SYNC,              0,              I32     },
 {"sync.p",  "",                0x0000040f, 0xffffffff, INSN_SYNC,              0,              I2      },
 {"sync.l",  "",                0x0000000f, 0xffffffff, INSN_SYNC,              0,              I2      },
 {"synci",   "o(b)",    0x041f0000, 0xfc1f0000, SM|RD_b,                0,              I33     },
@@ -1236,14 +1379,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"tne",     "s,t,q",   0x00000036, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
 {"tne",     "s,j",     0x040e0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tnei */
 {"tne",     "s,I",     0,    (int) M_TNE_I,    INSN_MACRO,             0,              I2      },
-{"trunc.l.d", "D,S",   0x46200009, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
-{"trunc.l.s", "D,S",   0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
+{"trunc.l.d", "D,S",   0x46200009, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3_33   },
+{"trunc.l.s", "D,S",   0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3_33   },
 {"trunc.w.d", "D,S",   0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
 {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
-{"trunc.w.d", "D,S,t", 0,    (int) M_TRUNCWD,  INSN_MACRO,             0,              I1      },
+{"trunc.w.d", "D,S,t", 0,    (int) M_TRUNCWD,  INSN_MACRO,             INSN2_M_FP_S|INSN2_M_FP_D, I1 },
 {"trunc.w.s", "D,S",   0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
 {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
-{"trunc.w.s", "D,S,t", 0,    (int) M_TRUNCWS,  INSN_MACRO,             0,              I1      },
+{"trunc.w.s", "D,S,t", 0,    (int) M_TRUNCWS,  INSN_MACRO,             INSN2_M_FP_S,   I1      },
 {"uld",     "t,o(b)",  0,    (int) M_ULD,      INSN_MACRO,             0,              I3      },
 {"uld",     "t,A(b)",  0,    (int) M_ULD_A,    INSN_MACRO,             0,              I3      },
 {"ulh",     "t,o(b)",  0,    (int) M_ULH,      INSN_MACRO,             0,              I1      },
@@ -1258,19 +1401,24 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ush",     "t,A(b)",  0,    (int) M_USH_A,    INSN_MACRO,             0,              I1      },
 {"usw",     "t,o(b)",  0,    (int) M_USW,      INSN_MACRO,             0,              I1      },
 {"usw",     "t,A(b)",  0,    (int) M_USW_A,    INSN_MACRO,             0,              I1      },
+{"v3mulu",  "d,v,t",   0x70000011, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              IOCT    },
+{"vmm0",    "d,v,t",   0x70000010, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              IOCT    },
+{"vmulu",   "d,v,t",   0x7000000f, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              IOCT    },
 {"wach.ob", "Y",       0x7a00003e, 0xffff07ff, RD_S|FP_D,              WR_MACC,        MX|SB1  },
 {"wach.ob", "S",       0x4a00003e, 0xffff07ff, RD_S,                   0,              N54     },
 {"wach.qh", "Y",       0x7a20003e, 0xffff07ff, RD_S|FP_D,              WR_MACC,        MX      },
 {"wacl.ob", "Y,Z",     0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
 {"wacl.ob", "S,T",     0x4800003e, 0xffe007ff, RD_S|RD_T,              0,              N54     },
 {"wacl.qh", "Y,Z",     0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
-{"wait",    "",         0x42000020, 0xffffffff, TRAP,                  0,              I3|I32  },
+{"wait",    "",         0x42000020, 0xffffffff, TRAP,                  0,              I3_32   },
 {"wait",    "J",        0x42000020, 0xfe00003f, TRAP,                  0,              I32|N55 },
 {"waiti",   "",                0x42000020, 0xffffffff, TRAP,                   0,              L1      },
 {"wrpgpr",  "d,w",     0x41c00000, 0xffe007ff, RD_t,                   0,              I33     },
 {"wsbh",    "d,w",     0x7c0000a0, 0xffe007ff, WR_d|RD_t,              0,              I33     },
 {"xor",     "d,v,t",   0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"xor",     "t,r,I",   0,    (int) M_XOR_I,    INSN_MACRO,             0,              I1      },
+{"xor",        "D,S,T",        0x47800002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"xor",        "D,S,T",        0x4b800002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"xor.ob",  "X,Y,Q",   0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
 {"xor.ob",  "D,S,T",   0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"xor.ob",  "D,S,T[e]",        0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
@@ -1358,8 +1506,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"bc2tl",   "N,p",     0x49030000, 0xffe30000, CBL|RD_CC,              0,              I32     },
 {"cfc2",    "t,G",     0x48400000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1      },
 {"ctc2",    "t,G",     0x48c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
+{"dmfc2",   "t,i",     0x48200000, 0xffe00000, LCD|WR_t|RD_C2,         0,              IOCT    },
 {"dmfc2",   "t,G",     0x48200000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I3      },
 {"dmfc2",   "t,G,H",   0x48200000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I64     },
+{"dmtc2",   "t,i",     0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   0,              IOCT    },
 {"dmtc2",   "t,G",     0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I3      },
 {"dmtc2",   "t,G,H",   0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I64     },
 {"mfc2",    "t,G",     0x48000000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1      },
@@ -1388,18 +1538,6 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtc3",    "t,G",     0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I1      },
 {"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   0,             I32     },
 
-/* No hazard protection on coprocessor instructions--they shouldn't
-   change the state of the processor and if they do it's up to the
-   user to put in nops as necessary.  These are at the end so that the
-   disassembler recognizes more specific versions first.  */
-{"c0",      "C",       0x42000000, 0xfe000000, 0,                      0,              I1      },
-{"c1",      "C",       0x46000000, 0xfe000000, 0,                      0,              I1      },
-{"c2",      "C",       0x4a000000, 0xfe000000, 0,                      0,              I1      },
-{"c3",      "C",       0x4e000000, 0xfe000000, 0,                      0,              I1      },
-{"cop0",     "C",      0,    (int) M_COP0,     INSN_MACRO,             0,              I1      },
-{"cop1",     "C",      0,    (int) M_COP1,     INSN_MACRO,             0,              I1      },
-{"cop2",     "C",      0,    (int) M_COP2,     INSN_MACRO,             0,              I1      },
-{"cop3",     "C",      0,    (int) M_COP3,     INSN_MACRO,             0,              I1      },
   /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
      4010 any more, so move this insn out of the way.  If the object
      format gave us more info, we could do this right.  */
@@ -1692,6 +1830,161 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"bc0fl",   "p",       0x41020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
 {"bc0t",    "p",       0x41010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
 {"bc0tl",   "p",       0x41030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
+/* ST Microelectronics Loongson-2E and -2F.  */
+{"mult.g",     "d,s,t",        0x7c000018,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"mult.g",     "d,s,t",        0x70000010,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"multu.g",    "d,s,t",        0x7c000019,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"multu.g",    "d,s,t",        0x70000012,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"dmult.g",    "d,s,t",        0x7c00001c,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"dmult.g",    "d,s,t",        0x70000011,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"dmultu.g",   "d,s,t",        0x7c00001d,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"dmultu.g",   "d,s,t",        0x70000013,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"div.g",      "d,s,t",        0x7c00001a,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"div.g",      "d,s,t",        0x70000014,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"divu.g",     "d,s,t",        0x7c00001b,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"divu.g",     "d,s,t",        0x70000016,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"ddiv.g",     "d,s,t",        0x7c00001e,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"ddiv.g",     "d,s,t",        0x70000015,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"ddivu.g",    "d,s,t",        0x7c00001f,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"ddivu.g",    "d,s,t",        0x70000017,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"mod.g",      "d,s,t",        0x7c000022,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"mod.g",      "d,s,t",        0x7000001c,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"modu.g",     "d,s,t",        0x7c000023,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"modu.g",     "d,s,t",        0x7000001e,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"dmod.g",     "d,s,t",        0x7c000026,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"dmod.g",     "d,s,t",        0x7000001d,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"dmodu.g",    "d,s,t",        0x7c000027,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"dmodu.g",    "d,s,t",        0x7000001f,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"packsshb",   "D,S,T",        0x47400002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"packsshb",   "D,S,T",        0x4b400002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"packsswh",   "D,S,T",        0x47200002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"packsswh",   "D,S,T",        0x4b200002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"packushb",   "D,S,T",        0x47600002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"packushb",   "D,S,T",        0x4b600002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddb",      "D,S,T",        0x47c00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"paddb",      "D,S,T",        0x4bc00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddh",      "D,S,T",        0x47400000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"paddh",      "D,S,T",        0x4b400000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddw",      "D,S,T",        0x47600000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"paddw",      "D,S,T",        0x4b600000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddd",      "D,S,T",        0x47e00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"paddd",      "D,S,T",        0x4be00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddsb",     "D,S,T",        0x47800000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"paddsb",     "D,S,T",        0x4b800000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddsh",     "D,S,T",        0x47000000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"paddsh",     "D,S,T",        0x4b000000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddusb",    "D,S,T",        0x47a00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"paddusb",    "D,S,T",        0x4ba00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddush",    "D,S,T",        0x47200000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"paddush",    "D,S,T",        0x4b200000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pandn",      "D,S,T",        0x47e00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pandn",      "D,S,T",        0x4be00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pavgb",      "D,S,T",        0x46600000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pavgb",      "D,S,T",        0x4b200008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pavgh",      "D,S,T",        0x46400000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pavgh",      "D,S,T",        0x4b000008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pcmpeqb",    "D,S,T",        0x46c00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pcmpeqb",    "D,S,T",        0x4b800009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pcmpeqh",    "D,S,T",        0x46800001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pcmpeqh",    "D,S,T",        0x4b400009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pcmpeqw",    "D,S,T",        0x46400001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pcmpeqw",    "D,S,T",        0x4b000009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pcmpgtb",    "D,S,T",        0x46e00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pcmpgtb",    "D,S,T",        0x4ba00009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pcmpgth",    "D,S,T",        0x46a00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pcmpgth",    "D,S,T",        0x4b600009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pcmpgtw",    "D,S,T",        0x46600001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pcmpgtw",    "D,S,T",        0x4b200009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pextrh",     "D,S,T",        0x45c00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pextrh",     "D,S,T",        0x4b40000e,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pinsrh_0",   "D,S,T",        0x47800003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pinsrh_0",   "D,S,T",        0x4b800003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pinsrh_1",   "D,S,T",        0x47a00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pinsrh_1",   "D,S,T",        0x4ba00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pinsrh_2",   "D,S,T",        0x47c00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pinsrh_2",   "D,S,T",        0x4bc00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pinsrh_3",   "D,S,T",        0x47e00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pinsrh_3",   "D,S,T",        0x4be00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pmaddhw",    "D,S,T",        0x45e00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pmaddhw",    "D,S,T",        0x4b60000e,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pmaxsh",     "D,S,T",        0x46800000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pmaxsh",     "D,S,T",        0x4b400008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pmaxub",     "D,S,T",        0x46c00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pmaxub",     "D,S,T",        0x4b800008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pminsh",     "D,S,T",        0x46a00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pminsh",     "D,S,T",        0x4b600008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pminub",     "D,S,T",        0x46e00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pminub",     "D,S,T",        0x4ba00008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pmovmskb",   "D,S",          0x46a00005,     0xffff003f,     RD_S|WR_D|FP_D, 0,      IL2E    },
+{"pmovmskb",   "D,S",          0x4ba0000f,     0xffff003f,     RD_S|WR_D|FP_D, 0,      IL2F    },
+{"pmulhuh",    "D,S,T",        0x46e00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pmulhuh",    "D,S,T",        0x4ba0000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pmulhh",     "D,S,T",        0x46a00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pmulhh",     "D,S,T",        0x4b60000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pmullh",     "D,S,T",        0x46800002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pmullh",     "D,S,T",        0x4b40000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pmuluw",     "D,S,T",        0x46c00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pmuluw",     "D,S,T",        0x4b80000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pasubub",    "D,S,T",        0x45a00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pasubub",    "D,S,T",        0x4b20000d,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"biadd",      "D,S",          0x46800005,     0xffff003f,     RD_S|WR_D|FP_D, 0,      IL2E    },
+{"biadd",      "D,S",          0x4b80000f,     0xffff003f,     RD_S|WR_D|FP_D, 0,      IL2F    },
+{"pshufh",     "D,S,T",        0x47000002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pshufh",     "D,S,T",        0x4b000002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psllh",      "D,S,T",        0x46600002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psllh",      "D,S,T",        0x4b20000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psllw",      "D,S,T",        0x46400002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psllw",      "D,S,T",        0x4b00000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psrah",      "D,S,T",        0x46a00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psrah",      "D,S,T",        0x4b60000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psraw",      "D,S,T",        0x46800003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psraw",      "D,S,T",        0x4b40000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psrlh",      "D,S,T",        0x46600003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psrlh",      "D,S,T",        0x4b20000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psrlw",      "D,S,T",        0x46400003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psrlw",      "D,S,T",        0x4b00000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubb",      "D,S,T",        0x47c00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psubb",      "D,S,T",        0x4bc00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubh",      "D,S,T",        0x47400001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psubh",      "D,S,T",        0x4b400001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubw",      "D,S,T",        0x47600001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psubw",      "D,S,T",        0x4b600001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubd",      "D,S,T",        0x47e00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psubd",      "D,S,T",        0x4be00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubsb",     "D,S,T",        0x47800001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psubsb",     "D,S,T",        0x4b800001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubsh",     "D,S,T",        0x47000001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psubsh",     "D,S,T",        0x4b000001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubusb",    "D,S,T",        0x47a00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psubusb",    "D,S,T",        0x4ba00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubush",    "D,S,T",        0x47200001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psubush",    "D,S,T",        0x4b200001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"punpckhbh",  "D,S,T",        0x47600003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"punpckhbh",  "D,S,T",        0x4b600003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"punpckhhw",  "D,S,T",        0x47200003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"punpckhhw",  "D,S,T",        0x4b200003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"punpckhwd",  "D,S,T",        0x46e00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"punpckhwd",  "D,S,T",        0x4ba0000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"punpcklbh",  "D,S,T",        0x47400003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"punpcklbh",  "D,S,T",        0x4b400003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"punpcklhw",  "D,S,T",        0x47000003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"punpcklhw",  "D,S,T",        0x4b000003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"punpcklwd",  "D,S,T",        0x46c00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"punpcklwd",  "D,S,T",        0x4b80000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"sequ",       "S,T",          0x46800032,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2E    },
+{"sequ",       "S,T",          0x4b80000c,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2F    },
+/* No hazard protection on coprocessor instructions--they shouldn't
+   change the state of the processor and if they do it's up to the
+   user to put in nops as necessary.  These are at the end so that the
+   disassembler recognizes more specific versions first.  */
+{"c0",      "C",       0x42000000, 0xfe000000, CP,                     0,              I1      },
+{"c1",      "C",       0x46000000, 0xfe000000, FP_S,                   0,              I1      },
+{"c2",      "C",       0x4a000000, 0xfe000000, CP,                     0,              I1      },
+{"c3",      "C",       0x4e000000, 0xfe000000, CP,                     0,              I1      },
+{"cop0",     "C",      0,    (int) M_COP0,     INSN_MACRO,             0,              I1      },
+{"cop1",     "C",      0,    (int) M_COP1,     INSN_MACRO,             INSN2_M_FP_S,   I1      },
+{"cop2",     "C",      0,    (int) M_COP2,     INSN_MACRO,             0,              I1      },
+{"cop3",     "C",      0,    (int) M_COP3,     INSN_MACRO,             0,              I1      }
 };
 
 #define MIPS_NUM_OPCODES \