/* Subroutines used for code generation on the DEC Alpha.
- Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001 Free Software Foundation, Inc.
+ Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
+ 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
+ Free Software Foundation, Inc.
Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
-This file is part of GNU CC.
+This file is part of GCC.
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
+the Free Software Foundation; either version 3, or (at your option)
any later version.
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
#include "rtl.h"
#include "tree.h"
#include "regs.h"
#include "target.h"
#include "target-def.h"
#include "debug.h"
+#include "langhooks.h"
+#include <splay-tree.h>
+#include "cfglayout.h"
+#include "gimple.h"
+#include "tree-flow.h"
+#include "tree-stdarg.h"
+#include "tm-constrs.h"
+#include "df.h"
/* Specify which cpu to schedule for. */
+enum processor_type alpha_tune;
+/* Which cpu we're generating code for. */
enum processor_type alpha_cpu;
-static const char * const alpha_cpu_name[] =
+
+static const char * const alpha_cpu_name[] =
{
"ev4", "ev5", "ev6"
};
enum alpha_fp_trap_mode alpha_fptm;
-/* Strings decoded into the above options. */
-
-const char *alpha_cpu_string; /* -mcpu= */
-const char *alpha_tune_string; /* -mtune= */
-const char *alpha_tp_string; /* -mtrap-precision=[p|s|i] */
-const char *alpha_fprm_string; /* -mfp-rounding-mode=[n|m|c|d] */
-const char *alpha_fptm_string; /* -mfp-trap-mode=[n|u|su|sui] */
-const char *alpha_mlat_string; /* -mmemory-latency= */
-
/* Save information from a "cmpxx" operation until the branch or scc is
emitted. */
struct alpha_compare alpha_compare;
-/* Non-zero if inside of a function, because the Alpha asm can't
+/* Nonzero if inside of a function, because the Alpha asm can't
handle .files inside of functions. */
static int inside_function = FALSE;
/* The alias set for prologue/epilogue register save/restore. */
-static int alpha_sr_alias_set;
+static GTY(()) alias_set_type alpha_sr_alias_set;
/* The assembler name of the current function. */
static const char *alpha_fnname;
/* The next explicit relocation sequence number. */
+extern GTY(()) int alpha_next_sequence_number;
int alpha_next_sequence_number = 1;
/* The literal and gpdisp sequence numbers for this insn, as printed
by %# and %* respectively. */
+extern GTY(()) int alpha_this_literal_sequence_number;
+extern GTY(()) int alpha_this_gpdisp_sequence_number;
int alpha_this_literal_sequence_number;
int alpha_this_gpdisp_sequence_number;
-/* Declarations of static functions. */
-static bool decl_in_text_section
- PARAMS ((tree));
-static int some_small_symbolic_operand_1
- PARAMS ((rtx *, void *));
-static int split_small_symbolic_operand_1
- PARAMS ((rtx *, void *));
-static bool local_symbol_p
- PARAMS ((rtx));
-static void alpha_set_memflags_1
- PARAMS ((rtx, int, int, int));
-static rtx alpha_emit_set_const_1
- PARAMS ((rtx, enum machine_mode, HOST_WIDE_INT, int));
-static void alpha_expand_unaligned_load_words
- PARAMS ((rtx *out_regs, rtx smem, HOST_WIDE_INT words, HOST_WIDE_INT ofs));
-static void alpha_expand_unaligned_store_words
- PARAMS ((rtx *out_regs, rtx smem, HOST_WIDE_INT words, HOST_WIDE_INT ofs));
-static void alpha_sa_mask
- PARAMS ((unsigned long *imaskP, unsigned long *fmaskP));
-static int find_lo_sum
- PARAMS ((rtx *, void *));
-static int alpha_does_function_need_gp
- PARAMS ((void));
-static int alpha_ra_ever_killed
- PARAMS ((void));
-static const char *get_trap_mode_suffix
- PARAMS ((void));
-static const char *get_round_mode_suffix
- PARAMS ((void));
-static rtx set_frame_related_p
- PARAMS ((void));
-static const char *alpha_lookup_xfloating_lib_func
- PARAMS ((enum rtx_code));
-static int alpha_compute_xfloating_mode_arg
- PARAMS ((enum rtx_code, enum alpha_fp_rounding_mode));
-static void alpha_emit_xfloating_libcall
- PARAMS ((const char *, rtx, rtx[], int, rtx));
-static rtx alpha_emit_xfloating_compare
- PARAMS ((enum rtx_code, rtx, rtx));
-static void alpha_output_function_end_prologue
- PARAMS ((FILE *));
-static int alpha_adjust_cost
- PARAMS ((rtx, rtx, rtx, int));
-static int alpha_issue_rate
- PARAMS ((void));
-static int alpha_variable_issue
- PARAMS ((FILE *, int, rtx, int));
+/* Costs of various operations on the different architectures. */
-#if TARGET_ABI_UNICOSMK
-static void alpha_init_machine_status
- PARAMS ((struct function *p));
-static void alpha_mark_machine_status
- PARAMS ((struct function *p));
-static void alpha_free_machine_status
- PARAMS ((struct function *p));
-#endif
+struct alpha_rtx_cost_data
+{
+ unsigned char fp_add;
+ unsigned char fp_mult;
+ unsigned char fp_div_sf;
+ unsigned char fp_div_df;
+ unsigned char int_mult_si;
+ unsigned char int_mult_di;
+ unsigned char int_shift;
+ unsigned char int_cmov;
+ unsigned short int_div;
+};
+
+static struct alpha_rtx_cost_data const alpha_rtx_cost_data[PROCESSOR_MAX] =
+{
+ { /* EV4 */
+ COSTS_N_INSNS (6), /* fp_add */
+ COSTS_N_INSNS (6), /* fp_mult */
+ COSTS_N_INSNS (34), /* fp_div_sf */
+ COSTS_N_INSNS (63), /* fp_div_df */
+ COSTS_N_INSNS (23), /* int_mult_si */
+ COSTS_N_INSNS (23), /* int_mult_di */
+ COSTS_N_INSNS (2), /* int_shift */
+ COSTS_N_INSNS (2), /* int_cmov */
+ COSTS_N_INSNS (97), /* int_div */
+ },
+ { /* EV5 */
+ COSTS_N_INSNS (4), /* fp_add */
+ COSTS_N_INSNS (4), /* fp_mult */
+ COSTS_N_INSNS (15), /* fp_div_sf */
+ COSTS_N_INSNS (22), /* fp_div_df */
+ COSTS_N_INSNS (8), /* int_mult_si */
+ COSTS_N_INSNS (12), /* int_mult_di */
+ COSTS_N_INSNS (1) + 1, /* int_shift */
+ COSTS_N_INSNS (1), /* int_cmov */
+ COSTS_N_INSNS (83), /* int_div */
+ },
+ { /* EV6 */
+ COSTS_N_INSNS (4), /* fp_add */
+ COSTS_N_INSNS (4), /* fp_mult */
+ COSTS_N_INSNS (12), /* fp_div_sf */
+ COSTS_N_INSNS (15), /* fp_div_df */
+ COSTS_N_INSNS (7), /* int_mult_si */
+ COSTS_N_INSNS (7), /* int_mult_di */
+ COSTS_N_INSNS (1), /* int_shift */
+ COSTS_N_INSNS (2), /* int_cmov */
+ COSTS_N_INSNS (86), /* int_div */
+ },
+};
-static void unicosmk_output_deferred_case_vectors PARAMS ((FILE *));
-static void unicosmk_gen_dsib PARAMS ((unsigned long *imaskP));
-static void unicosmk_output_ssib PARAMS ((FILE *, const char *));
-static int unicosmk_need_dex PARAMS ((rtx));
+/* Similar but tuned for code size instead of execution latency. The
+ extra +N is fractional cost tuning based on latency. It's used to
+ encourage use of cheaper insns like shift, but only if there's just
+ one of them. */
+
+static struct alpha_rtx_cost_data const alpha_rtx_cost_size =
+{
+ COSTS_N_INSNS (1), /* fp_add */
+ COSTS_N_INSNS (1), /* fp_mult */
+ COSTS_N_INSNS (1), /* fp_div_sf */
+ COSTS_N_INSNS (1) + 1, /* fp_div_df */
+ COSTS_N_INSNS (1) + 1, /* int_mult_si */
+ COSTS_N_INSNS (1) + 2, /* int_mult_di */
+ COSTS_N_INSNS (1), /* int_shift */
+ COSTS_N_INSNS (1), /* int_cmov */
+ COSTS_N_INSNS (6), /* int_div */
+};
/* Get the number of args of a function in one of two ways. */
#if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
-#define NUM_ARGS current_function_args_info.num_args
+#define NUM_ARGS crtl->args.info.num_args
#else
-#define NUM_ARGS current_function_args_info
+#define NUM_ARGS crtl->args.info
#endif
#define REG_PV 27
#define REG_RA 26
-\f
-/* Initialize the GCC target structure. */
+
+/* Declarations of static functions. */
+static struct machine_function *alpha_init_machine_status (void);
+static rtx alpha_emit_xfloating_compare (enum rtx_code *, rtx, rtx);
+
#if TARGET_ABI_OPEN_VMS
-const struct attribute_spec vms_attribute_table[];
-static unsigned int vms_section_type_flags PARAMS ((tree, const char *, int));
-static void vms_asm_named_section PARAMS ((const char *, unsigned int));
-static void vms_asm_out_constructor PARAMS ((rtx, int));
-static void vms_asm_out_destructor PARAMS ((rtx, int));
-# undef TARGET_ATTRIBUTE_TABLE
-# define TARGET_ATTRIBUTE_TABLE vms_attribute_table
-# undef TARGET_SECTION_TYPE_FLAGS
-# define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
+static void alpha_write_linkage (FILE *, const char *, tree);
#endif
-#if TARGET_ABI_UNICOSMK
-static void unicosmk_asm_named_section PARAMS ((const char *, unsigned int));
-static void unicosmk_insert_attributes PARAMS ((tree, tree *));
-static unsigned int unicosmk_section_type_flags PARAMS ((tree, const char *,
- int));
-# undef TARGET_INSERT_ATTRIBUTES
-# define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
-# undef TARGET_SECTION_TYPE_FLAGS
-# define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
-#endif
+static void unicosmk_output_deferred_case_vectors (FILE *);
+static void unicosmk_gen_dsib (unsigned long *);
+static void unicosmk_output_ssib (FILE *, const char *);
+static int unicosmk_need_dex (rtx);
+\f
+/* Implement TARGET_HANDLE_OPTION. */
-#undef TARGET_ASM_ALIGNED_HI_OP
-#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
-#undef TARGET_ASM_ALIGNED_DI_OP
-#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
+static bool
+alpha_handle_option (size_t code, const char *arg, int value)
+{
+ switch (code)
+ {
+ case OPT_mfp_regs:
+ if (value == 0)
+ target_flags |= MASK_SOFT_FP;
+ break;
-/* Default unaligned ops are provided for ELF systems. To get unaligned
- data for non-ELF systems, we have to turn off auto alignment. */
-#ifndef OBJECT_FORMAT_ELF
-#undef TARGET_ASM_UNALIGNED_HI_OP
-#define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
-#undef TARGET_ASM_UNALIGNED_SI_OP
-#define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
-#undef TARGET_ASM_UNALIGNED_DI_OP
-#define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
-#endif
+ case OPT_mieee:
+ case OPT_mieee_with_inexact:
+ target_flags |= MASK_IEEE_CONFORMANT;
+ break;
-#undef TARGET_ASM_FUNCTION_END_PROLOGUE
-#define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
+ case OPT_mtls_size_:
+ if (value != 16 && value != 32 && value != 64)
+ error ("bad value %qs for -mtls-size switch", arg);
+ break;
+ }
-#undef TARGET_SCHED_ADJUST_COST
-#define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
-#undef TARGET_SCHED_ISSUE_RATE
-#define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
-#undef TARGET_SCHED_VARIABLE_ISSUE
-#define TARGET_SCHED_VARIABLE_ISSUE alpha_variable_issue
+ return true;
+}
+
+#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
+/* Implement TARGET_MANGLE_TYPE. */
+
+static const char *
+alpha_mangle_type (const_tree type)
+{
+ if (TYPE_MAIN_VARIANT (type) == long_double_type_node
+ && TARGET_LONG_DOUBLE_128)
+ return "g";
+
+ /* For all other types, use normal C++ mangling. */
+ return NULL;
+}
+#endif
-struct gcc_target targetm = TARGET_INITIALIZER;
-\f
/* Parse target option strings. */
void
-override_options ()
+override_options (void)
{
- int i;
static const struct cpu_table {
const char *const name;
const enum processor_type processor;
const int flags;
} cpu_table[] = {
-#define EV5_MASK (MASK_CPU_EV5)
-#define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
{ "ev4", PROCESSOR_EV4, 0 },
{ "ev45", PROCESSOR_EV4, 0 },
{ "21064", PROCESSOR_EV4, 0 },
- { "ev5", PROCESSOR_EV5, EV5_MASK },
- { "21164", PROCESSOR_EV5, EV5_MASK },
- { "ev56", PROCESSOR_EV5, EV5_MASK|MASK_BWX },
- { "21164a", PROCESSOR_EV5, EV5_MASK|MASK_BWX },
- { "pca56", PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
- { "21164PC",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
- { "21164pc",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
- { "ev6", PROCESSOR_EV6, EV6_MASK },
- { "21264", PROCESSOR_EV6, EV6_MASK },
- { "ev67", PROCESSOR_EV6, EV6_MASK|MASK_CIX },
- { "21264a", PROCESSOR_EV6, EV6_MASK|MASK_CIX },
+ { "ev5", PROCESSOR_EV5, 0 },
+ { "21164", PROCESSOR_EV5, 0 },
+ { "ev56", PROCESSOR_EV5, MASK_BWX },
+ { "21164a", PROCESSOR_EV5, MASK_BWX },
+ { "pca56", PROCESSOR_EV5, MASK_BWX|MASK_MAX },
+ { "21164PC",PROCESSOR_EV5, MASK_BWX|MASK_MAX },
+ { "21164pc",PROCESSOR_EV5, MASK_BWX|MASK_MAX },
+ { "ev6", PROCESSOR_EV6, MASK_BWX|MASK_MAX|MASK_FIX },
+ { "21264", PROCESSOR_EV6, MASK_BWX|MASK_MAX|MASK_FIX },
+ { "ev67", PROCESSOR_EV6, MASK_BWX|MASK_MAX|MASK_FIX|MASK_CIX },
+ { "21264a", PROCESSOR_EV6, MASK_BWX|MASK_MAX|MASK_FIX|MASK_CIX },
{ 0, 0, 0 }
};
-
+
+ int i;
+
/* Unicos/Mk doesn't have shared libraries. */
if (TARGET_ABI_UNICOSMK && flag_pic)
{
- warning ("-f%s ignored for Unicos/Mk (not supported)",
+ warning (0, "-f%s ignored for Unicos/Mk (not supported)",
(flag_pic > 1) ? "PIC" : "pic");
flag_pic = 0;
}
- /* On Unicos/Mk, the native compiler consistenly generates /d suffices for
+ /* On Unicos/Mk, the native compiler consistently generates /d suffices for
floating-point instructions. Make that the default for this target. */
if (TARGET_ABI_UNICOSMK)
alpha_fprm = ALPHA_FPRM_DYN;
alpha_tp = ALPHA_TP_PROG;
alpha_fptm = ALPHA_FPTM_N;
- /* We cannot use su and sui qualifiers for conversion instructions on
+ /* We cannot use su and sui qualifiers for conversion instructions on
Unicos/Mk. I'm not sure if this is due to assembler or hardware
limitations. Right now, we issue a warning if -mieee is specified
and then ignore it; eventually, we should either get it right or
if (TARGET_IEEE)
{
if (TARGET_ABI_UNICOSMK)
- warning ("-mieee not supported on Unicos/Mk");
+ warning (0, "-mieee not supported on Unicos/Mk");
else
{
alpha_tp = ALPHA_TP_INSN;
if (TARGET_IEEE_WITH_INEXACT)
{
if (TARGET_ABI_UNICOSMK)
- warning ("-mieee-with-inexact not supported on Unicos/Mk");
+ warning (0, "-mieee-with-inexact not supported on Unicos/Mk");
else
{
alpha_tp = ALPHA_TP_INSN;
else if (! strcmp (alpha_tp_string, "i"))
alpha_tp = ALPHA_TP_INSN;
else
- error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string);
+ error ("bad value %qs for -mtrap-precision switch", alpha_tp_string);
}
if (alpha_fprm_string)
else if (! strcmp (alpha_fprm_string,"d"))
alpha_fprm = ALPHA_FPRM_DYN;
else
- error ("bad value `%s' for -mfp-rounding-mode switch",
+ error ("bad value %qs for -mfp-rounding-mode switch",
alpha_fprm_string);
}
else if (strcmp (alpha_fptm_string, "sui") == 0)
alpha_fptm = ALPHA_FPTM_SUI;
else
- error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string);
+ error ("bad value %qs for -mfp-trap-mode switch", alpha_fptm_string);
}
- alpha_cpu
- = TARGET_CPU_DEFAULT & MASK_CPU_EV6 ? PROCESSOR_EV6
- : (TARGET_CPU_DEFAULT & MASK_CPU_EV5 ? PROCESSOR_EV5 : PROCESSOR_EV4);
-
if (alpha_cpu_string)
{
for (i = 0; cpu_table [i].name; i++)
if (! strcmp (alpha_cpu_string, cpu_table [i].name))
{
- alpha_cpu = cpu_table [i].processor;
- target_flags &= ~ (MASK_BWX | MASK_MAX | MASK_FIX | MASK_CIX
- | MASK_CPU_EV5 | MASK_CPU_EV6);
+ alpha_tune = alpha_cpu = cpu_table [i].processor;
+ target_flags &= ~ (MASK_BWX | MASK_MAX | MASK_FIX | MASK_CIX);
target_flags |= cpu_table [i].flags;
break;
}
if (! cpu_table [i].name)
- error ("bad value `%s' for -mcpu switch", alpha_cpu_string);
+ error ("bad value %qs for -mcpu switch", alpha_cpu_string);
}
if (alpha_tune_string)
for (i = 0; cpu_table [i].name; i++)
if (! strcmp (alpha_tune_string, cpu_table [i].name))
{
- alpha_cpu = cpu_table [i].processor;
+ alpha_tune = cpu_table [i].processor;
break;
}
if (! cpu_table [i].name)
- error ("bad value `%s' for -mcpu switch", alpha_tune_string);
+ error ("bad value %qs for -mcpu switch", alpha_tune_string);
}
/* Do some sanity checks on the above options. */
if (TARGET_ABI_UNICOSMK && alpha_fptm != ALPHA_FPTM_N)
{
- warning ("trap mode not supported on Unicos/Mk");
+ warning (0, "trap mode not supported on Unicos/Mk");
alpha_fptm = ALPHA_FPTM_N;
}
if ((alpha_fptm == ALPHA_FPTM_SU || alpha_fptm == ALPHA_FPTM_SUI)
- && alpha_tp != ALPHA_TP_INSN && ! TARGET_CPU_EV6)
+ && alpha_tp != ALPHA_TP_INSN && alpha_cpu != PROCESSOR_EV6)
{
- warning ("fp software completion requires -mtrap-precision=i");
+ warning (0, "fp software completion requires -mtrap-precision=i");
alpha_tp = ALPHA_TP_INSN;
}
- if (TARGET_CPU_EV6)
+ if (alpha_cpu == PROCESSOR_EV6)
{
/* Except for EV6 pass 1 (not released), we always have precise
arithmetic traps. Which means we can do software completion
{
if (alpha_fprm == ALPHA_FPRM_MINF || alpha_fprm == ALPHA_FPRM_DYN)
{
- warning ("rounding mode not supported for VAX floats");
+ warning (0, "rounding mode not supported for VAX floats");
alpha_fprm = ALPHA_FPRM_NORM;
}
if (alpha_fptm == ALPHA_FPTM_SUI)
{
- warning ("trap mode not supported for VAX floats");
+ warning (0, "trap mode not supported for VAX floats");
alpha_fptm = ALPHA_FPTM_SU;
}
+ if (target_flags_explicit & MASK_LONG_DOUBLE_128)
+ warning (0, "128-bit long double not supported for VAX floats");
+ target_flags &= ~MASK_LONG_DOUBLE_128;
}
{
&& ISDIGIT ((unsigned char)alpha_mlat_string[1])
&& alpha_mlat_string[2] == '\0')
{
- static int const cache_latency[][4] =
+ static int const cache_latency[][4] =
{
{ 3, 30, -1 }, /* ev4 -- Bcache is a guess */
{ 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
};
lat = alpha_mlat_string[1] - '0';
- if (lat <= 0 || lat > 3 || cache_latency[alpha_cpu][lat-1] == -1)
+ if (lat <= 0 || lat > 3 || cache_latency[alpha_tune][lat-1] == -1)
{
- warning ("L%d cache latency unknown for %s",
- lat, alpha_cpu_name[alpha_cpu]);
+ warning (0, "L%d cache latency unknown for %s",
+ lat, alpha_cpu_name[alpha_tune]);
lat = 3;
}
else
- lat = cache_latency[alpha_cpu][lat-1];
+ lat = cache_latency[alpha_tune][lat-1];
}
else if (! strcmp (alpha_mlat_string, "main"))
{
}
else
{
- warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string);
+ warning (0, "bad value %qs for -mmemory-latency", alpha_mlat_string);
lat = 3;
}
/* Register variables and functions with the garbage collector. */
-#if TARGET_ABI_UNICOSMK
/* Set up function hooks. */
init_machine_status = alpha_init_machine_status;
- mark_machine_status = alpha_mark_machine_status;
- free_machine_status = alpha_free_machine_status;
+
+ /* Tell the compiler when we're using VAX floating point. */
+ if (TARGET_FLOAT_VAX)
+ {
+ REAL_MODE_FORMAT (SFmode) = &vax_f_format;
+ REAL_MODE_FORMAT (DFmode) = &vax_g_format;
+ REAL_MODE_FORMAT (TFmode) = NULL;
+ }
+
+#ifdef TARGET_DEFAULT_LONG_DOUBLE_128
+ if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
+ target_flags |= MASK_LONG_DOUBLE_128;
#endif
+
+ /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
+ can be optimized to ap = __builtin_next_arg (0). */
+ if (TARGET_ABI_UNICOSMK)
+ targetm.expand_builtin_va_start = NULL;
}
\f
/* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
int
-zap_mask (value)
- HOST_WIDE_INT value;
+zap_mask (HOST_WIDE_INT value)
{
int i;
return 1;
}
-/* Returns 1 if OP is either the constant zero or a register. If a
- register, it must be in the proper mode unless MODE is VOIDmode. */
+/* Return true if OP is valid for a particular TLS relocation.
+ We are already guaranteed that OP is a CONST. */
int
-reg_or_0_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
+tls_symbolic_operand_1 (rtx op, int size, int unspec)
{
- return op == const0_rtx || register_operand (op, mode);
-}
-
-/* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
- any register. */
-
-int
-reg_or_6bit_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
-{
- return ((GET_CODE (op) == CONST_INT
- && (unsigned HOST_WIDE_INT) INTVAL (op) < 64)
- || register_operand (op, mode));
-}
+ op = XEXP (op, 0);
+ if (GET_CODE (op) != UNSPEC || XINT (op, 1) != unspec)
+ return 0;
+ op = XVECEXP (op, 0, 0);
-/* Return 1 if OP is an 8-bit constant or any register. */
+ if (GET_CODE (op) != SYMBOL_REF)
+ return 0;
-int
-reg_or_8bit_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
-{
- return ((GET_CODE (op) == CONST_INT
- && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100)
- || register_operand (op, mode));
+ switch (SYMBOL_REF_TLS_MODEL (op))
+ {
+ case TLS_MODEL_LOCAL_DYNAMIC:
+ return unspec == UNSPEC_DTPREL && size == alpha_tls_size;
+ case TLS_MODEL_INITIAL_EXEC:
+ return unspec == UNSPEC_TPREL && size == 64;
+ case TLS_MODEL_LOCAL_EXEC:
+ return unspec == UNSPEC_TPREL && size == alpha_tls_size;
+ default:
+ gcc_unreachable ();
+ }
}
-/* Return 1 if OP is an 8-bit constant. */
+/* Used by aligned_memory_operand and unaligned_memory_operand to
+ resolve what reload is going to do with OP if it's a register. */
-int
-cint8_operand (op, mode)
- register rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
+rtx
+resolve_reload_operand (rtx op)
{
- return ((GET_CODE (op) == CONST_INT
- && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100));
+ if (reload_in_progress)
+ {
+ rtx tmp = op;
+ if (GET_CODE (tmp) == SUBREG)
+ tmp = SUBREG_REG (tmp);
+ if (GET_CODE (tmp) == REG
+ && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
+ {
+ op = reg_equiv_memory_loc[REGNO (tmp)];
+ if (op == 0)
+ return 0;
+ }
+ }
+ return op;
}
-/* Return 1 if the operand is a valid second operand to an add insn. */
+/* The scalar modes supported differs from the default check-what-c-supports
+ version in that sometimes TFmode is available even when long double
+ indicates only DFmode. On unicosmk, we have the situation that HImode
+ doesn't map to any C type, but of course we still support that. */
-int
-add_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
+static bool
+alpha_scalar_mode_supported_p (enum machine_mode mode)
{
- if (GET_CODE (op) == CONST_INT)
- /* Constraints I, J, O and P are covered by K. */
- return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')
- || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
-
- return register_operand (op, mode);
-}
+ switch (mode)
+ {
+ case QImode:
+ case HImode:
+ case SImode:
+ case DImode:
+ case TImode: /* via optabs.c */
+ return true;
-/* Return 1 if the operand is a valid second operand to a sign-extending
- add insn. */
+ case SFmode:
+ case DFmode:
+ return true;
-int
-sext_add_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
-{
- if (GET_CODE (op) == CONST_INT)
- return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
- || CONST_OK_FOR_LETTER_P (INTVAL (op), 'O'));
+ case TFmode:
+ return TARGET_HAS_XFLOATING_LIBS;
- return reg_not_elim_operand (op, mode);
+ default:
+ return false;
+ }
}
-/* Return 1 if OP is the constant 4 or 8. */
+/* Alpha implements a couple of integer vector mode operations when
+ TARGET_MAX is enabled. We do not check TARGET_MAX here, however,
+ which allows the vectorizer to operate on e.g. move instructions,
+ or when expand_vector_operations can do something useful. */
-int
-const48_operand (op, mode)
- register rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
+static bool
+alpha_vector_mode_supported_p (enum machine_mode mode)
{
- return (GET_CODE (op) == CONST_INT
- && (INTVAL (op) == 4 || INTVAL (op) == 8));
+ return mode == V8QImode || mode == V4HImode || mode == V2SImode;
}
-/* Return 1 if OP is a valid first operand to an AND insn. */
+/* Return 1 if this function can directly return via $26. */
int
-and_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
+direct_return (void)
{
- if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == VOIDmode)
- return (zap_mask (CONST_DOUBLE_LOW (op))
- && zap_mask (CONST_DOUBLE_HIGH (op)));
-
- if (GET_CODE (op) == CONST_INT)
- return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
- || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100
- || zap_mask (INTVAL (op)));
-
- return register_operand (op, mode);
+ return (! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK
+ && reload_completed
+ && alpha_sa_size () == 0
+ && get_frame_size () == 0
+ && crtl->outgoing_args_size == 0
+ && crtl->args.pretend_args_size == 0);
}
-/* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
+/* Return the ADDR_VEC associated with a tablejump insn. */
-int
-or_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
+rtx
+alpha_tablejump_addr_vec (rtx insn)
{
- if (GET_CODE (op) == CONST_INT)
- return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
- || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100);
+ rtx tmp;
- return register_operand (op, mode);
+ tmp = JUMP_LABEL (insn);
+ if (!tmp)
+ return NULL_RTX;
+ tmp = NEXT_INSN (tmp);
+ if (!tmp)
+ return NULL_RTX;
+ if (GET_CODE (tmp) == JUMP_INSN
+ && GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC)
+ return PATTERN (tmp);
+ return NULL_RTX;
}
-/* Return 1 if OP is a constant that is the width, in bits, of an integral
- mode smaller than DImode. */
+/* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
-int
-mode_width_operand (op, mode)
- register rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
+rtx
+alpha_tablejump_best_label (rtx insn)
{
- return (GET_CODE (op) == CONST_INT
- && (INTVAL (op) == 8 || INTVAL (op) == 16
- || INTVAL (op) == 32 || INTVAL (op) == 64));
-}
-
-/* Return 1 if OP is a constant that is the width of an integral machine mode
- smaller than an integer. */
+ rtx jump_table = alpha_tablejump_addr_vec (insn);
+ rtx best_label = NULL_RTX;
-int
-mode_mask_operand (op, mode)
- register rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-#if HOST_BITS_PER_WIDE_INT == 32
- if (GET_CODE (op) == CONST_DOUBLE)
- return (CONST_DOUBLE_LOW (op) == -1
- && (CONST_DOUBLE_HIGH (op) == -1
- || CONST_DOUBLE_HIGH (op) == 0));
-#else
- if (GET_CODE (op) == CONST_DOUBLE)
- return (CONST_DOUBLE_LOW (op) == -1 && CONST_DOUBLE_HIGH (op) == 0);
-#endif
+ /* ??? Once the CFG doesn't keep getting completely rebuilt, look
+ there for edge frequency counts from profile data. */
- return (GET_CODE (op) == CONST_INT
- && (INTVAL (op) == 0xff
- || INTVAL (op) == 0xffff
- || INTVAL (op) == (HOST_WIDE_INT)0xffffffff
-#if HOST_BITS_PER_WIDE_INT == 64
- || INTVAL (op) == -1
-#endif
- ));
-}
+ if (jump_table)
+ {
+ int n_labels = XVECLEN (jump_table, 1);
+ int best_count = -1;
+ int i, j;
-/* Return 1 if OP is a multiple of 8 less than 64. */
+ for (i = 0; i < n_labels; i++)
+ {
+ int count = 1;
-int
-mul8_operand (op, mode)
- register rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- return (GET_CODE (op) == CONST_INT
- && (unsigned HOST_WIDE_INT) INTVAL (op) < 64
- && (INTVAL (op) & 7) == 0);
-}
+ for (j = i + 1; j < n_labels; j++)
+ if (XEXP (XVECEXP (jump_table, 1, i), 0)
+ == XEXP (XVECEXP (jump_table, 1, j), 0))
+ count++;
-/* Return 1 if OP is the constant zero in floating-point. */
+ if (count > best_count)
+ best_count = count, best_label = XVECEXP (jump_table, 1, i);
+ }
+ }
-int
-fp0_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
-{
- return (GET_MODE (op) == mode
- && GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode));
+ return best_label ? best_label : const0_rtx;
}
-/* Return 1 if OP is the floating-point constant zero or a register. */
+/* Return the TLS model to use for SYMBOL. */
-int
-reg_or_fp0_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
+static enum tls_model
+tls_symbolic_operand_type (rtx symbol)
{
- return fp0_operand (op, mode) || register_operand (op, mode);
-}
-
-/* Return 1 if OP is a hard floating-point register. */
+ enum tls_model model;
-int
-hard_fp_register_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
-{
- if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
+ if (GET_CODE (symbol) != SYMBOL_REF)
return 0;
+ model = SYMBOL_REF_TLS_MODEL (symbol);
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
- return GET_CODE (op) == REG && REGNO_REG_CLASS (REGNO (op)) == FLOAT_REGS;
-}
-
-/* Return 1 if OP is a hard general register. */
-
-int
-hard_int_register_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
-{
- if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
- return 0;
+ /* Local-exec with a 64-bit size is the same code as initial-exec. */
+ if (model == TLS_MODEL_LOCAL_EXEC && alpha_tls_size == 64)
+ model = TLS_MODEL_INITIAL_EXEC;
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
- return GET_CODE (op) == REG && REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS;
+ return model;
}
+\f
+/* Return true if the function DECL will share the same GP as any
+ function in the current unit of translation. */
-/* Return 1 if OP is a register or a constant integer. */
+static bool
+decl_has_samegp (const_tree decl)
+{
+ /* Functions that are not local can be overridden, and thus may
+ not share the same gp. */
+ if (!(*targetm.binds_local_p) (decl))
+ return false;
+ /* If -msmall-data is in effect, assume that there is only one GP
+ for the module, and so any local symbol has this property. We
+ need explicit relocations to be able to enforce this for symbols
+ not defined in this unit of translation, however. */
+ if (TARGET_EXPLICIT_RELOCS && TARGET_SMALL_DATA)
+ return true;
-int
-reg_or_cint_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
-{
- return (GET_CODE (op) == CONST_INT
- || register_operand (op, mode));
+ /* Functions that are not external are defined in this UoT. */
+ /* ??? Irritatingly, static functions not yet emitted are still
+ marked "external". Apply this to non-static functions only. */
+ return !TREE_PUBLIC (decl) || !DECL_EXTERNAL (decl);
}
-/* Return 1 if OP is something that can be reloaded into a register;
- if it is a MEM, it need not be valid. */
+/* Return true if EXP should be placed in the small data section. */
-int
-some_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
+static bool
+alpha_in_small_data_p (const_tree exp)
{
- if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
- return 0;
+ /* We want to merge strings, so we never consider them small data. */
+ if (TREE_CODE (exp) == STRING_CST)
+ return false;
- switch (GET_CODE (op))
- {
- case REG: case MEM: case CONST_DOUBLE: case CONST_INT: case LABEL_REF:
- case SYMBOL_REF: case CONST: case HIGH:
- return 1;
+ /* Functions are never in the small data area. Duh. */
+ if (TREE_CODE (exp) == FUNCTION_DECL)
+ return false;
- case SUBREG:
- return some_operand (SUBREG_REG (op), VOIDmode);
+ if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
+ {
+ const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
+ if (strcmp (section, ".sdata") == 0
+ || strcmp (section, ".sbss") == 0)
+ return true;
+ }
+ else
+ {
+ HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
- default:
- break;
+ /* If this is an incomplete type with size 0, then we can't put it
+ in sdata because it might be too big when completed. */
+ if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
+ return true;
}
- return 0;
+ return false;
}
-/* Likewise, but don't accept constants. */
-
-int
-some_ni_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
+#if TARGET_ABI_OPEN_VMS
+static bool
+alpha_linkage_symbol_p (const char *symname)
{
- if (GET_MODE (op) != mode && mode != VOIDmode)
- return 0;
+ int symlen = strlen (symname);
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
+ if (symlen > 4)
+ return strcmp (&symname [symlen - 4], "..lk") == 0;
- return (GET_CODE (op) == REG || GET_CODE (op) == MEM);
+ return false;
}
-/* Return 1 if OP is a valid operand for the source of a move insn. */
-
-int
-input_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
-{
- if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
- return 0;
-
- if (GET_MODE_CLASS (mode) == MODE_FLOAT && GET_MODE (op) != mode)
- return 0;
-
- switch (GET_CODE (op))
- {
- case LABEL_REF:
- case SYMBOL_REF:
- case CONST:
- if (TARGET_EXPLICIT_RELOCS)
- {
- /* We don't split symbolic operands into something unintelligable
- until after reload, but we do not wish non-small, non-global
- symbolic operands to be reconstructed from their high/lo_sum
- form. */
- return (small_symbolic_operand (op, mode)
- || global_symbolic_operand (op, mode));
- }
+#define LINKAGE_SYMBOL_REF_P(X) \
+ ((GET_CODE (X) == SYMBOL_REF \
+ && alpha_linkage_symbol_p (XSTR (X, 0))) \
+ || (GET_CODE (X) == CONST \
+ && GET_CODE (XEXP (X, 0)) == PLUS \
+ && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
+ && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
+#endif
- /* This handles both the Windows/NT and OSF cases. */
- return mode == ptr_mode || mode == DImode;
+/* legitimate_address_p recognizes an RTL expression that is a valid
+ memory address for an instruction. The MODE argument is the
+ machine mode for the MEM expression that wants to use this address.
- case HIGH:
- return (TARGET_EXPLICIT_RELOCS
- && local_symbolic_operand (XEXP (op, 0), mode));
+ For Alpha, we have either a constant address or the sum of a
+ register and a constant address, or just a register. For DImode,
+ any of those forms can be surrounded with an AND that clear the
+ low-order three bits; this is an "unaligned" access. */
- case REG:
- case ADDRESSOF:
- return 1;
-
- case SUBREG:
- if (register_operand (op, mode))
- return 1;
- /* ... fall through ... */
- case MEM:
- return ((TARGET_BWX || (mode != HImode && mode != QImode))
- && general_operand (op, mode));
-
- case CONST_DOUBLE:
- return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
+bool
+alpha_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
+{
+ /* If this is an ldq_u type address, discard the outer AND. */
+ if (mode == DImode
+ && GET_CODE (x) == AND
+ && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && INTVAL (XEXP (x, 1)) == -8)
+ x = XEXP (x, 0);
- case CONST_INT:
- return mode == QImode || mode == HImode || add_operand (op, mode);
+ /* Discard non-paradoxical subregs. */
+ if (GET_CODE (x) == SUBREG
+ && (GET_MODE_SIZE (GET_MODE (x))
+ < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
+ x = SUBREG_REG (x);
- case CONSTANT_P_RTX:
- return 1;
+ /* Unadorned general registers are valid. */
+ if (REG_P (x)
+ && (strict
+ ? STRICT_REG_OK_FOR_BASE_P (x)
+ : NONSTRICT_REG_OK_FOR_BASE_P (x)))
+ return true;
- default:
- break;
- }
+ /* Constant addresses (i.e. +/- 32k) are valid. */
+ if (CONSTANT_ADDRESS_P (x))
+ return true;
- return 0;
-}
+#if TARGET_ABI_OPEN_VMS
+ if (LINKAGE_SYMBOL_REF_P (x))
+ return true;
+#endif
-/* Return 1 if OP is a SYMBOL_REF for a function known to be in this
- file, and in the same section as the current function. */
+ /* Register plus a small constant offset is valid. */
+ if (GET_CODE (x) == PLUS)
+ {
+ rtx ofs = XEXP (x, 1);
+ x = XEXP (x, 0);
-int
-current_file_function_operand (op, mode)
- rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- if (GET_CODE (op) != SYMBOL_REF)
- return 0;
+ /* Discard non-paradoxical subregs. */
+ if (GET_CODE (x) == SUBREG
+ && (GET_MODE_SIZE (GET_MODE (x))
+ < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
+ x = SUBREG_REG (x);
- /* Easy test for recursion. */
- if (op == XEXP (DECL_RTL (current_function_decl), 0))
- return 1;
+ if (REG_P (x))
+ {
+ if (! strict
+ && NONSTRICT_REG_OK_FP_BASE_P (x)
+ && GET_CODE (ofs) == CONST_INT)
+ return true;
+ if ((strict
+ ? STRICT_REG_OK_FOR_BASE_P (x)
+ : NONSTRICT_REG_OK_FOR_BASE_P (x))
+ && CONSTANT_ADDRESS_P (ofs))
+ return true;
+ }
+ }
- /* Otherwise, we need the DECL for the SYMBOL_REF, which we can't get.
- So SYMBOL_REF_FLAG has been declared to imply that the function is
- in the default text section. So we must also check that the current
- function is also in the text section. */
- if (SYMBOL_REF_FLAG (op) && decl_in_text_section (current_function_decl))
- return 1;
+ /* If we're managing explicit relocations, LO_SUM is valid, as are small
+ data symbols. Avoid explicit relocations of modes larger than word
+ mode since i.e. $LC0+8($1) can fold around +/- 32k offset. */
+ else if (TARGET_EXPLICIT_RELOCS
+ && GET_MODE_SIZE (mode) <= UNITS_PER_WORD)
+ {
+ if (small_symbolic_operand (x, Pmode))
+ return true;
- return 0;
-}
+ if (GET_CODE (x) == LO_SUM)
+ {
+ rtx ofs = XEXP (x, 1);
+ x = XEXP (x, 0);
-/* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
+ /* Discard non-paradoxical subregs. */
+ if (GET_CODE (x) == SUBREG
+ && (GET_MODE_SIZE (GET_MODE (x))
+ < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
+ x = SUBREG_REG (x);
-int
-direct_call_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- /* Must be defined in this file. */
- if (! current_file_function_operand (op, mode))
- return 0;
+ /* Must have a valid base register. */
+ if (! (REG_P (x)
+ && (strict
+ ? STRICT_REG_OK_FOR_BASE_P (x)
+ : NONSTRICT_REG_OK_FOR_BASE_P (x))))
+ return false;
- /* If profiling is implemented via linker tricks, we can't jump
- to the nogp alternate entry point. */
- /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
- but is approximately correct for the OSF ABIs. Don't know
- what to do for VMS, NT, or UMK. */
- if (! TARGET_PROFILING_NEEDS_GP
- && ! current_function_profile)
- return 0;
+ /* The symbol must be local. */
+ if (local_symbolic_operand (ofs, Pmode)
+ || dtp32_symbolic_operand (ofs, Pmode)
+ || tp32_symbolic_operand (ofs, Pmode))
+ return true;
+ }
+ }
- return 1;
+ return false;
}
-/* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
- a variable known to be defined in this file. */
-
-static bool
-local_symbol_p (op)
- rtx op;
-{
- const char *str = XSTR (op, 0);
+/* Build the SYMBOL_REF for __tls_get_addr. */
- /* ??? SYMBOL_REF_FLAG is set for local function symbols, but we
- run into problems with the rtl inliner in that the symbol was
- once external, but is local after inlining, which results in
- unrecognizable insns. */
+static GTY(()) rtx tls_get_addr_libfunc;
- return (CONSTANT_POOL_ADDRESS_P (op)
- /* If @, then ENCODE_SECTION_INFO sez it's local. */
- || str[0] == '@'
- /* If *$, then ASM_GENERATE_INTERNAL_LABEL sez it's local. */
- || (str[0] == '*' && str[1] == '$'));
+static rtx
+get_tls_get_addr (void)
+{
+ if (!tls_get_addr_libfunc)
+ tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr");
+ return tls_get_addr_libfunc;
}
-int
-local_symbolic_operand (op, mode)
- rtx op;
- enum machine_mode mode;
+/* Try machine-dependent ways of modifying an illegitimate address
+ to be legitimate. If we find one, return the new, valid address. */
+
+rtx
+alpha_legitimize_address (rtx x, rtx scratch, enum machine_mode mode)
{
- if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
- return 0;
+ HOST_WIDE_INT addend;
- if (GET_CODE (op) == LABEL_REF)
- return 1;
+ /* If the address is (plus reg const_int) and the CONST_INT is not a
+ valid offset, compute the high part of the constant and add it to
+ the register. Then our address is (plus temp low-part-const). */
+ if (GET_CODE (x) == PLUS
+ && GET_CODE (XEXP (x, 0)) == REG
+ && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && ! CONSTANT_ADDRESS_P (XEXP (x, 1)))
+ {
+ addend = INTVAL (XEXP (x, 1));
+ x = XEXP (x, 0);
+ goto split_addend;
+ }
- if (GET_CODE (op) == CONST
- && GET_CODE (XEXP (op, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
- op = XEXP (XEXP (op, 0), 0);
+ /* If the address is (const (plus FOO const_int)), find the low-order
+ part of the CONST_INT. Then load FOO plus any high-order part of the
+ CONST_INT into a register. Our address is (plus reg low-part-const).
+ This is done to reduce the number of GOT entries. */
+ if (can_create_pseudo_p ()
+ && GET_CODE (x) == CONST
+ && GET_CODE (XEXP (x, 0)) == PLUS
+ && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
+ {
+ addend = INTVAL (XEXP (XEXP (x, 0), 1));
+ x = force_reg (Pmode, XEXP (XEXP (x, 0), 0));
+ goto split_addend;
+ }
- if (GET_CODE (op) != SYMBOL_REF)
- return 0;
+ /* If we have a (plus reg const), emit the load as in (2), then add
+ the two registers, and finally generate (plus reg low-part-const) as
+ our address. */
+ if (can_create_pseudo_p ()
+ && GET_CODE (x) == PLUS
+ && GET_CODE (XEXP (x, 0)) == REG
+ && GET_CODE (XEXP (x, 1)) == CONST
+ && GET_CODE (XEXP (XEXP (x, 1), 0)) == PLUS
+ && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == CONST_INT)
+ {
+ addend = INTVAL (XEXP (XEXP (XEXP (x, 1), 0), 1));
+ x = expand_simple_binop (Pmode, PLUS, XEXP (x, 0),
+ XEXP (XEXP (XEXP (x, 1), 0), 0),
+ NULL_RTX, 1, OPTAB_LIB_WIDEN);
+ goto split_addend;
+ }
- return local_symbol_p (op);
-}
+ /* If this is a local symbol, split the address into HIGH/LO_SUM parts.
+ Avoid modes larger than word mode since i.e. $LC0+8($1) can fold
+ around +/- 32k offset. */
+ if (TARGET_EXPLICIT_RELOCS
+ && GET_MODE_SIZE (mode) <= UNITS_PER_WORD
+ && symbolic_operand (x, Pmode))
+ {
+ rtx r0, r16, eqv, tga, tp, insn, dest, seq;
-/* Return true if OP is a SYMBOL_REF or CONST referencing a variable
- known to be defined in this file in the small data area. */
+ switch (tls_symbolic_operand_type (x))
+ {
+ case TLS_MODEL_NONE:
+ break;
-int
-small_symbolic_operand (op, mode)
- rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- const char *str;
+ case TLS_MODEL_GLOBAL_DYNAMIC:
+ start_sequence ();
- if (! TARGET_SMALL_DATA)
- return 0;
+ r0 = gen_rtx_REG (Pmode, 0);
+ r16 = gen_rtx_REG (Pmode, 16);
+ tga = get_tls_get_addr ();
+ dest = gen_reg_rtx (Pmode);
+ seq = GEN_INT (alpha_next_sequence_number++);
- if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
- return 0;
+ emit_insn (gen_movdi_er_tlsgd (r16, pic_offset_table_rtx, x, seq));
+ insn = gen_call_value_osf_tlsgd (r0, tga, seq);
+ insn = emit_call_insn (insn);
+ RTL_CONST_CALL_P (insn) = 1;
+ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
- if (GET_CODE (op) == CONST
- && GET_CODE (XEXP (op, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
- op = XEXP (XEXP (op, 0), 0);
+ insn = get_insns ();
+ end_sequence ();
- if (GET_CODE (op) != SYMBOL_REF)
- return 0;
+ emit_libcall_block (insn, dest, r0, x);
+ return dest;
- if (CONSTANT_POOL_ADDRESS_P (op))
- return GET_MODE_SIZE (get_pool_mode (op)) <= (unsigned) g_switch_value;
- else
- {
- str = XSTR (op, 0);
- return str[0] == '@' && str[1] == 's';
- }
-}
+ case TLS_MODEL_LOCAL_DYNAMIC:
+ start_sequence ();
-/* Return true if OP is a SYMBOL_REF or CONST referencing a variable
- not known (or known not) to be defined in this file. */
+ r0 = gen_rtx_REG (Pmode, 0);
+ r16 = gen_rtx_REG (Pmode, 16);
+ tga = get_tls_get_addr ();
+ scratch = gen_reg_rtx (Pmode);
+ seq = GEN_INT (alpha_next_sequence_number++);
-int
-global_symbolic_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
- return 0;
+ emit_insn (gen_movdi_er_tlsldm (r16, pic_offset_table_rtx, seq));
+ insn = gen_call_value_osf_tlsldm (r0, tga, seq);
+ insn = emit_call_insn (insn);
+ RTL_CONST_CALL_P (insn) = 1;
+ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
- if (GET_CODE (op) == CONST
- && GET_CODE (XEXP (op, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
- op = XEXP (XEXP (op, 0), 0);
+ insn = get_insns ();
+ end_sequence ();
- if (GET_CODE (op) != SYMBOL_REF)
- return 0;
+ eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
+ UNSPEC_TLSLDM_CALL);
+ emit_libcall_block (insn, scratch, r0, eqv);
- return ! local_symbol_p (op);
-}
+ eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPREL);
+ eqv = gen_rtx_CONST (Pmode, eqv);
-/* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
+ if (alpha_tls_size == 64)
+ {
+ dest = gen_reg_rtx (Pmode);
+ emit_insn (gen_rtx_SET (VOIDmode, dest, eqv));
+ emit_insn (gen_adddi3 (dest, dest, scratch));
+ return dest;
+ }
+ if (alpha_tls_size == 32)
+ {
+ insn = gen_rtx_HIGH (Pmode, eqv);
+ insn = gen_rtx_PLUS (Pmode, scratch, insn);
+ scratch = gen_reg_rtx (Pmode);
+ emit_insn (gen_rtx_SET (VOIDmode, scratch, insn));
+ }
+ return gen_rtx_LO_SUM (Pmode, scratch, eqv);
+
+ case TLS_MODEL_INITIAL_EXEC:
+ eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
+ eqv = gen_rtx_CONST (Pmode, eqv);
+ tp = gen_reg_rtx (Pmode);
+ scratch = gen_reg_rtx (Pmode);
+ dest = gen_reg_rtx (Pmode);
+
+ emit_insn (gen_load_tp (tp));
+ emit_insn (gen_rtx_SET (VOIDmode, scratch, eqv));
+ emit_insn (gen_adddi3 (dest, tp, scratch));
+ return dest;
+
+ case TLS_MODEL_LOCAL_EXEC:
+ eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
+ eqv = gen_rtx_CONST (Pmode, eqv);
+ tp = gen_reg_rtx (Pmode);
+
+ emit_insn (gen_load_tp (tp));
+ if (alpha_tls_size == 32)
+ {
+ insn = gen_rtx_HIGH (Pmode, eqv);
+ insn = gen_rtx_PLUS (Pmode, tp, insn);
+ tp = gen_reg_rtx (Pmode);
+ emit_insn (gen_rtx_SET (VOIDmode, tp, insn));
+ }
+ return gen_rtx_LO_SUM (Pmode, tp, eqv);
-int
-call_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- if (mode != Pmode)
- return 0;
+ default:
+ gcc_unreachable ();
+ }
- if (GET_CODE (op) == REG)
- {
- if (TARGET_ABI_OSF)
+ if (local_symbolic_operand (x, Pmode))
{
- /* Disallow virtual registers to cope with pathalogical test cases
- such as compile/930117-1.c in which the virtual reg decomposes
- to the frame pointer. Which is a hard reg that is not $27. */
- return (REGNO (op) == 27 || REGNO (op) > LAST_VIRTUAL_REGISTER);
+ if (small_symbolic_operand (x, Pmode))
+ return x;
+ else
+ {
+ if (can_create_pseudo_p ())
+ scratch = gen_reg_rtx (Pmode);
+ emit_insn (gen_rtx_SET (VOIDmode, scratch,
+ gen_rtx_HIGH (Pmode, x)));
+ return gen_rtx_LO_SUM (Pmode, scratch, x);
+ }
}
- else
- return 1;
}
- if (TARGET_ABI_UNICOSMK)
- return 0;
- if (GET_CODE (op) == SYMBOL_REF)
- return 1;
-
- return 0;
-}
-/* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
- possibly with an offset. */
-
-int
-symbolic_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
-{
- if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
- return 0;
- if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
- return 1;
- if (GET_CODE (op) == CONST
- && GET_CODE (XEXP (op,0)) == PLUS
- && GET_CODE (XEXP (XEXP (op,0), 0)) == SYMBOL_REF
- && GET_CODE (XEXP (XEXP (op,0), 1)) == CONST_INT)
- return 1;
- return 0;
-}
+ return NULL;
-/* Return 1 if OP is a valid Alpha comparison operator. Here we know which
- comparisons are valid in which insn. */
+ split_addend:
+ {
+ HOST_WIDE_INT low, high;
-int
-alpha_comparison_operator (op, mode)
- register rtx op;
- enum machine_mode mode;
-{
- enum rtx_code code = GET_CODE (op);
+ low = ((addend & 0xffff) ^ 0x8000) - 0x8000;
+ addend -= low;
+ high = ((addend & 0xffffffff) ^ 0x80000000) - 0x80000000;
+ addend -= high;
- if (mode != GET_MODE (op) && mode != VOIDmode)
- return 0;
+ if (addend)
+ x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (addend),
+ (!can_create_pseudo_p () ? scratch : NULL_RTX),
+ 1, OPTAB_LIB_WIDEN);
+ if (high)
+ x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (high),
+ (!can_create_pseudo_p () ? scratch : NULL_RTX),
+ 1, OPTAB_LIB_WIDEN);
- return (code == EQ || code == LE || code == LT
- || code == LEU || code == LTU);
+ return plus_constant (x, low);
+ }
}
-/* Return 1 if OP is a valid Alpha comparison operator against zero.
- Here we know which comparisons are valid in which insn. */
+/* Primarily this is required for TLS symbols, but given that our move
+ patterns *ought* to be able to handle any symbol at any time, we
+ should never be spilling symbolic operands to the constant pool, ever. */
-int
-alpha_zero_comparison_operator (op, mode)
- register rtx op;
- enum machine_mode mode;
+static bool
+alpha_cannot_force_const_mem (rtx x)
{
- enum rtx_code code = GET_CODE (op);
-
- if (mode != GET_MODE (op) && mode != VOIDmode)
- return 0;
-
- return (code == EQ || code == NE || code == LE || code == LT
- || code == LEU || code == LTU);
+ enum rtx_code code = GET_CODE (x);
+ return code == SYMBOL_REF || code == LABEL_REF || code == CONST;
}
-/* Return 1 if OP is a valid Alpha swapped comparison operator. */
+/* We do not allow indirect calls to be optimized into sibling calls, nor
+ can we allow a call to a function with a different GP to be optimized
+ into a sibcall. */
-int
-alpha_swapped_comparison_operator (op, mode)
- register rtx op;
- enum machine_mode mode;
+static bool
+alpha_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
{
- enum rtx_code code = GET_CODE (op);
-
- if ((mode != GET_MODE (op) && mode != VOIDmode)
- || GET_RTX_CLASS (code) != '<')
- return 0;
+ /* Can't do indirect tail calls, since we don't know if the target
+ uses the same GP. */
+ if (!decl)
+ return false;
- code = swap_condition (code);
- return (code == EQ || code == LE || code == LT
- || code == LEU || code == LTU);
+ /* Otherwise, we can make a tail call if the target function shares
+ the same GP. */
+ return decl_has_samegp (decl);
}
-/* Return 1 if OP is a signed comparison operation. */
-
int
-signed_comparison_operator (op, mode)
- register rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
+some_small_symbolic_operand_int (rtx *px, void *data ATTRIBUTE_UNUSED)
{
- enum rtx_code code = GET_CODE (op);
+ rtx x = *px;
- if (mode != GET_MODE (op) && mode != VOIDmode)
- return 0;
+ /* Don't re-split. */
+ if (GET_CODE (x) == LO_SUM)
+ return -1;
- return (code == EQ || code == NE
- || code == LE || code == LT
- || code == GE || code == GT);
+ return small_symbolic_operand (x, Pmode) != 0;
}
-/* Return 1 if OP is a valid Alpha floating point comparison operator.
- Here we know which comparisons are valid in which insn. */
-
-int
-alpha_fp_comparison_operator (op, mode)
- register rtx op;
- enum machine_mode mode;
+static int
+split_small_symbolic_operand_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
{
- enum rtx_code code = GET_CODE (op);
-
- if (mode != GET_MODE (op) && mode != VOIDmode)
- return 0;
-
- return (code == EQ || code == LE || code == LT || code == UNORDERED);
-}
+ rtx x = *px;
-/* Return 1 if this is a divide or modulus operator. */
+ /* Don't re-split. */
+ if (GET_CODE (x) == LO_SUM)
+ return -1;
-int
-divmod_operator (op, mode)
- register rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- switch (GET_CODE (op))
+ if (small_symbolic_operand (x, Pmode))
{
- case DIV: case MOD: case UDIV: case UMOD:
- return 1;
-
- default:
- break;
+ x = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, x);
+ *px = x;
+ return -1;
}
return 0;
}
-/* Return 1 if this memory address is a known aligned register plus
- a constant. It must be a valid address. This means that we can do
- this as an aligned reference plus some offset.
-
- Take into account what reload will do. */
-
-int
-aligned_memory_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
+rtx
+split_small_symbolic_operand (rtx x)
{
- rtx base;
+ x = copy_insn (x);
+ for_each_rtx (&x, split_small_symbolic_operand_1, NULL);
+ return x;
+}
- if (reload_in_progress)
- {
- rtx tmp = op;
- if (GET_CODE (tmp) == SUBREG)
- tmp = SUBREG_REG (tmp);
- if (GET_CODE (tmp) == REG
- && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
- {
- op = reg_equiv_memory_loc[REGNO (tmp)];
- if (op == 0)
- return 0;
- }
- }
+/* Indicate that INSN cannot be duplicated. This is true for any insn
+ that we've marked with gpdisp relocs, since those have to stay in
+ 1-1 correspondence with one another.
- if (GET_CODE (op) != MEM
- || GET_MODE (op) != mode)
- return 0;
- op = XEXP (op, 0);
+ Technically we could copy them if we could set up a mapping from one
+ sequence number to another, across the set of insns to be duplicated.
+ This seems overly complicated and error-prone since interblock motion
+ from sched-ebb could move one of the pair of insns to a different block.
- /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
- sorts of constructs. Dig for the real base register. */
- if (reload_in_progress
- && GET_CODE (op) == PLUS
- && GET_CODE (XEXP (op, 0)) == PLUS)
- base = XEXP (XEXP (op, 0), 0);
- else
- {
- if (! memory_address_p (mode, op))
- return 0;
- base = (GET_CODE (op) == PLUS ? XEXP (op, 0) : op);
- }
+ Also cannot allow jsr insns to be duplicated. If they throw exceptions,
+ then they'll be in a different block from their ldgp. Which could lead
+ the bb reorder code to think that it would be ok to copy just the block
+ containing the call and branch to the block containing the ldgp. */
- return (GET_CODE (base) == REG && REGNO_POINTER_ALIGN (REGNO (base)) >= 32);
+static bool
+alpha_cannot_copy_insn_p (rtx insn)
+{
+ if (!reload_completed || !TARGET_EXPLICIT_RELOCS)
+ return false;
+ if (recog_memoized (insn) >= 0)
+ return get_attr_cannot_copy (insn);
+ else
+ return false;
}
-/* Similar, but return 1 if OP is a MEM which is not alignable. */
-int
-unaligned_memory_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
-{
- rtx base;
+/* Try a machine-dependent way of reloading an illegitimate address
+ operand. If we find one, push the reload and return the new rtx. */
- if (reload_in_progress)
+rtx
+alpha_legitimize_reload_address (rtx x,
+ enum machine_mode mode ATTRIBUTE_UNUSED,
+ int opnum, int type,
+ int ind_levels ATTRIBUTE_UNUSED)
+{
+ /* We must recognize output that we have already generated ourselves. */
+ if (GET_CODE (x) == PLUS
+ && GET_CODE (XEXP (x, 0)) == PLUS
+ && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
+ && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+ && GET_CODE (XEXP (x, 1)) == CONST_INT)
{
- rtx tmp = op;
- if (GET_CODE (tmp) == SUBREG)
- tmp = SUBREG_REG (tmp);
- if (GET_CODE (tmp) == REG
- && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
- {
- op = reg_equiv_memory_loc[REGNO (tmp)];
- if (op == 0)
- return 0;
- }
+ push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
+ BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
+ opnum, type);
+ return x;
}
- if (GET_CODE (op) != MEM
- || GET_MODE (op) != mode)
- return 0;
- op = XEXP (op, 0);
-
- /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
- sorts of constructs. Dig for the real base register. */
- if (reload_in_progress
- && GET_CODE (op) == PLUS
- && GET_CODE (XEXP (op, 0)) == PLUS)
- base = XEXP (XEXP (op, 0), 0);
- else
+ /* We wish to handle large displacements off a base register by
+ splitting the addend across an ldah and the mem insn. This
+ cuts number of extra insns needed from 3 to 1. */
+ if (GET_CODE (x) == PLUS
+ && GET_CODE (XEXP (x, 0)) == REG
+ && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
+ && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x, 0)))
+ && GET_CODE (XEXP (x, 1)) == CONST_INT)
{
- if (! memory_address_p (mode, op))
- return 0;
- base = (GET_CODE (op) == PLUS ? XEXP (op, 0) : op);
- }
+ HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
+ HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
+ HOST_WIDE_INT high
+ = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
- return (GET_CODE (base) == REG && REGNO_POINTER_ALIGN (REGNO (base)) < 32);
-}
+ /* Check for 32-bit overflow. */
+ if (high + low != val)
+ return NULL_RTX;
+
+ /* Reload the high part into a base reg; leave the low part
+ in the mem directly. */
+ x = gen_rtx_PLUS (GET_MODE (x),
+ gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
+ GEN_INT (high)),
+ GEN_INT (low));
-/* Return 1 if OP is either a register or an unaligned memory location. */
+ push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
+ BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
+ opnum, type);
+ return x;
+ }
-int
-reg_or_unaligned_mem_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return register_operand (op, mode) || unaligned_memory_operand (op, mode);
+ return NULL_RTX;
}
+\f
+/* Compute a (partial) cost for rtx X. Return true if the complete
+ cost has been computed, and false if subexpressions should be
+ scanned. In either case, *TOTAL contains the cost result. */
-/* Return 1 if OP is any memory location. During reload a pseudo matches. */
-
-int
-any_memory_operand (op, mode)
- register rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
+static bool
+alpha_rtx_costs (rtx x, int code, int outer_code, int *total,
+ bool speed)
{
- return (GET_CODE (op) == MEM
- || (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
- || (reload_in_progress && GET_CODE (op) == REG
- && REGNO (op) >= FIRST_PSEUDO_REGISTER)
- || (reload_in_progress && GET_CODE (op) == SUBREG
- && GET_CODE (SUBREG_REG (op)) == REG
- && REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER));
-}
+ enum machine_mode mode = GET_MODE (x);
+ bool float_mode_p = FLOAT_MODE_P (mode);
+ const struct alpha_rtx_cost_data *cost_data;
-/* Returns 1 if OP is not an eliminable register.
+ if (!speed)
+ cost_data = &alpha_rtx_cost_size;
+ else
+ cost_data = &alpha_rtx_cost_data[alpha_tune];
- This exists to cure a pathological abort in the s8addq (et al) patterns,
+ switch (code)
+ {
+ case CONST_INT:
+ /* If this is an 8-bit constant, return zero since it can be used
+ nearly anywhere with no cost. If it is a valid operand for an
+ ADD or AND, likewise return 0 if we know it will be used in that
+ context. Otherwise, return 2 since it might be used there later.
+ All other constants take at least two insns. */
+ if (INTVAL (x) >= 0 && INTVAL (x) < 256)
+ {
+ *total = 0;
+ return true;
+ }
+ /* FALLTHRU */
- long foo () { long t; bar(); return (long) &t * 26107; }
+ case CONST_DOUBLE:
+ if (x == CONST0_RTX (mode))
+ *total = 0;
+ else if ((outer_code == PLUS && add_operand (x, VOIDmode))
+ || (outer_code == AND && and_operand (x, VOIDmode)))
+ *total = 0;
+ else if (add_operand (x, VOIDmode) || and_operand (x, VOIDmode))
+ *total = 2;
+ else
+ *total = COSTS_N_INSNS (2);
+ return true;
- which run afoul of a hack in reload to cure a (presumably) similar
- problem with lea-type instructions on other targets. But there is
- one of us and many of them, so work around the problem by selectively
- preventing combine from making the optimization. */
+ case CONST:
+ case SYMBOL_REF:
+ case LABEL_REF:
+ if (TARGET_EXPLICIT_RELOCS && small_symbolic_operand (x, VOIDmode))
+ *total = COSTS_N_INSNS (outer_code != MEM);
+ else if (TARGET_EXPLICIT_RELOCS && local_symbolic_operand (x, VOIDmode))
+ *total = COSTS_N_INSNS (1 + (outer_code != MEM));
+ else if (tls_symbolic_operand_type (x))
+ /* Estimate of cost for call_pal rduniq. */
+ /* ??? How many insns do we emit here? More than one... */
+ *total = COSTS_N_INSNS (15);
+ else
+ /* Otherwise we do a load from the GOT. */
+ *total = COSTS_N_INSNS (!speed ? 1 : alpha_memory_latency);
+ return true;
-int
-reg_not_elim_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
-{
- rtx inner = op;
- if (GET_CODE (op) == SUBREG)
- inner = SUBREG_REG (op);
- if (inner == frame_pointer_rtx || inner == arg_pointer_rtx)
- return 0;
+ case HIGH:
+ /* This is effectively an add_operand. */
+ *total = 2;
+ return true;
- return register_operand (op, mode);
-}
+ case PLUS:
+ case MINUS:
+ if (float_mode_p)
+ *total = cost_data->fp_add;
+ else if (GET_CODE (XEXP (x, 0)) == MULT
+ && const48_operand (XEXP (XEXP (x, 0), 1), VOIDmode))
+ {
+ *total = (rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed)
+ + rtx_cost (XEXP (x, 1), outer_code, speed) + COSTS_N_INSNS (1));
+ return true;
+ }
+ return false;
-/* Return 1 is OP is a memory location that is not a reference (using
- an AND) to an unaligned location. Take into account what reload
- will do. */
+ case MULT:
+ if (float_mode_p)
+ *total = cost_data->fp_mult;
+ else if (mode == DImode)
+ *total = cost_data->int_mult_di;
+ else
+ *total = cost_data->int_mult_si;
+ return false;
-int
-normal_memory_operand (op, mode)
- register rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- if (reload_in_progress)
- {
- rtx tmp = op;
- if (GET_CODE (tmp) == SUBREG)
- tmp = SUBREG_REG (tmp);
- if (GET_CODE (tmp) == REG
- && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
+ case ASHIFT:
+ if (GET_CODE (XEXP (x, 1)) == CONST_INT
+ && INTVAL (XEXP (x, 1)) <= 3)
{
- op = reg_equiv_memory_loc[REGNO (tmp)];
-
- /* This may not have been assigned an equivalent address if it will
- be eliminated. In that case, it doesn't matter what we do. */
- if (op == 0)
- return 1;
+ *total = COSTS_N_INSNS (1);
+ return false;
}
- }
+ /* FALLTHRU */
- return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) != AND;
-}
+ case ASHIFTRT:
+ case LSHIFTRT:
+ *total = cost_data->int_shift;
+ return false;
-/* Accept a register, but not a subreg of any kind. This allows us to
- avoid pathological cases in reload wrt data movement common in
- int->fp conversion. */
+ case IF_THEN_ELSE:
+ if (float_mode_p)
+ *total = cost_data->fp_add;
+ else
+ *total = cost_data->int_cmov;
+ return false;
-int
-reg_no_subreg_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
-{
- if (GET_CODE (op) != REG)
- return 0;
- return register_operand (op, mode);
-}
+ case DIV:
+ case UDIV:
+ case MOD:
+ case UMOD:
+ if (!float_mode_p)
+ *total = cost_data->int_div;
+ else if (mode == SFmode)
+ *total = cost_data->fp_div_sf;
+ else
+ *total = cost_data->fp_div_df;
+ return false;
-/* Recognize an addition operation that includes a constant. Used to
- convince reload to canonize (plus (plus reg c1) c2) during register
- elimination. */
+ case MEM:
+ *total = COSTS_N_INSNS (!speed ? 1 : alpha_memory_latency);
+ return true;
-int
-addition_operation (op, mode)
- register rtx op;
- enum machine_mode mode;
-{
- if (GET_MODE (op) != mode && mode != VOIDmode)
- return 0;
- if (GET_CODE (op) == PLUS
- && register_operand (XEXP (op, 0), mode)
- && GET_CODE (XEXP (op, 1)) == CONST_INT
- && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op, 1)), 'K'))
- return 1;
- return 0;
-}
+ case NEG:
+ if (! float_mode_p)
+ {
+ *total = COSTS_N_INSNS (1);
+ return false;
+ }
+ /* FALLTHRU */
-/* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
- the range defined for C in [I-P]. */
+ case ABS:
+ if (! float_mode_p)
+ {
+ *total = COSTS_N_INSNS (1) + cost_data->int_cmov;
+ return false;
+ }
+ /* FALLTHRU */
-bool
-alpha_const_ok_for_letter_p (value, c)
- HOST_WIDE_INT value;
- int c;
-{
- switch (c)
- {
- case 'I':
- /* An unsigned 8 bit constant. */
- return (unsigned HOST_WIDE_INT) value < 0x100;
- case 'J':
- /* The constant zero. */
- return value == 0;
- case 'K':
- /* A signed 16 bit constant. */
- return (unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000;
- case 'L':
- /* A shifted signed 16 bit constant appropriate for LDAH. */
- return ((value & 0xffff) == 0
- && ((value) >> 31 == -1 || value >> 31 == 0));
- case 'M':
- /* A constant that can be AND'ed with using a ZAP insn. */
- return zap_mask (value);
- case 'N':
- /* A complemented unsigned 8 bit constant. */
- return (unsigned HOST_WIDE_INT) (~ value) < 0x100;
- case 'O':
- /* A negated unsigned 8 bit constant. */
- return (unsigned HOST_WIDE_INT) (- value) < 0x100;
- case 'P':
- /* The constant 1, 2 or 3. */
- return value == 1 || value == 2 || value == 3;
+ case FLOAT:
+ case UNSIGNED_FLOAT:
+ case FIX:
+ case UNSIGNED_FIX:
+ case FLOAT_TRUNCATE:
+ *total = cost_data->fp_add;
+ return false;
+
+ case FLOAT_EXTEND:
+ if (GET_CODE (XEXP (x, 0)) == MEM)
+ *total = 0;
+ else
+ *total = cost_data->fp_add;
+ return false;
default:
return false;
}
}
+\f
+/* REF is an alignable memory location. Place an aligned SImode
+ reference into *PALIGNED_MEM and the number of bits to shift into
+ *PBITNUM. SCRATCH is a free register for use in reloading out
+ of range stack slots. */
-/* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
- matches for C in [GH]. */
-
-bool
-alpha_const_double_ok_for_letter_p (value, c)
- rtx value;
- int c;
+void
+get_aligned_mem (rtx ref, rtx *paligned_mem, rtx *pbitnum)
{
- switch (c)
- {
- case 'G':
- /* The floating point zero constant. */
- return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
- && value == CONST0_RTX (GET_MODE (value)));
+ rtx base;
+ HOST_WIDE_INT disp, offset;
- case 'H':
- /* A valid operand of a ZAP insn. */
- return (GET_MODE (value) == VOIDmode
- && zap_mask (CONST_DOUBLE_LOW (value))
- && zap_mask (CONST_DOUBLE_HIGH (value)));
+ gcc_assert (GET_CODE (ref) == MEM);
- default:
- return false;
+ if (reload_in_progress
+ && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
+ {
+ base = find_replacement (&XEXP (ref, 0));
+ gcc_assert (memory_address_p (GET_MODE (ref), base));
}
+ else
+ base = XEXP (ref, 0);
+
+ if (GET_CODE (base) == PLUS)
+ disp = INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
+ else
+ disp = 0;
+
+ /* Find the byte offset within an aligned word. If the memory itself is
+ claimed to be aligned, believe it. Otherwise, aligned_memory_operand
+ will have examined the base register and determined it is aligned, and
+ thus displacements from it are naturally alignable. */
+ if (MEM_ALIGN (ref) >= 32)
+ offset = 0;
+ else
+ offset = disp & 3;
+
+ /* The location should not cross aligned word boundary. */
+ gcc_assert (offset + GET_MODE_SIZE (GET_MODE (ref))
+ <= GET_MODE_SIZE (SImode));
+
+ /* Access the entire aligned word. */
+ *paligned_mem = widen_memory_access (ref, SImode, -offset);
+
+ /* Convert the byte offset within the word to a bit offset. */
+ if (WORDS_BIG_ENDIAN)
+ offset = 32 - (GET_MODE_BITSIZE (GET_MODE (ref)) + offset * 8);
+ else
+ offset *= 8;
+ *pbitnum = GEN_INT (offset);
}
-/* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
- matches for C. */
+/* Similar, but just get the address. Handle the two reload cases.
+ Add EXTRA_OFFSET to the address we return. */
-bool
-alpha_extra_constraint (value, c)
- rtx value;
- int c;
+rtx
+get_unaligned_address (rtx ref)
{
- switch (c)
+ rtx base;
+ HOST_WIDE_INT offset = 0;
+
+ gcc_assert (GET_CODE (ref) == MEM);
+
+ if (reload_in_progress
+ && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
{
- case 'Q':
- return normal_memory_operand (value, VOIDmode);
- case 'R':
- return direct_call_operand (value, Pmode);
- case 'S':
- return (GET_CODE (value) == CONST_INT
- && (unsigned HOST_WIDE_INT) INTVAL (value) < 64);
- case 'T':
- return GET_CODE (value) == HIGH;
- case 'U':
- return TARGET_ABI_UNICOSMK && symbolic_operand (value, VOIDmode);
+ base = find_replacement (&XEXP (ref, 0));
- default:
- return false;
+ gcc_assert (memory_address_p (GET_MODE (ref), base));
}
-}
+ else
+ base = XEXP (ref, 0);
-/* Return 1 if this function can directly return via $26. */
+ if (GET_CODE (base) == PLUS)
+ offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
-int
-direct_return ()
-{
- return (! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK
- && reload_completed
- && alpha_sa_size () == 0
- && get_frame_size () == 0
- && current_function_outgoing_args_size == 0
- && current_function_pretend_args_size == 0);
+ return plus_constant (base, offset);
}
-/* Return the ADDR_VEC associated with a tablejump insn. */
+/* Compute a value X, such that X & 7 == (ADDR + OFS) & 7.
+ X is always returned in a register. */
rtx
-alpha_tablejump_addr_vec (insn)
- rtx insn;
+get_unaligned_offset (rtx addr, HOST_WIDE_INT ofs)
{
- rtx tmp;
+ if (GET_CODE (addr) == PLUS)
+ {
+ ofs += INTVAL (XEXP (addr, 1));
+ addr = XEXP (addr, 0);
+ }
- tmp = JUMP_LABEL (insn);
- if (!tmp)
- return NULL_RTX;
- tmp = NEXT_INSN (tmp);
- if (!tmp)
- return NULL_RTX;
- if (GET_CODE (tmp) == JUMP_INSN
- && GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC)
- return PATTERN (tmp);
- return NULL_RTX;
+ return expand_simple_binop (Pmode, PLUS, addr, GEN_INT (ofs & 7),
+ NULL_RTX, 1, OPTAB_LIB_WIDEN);
}
-/* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
+/* On the Alpha, all (non-symbolic) constants except zero go into
+ a floating-point register via memory. Note that we cannot
+ return anything that is not a subset of RCLASS, and that some
+ symbolic constants cannot be dropped to memory. */
-rtx
-alpha_tablejump_best_label (insn)
- rtx insn;
+enum reg_class
+alpha_preferred_reload_class(rtx x, enum reg_class rclass)
{
- rtx jump_table = alpha_tablejump_addr_vec (insn);
- rtx best_label = NULL_RTX;
-
- /* ??? Once the CFG doesn't keep getting completely rebuilt, look
- there for edge frequency counts from profile data. */
+ /* Zero is present in any register class. */
+ if (x == CONST0_RTX (GET_MODE (x)))
+ return rclass;
- if (jump_table)
+ /* These sorts of constants we can easily drop to memory. */
+ if (GET_CODE (x) == CONST_INT
+ || GET_CODE (x) == CONST_DOUBLE
+ || GET_CODE (x) == CONST_VECTOR)
{
- int n_labels = XVECLEN (jump_table, 1);
- int best_count = -1;
- int i, j;
-
- for (i = 0; i < n_labels; i++)
- {
- int count = 1;
-
- for (j = i + 1; j < n_labels; j++)
- if (XEXP (XVECEXP (jump_table, 1, i), 0)
- == XEXP (XVECEXP (jump_table, 1, j), 0))
- count++;
-
- if (count > best_count)
- best_count = count, best_label = XVECEXP (jump_table, 1, i);
- }
+ if (rclass == FLOAT_REGS)
+ return NO_REGS;
+ if (rclass == ALL_REGS)
+ return GENERAL_REGS;
+ return rclass;
}
- return best_label ? best_label : const0_rtx;
-}
-\f
-/* Return true if the function DECL will be placed in the default text
- section. */
-/* ??? Ideally we'd be able to always move from a SYMBOL_REF back to the
- decl, as that would allow us to determine if two functions are in the
- same section, which is what we really want to know. */
+ /* All other kinds of constants should not (and in the case of HIGH
+ cannot) be dropped to memory -- instead we use a GENERAL_REGS
+ secondary reload. */
+ if (CONSTANT_P (x))
+ return (rclass == ALL_REGS ? GENERAL_REGS : rclass);
-static bool
-decl_in_text_section (decl)
- tree decl;
-{
- return (DECL_SECTION_NAME (decl) == NULL_TREE
- && ! (flag_function_sections
- || (targetm.have_named_sections
- && DECL_ONE_ONLY (decl))));
+ return rclass;
}
-/* If we are referencing a function that is static, make the SYMBOL_REF
- special. We use this to see indicate we can branch to this function
- without setting PV or restoring GP.
+/* Inform reload about cases where moving X with a mode MODE to a register in
+ RCLASS requires an extra scratch or immediate register. Return the class
+ needed for the immediate register. */
- If this is a variable that is known to be defined locally, add "@v"
- to the name. If in addition the variable is to go in .sdata/.sbss,
- then add "@s" instead. */
-
-void
-alpha_encode_section_info (decl)
- tree decl;
+static enum reg_class
+alpha_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
+ enum machine_mode mode, secondary_reload_info *sri)
{
- const char *symbol_str;
- bool is_local, is_small;
-
- if (TREE_CODE (decl) == FUNCTION_DECL)
+ /* Loading and storing HImode or QImode values to and from memory
+ usually requires a scratch register. */
+ if (!TARGET_BWX && (mode == QImode || mode == HImode || mode == CQImode))
{
- /* We mark public functions once they are emitted; otherwise we
- don't know that they exist in this unit of translation. */
- if (TREE_PUBLIC (decl))
- return;
- /* Do not mark functions that are not in .text; otherwise we
- don't know that they are near enough for a direct branch. */
- if (! decl_in_text_section (decl))
- return;
+ if (any_memory_operand (x, mode))
+ {
+ if (in_p)
+ {
+ if (!aligned_memory_operand (x, mode))
+ sri->icode = reload_in_optab[mode];
+ }
+ else
+ sri->icode = reload_out_optab[mode];
+ return NO_REGS;
+ }
+ }
- SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
- return;
+ /* We also cannot do integral arithmetic into FP regs, as might result
+ from register elimination into a DImode fp register. */
+ if (rclass == FLOAT_REGS)
+ {
+ if (MEM_P (x) && GET_CODE (XEXP (x, 0)) == AND)
+ return GENERAL_REGS;
+ if (in_p && INTEGRAL_MODE_P (mode)
+ && !MEM_P (x) && !REG_P (x) && !CONST_INT_P (x))
+ return GENERAL_REGS;
}
- /* Early out if we're not going to do anything with this data. */
- if (! TARGET_EXPLICIT_RELOCS)
- return;
+ return NO_REGS;
+}
+\f
+/* Subfunction of the following function. Update the flags of any MEM
+ found in part of X. */
- /* Careful not to prod global register variables. */
- if (TREE_CODE (decl) != VAR_DECL
- || GET_CODE (DECL_RTL (decl)) != MEM
- || GET_CODE (XEXP (DECL_RTL (decl), 0)) != SYMBOL_REF)
- return;
-
- symbol_str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
-
- /* A variable is considered "local" if it is defined in this module. */
-
- if (DECL_EXTERNAL (decl))
- is_local = false;
- /* Linkonce and weak data is never local. */
- else if (DECL_ONE_ONLY (decl) || DECL_WEAK (decl))
- is_local = false;
- else if (! TREE_PUBLIC (decl))
- is_local = true;
- /* If PIC, then assume that any global name can be overridden by
- symbols resolved from other modules. */
- else if (flag_pic)
- is_local = false;
- /* Uninitialized COMMON variable may be unified with symbols
- resolved from other modules. */
- else if (DECL_COMMON (decl)
- && (DECL_INITIAL (decl) == NULL
- || DECL_INITIAL (decl) == error_mark_node))
- is_local = false;
- /* Otherwise we're left with initialized (or non-common) global data
- which is of necessity defined locally. */
- else
- is_local = true;
+static int
+alpha_set_memflags_1 (rtx *xp, void *data)
+{
+ rtx x = *xp, orig = (rtx) data;
- /* Determine if DECL will wind up in .sdata/.sbss. */
+ if (GET_CODE (x) != MEM)
+ return 0;
- is_small = false;
- if (DECL_SECTION_NAME (decl))
- {
- const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
- if (strcmp (section, ".sdata") == 0
- || strcmp (section, ".sbss") == 0)
- is_small = true;
- }
- else
- {
- HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
+ MEM_VOLATILE_P (x) = MEM_VOLATILE_P (orig);
+ MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (orig);
+ MEM_SCALAR_P (x) = MEM_SCALAR_P (orig);
+ MEM_NOTRAP_P (x) = MEM_NOTRAP_P (orig);
+ MEM_READONLY_P (x) = MEM_READONLY_P (orig);
- /* If the variable has already been defined in the output file, then it
- is too late to put it in sdata if it wasn't put there in the first
- place. The test is here rather than above, because if it is already
- in sdata, then it can stay there. */
+ /* Sadly, we cannot use alias sets because the extra aliasing
+ produced by the AND interferes. Given that two-byte quantities
+ are the only thing we would be able to differentiate anyway,
+ there does not seem to be any point in convoluting the early
+ out of the alias check. */
- if (TREE_ASM_WRITTEN (decl))
- ;
+ return -1;
+}
- /* If this is an incomplete type with size 0, then we can't put it in
- sdata because it might be too big when completed. */
- else if (size > 0 && size <= g_switch_value)
- is_small = true;
- }
+/* Given SEQ, which is an INSN list, look for any MEMs in either
+ a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
+ volatile flags from REF into each of the MEMs found. If REF is not
+ a MEM, don't do anything. */
- /* Finally, encode this into the symbol string. */
- if (is_local)
- {
- const char *string;
- char *newstr;
- size_t len;
+void
+alpha_set_memflags (rtx seq, rtx ref)
+{
+ rtx insn;
- if (symbol_str[0] == '@')
- {
- if (symbol_str[1] == (is_small ? 's' : 'v'))
- return;
- symbol_str += 2;
- }
+ if (!MEM_P (ref))
+ return;
- len = strlen (symbol_str) + 1;
- newstr = alloca (len + 2);
+ /* This is only called from alpha.md, after having had something
+ generated from one of the insn patterns. So if everything is
+ zero, the pattern is already up-to-date. */
+ if (!MEM_VOLATILE_P (ref)
+ && !MEM_IN_STRUCT_P (ref)
+ && !MEM_SCALAR_P (ref)
+ && !MEM_NOTRAP_P (ref)
+ && !MEM_READONLY_P (ref))
+ return;
- newstr[0] = '@';
- newstr[1] = (is_small ? 's' : 'v');
- memcpy (newstr + 2, symbol_str, len);
-
- string = ggc_alloc_string (newstr, len + 2 - 1);
- XSTR (XEXP (DECL_RTL (decl), 0), 0) = string;
- }
- else if (symbol_str[0] == '@')
- {
- /* We're hosed. This can happen when the user adds a weak
- attribute after rtl generation. They should have gotten
- a warning about unspecified behaviour from varasm.c. */
- }
+ for (insn = seq; insn; insn = NEXT_INSN (insn))
+ if (INSN_P (insn))
+ for_each_rtx (&PATTERN (insn), alpha_set_memflags_1, (void *) ref);
+ else
+ gcc_unreachable ();
}
+\f
+static rtx alpha_emit_set_const (rtx, enum machine_mode, HOST_WIDE_INT,
+ int, bool);
-/* legitimate_address_p recognizes an RTL expression that is a valid
- memory address for an instruction. The MODE argument is the
- machine mode for the MEM expression that wants to use this address.
-
- For Alpha, we have either a constant address or the sum of a
- register and a constant address, or just a register. For DImode,
- any of those forms can be surrounded with an AND that clear the
- low-order three bits; this is an "unaligned" access. */
+/* Internal routine for alpha_emit_set_const to check for N or below insns.
+ If NO_OUTPUT is true, then we only check to see if N insns are possible,
+ and return pc_rtx if successful. */
-bool
-alpha_legitimate_address_p (mode, x, strict)
- enum machine_mode mode;
- rtx x;
- int strict;
+static rtx
+alpha_emit_set_const_1 (rtx target, enum machine_mode mode,
+ HOST_WIDE_INT c, int n, bool no_output)
{
- /* If this is an ldq_u type address, discard the outer AND. */
- if (mode == DImode
- && GET_CODE (x) == AND
- && GET_CODE (XEXP (x, 1)) == CONST_INT
- && INTVAL (XEXP (x, 1)) == -8)
- x = XEXP (x, 0);
-
- /* Discard non-paradoxical subregs. */
- if (GET_CODE (x) == SUBREG
- && (GET_MODE_SIZE (GET_MODE (x))
- < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
- x = SUBREG_REG (x);
-
- /* Unadorned general registers are valid. */
- if (REG_P (x)
- && (strict
- ? STRICT_REG_OK_FOR_BASE_P (x)
- : NONSTRICT_REG_OK_FOR_BASE_P (x)))
- return true;
+ HOST_WIDE_INT new_const;
+ int i, bits;
+ /* Use a pseudo if highly optimizing and still generating RTL. */
+ rtx subtarget
+ = (flag_expensive_optimizations && can_create_pseudo_p () ? 0 : target);
+ rtx temp, insn;
- /* Constant addresses (i.e. +/- 32k) are valid. */
- if (CONSTANT_ADDRESS_P (x))
- return true;
+ /* If this is a sign-extended 32-bit constant, we can do this in at most
+ three insns, so do it if we have enough insns left. We always have
+ a sign-extended 32-bit constant when compiling on a narrow machine. */
- /* Register plus a small constant offset is valid. */
- if (GET_CODE (x) == PLUS)
+ if (HOST_BITS_PER_WIDE_INT != 64
+ || c >> 31 == -1 || c >> 31 == 0)
{
- rtx ofs = XEXP (x, 1);
- x = XEXP (x, 0);
+ HOST_WIDE_INT low = ((c & 0xffff) ^ 0x8000) - 0x8000;
+ HOST_WIDE_INT tmp1 = c - low;
+ HOST_WIDE_INT high = (((tmp1 >> 16) & 0xffff) ^ 0x8000) - 0x8000;
+ HOST_WIDE_INT extra = 0;
- /* Discard non-paradoxical subregs. */
- if (GET_CODE (x) == SUBREG
- && (GET_MODE_SIZE (GET_MODE (x))
- < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
- x = SUBREG_REG (x);
+ /* If HIGH will be interpreted as negative but the constant is
+ positive, we must adjust it to do two ldha insns. */
- if (REG_P (x))
+ if ((high & 0x8000) != 0 && c >= 0)
{
- if (! strict
- && NONSTRICT_REG_OK_FP_BASE_P (x)
- && GET_CODE (ofs) == CONST_INT)
- return true;
- if ((strict
- ? STRICT_REG_OK_FOR_BASE_P (x)
- : NONSTRICT_REG_OK_FOR_BASE_P (x))
- && CONSTANT_ADDRESS_P (ofs))
- return true;
+ extra = 0x4000;
+ tmp1 -= 0x40000000;
+ high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
}
- else if (GET_CODE (x) == ADDRESSOF
- && GET_CODE (ofs) == CONST_INT)
- return true;
- }
- /* If we're managing explicit relocations, LO_SUM is valid, as
- are small data symbols. */
- else if (TARGET_EXPLICIT_RELOCS)
- {
- if (small_symbolic_operand (x, Pmode))
- return true;
+ if (c == low || (low == 0 && extra == 0))
+ {
+ /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
+ but that meant that we can't handle INT_MIN on 32-bit machines
+ (like NT/Alpha), because we recurse indefinitely through
+ emit_move_insn to gen_movdi. So instead, since we know exactly
+ what we want, create it explicitly. */
- if (GET_CODE (x) == LO_SUM)
+ if (no_output)
+ return pc_rtx;
+ if (target == NULL)
+ target = gen_reg_rtx (mode);
+ emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (c)));
+ return target;
+ }
+ else if (n >= 2 + (extra != 0))
{
- rtx ofs = XEXP (x, 1);
- x = XEXP (x, 0);
+ if (no_output)
+ return pc_rtx;
+ if (!can_create_pseudo_p ())
+ {
+ emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (high << 16)));
+ temp = target;
+ }
+ else
+ temp = copy_to_suggested_reg (GEN_INT (high << 16),
+ subtarget, mode);
- /* Discard non-paradoxical subregs. */
- if (GET_CODE (x) == SUBREG
- && (GET_MODE_SIZE (GET_MODE (x))
- < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
- x = SUBREG_REG (x);
+ /* As of 2002-02-23, addsi3 is only available when not optimizing.
+ This means that if we go through expand_binop, we'll try to
+ generate extensions, etc, which will require new pseudos, which
+ will fail during some split phases. The SImode add patterns
+ still exist, but are not named. So build the insns by hand. */
- /* Must have a valid base register. */
- if (! (REG_P (x)
- && (strict
- ? STRICT_REG_OK_FOR_BASE_P (x)
- : NONSTRICT_REG_OK_FOR_BASE_P (x))))
- return false;
+ if (extra != 0)
+ {
+ if (! subtarget)
+ subtarget = gen_reg_rtx (mode);
+ insn = gen_rtx_PLUS (mode, temp, GEN_INT (extra << 16));
+ insn = gen_rtx_SET (VOIDmode, subtarget, insn);
+ emit_insn (insn);
+ temp = subtarget;
+ }
- /* The symbol must be local. */
- if (local_symbolic_operand (ofs, Pmode))
- return true;
+ if (target == NULL)
+ target = gen_reg_rtx (mode);
+ insn = gen_rtx_PLUS (mode, temp, GEN_INT (low));
+ insn = gen_rtx_SET (VOIDmode, target, insn);
+ emit_insn (insn);
+ return target;
}
}
- return false;
-}
+ /* If we couldn't do it that way, try some other methods. But if we have
+ no instructions left, don't bother. Likewise, if this is SImode and
+ we can't make pseudos, we can't do anything since the expand_binop
+ and expand_unop calls will widen and try to make pseudos. */
-/* Try machine-dependent ways of modifying an illegitimate address
- to be legitimate. If we find one, return the new, valid address. */
+ if (n == 1 || (mode == SImode && !can_create_pseudo_p ()))
+ return 0;
-rtx
-alpha_legitimize_address (x, scratch, mode)
- rtx x;
- rtx scratch;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- HOST_WIDE_INT addend;
+ /* Next, see if we can load a related constant and then shift and possibly
+ negate it to get the constant we want. Try this once each increasing
+ numbers of insns. */
- /* If the address is (plus reg const_int) and the CONST_INT is not a
- valid offset, compute the high part of the constant and add it to
- the register. Then our address is (plus temp low-part-const). */
- if (GET_CODE (x) == PLUS
- && GET_CODE (XEXP (x, 0)) == REG
- && GET_CODE (XEXP (x, 1)) == CONST_INT
- && ! CONSTANT_ADDRESS_P (XEXP (x, 1)))
+ for (i = 1; i < n; i++)
{
- addend = INTVAL (XEXP (x, 1));
- x = XEXP (x, 0);
- goto split_addend;
- }
+ /* First, see if minus some low bits, we've an easy load of
+ high bits. */
- /* If the address is (const (plus FOO const_int)), find the low-order
- part of the CONST_INT. Then load FOO plus any high-order part of the
- CONST_INT into a register. Our address is (plus reg low-part-const).
- This is done to reduce the number of GOT entries. */
- if (!no_new_pseudos
- && GET_CODE (x) == CONST
- && GET_CODE (XEXP (x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
- {
- addend = INTVAL (XEXP (XEXP (x, 0), 1));
- x = force_reg (Pmode, XEXP (XEXP (x, 0), 0));
- goto split_addend;
- }
-
- /* If we have a (plus reg const), emit the load as in (2), then add
- the two registers, and finally generate (plus reg low-part-const) as
- our address. */
- if (!no_new_pseudos
- && GET_CODE (x) == PLUS
- && GET_CODE (XEXP (x, 0)) == REG
- && GET_CODE (XEXP (x, 1)) == CONST
- && GET_CODE (XEXP (XEXP (x, 1), 0)) == PLUS
- && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == CONST_INT)
- {
- addend = INTVAL (XEXP (XEXP (XEXP (x, 1), 0), 1));
- x = expand_simple_binop (Pmode, PLUS, XEXP (x, 0),
- XEXP (XEXP (XEXP (x, 1), 0), 0),
- NULL_RTX, 1, OPTAB_LIB_WIDEN);
- goto split_addend;
- }
-
- /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
- if (TARGET_EXPLICIT_RELOCS && symbolic_operand (x, Pmode))
- {
- if (local_symbolic_operand (x, Pmode))
+ new_const = ((c & 0xffff) ^ 0x8000) - 0x8000;
+ if (new_const != 0)
{
- if (small_symbolic_operand (x, Pmode))
- return x;
- else
+ temp = alpha_emit_set_const (subtarget, mode, c - new_const, i, no_output);
+ if (temp)
{
- if (!no_new_pseudos)
- scratch = gen_reg_rtx (Pmode);
- emit_insn (gen_rtx_SET (VOIDmode, scratch,
- gen_rtx_HIGH (Pmode, x)));
- return gen_rtx_LO_SUM (Pmode, scratch, x);
+ if (no_output)
+ return temp;
+ return expand_binop (mode, add_optab, temp, GEN_INT (new_const),
+ target, 0, OPTAB_WIDEN);
}
}
- }
-
- return NULL;
-
- split_addend:
- {
- HOST_WIDE_INT low, high;
- low = ((addend & 0xffff) ^ 0x8000) - 0x8000;
- addend -= low;
- high = ((addend & 0xffffffff) ^ 0x80000000) - 0x80000000;
- addend -= high;
+ /* Next try complementing. */
+ temp = alpha_emit_set_const (subtarget, mode, ~c, i, no_output);
+ if (temp)
+ {
+ if (no_output)
+ return temp;
+ return expand_unop (mode, one_cmpl_optab, temp, target, 0);
+ }
- if (addend)
- x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (addend),
- (no_new_pseudos ? scratch : NULL_RTX),
- 1, OPTAB_LIB_WIDEN);
- if (high)
- x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (high),
- (no_new_pseudos ? scratch : NULL_RTX),
- 1, OPTAB_LIB_WIDEN);
+ /* Next try to form a constant and do a left shift. We can do this
+ if some low-order bits are zero; the exact_log2 call below tells
+ us that information. The bits we are shifting out could be any
+ value, but here we'll just try the 0- and sign-extended forms of
+ the constant. To try to increase the chance of having the same
+ constant in more than one insn, start at the highest number of
+ bits to shift, but try all possibilities in case a ZAPNOT will
+ be useful. */
- return plus_constant (x, low);
- }
-}
+ bits = exact_log2 (c & -c);
+ if (bits > 0)
+ for (; bits > 0; bits--)
+ {
+ new_const = c >> bits;
+ temp = alpha_emit_set_const (subtarget, mode, new_const, i, no_output);
+ if (!temp && c < 0)
+ {
+ new_const = (unsigned HOST_WIDE_INT)c >> bits;
+ temp = alpha_emit_set_const (subtarget, mode, new_const,
+ i, no_output);
+ }
+ if (temp)
+ {
+ if (no_output)
+ return temp;
+ return expand_binop (mode, ashl_optab, temp, GEN_INT (bits),
+ target, 0, OPTAB_WIDEN);
+ }
+ }
-/* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
- small symbolic operand until after reload. At which point we need
- to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
- so that sched2 has the proper dependency information. */
+ /* Now try high-order zero bits. Here we try the shifted-in bits as
+ all zero and all ones. Be careful to avoid shifting outside the
+ mode and to avoid shifting outside the host wide int size. */
+ /* On narrow hosts, don't shift a 1 into the high bit, since we'll
+ confuse the recursive call and set all of the high 32 bits. */
-int
-some_small_symbolic_operand (x, mode)
- rtx x;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- return for_each_rtx (&x, some_small_symbolic_operand_1, NULL);
-}
+ bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
+ - floor_log2 (c) - 1 - (HOST_BITS_PER_WIDE_INT < 64));
+ if (bits > 0)
+ for (; bits > 0; bits--)
+ {
+ new_const = c << bits;
+ temp = alpha_emit_set_const (subtarget, mode, new_const, i, no_output);
+ if (!temp)
+ {
+ new_const = (c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1);
+ temp = alpha_emit_set_const (subtarget, mode, new_const,
+ i, no_output);
+ }
+ if (temp)
+ {
+ if (no_output)
+ return temp;
+ return expand_binop (mode, lshr_optab, temp, GEN_INT (bits),
+ target, 1, OPTAB_WIDEN);
+ }
+ }
-static int
-some_small_symbolic_operand_1 (px, data)
- rtx *px;
- void *data ATTRIBUTE_UNUSED;
-{
- rtx x = *px;
+ /* Now try high-order 1 bits. We get that with a sign-extension.
+ But one bit isn't enough here. Be careful to avoid shifting outside
+ the mode and to avoid shifting outside the host wide int size. */
- /* Don't re-split. */
- if (GET_CODE (x) == LO_SUM)
- return -1;
+ bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
+ - floor_log2 (~ c) - 2);
+ if (bits > 0)
+ for (; bits > 0; bits--)
+ {
+ new_const = c << bits;
+ temp = alpha_emit_set_const (subtarget, mode, new_const, i, no_output);
+ if (!temp)
+ {
+ new_const = (c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1);
+ temp = alpha_emit_set_const (subtarget, mode, new_const,
+ i, no_output);
+ }
+ if (temp)
+ {
+ if (no_output)
+ return temp;
+ return expand_binop (mode, ashr_optab, temp, GEN_INT (bits),
+ target, 0, OPTAB_WIDEN);
+ }
+ }
+ }
- return small_symbolic_operand (x, Pmode) != 0;
-}
+#if HOST_BITS_PER_WIDE_INT == 64
+ /* Finally, see if can load a value into the target that is the same as the
+ constant except that all bytes that are 0 are changed to be 0xff. If we
+ can, then we can do a ZAPNOT to obtain the desired constant. */
-rtx
-split_small_symbolic_operand (x)
- rtx x;
-{
- x = copy_insn (x);
- for_each_rtx (&x, split_small_symbolic_operand_1, NULL);
- return x;
-}
+ new_const = c;
+ for (i = 0; i < 64; i += 8)
+ if ((new_const & ((HOST_WIDE_INT) 0xff << i)) == 0)
+ new_const |= (HOST_WIDE_INT) 0xff << i;
-static int
-split_small_symbolic_operand_1 (px, data)
- rtx *px;
- void *data ATTRIBUTE_UNUSED;
-{
- rtx x = *px;
+ /* We are only called for SImode and DImode. If this is SImode, ensure that
+ we are sign extended to a full word. */
- /* Don't re-split. */
- if (GET_CODE (x) == LO_SUM)
- return -1;
+ if (mode == SImode)
+ new_const = ((new_const & 0xffffffff) ^ 0x80000000) - 0x80000000;
- if (small_symbolic_operand (x, Pmode))
+ if (new_const != c)
{
- x = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, x);
- *px = x;
- return -1;
+ temp = alpha_emit_set_const (subtarget, mode, new_const, n - 1, no_output);
+ if (temp)
+ {
+ if (no_output)
+ return temp;
+ return expand_binop (mode, and_optab, temp, GEN_INT (c | ~ new_const),
+ target, 0, OPTAB_WIDEN);
+ }
}
+#endif
return 0;
}
-/* Try a machine-dependent way of reloading an illegitimate address
- operand. If we find one, push the reload and return the new rtx. */
-
-rtx
-alpha_legitimize_reload_address (x, mode, opnum, type, ind_levels)
- rtx x;
- enum machine_mode mode ATTRIBUTE_UNUSED;
- int opnum;
- int type;
- int ind_levels ATTRIBUTE_UNUSED;
+/* Try to output insns to set TARGET equal to the constant C if it can be
+ done in less than N insns. Do all computations in MODE. Returns the place
+ where the output has been placed if it can be done and the insns have been
+ emitted. If it would take more than N insns, zero is returned and no
+ insns and emitted. */
+
+static rtx
+alpha_emit_set_const (rtx target, enum machine_mode mode,
+ HOST_WIDE_INT c, int n, bool no_output)
{
- /* We must recognize output that we have already generated ourselves. */
- if (GET_CODE (x) == PLUS
- && GET_CODE (XEXP (x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
- && GET_CODE (XEXP (x, 1)) == CONST_INT)
+ enum machine_mode orig_mode = mode;
+ rtx orig_target = target;
+ rtx result = 0;
+ int i;
+
+ /* If we can't make any pseudos, TARGET is an SImode hard register, we
+ can't load this constant in one insn, do this in DImode. */
+ if (!can_create_pseudo_p () && mode == SImode
+ && GET_CODE (target) == REG && REGNO (target) < FIRST_PSEUDO_REGISTER)
{
- push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
- BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
- opnum, type);
- return x;
+ result = alpha_emit_set_const_1 (target, mode, c, 1, no_output);
+ if (result)
+ return result;
+
+ target = no_output ? NULL : gen_lowpart (DImode, target);
+ mode = DImode;
+ }
+ else if (mode == V8QImode || mode == V4HImode || mode == V2SImode)
+ {
+ target = no_output ? NULL : gen_lowpart (DImode, target);
+ mode = DImode;
}
- /* We wish to handle large displacements off a base register by
- splitting the addend across an ldah and the mem insn. This
- cuts number of extra insns needed from 3 to 1. */
- if (GET_CODE (x) == PLUS
- && GET_CODE (XEXP (x, 0)) == REG
- && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
- && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x, 0)))
- && GET_CODE (XEXP (x, 1)) == CONST_INT)
+ /* Try 1 insn, then 2, then up to N. */
+ for (i = 1; i <= n; i++)
{
- HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
- HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
- HOST_WIDE_INT high
- = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
+ result = alpha_emit_set_const_1 (target, mode, c, i, no_output);
+ if (result)
+ {
+ rtx insn, set;
- /* Check for 32-bit overflow. */
- if (high + low != val)
- return NULL_RTX;
+ if (no_output)
+ return result;
- /* Reload the high part into a base reg; leave the low part
- in the mem directly. */
- x = gen_rtx_PLUS (GET_MODE (x),
- gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
- GEN_INT (high)),
- GEN_INT (low));
+ insn = get_last_insn ();
+ set = single_set (insn);
+ if (! CONSTANT_P (SET_SRC (set)))
+ set_unique_reg_note (get_last_insn (), REG_EQUAL, GEN_INT (c));
+ break;
+ }
+ }
- push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
- BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
- opnum, type);
- return x;
+ /* Allow for the case where we changed the mode of TARGET. */
+ if (result)
+ {
+ if (result == target)
+ result = orig_target;
+ else if (mode != orig_mode)
+ result = gen_lowpart (orig_mode, result);
}
- return NULL_RTX;
+ return result;
}
-\f
-/* REF is an alignable memory location. Place an aligned SImode
- reference into *PALIGNED_MEM and the number of bits to shift into
- *PBITNUM. SCRATCH is a free register for use in reloading out
- of range stack slots. */
-void
-get_aligned_mem (ref, paligned_mem, pbitnum)
- rtx ref;
- rtx *paligned_mem, *pbitnum;
+/* Having failed to find a 3 insn sequence in alpha_emit_set_const,
+ fall back to a straight forward decomposition. We do this to avoid
+ exponential run times encountered when looking for longer sequences
+ with alpha_emit_set_const. */
+
+static rtx
+alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
{
- rtx base;
- HOST_WIDE_INT offset = 0;
+ HOST_WIDE_INT d1, d2, d3, d4;
- if (GET_CODE (ref) != MEM)
- abort ();
+ /* Decompose the entire word */
+#if HOST_BITS_PER_WIDE_INT >= 64
+ gcc_assert (c2 == -(c1 < 0));
+ d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
+ c1 -= d1;
+ d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
+ c1 = (c1 - d2) >> 32;
+ d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
+ c1 -= d3;
+ d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
+ gcc_assert (c1 == d4);
+#else
+ d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
+ c1 -= d1;
+ d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
+ gcc_assert (c1 == d2);
+ c2 += (d2 < 0);
+ d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000;
+ c2 -= d3;
+ d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000;
+ gcc_assert (c2 == d4);
+#endif
- if (reload_in_progress
- && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
+ /* Construct the high word */
+ if (d4)
{
- base = find_replacement (&XEXP (ref, 0));
-
- if (! memory_address_p (GET_MODE (ref), base))
- abort ();
+ emit_move_insn (target, GEN_INT (d4));
+ if (d3)
+ emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d3)));
}
else
- {
- base = XEXP (ref, 0);
- }
+ emit_move_insn (target, GEN_INT (d3));
- if (GET_CODE (base) == PLUS)
- offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
+ /* Shift it into place */
+ emit_move_insn (target, gen_rtx_ASHIFT (DImode, target, GEN_INT (32)));
- *paligned_mem
- = widen_memory_access (ref, SImode, (offset & ~3) - offset);
+ /* Add in the low bits. */
+ if (d2)
+ emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d2)));
+ if (d1)
+ emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d1)));
- if (WORDS_BIG_ENDIAN)
- *pbitnum = GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref))
- + (offset & 3) * 8));
- else
- *pbitnum = GEN_INT ((offset & 3) * 8);
+ return target;
}
-/* Similar, but just get the address. Handle the two reload cases.
- Add EXTRA_OFFSET to the address we return. */
+/* Given an integral CONST_INT, CONST_DOUBLE, or CONST_VECTOR, return
+ the low 64 bits. */
-rtx
-get_unaligned_address (ref, extra_offset)
- rtx ref;
- int extra_offset;
+static void
+alpha_extract_integer (rtx x, HOST_WIDE_INT *p0, HOST_WIDE_INT *p1)
{
- rtx base;
- HOST_WIDE_INT offset = 0;
+ HOST_WIDE_INT i0, i1;
- if (GET_CODE (ref) != MEM)
- abort ();
+ if (GET_CODE (x) == CONST_VECTOR)
+ x = simplify_subreg (DImode, x, GET_MODE (x), 0);
- if (reload_in_progress
- && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
- {
- base = find_replacement (&XEXP (ref, 0));
- if (! memory_address_p (GET_MODE (ref), base))
- abort ();
+ if (GET_CODE (x) == CONST_INT)
+ {
+ i0 = INTVAL (x);
+ i1 = -(i0 < 0);
}
- else
+ else if (HOST_BITS_PER_WIDE_INT >= 64)
{
- base = XEXP (ref, 0);
+ i0 = CONST_DOUBLE_LOW (x);
+ i1 = -(i0 < 0);
}
-
- if (GET_CODE (base) == PLUS)
- offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
-
- return plus_constant (base, offset + extra_offset);
-}
-
-/* On the Alpha, all (non-symbolic) constants except zero go into
- a floating-point register via memory. Note that we cannot
- return anything that is not a subset of CLASS, and that some
- symbolic constants cannot be dropped to memory. */
-
-enum reg_class
-alpha_preferred_reload_class(x, class)
- rtx x;
- enum reg_class class;
-{
- /* Zero is present in any register class. */
- if (x == CONST0_RTX (GET_MODE (x)))
- return class;
-
- /* These sorts of constants we can easily drop to memory. */
- if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
+ else
{
- if (class == FLOAT_REGS)
- return NO_REGS;
- if (class == ALL_REGS)
- return GENERAL_REGS;
- return class;
+ i0 = CONST_DOUBLE_LOW (x);
+ i1 = CONST_DOUBLE_HIGH (x);
}
- /* All other kinds of constants should not (and in the case of HIGH
- cannot) be dropped to memory -- instead we use a GENERAL_REGS
- secondary reload. */
- if (CONSTANT_P (x))
- return (class == ALL_REGS ? GENERAL_REGS : class);
-
- return class;
+ *p0 = i0;
+ *p1 = i1;
}
-/* Loading and storing HImode or QImode values to and from memory
- usually requires a scratch register. The exceptions are loading
- QImode and HImode from an aligned address to a general register
- unless byte instructions are permitted.
+/* Implement LEGITIMATE_CONSTANT_P. This is all constants for which we
+ are willing to load the value into a register via a move pattern.
+ Normally this is all symbolic constants, integral constants that
+ take three or fewer instructions, and floating-point zero. */
- We also cannot load an unaligned address or a paradoxical SUBREG
- into an FP register.
-
- We also cannot do integral arithmetic into FP regs, as might result
- from register elimination into a DImode fp register. */
-
-enum reg_class
-secondary_reload_class (class, mode, x, in)
- enum reg_class class;
- enum machine_mode mode;
- rtx x;
- int in;
+bool
+alpha_legitimate_constant_p (rtx x)
{
- if ((mode == QImode || mode == HImode) && ! TARGET_BWX)
- {
- if (GET_CODE (x) == MEM
- || (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER)
- || (GET_CODE (x) == SUBREG
- && (GET_CODE (SUBREG_REG (x)) == MEM
- || (GET_CODE (SUBREG_REG (x)) == REG
- && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER))))
- {
- if (!in || !aligned_memory_operand(x, mode))
- return GENERAL_REGS;
- }
- }
+ enum machine_mode mode = GET_MODE (x);
+ HOST_WIDE_INT i0, i1;
- if (class == FLOAT_REGS)
+ switch (GET_CODE (x))
{
- if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
- return GENERAL_REGS;
-
- if (GET_CODE (x) == SUBREG
- && (GET_MODE_SIZE (GET_MODE (x))
- > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
- return GENERAL_REGS;
+ case LABEL_REF:
+ case HIGH:
+ return true;
- if (in && INTEGRAL_MODE_P (mode)
- && ! (memory_operand (x, mode) || x == const0_rtx))
- return GENERAL_REGS;
- }
+ case CONST:
+ if (GET_CODE (XEXP (x, 0)) == PLUS
+ && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
+ x = XEXP (XEXP (x, 0), 0);
+ else
+ return true;
- return NO_REGS;
-}
-\f
-/* Subfunction of the following function. Update the flags of any MEM
- found in part of X. */
+ if (GET_CODE (x) != SYMBOL_REF)
+ return true;
-static void
-alpha_set_memflags_1 (x, in_struct_p, volatile_p, unchanging_p)
- rtx x;
- int in_struct_p, volatile_p, unchanging_p;
-{
- int i;
+ /* FALLTHRU */
- switch (GET_CODE (x))
- {
- case SEQUENCE:
- case PARALLEL:
- for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
- alpha_set_memflags_1 (XVECEXP (x, 0, i), in_struct_p, volatile_p,
- unchanging_p);
- break;
+ case SYMBOL_REF:
+ /* TLS symbols are never valid. */
+ return SYMBOL_REF_TLS_MODEL (x) == 0;
- case INSN:
- alpha_set_memflags_1 (PATTERN (x), in_struct_p, volatile_p,
- unchanging_p);
- break;
+ case CONST_DOUBLE:
+ if (x == CONST0_RTX (mode))
+ return true;
+ if (FLOAT_MODE_P (mode))
+ return false;
+ goto do_integer;
- case SET:
- alpha_set_memflags_1 (SET_DEST (x), in_struct_p, volatile_p,
- unchanging_p);
- alpha_set_memflags_1 (SET_SRC (x), in_struct_p, volatile_p,
- unchanging_p);
- break;
+ case CONST_VECTOR:
+ if (x == CONST0_RTX (mode))
+ return true;
+ if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
+ return false;
+ if (GET_MODE_SIZE (mode) != 8)
+ return false;
+ goto do_integer;
- case MEM:
- MEM_IN_STRUCT_P (x) = in_struct_p;
- MEM_VOLATILE_P (x) = volatile_p;
- RTX_UNCHANGING_P (x) = unchanging_p;
- /* Sadly, we cannot use alias sets because the extra aliasing
- produced by the AND interferes. Given that two-byte quantities
- are the only thing we would be able to differentiate anyway,
- there does not seem to be any point in convoluting the early
- out of the alias check. */
- break;
+ case CONST_INT:
+ do_integer:
+ if (TARGET_BUILD_CONSTANTS)
+ return true;
+ alpha_extract_integer (x, &i0, &i1);
+ if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == (-i0 < 0))
+ return alpha_emit_set_const_1 (x, mode, i0, 3, true) != NULL;
+ return false;
default:
- break;
+ return false;
}
}
-/* Given INSN, which is either an INSN or a SEQUENCE generated to
- perform a memory operation, look for any MEMs in either a SET_DEST or
- a SET_SRC and copy the in-struct, unchanging, and volatile flags from
- REF into each of the MEMs found. If REF is not a MEM, don't do
- anything. */
+/* Operand 1 is known to be a constant, and should require more than one
+ instruction to load. Emit that multi-part load. */
-void
-alpha_set_memflags (insn, ref)
- rtx insn;
- rtx ref;
+bool
+alpha_split_const_mov (enum machine_mode mode, rtx *operands)
{
- int in_struct_p, volatile_p, unchanging_p;
+ HOST_WIDE_INT i0, i1;
+ rtx temp = NULL_RTX;
- if (GET_CODE (ref) != MEM)
- return;
+ alpha_extract_integer (operands[1], &i0, &i1);
- in_struct_p = MEM_IN_STRUCT_P (ref);
- volatile_p = MEM_VOLATILE_P (ref);
- unchanging_p = RTX_UNCHANGING_P (ref);
+ if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == -(i0 < 0))
+ temp = alpha_emit_set_const (operands[0], mode, i0, 3, false);
- /* This is only called from alpha.md, after having had something
- generated from one of the insn patterns. So if everything is
- zero, the pattern is already up-to-date. */
- if (! in_struct_p && ! volatile_p && ! unchanging_p)
- return;
+ if (!temp && TARGET_BUILD_CONSTANTS)
+ temp = alpha_emit_set_long_const (operands[0], i0, i1);
+
+ if (temp)
+ {
+ if (!rtx_equal_p (operands[0], temp))
+ emit_move_insn (operands[0], temp);
+ return true;
+ }
- alpha_set_memflags_1 (insn, in_struct_p, volatile_p, unchanging_p);
+ return false;
}
-\f
-/* Try to output insns to set TARGET equal to the constant C if it can be
- done in less than N insns. Do all computations in MODE. Returns the place
- where the output has been placed if it can be done and the insns have been
- emitted. If it would take more than N insns, zero is returned and no
- insns and emitted. */
-rtx
-alpha_emit_set_const (target, mode, c, n)
- rtx target;
- enum machine_mode mode;
- HOST_WIDE_INT c;
- int n;
+/* Expand a move instruction; return true if all work is done.
+ We don't handle non-bwx subword loads here. */
+
+bool
+alpha_expand_mov (enum machine_mode mode, rtx *operands)
{
- rtx result = 0;
- rtx orig_target = target;
- int i;
+ rtx tmp;
- /* If we can't make any pseudos, TARGET is an SImode hard register, we
- can't load this constant in one insn, do this in DImode. */
- if (no_new_pseudos && mode == SImode
- && GET_CODE (target) == REG && REGNO (target) < FIRST_PSEUDO_REGISTER
- && (result = alpha_emit_set_const_1 (target, mode, c, 1)) == 0)
- {
- target = gen_lowpart (DImode, target);
- mode = DImode;
- }
+ /* If the output is not a register, the input must be. */
+ if (GET_CODE (operands[0]) == MEM
+ && ! reg_or_0_operand (operands[1], mode))
+ operands[1] = force_reg (mode, operands[1]);
- /* Try 1 insn, then 2, then up to N. */
- for (i = 1; i <= n; i++)
+ /* Allow legitimize_address to perform some simplifications. */
+ if (mode == Pmode && symbolic_operand (operands[1], mode))
{
- result = alpha_emit_set_const_1 (target, mode, c, i);
- if (result)
+ tmp = alpha_legitimize_address (operands[1], operands[0], mode);
+ if (tmp)
{
- rtx insn = get_last_insn ();
- rtx set = single_set (insn);
- if (! CONSTANT_P (SET_SRC (set)))
- set_unique_reg_note (get_last_insn (), REG_EQUAL, GEN_INT (c));
- break;
+ if (tmp == operands[0])
+ return true;
+ operands[1] = tmp;
+ return false;
}
}
- /* Allow for the case where we changed the mode of TARGET. */
- if (result == target)
- result = orig_target;
+ /* Early out for non-constants and valid constants. */
+ if (! CONSTANT_P (operands[1]) || input_operand (operands[1], mode))
+ return false;
- return result;
+ /* Split large integers. */
+ if (GET_CODE (operands[1]) == CONST_INT
+ || GET_CODE (operands[1]) == CONST_DOUBLE
+ || GET_CODE (operands[1]) == CONST_VECTOR)
+ {
+ if (alpha_split_const_mov (mode, operands))
+ return true;
+ }
+
+ /* Otherwise we've nothing left but to drop the thing to memory. */
+ tmp = force_const_mem (mode, operands[1]);
+
+ if (tmp == NULL_RTX)
+ return false;
+
+ if (reload_in_progress)
+ {
+ emit_move_insn (operands[0], XEXP (tmp, 0));
+ operands[1] = replace_equiv_address (tmp, operands[0]);
+ }
+ else
+ operands[1] = validize_mem (tmp);
+ return false;
}
-/* Internal routine for the above to check for N or below insns. */
+/* Expand a non-bwx QImode or HImode move instruction;
+ return true if all work is done. */
-static rtx
-alpha_emit_set_const_1 (target, mode, c, n)
- rtx target;
- enum machine_mode mode;
- HOST_WIDE_INT c;
- int n;
+bool
+alpha_expand_mov_nobwx (enum machine_mode mode, rtx *operands)
{
- HOST_WIDE_INT new;
- int i, bits;
- /* Use a pseudo if highly optimizing and still generating RTL. */
- rtx subtarget
- = (flag_expensive_optimizations && !no_new_pseudos ? 0 : target);
- rtx temp, insn;
+ rtx seq;
- /* If this is a sign-extended 32-bit constant, we can do this in at most
- three insns, so do it if we have enough insns left. We always have
- a sign-extended 32-bit constant when compiling on a narrow machine. */
+ /* If the output is not a register, the input must be. */
+ if (MEM_P (operands[0]))
+ operands[1] = force_reg (mode, operands[1]);
- if (HOST_BITS_PER_WIDE_INT != 64
- || c >> 31 == -1 || c >> 31 == 0)
+ /* Handle four memory cases, unaligned and aligned for either the input
+ or the output. The only case where we can be called during reload is
+ for aligned loads; all other cases require temporaries. */
+
+ if (any_memory_operand (operands[1], mode))
{
- HOST_WIDE_INT low = ((c & 0xffff) ^ 0x8000) - 0x8000;
- HOST_WIDE_INT tmp1 = c - low;
- HOST_WIDE_INT high = (((tmp1 >> 16) & 0xffff) ^ 0x8000) - 0x8000;
- HOST_WIDE_INT extra = 0;
+ if (aligned_memory_operand (operands[1], mode))
+ {
+ if (reload_in_progress)
+ {
+ if (mode == QImode)
+ seq = gen_reload_inqi_aligned (operands[0], operands[1]);
+ else
+ seq = gen_reload_inhi_aligned (operands[0], operands[1]);
+ emit_insn (seq);
+ }
+ else
+ {
+ rtx aligned_mem, bitnum;
+ rtx scratch = gen_reg_rtx (SImode);
+ rtx subtarget;
+ bool copyout;
- /* If HIGH will be interpreted as negative but the constant is
- positive, we must adjust it to do two ldha insns. */
+ get_aligned_mem (operands[1], &aligned_mem, &bitnum);
- if ((high & 0x8000) != 0 && c >= 0)
- {
- extra = 0x4000;
- tmp1 -= 0x40000000;
- high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
- }
+ subtarget = operands[0];
+ if (GET_CODE (subtarget) == REG)
+ subtarget = gen_lowpart (DImode, subtarget), copyout = false;
+ else
+ subtarget = gen_reg_rtx (DImode), copyout = true;
- if (c == low || (low == 0 && extra == 0))
- {
- /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
- but that meant that we can't handle INT_MIN on 32-bit machines
- (like NT/Alpha), because we recurse indefinitely through
- emit_move_insn to gen_movdi. So instead, since we know exactly
- what we want, create it explicitly. */
+ if (mode == QImode)
+ seq = gen_aligned_loadqi (subtarget, aligned_mem,
+ bitnum, scratch);
+ else
+ seq = gen_aligned_loadhi (subtarget, aligned_mem,
+ bitnum, scratch);
+ emit_insn (seq);
- if (target == NULL)
- target = gen_reg_rtx (mode);
- emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (c)));
- return target;
+ if (copyout)
+ emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
+ }
}
- else if (n >= 2 + (extra != 0))
+ else
{
- temp = copy_to_suggested_reg (GEN_INT (high << 16), subtarget, mode);
+ /* Don't pass these as parameters since that makes the generated
+ code depend on parameter evaluation order which will cause
+ bootstrap failures. */
- /* As of 2002-02-23, addsi3 is only available when not optimizing.
- This means that if we go through expand_binop, we'll try to
- generate extensions, etc, which will require new pseudos, which
- will fail during some split phases. The SImode add patterns
- still exist, but are not named. So build the insns by hand. */
+ rtx temp1, temp2, subtarget, ua;
+ bool copyout;
- if (extra != 0)
- {
- if (! subtarget)
- subtarget = gen_reg_rtx (mode);
- insn = gen_rtx_PLUS (mode, temp, GEN_INT (extra << 16));
- insn = gen_rtx_SET (VOIDmode, subtarget, insn);
- emit_insn (insn);
- temp = subtarget;
- }
+ temp1 = gen_reg_rtx (DImode);
+ temp2 = gen_reg_rtx (DImode);
- if (target == NULL)
- target = gen_reg_rtx (mode);
- insn = gen_rtx_PLUS (mode, temp, GEN_INT (low));
- insn = gen_rtx_SET (VOIDmode, target, insn);
- emit_insn (insn);
- return target;
- }
- }
+ subtarget = operands[0];
+ if (GET_CODE (subtarget) == REG)
+ subtarget = gen_lowpart (DImode, subtarget), copyout = false;
+ else
+ subtarget = gen_reg_rtx (DImode), copyout = true;
- /* If we couldn't do it that way, try some other methods. But if we have
- no instructions left, don't bother. Likewise, if this is SImode and
- we can't make pseudos, we can't do anything since the expand_binop
- and expand_unop calls will widen and try to make pseudos. */
+ ua = get_unaligned_address (operands[1]);
+ if (mode == QImode)
+ seq = gen_unaligned_loadqi (subtarget, ua, temp1, temp2);
+ else
+ seq = gen_unaligned_loadhi (subtarget, ua, temp1, temp2);
- if (n == 1 || (mode == SImode && no_new_pseudos))
- return 0;
+ alpha_set_memflags (seq, operands[1]);
+ emit_insn (seq);
- /* Next, see if we can load a related constant and then shift and possibly
- negate it to get the constant we want. Try this once each increasing
- numbers of insns. */
-
- for (i = 1; i < n; i++)
- {
- /* First, see if minus some low bits, we've an easy load of
- high bits. */
-
- new = ((c & 0xffff) ^ 0x8000) - 0x8000;
- if (new != 0
- && (temp = alpha_emit_set_const (subtarget, mode, c - new, i)) != 0)
- return expand_binop (mode, add_optab, temp, GEN_INT (new),
- target, 0, OPTAB_WIDEN);
-
- /* Next try complementing. */
- if ((temp = alpha_emit_set_const (subtarget, mode, ~ c, i)) != 0)
- return expand_unop (mode, one_cmpl_optab, temp, target, 0);
-
- /* Next try to form a constant and do a left shift. We can do this
- if some low-order bits are zero; the exact_log2 call below tells
- us that information. The bits we are shifting out could be any
- value, but here we'll just try the 0- and sign-extended forms of
- the constant. To try to increase the chance of having the same
- constant in more than one insn, start at the highest number of
- bits to shift, but try all possibilities in case a ZAPNOT will
- be useful. */
-
- if ((bits = exact_log2 (c & - c)) > 0)
- for (; bits > 0; bits--)
- if ((temp = (alpha_emit_set_const
- (subtarget, mode, c >> bits, i))) != 0
- || ((temp = (alpha_emit_set_const
- (subtarget, mode,
- ((unsigned HOST_WIDE_INT) c) >> bits, i)))
- != 0))
- return expand_binop (mode, ashl_optab, temp, GEN_INT (bits),
- target, 0, OPTAB_WIDEN);
-
- /* Now try high-order zero bits. Here we try the shifted-in bits as
- all zero and all ones. Be careful to avoid shifting outside the
- mode and to avoid shifting outside the host wide int size. */
- /* On narrow hosts, don't shift a 1 into the high bit, since we'll
- confuse the recursive call and set all of the high 32 bits. */
-
- if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
- - floor_log2 (c) - 1 - (HOST_BITS_PER_WIDE_INT < 64))) > 0)
- for (; bits > 0; bits--)
- if ((temp = alpha_emit_set_const (subtarget, mode,
- c << bits, i)) != 0
- || ((temp = (alpha_emit_set_const
- (subtarget, mode,
- ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
- i)))
- != 0))
- return expand_binop (mode, lshr_optab, temp, GEN_INT (bits),
- target, 1, OPTAB_WIDEN);
-
- /* Now try high-order 1 bits. We get that with a sign-extension.
- But one bit isn't enough here. Be careful to avoid shifting outside
- the mode and to avoid shifting outside the host wide int size. */
-
- if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
- - floor_log2 (~ c) - 2)) > 0)
- for (; bits > 0; bits--)
- if ((temp = alpha_emit_set_const (subtarget, mode,
- c << bits, i)) != 0
- || ((temp = (alpha_emit_set_const
- (subtarget, mode,
- ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
- i)))
- != 0))
- return expand_binop (mode, ashr_optab, temp, GEN_INT (bits),
- target, 0, OPTAB_WIDEN);
- }
-
-#if HOST_BITS_PER_WIDE_INT == 64
- /* Finally, see if can load a value into the target that is the same as the
- constant except that all bytes that are 0 are changed to be 0xff. If we
- can, then we can do a ZAPNOT to obtain the desired constant. */
-
- new = c;
- for (i = 0; i < 64; i += 8)
- if ((new & ((HOST_WIDE_INT) 0xff << i)) == 0)
- new |= (HOST_WIDE_INT) 0xff << i;
-
- /* We are only called for SImode and DImode. If this is SImode, ensure that
- we are sign extended to a full word. */
-
- if (mode == SImode)
- new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
-
- if (new != c && new != -1
- && (temp = alpha_emit_set_const (subtarget, mode, new, n - 1)) != 0)
- return expand_binop (mode, and_optab, temp, GEN_INT (c | ~ new),
- target, 0, OPTAB_WIDEN);
-#endif
-
- return 0;
-}
-
-/* Having failed to find a 3 insn sequence in alpha_emit_set_const,
- fall back to a straight forward decomposition. We do this to avoid
- exponential run times encountered when looking for longer sequences
- with alpha_emit_set_const. */
-
-rtx
-alpha_emit_set_long_const (target, c1, c2)
- rtx target;
- HOST_WIDE_INT c1, c2;
-{
- HOST_WIDE_INT d1, d2, d3, d4;
-
- /* Decompose the entire word */
-#if HOST_BITS_PER_WIDE_INT >= 64
- if (c2 != -(c1 < 0))
- abort ();
- d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
- c1 -= d1;
- d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
- c1 = (c1 - d2) >> 32;
- d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
- c1 -= d3;
- d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
- if (c1 != d4)
- abort ();
-#else
- d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
- c1 -= d1;
- d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
- if (c1 != d2)
- abort ();
- c2 += (d2 < 0);
- d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000;
- c2 -= d3;
- d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000;
- if (c2 != d4)
- abort ();
-#endif
-
- /* Construct the high word */
- if (d4)
- {
- emit_move_insn (target, GEN_INT (d4));
- if (d3)
- emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d3)));
- }
- else
- emit_move_insn (target, GEN_INT (d3));
-
- /* Shift it into place */
- emit_move_insn (target, gen_rtx_ASHIFT (DImode, target, GEN_INT (32)));
-
- /* Add in the low bits. */
- if (d2)
- emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d2)));
- if (d1)
- emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d1)));
-
- return target;
-}
-
-/* Expand a move instruction; return true if all work is done.
- We don't handle non-bwx subword loads here. */
-
-bool
-alpha_expand_mov (mode, operands)
- enum machine_mode mode;
- rtx *operands;
-{
- /* If the output is not a register, the input must be. */
- if (GET_CODE (operands[0]) == MEM
- && ! reg_or_0_operand (operands[1], mode))
- operands[1] = force_reg (mode, operands[1]);
-
- /* Allow legitimize_address to perform some simplifications. */
- if (mode == Pmode && symbolic_operand (operands[1], mode))
- {
- rtx tmp;
-
- /* With RTL inlining, at -O3, rtl is generated, stored, then actually
- compiled at the end of compilation. In the meantime, someone can
- re-encode-section-info on some symbol changing it e.g. from global
- to local-not-small. If this happens, we'd have emitted a plain
- load rather than a high+losum load and not recognize the insn.
-
- So if rtl inlining is in effect, we delay the global/not-global
- decision until rest_of_compilation by wrapping it in an
- UNSPEC_SYMBOL. */
- if (TARGET_EXPLICIT_RELOCS && flag_inline_functions
- && rtx_equal_function_value_matters
- && global_symbolic_operand (operands[1], mode))
- {
- emit_insn (gen_movdi_er_maybe_g (operands[0], operands[1]));
- return true;
- }
-
- tmp = alpha_legitimize_address (operands[1], operands[0], mode);
- if (tmp)
- {
- operands[1] = tmp;
- return false;
- }
- }
-
- /* Early out for non-constants and valid constants. */
- if (! CONSTANT_P (operands[1]) || input_operand (operands[1], mode))
- return false;
-
- /* Split large integers. */
- if (GET_CODE (operands[1]) == CONST_INT
- || GET_CODE (operands[1]) == CONST_DOUBLE)
- {
- HOST_WIDE_INT i0, i1;
- rtx temp = NULL_RTX;
-
- if (GET_CODE (operands[1]) == CONST_INT)
- {
- i0 = INTVAL (operands[1]);
- i1 = -(i0 < 0);
- }
- else if (HOST_BITS_PER_WIDE_INT >= 64)
- {
- i0 = CONST_DOUBLE_LOW (operands[1]);
- i1 = -(i0 < 0);
- }
- else
- {
- i0 = CONST_DOUBLE_LOW (operands[1]);
- i1 = CONST_DOUBLE_HIGH (operands[1]);
- }
-
- if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == -(i0 < 0))
- temp = alpha_emit_set_const (operands[0], mode, i0, 3);
-
- if (!temp && TARGET_BUILD_CONSTANTS)
- temp = alpha_emit_set_long_const (operands[0], i0, i1);
-
- if (temp)
- {
- if (rtx_equal_p (operands[0], temp))
- return true;
- operands[1] = temp;
- return false;
- }
- }
-
- /* Otherwise we've nothing left but to drop the thing to memory. */
- operands[1] = force_const_mem (DImode, operands[1]);
- if (reload_in_progress)
- {
- emit_move_insn (operands[0], XEXP (operands[1], 0));
- operands[1] = copy_rtx (operands[1]);
- XEXP (operands[1], 0) = operands[0];
- }
- else
- operands[1] = validize_mem (operands[1]);
- return false;
-}
-
-/* Expand a non-bwx QImode or HImode move instruction;
- return true if all work is done. */
-
-bool
-alpha_expand_mov_nobwx (mode, operands)
- enum machine_mode mode;
- rtx *operands;
-{
- /* If the output is not a register, the input must be. */
- if (GET_CODE (operands[0]) == MEM)
- operands[1] = force_reg (mode, operands[1]);
-
- /* Handle four memory cases, unaligned and aligned for either the input
- or the output. The only case where we can be called during reload is
- for aligned loads; all other cases require temporaries. */
-
- if (GET_CODE (operands[1]) == MEM
- || (GET_CODE (operands[1]) == SUBREG
- && GET_CODE (SUBREG_REG (operands[1])) == MEM)
- || (reload_in_progress && GET_CODE (operands[1]) == REG
- && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
- || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
- && GET_CODE (SUBREG_REG (operands[1])) == REG
- && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
- {
- if (aligned_memory_operand (operands[1], mode))
- {
- if (reload_in_progress)
- {
- emit_insn ((mode == QImode
- ? gen_reload_inqi_help
- : gen_reload_inhi_help)
- (operands[0], operands[1],
- gen_rtx_REG (SImode, REGNO (operands[0]))));
- }
- else
- {
- rtx aligned_mem, bitnum;
- rtx scratch = gen_reg_rtx (SImode);
-
- get_aligned_mem (operands[1], &aligned_mem, &bitnum);
-
- emit_insn ((mode == QImode
- ? gen_aligned_loadqi
- : gen_aligned_loadhi)
- (operands[0], aligned_mem, bitnum, scratch));
- }
- }
- else
- {
- /* Don't pass these as parameters since that makes the generated
- code depend on parameter evaluation order which will cause
- bootstrap failures. */
-
- rtx temp1 = gen_reg_rtx (DImode);
- rtx temp2 = gen_reg_rtx (DImode);
- rtx seq = ((mode == QImode
- ? gen_unaligned_loadqi
- : gen_unaligned_loadhi)
- (operands[0], get_unaligned_address (operands[1], 0),
- temp1, temp2));
-
- alpha_set_memflags (seq, operands[1]);
- emit_insn (seq);
+ if (copyout)
+ emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
}
return true;
}
- if (GET_CODE (operands[0]) == MEM
- || (GET_CODE (operands[0]) == SUBREG
- && GET_CODE (SUBREG_REG (operands[0])) == MEM)
- || (reload_in_progress && GET_CODE (operands[0]) == REG
- && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
- || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
- && GET_CODE (SUBREG_REG (operands[0])) == REG
- && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
+ if (any_memory_operand (operands[0], mode))
{
if (aligned_memory_operand (operands[0], mode))
{
rtx temp1 = gen_reg_rtx (DImode);
rtx temp2 = gen_reg_rtx (DImode);
rtx temp3 = gen_reg_rtx (DImode);
- rtx seq = ((mode == QImode
- ? gen_unaligned_storeqi
- : gen_unaligned_storehi)
- (get_unaligned_address (operands[0], 0),
- operands[1], temp1, temp2, temp3));
+ rtx ua = get_unaligned_address (operands[0]);
+
+ if (mode == QImode)
+ seq = gen_unaligned_storeqi (ua, operands[1], temp1, temp2, temp3);
+ else
+ seq = gen_unaligned_storehi (ua, operands[1], temp1, temp2, temp3);
alpha_set_memflags (seq, operands[0]);
emit_insn (seq);
return false;
}
+/* Implement the movmisalign patterns. One of the operands is a memory
+ that is not naturally aligned. Emit instructions to load it. */
+
+void
+alpha_expand_movmisalign (enum machine_mode mode, rtx *operands)
+{
+ /* Honor misaligned loads, for those we promised to do so. */
+ if (MEM_P (operands[1]))
+ {
+ rtx tmp;
+
+ if (register_operand (operands[0], mode))
+ tmp = operands[0];
+ else
+ tmp = gen_reg_rtx (mode);
+
+ alpha_expand_unaligned_load (tmp, operands[1], 8, 0, 0);
+ if (tmp != operands[0])
+ emit_move_insn (operands[0], tmp);
+ }
+ else if (MEM_P (operands[0]))
+ {
+ if (!reg_or_0_operand (operands[1], mode))
+ operands[1] = force_reg (mode, operands[1]);
+ alpha_expand_unaligned_store (operands[0], operands[1], 8, 0);
+ }
+ else
+ gcc_unreachable ();
+}
+
/* Generate an unsigned DImode to FP conversion. This is the same code
optabs would emit if we didn't have TFmode patterns.
much lower minimum execution time. */
void
-alpha_emit_floatuns (operands)
- rtx operands[2];
+alpha_emit_floatuns (rtx operands[2])
{
rtx neglab, donelab, i0, i1, f0, in, out;
enum machine_mode mode;
/* Generate the comparison for a conditional branch. */
rtx
-alpha_emit_conditional_branch (code)
- enum rtx_code code;
+alpha_emit_conditional_branch (enum rtx_code code)
{
enum rtx_code cmp_code, branch_code;
enum machine_mode cmp_mode, branch_mode = VOIDmode;
if (alpha_compare.fp_p && GET_MODE (op0) == TFmode)
{
- if (! TARGET_HAS_XFLOATING_LIBS)
- abort ();
-
- /* X_floating library comparison functions return
- -1 unordered
- 0 false
- 1 true
- Convert the compare against the raw return value. */
-
- switch (code)
- {
- case UNORDERED:
- cmp_code = EQ;
- code = LT;
- break;
- case ORDERED:
- cmp_code = EQ;
- code = GE;
- break;
- case NE:
- cmp_code = NE;
- code = NE;
- break;
- default:
- cmp_code = code;
- code = GT;
- break;
- }
-
- op0 = alpha_emit_xfloating_compare (cmp_code, op0, op1);
+ op0 = alpha_emit_xfloating_compare (&code, op0, op1);
op1 = const0_rtx;
alpha_compare.fp_p = 0;
}
break;
default:
- abort ();
+ gcc_unreachable ();
}
if (alpha_compare.fp_p)
{
cmp_mode = DFmode;
- if (flag_unsafe_math_optimizations)
+ if (flag_unsafe_math_optimizations && cmp_code != UNORDERED)
{
/* When we are not as concerned about non-finite values, and we
are comparing against zero, we can branch directly. */
if (op1 == CONST0_RTX (DFmode))
- cmp_code = NIL, branch_code = code;
+ cmp_code = UNKNOWN, branch_code = code;
else if (op0 == CONST0_RTX (DFmode))
{
/* Undo the swap we probably did just above. */
tem = op0, op0 = op1, op1 = tem;
branch_code = swap_condition (cmp_code);
- cmp_code = NIL;
+ cmp_code = UNKNOWN;
}
}
else
{
- /* ??? We mark the the branch mode to be CCmode to prevent the
- compare and branch from being combined, since the compare
+ /* ??? We mark the branch mode to be CCmode to prevent the
+ compare and branch from being combined, since the compare
insn follows IEEE rules that the branch does not. */
branch_mode = CCmode;
}
{
/* Whee. Compare and branch against 0 directly. */
if (op1 == const0_rtx)
- cmp_code = NIL, branch_code = code;
-
- /* We want to use cmpcc/bcc when we can, since there is a zero delay
- bypass between logicals and br/cmov on EV5. But we don't want to
- force valid immediate constants into registers needlessly. */
- else if (GET_CODE (op1) == CONST_INT)
+ cmp_code = UNKNOWN, branch_code = code;
+
+ /* If the constants doesn't fit into an immediate, but can
+ be generated by lda/ldah, we adjust the argument and
+ compare against zero, so we can use beq/bne directly. */
+ /* ??? Don't do this when comparing against symbols, otherwise
+ we'll reduce (&x == 0x1234) to (&x-0x1234 == 0), which will
+ be declared false out of hand (at least for non-weak). */
+ else if (GET_CODE (op1) == CONST_INT
+ && (code == EQ || code == NE)
+ && !(symbolic_operand (op0, VOIDmode)
+ || (GET_CODE (op0) == REG && REG_POINTER (op0))))
{
- HOST_WIDE_INT v = INTVAL (op1), n = -v;
+ rtx n_op1 = GEN_INT (-INTVAL (op1));
- if (! CONST_OK_FOR_LETTER_P (v, 'I')
- && (CONST_OK_FOR_LETTER_P (n, 'K')
- || CONST_OK_FOR_LETTER_P (n, 'L')))
- {
- cmp_code = PLUS, branch_code = code;
- op1 = GEN_INT (n);
- }
+ if (! satisfies_constraint_I (op1)
+ && (satisfies_constraint_K (n_op1)
+ || satisfies_constraint_L (n_op1)))
+ cmp_code = PLUS, branch_code = code, op1 = n_op1;
}
}
/* Emit an initial compare instruction, if necessary. */
tem = op0;
- if (cmp_code != NIL)
+ if (cmp_code != UNKNOWN)
{
tem = gen_reg_rtx (cmp_mode);
emit_move_insn (tem, gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1));
valid. Return the final comparison, or NULL if we can't work. */
rtx
-alpha_emit_setcc (code)
- enum rtx_code code;
+alpha_emit_setcc (enum rtx_code code)
{
enum rtx_code cmp_code;
rtx op0 = alpha_compare.op0, op1 = alpha_compare.op1;
if (fp_p && GET_MODE (op0) == TFmode)
{
- if (! TARGET_HAS_XFLOATING_LIBS)
- abort ();
-
- /* X_floating library comparison functions return
- -1 unordered
- 0 false
- 1 true
- Convert the compare against the raw return value. */
-
- if (code == UNORDERED || code == ORDERED)
- cmp_code = EQ;
- else
- cmp_code = code;
-
- op0 = alpha_emit_xfloating_compare (cmp_code, op0, op1);
+ op0 = alpha_emit_xfloating_compare (&code, op0, op1);
op1 = const0_rtx;
fp_p = 0;
-
- if (code == UNORDERED)
- code = LT;
- else if (code == ORDERED)
- code = GE;
- else
- code = GT;
}
if (fp_p && !TARGET_FIX)
/* The general case: fold the comparison code to the types of compares
that we have, choosing the branch as necessary. */
- cmp_code = NIL;
+ cmp_code = UNKNOWN;
switch (code)
{
case EQ: case LE: case LT: case LEU: case LTU:
break;
default:
- abort ();
+ gcc_unreachable ();
}
if (!fp_p)
}
/* Emit an initial compare instruction, if necessary. */
- if (cmp_code != NIL)
+ if (cmp_code != UNKNOWN)
{
enum machine_mode mode = fp_p ? DFmode : DImode;
/* Rewrite a comparison against zero CMP of the form
(CODE (cc0) (const_int 0)) so it can be written validly in
a conditional move (if_then_else CMP ...).
- If both of the operands that set cc0 are non-zero we must emit
+ If both of the operands that set cc0 are nonzero we must emit
an insn to perform the compare (it can't be done within
the conditional move). */
+
rtx
-alpha_emit_conditional_move (cmp, mode)
- rtx cmp;
- enum machine_mode mode;
+alpha_emit_conditional_move (rtx cmp, enum machine_mode mode)
{
enum rtx_code code = GET_CODE (cmp);
enum rtx_code cmov_code = NE;
/* If we have fp<->int register move instructions, do a cmov by
performing the comparison in fp registers, and move the
- zero/non-zero value to integer registers, where we can then
+ zero/nonzero value to integer registers, where we can then
use a normal cmov, or vice-versa. */
switch (code)
break;
default:
- abort ();
+ gcc_unreachable ();
}
tem = gen_reg_rtx (cmp_op_mode);
conditional move. Make sure we emit only comparisons we have;
swap or reverse as necessary. */
- if (no_new_pseudos)
+ if (!can_create_pseudo_p ())
return NULL_RTX;
switch (code)
break;
default:
- abort ();
+ gcc_unreachable ();
}
if (!fp_p)
cases we wouldn't have before cse. */
int
-alpha_split_conditional_move (code, dest, cond, t_rtx, f_rtx)
- enum rtx_code code;
- rtx dest, cond, t_rtx, f_rtx;
+alpha_split_conditional_move (enum rtx_code code, rtx dest, rtx cond,
+ rtx t_rtx, rtx f_rtx)
{
HOST_WIDE_INT t, f, diff;
enum machine_mode mode;
if (mode != DImode)
{
target = gen_lowpart (DImode, dest);
- if (! no_new_pseudos)
+ if (can_create_pseudo_p ())
subtarget = gen_reg_rtx (DImode);
else
subtarget = target;
be shared. */
if (f == 0 && exact_log2 (diff) > 0
- /* On EV6, we've got enough shifters to make non-arithmatic shifts
+ /* On EV6, we've got enough shifters to make non-arithmetic shifts
viable over a longer latency cmove. On EV5, the E0 slot is a
scarce resource, and on EV4 shift has the same latency as a cmove. */
- && (diff <= 8 || alpha_cpu == PROCESSOR_EV6))
+ && (diff <= 8 || alpha_tune == PROCESSOR_EV6))
{
tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
/* Look up the function X_floating library function name for the
given operation. */
-static const char *
-alpha_lookup_xfloating_lib_func (code)
- enum rtx_code code;
-{
- struct xfloating_op
- {
- const enum rtx_code code;
- const char *const func;
- };
-
- static const struct xfloating_op vms_xfloating_ops[] =
- {
- { PLUS, "OTS$ADD_X" },
- { MINUS, "OTS$SUB_X" },
- { MULT, "OTS$MUL_X" },
- { DIV, "OTS$DIV_X" },
- { EQ, "OTS$EQL_X" },
- { NE, "OTS$NEQ_X" },
- { LT, "OTS$LSS_X" },
- { LE, "OTS$LEQ_X" },
- { GT, "OTS$GTR_X" },
- { GE, "OTS$GEQ_X" },
- { FIX, "OTS$CVTXQ" },
- { FLOAT, "OTS$CVTQX" },
- { UNSIGNED_FLOAT, "OTS$CVTQUX" },
- { FLOAT_EXTEND, "OTS$CVT_FLOAT_T_X" },
- { FLOAT_TRUNCATE, "OTS$CVT_FLOAT_X_T" },
- };
-
- static const struct xfloating_op osf_xfloating_ops[] =
- {
- { PLUS, "_OtsAddX" },
- { MINUS, "_OtsSubX" },
- { MULT, "_OtsMulX" },
- { DIV, "_OtsDivX" },
- { EQ, "_OtsEqlX" },
- { NE, "_OtsNeqX" },
- { LT, "_OtsLssX" },
- { LE, "_OtsLeqX" },
- { GT, "_OtsGtrX" },
- { GE, "_OtsGeqX" },
- { FIX, "_OtsCvtXQ" },
- { FLOAT, "_OtsCvtQX" },
- { UNSIGNED_FLOAT, "_OtsCvtQUX" },
- { FLOAT_EXTEND, "_OtsConvertFloatTX" },
- { FLOAT_TRUNCATE, "_OtsConvertFloatXT" },
- };
-
- const struct xfloating_op *ops;
- const long n = ARRAY_SIZE (osf_xfloating_ops);
- long i;
+struct xfloating_op GTY(())
+{
+ const enum rtx_code code;
+ const char *const GTY((skip)) osf_func;
+ const char *const GTY((skip)) vms_func;
+ rtx libcall;
+};
- /* How irritating. Nothing to key off for the table. Hardcode
- knowledge of the G_floating routines. */
- if (TARGET_FLOAT_VAX)
- {
- if (TARGET_ABI_OPEN_VMS)
- {
- if (code == FLOAT_EXTEND)
- return "OTS$CVT_FLOAT_G_X";
- if (code == FLOAT_TRUNCATE)
- return "OTS$CVT_FLOAT_X_G";
- }
- else
- {
- if (code == FLOAT_EXTEND)
- return "_OtsConvertFloatGX";
- if (code == FLOAT_TRUNCATE)
- return "_OtsConvertFloatXG";
- }
- }
+static GTY(()) struct xfloating_op xfloating_ops[] =
+{
+ { PLUS, "_OtsAddX", "OTS$ADD_X", 0 },
+ { MINUS, "_OtsSubX", "OTS$SUB_X", 0 },
+ { MULT, "_OtsMulX", "OTS$MUL_X", 0 },
+ { DIV, "_OtsDivX", "OTS$DIV_X", 0 },
+ { EQ, "_OtsEqlX", "OTS$EQL_X", 0 },
+ { NE, "_OtsNeqX", "OTS$NEQ_X", 0 },
+ { LT, "_OtsLssX", "OTS$LSS_X", 0 },
+ { LE, "_OtsLeqX", "OTS$LEQ_X", 0 },
+ { GT, "_OtsGtrX", "OTS$GTR_X", 0 },
+ { GE, "_OtsGeqX", "OTS$GEQ_X", 0 },
+ { FIX, "_OtsCvtXQ", "OTS$CVTXQ", 0 },
+ { FLOAT, "_OtsCvtQX", "OTS$CVTQX", 0 },
+ { UNSIGNED_FLOAT, "_OtsCvtQUX", "OTS$CVTQUX", 0 },
+ { FLOAT_EXTEND, "_OtsConvertFloatTX", "OTS$CVT_FLOAT_T_X", 0 },
+ { FLOAT_TRUNCATE, "_OtsConvertFloatXT", "OTS$CVT_FLOAT_X_T", 0 }
+};
- if (TARGET_ABI_OPEN_VMS)
- ops = vms_xfloating_ops;
- else
- ops = osf_xfloating_ops;
+static GTY(()) struct xfloating_op vax_cvt_ops[] =
+{
+ { FLOAT_EXTEND, "_OtsConvertFloatGX", "OTS$CVT_FLOAT_G_X", 0 },
+ { FLOAT_TRUNCATE, "_OtsConvertFloatXG", "OTS$CVT_FLOAT_X_G", 0 }
+};
+
+static rtx
+alpha_lookup_xfloating_lib_func (enum rtx_code code)
+{
+ struct xfloating_op *ops = xfloating_ops;
+ long n = ARRAY_SIZE (xfloating_ops);
+ long i;
+
+ gcc_assert (TARGET_HAS_XFLOATING_LIBS);
+
+ /* How irritating. Nothing to key off for the main table. */
+ if (TARGET_FLOAT_VAX && (code == FLOAT_EXTEND || code == FLOAT_TRUNCATE))
+ {
+ ops = vax_cvt_ops;
+ n = ARRAY_SIZE (vax_cvt_ops);
+ }
- for (i = 0; i < n; ++i)
- if (ops[i].code == code)
- return ops[i].func;
+ for (i = 0; i < n; ++i, ++ops)
+ if (ops->code == code)
+ {
+ rtx func = ops->libcall;
+ if (!func)
+ {
+ func = init_one_libfunc (TARGET_ABI_OPEN_VMS
+ ? ops->vms_func : ops->osf_func);
+ ops->libcall = func;
+ }
+ return func;
+ }
- abort();
+ gcc_unreachable ();
}
/* Most X_floating operations take the rounding mode as an argument.
Compute that here. */
static int
-alpha_compute_xfloating_mode_arg (code, round)
- enum rtx_code code;
- enum alpha_fp_rounding_mode round;
+alpha_compute_xfloating_mode_arg (enum rtx_code code,
+ enum alpha_fp_rounding_mode round)
{
int mode;
mode = 4;
break;
default:
- abort ();
+ gcc_unreachable ();
/* XXX For reference, round to +inf is mode = 3. */
}
Note that these functions do not follow normal calling conventions:
TFmode arguments are passed in two integer registers (as opposed to
- indirect); TFmode return values appear in R16+R17.
+ indirect); TFmode return values appear in R16+R17.
- FUNC is the function name to call.
+ FUNC is the function to call.
TARGET is where the output belongs.
OPERANDS are the inputs.
NOPERANDS is the count of inputs.
*/
static void
-alpha_emit_xfloating_libcall (func, target, operands, noperands, equiv)
- const char *func;
- rtx target;
- rtx operands[];
- int noperands;
- rtx equiv;
+alpha_emit_xfloating_libcall (rtx func, rtx target, rtx operands[],
+ int noperands, rtx equiv)
{
rtx usage = NULL_RTX, tmp, reg;
int regno = 16, i;
break;
case VOIDmode:
- if (GET_CODE (operands[i]) != CONST_INT)
- abort ();
+ gcc_assert (GET_CODE (operands[i]) == CONST_INT);
/* FALLTHRU */
case DImode:
reg = gen_rtx_REG (DImode, regno);
break;
default:
- abort ();
+ gcc_unreachable ();
}
emit_move_insn (reg, operands[i]);
reg = gen_rtx_REG (DImode, 0);
break;
default:
- abort ();
+ gcc_unreachable ();
}
- tmp = gen_rtx_MEM (QImode, gen_rtx_SYMBOL_REF (Pmode, (char *) func));
+ tmp = gen_rtx_MEM (QImode, func);
tmp = emit_call_insn (GEN_CALL_VALUE (reg, tmp, const0_rtx,
const0_rtx, const0_rtx));
CALL_INSN_FUNCTION_USAGE (tmp) = usage;
+ RTL_CONST_CALL_P (tmp) = 1;
tmp = get_insns ();
end_sequence ();
/* Emit an X_floating library function call for arithmetic (+,-,*,/). */
void
-alpha_emit_xfloating_arith (code, operands)
- enum rtx_code code;
- rtx operands[];
+alpha_emit_xfloating_arith (enum rtx_code code, rtx operands[])
{
- const char *func;
+ rtx func;
int mode;
rtx out_operands[3];
out_operands[0] = operands[1];
out_operands[1] = operands[2];
out_operands[2] = GEN_INT (mode);
- alpha_emit_xfloating_libcall (func, operands[0], out_operands, 3,
+ alpha_emit_xfloating_libcall (func, operands[0], out_operands, 3,
gen_rtx_fmt_ee (code, TFmode, operands[1],
operands[2]));
}
/* Emit an X_floating library function call for a comparison. */
static rtx
-alpha_emit_xfloating_compare (code, op0, op1)
- enum rtx_code code;
- rtx op0, op1;
+alpha_emit_xfloating_compare (enum rtx_code *pcode, rtx op0, rtx op1)
{
- const char *func;
- rtx out, operands[2];
+ enum rtx_code cmp_code, res_code;
+ rtx func, out, operands[2], note;
- func = alpha_lookup_xfloating_lib_func (code);
+ /* X_floating library comparison functions return
+ -1 unordered
+ 0 false
+ 1 true
+ Convert the compare against the raw return value. */
+
+ cmp_code = *pcode;
+ switch (cmp_code)
+ {
+ case UNORDERED:
+ cmp_code = EQ;
+ res_code = LT;
+ break;
+ case ORDERED:
+ cmp_code = EQ;
+ res_code = GE;
+ break;
+ case NE:
+ res_code = NE;
+ break;
+ case EQ:
+ case LT:
+ case GT:
+ case LE:
+ case GE:
+ res_code = GT;
+ break;
+ default:
+ gcc_unreachable ();
+ }
+ *pcode = res_code;
+
+ func = alpha_lookup_xfloating_lib_func (cmp_code);
operands[0] = op0;
operands[1] = op1;
out = gen_reg_rtx (DImode);
- /* ??? Strange mode for equiv because what's actually returned
- is -1,0,1, not a proper boolean value. */
- alpha_emit_xfloating_libcall (func, out, operands, 2,
- gen_rtx_fmt_ee (code, CCmode, op0, op1));
+ /* What's actually returned is -1,0,1, not a proper boolean value,
+ so use an EXPR_LIST as with a generic libcall instead of a
+ comparison type expression. */
+ note = gen_rtx_EXPR_LIST (VOIDmode, op1, NULL_RTX);
+ note = gen_rtx_EXPR_LIST (VOIDmode, op0, note);
+ note = gen_rtx_EXPR_LIST (VOIDmode, func, note);
+ alpha_emit_xfloating_libcall (func, out, operands, 2, note);
return out;
}
/* Emit an X_floating library function call for a conversion. */
void
-alpha_emit_xfloating_cvt (code, operands)
- enum rtx_code code;
- rtx operands[];
+alpha_emit_xfloating_cvt (enum rtx_code orig_code, rtx operands[])
{
int noperands = 1, mode;
rtx out_operands[2];
- const char *func;
+ rtx func;
+ enum rtx_code code = orig_code;
+
+ if (code == UNSIGNED_FIX)
+ code = FIX;
func = alpha_lookup_xfloating_lib_func (code);
}
alpha_emit_xfloating_libcall (func, operands[0], out_operands, noperands,
- gen_rtx_fmt_e (code, GET_MODE (operands[0]),
+ gen_rtx_fmt_e (orig_code,
+ GET_MODE (operands[0]),
operands[1]));
}
-/* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
- OP[0] into OP[0,1]. Naturally, output operand ordering is
- little-endian. */
-
+/* Split a TImode or TFmode move from OP[1] to OP[0] into a pair of
+ DImode moves from OP[2,3] to OP[0,1]. If FIXUP_OVERLAP is true,
+ guarantee that the sequence
+ set (OP[0] OP[2])
+ set (OP[1] OP[3])
+ is valid. Naturally, output operand ordering is little-endian.
+ This is used by *movtf_internal and *movti_internal. */
+
void
-alpha_split_tfmode_pair (operands)
- rtx operands[4];
+alpha_split_tmode_pair (rtx operands[4], enum machine_mode mode,
+ bool fixup_overlap)
{
- if (GET_CODE (operands[1]) == REG)
+ switch (GET_CODE (operands[1]))
{
+ case REG:
operands[3] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
operands[2] = gen_rtx_REG (DImode, REGNO (operands[1]));
- }
- else if (GET_CODE (operands[1]) == MEM)
- {
+ break;
+
+ case MEM:
operands[3] = adjust_address (operands[1], DImode, 8);
operands[2] = adjust_address (operands[1], DImode, 0);
+ break;
+
+ case CONST_INT:
+ case CONST_DOUBLE:
+ gcc_assert (operands[1] == CONST0_RTX (mode));
+ operands[2] = operands[3] = const0_rtx;
+ break;
+
+ default:
+ gcc_unreachable ();
}
- else if (operands[1] == CONST0_RTX (TFmode))
- operands[2] = operands[3] = const0_rtx;
- else
- abort ();
- if (GET_CODE (operands[0]) == REG)
+ switch (GET_CODE (operands[0]))
{
+ case REG:
operands[1] = gen_rtx_REG (DImode, REGNO (operands[0]) + 1);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
- }
- else if (GET_CODE (operands[0]) == MEM)
- {
+ break;
+
+ case MEM:
operands[1] = adjust_address (operands[0], DImode, 8);
operands[0] = adjust_address (operands[0], DImode, 0);
+ break;
+
+ default:
+ gcc_unreachable ();
+ }
+
+ if (fixup_overlap && reg_overlap_mentioned_p (operands[0], operands[3]))
+ {
+ rtx tmp;
+ tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
+ tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
}
- else
- abort ();
}
-/* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
- op2 is a register containing the sign bit, operation is the
+/* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
+ op2 is a register containing the sign bit, operation is the
logical operation to be performed. */
void
-alpha_split_tfmode_frobsign (operands, operation)
- rtx operands[3];
- rtx (*operation) PARAMS ((rtx, rtx, rtx));
+alpha_split_tfmode_frobsign (rtx operands[3], rtx (*operation) (rtx, rtx, rtx))
{
rtx high_bit = operands[2];
rtx scratch;
int move;
- alpha_split_tfmode_pair (operands);
+ alpha_split_tmode_pair (operands, TFmode, false);
- /* Detect three flavours of operand overlap. */
+ /* Detect three flavors of operand overlap. */
move = 1;
if (rtx_equal_p (operands[0], operands[2]))
move = 0;
*/
void
-alpha_expand_unaligned_load (tgt, mem, size, ofs, sign)
- rtx tgt, mem;
- HOST_WIDE_INT size, ofs;
- int sign;
+alpha_expand_unaligned_load (rtx tgt, rtx mem, HOST_WIDE_INT size,
+ HOST_WIDE_INT ofs, int sign)
{
rtx meml, memh, addr, extl, exth, tmp, mema;
enum machine_mode mode;
+ if (TARGET_BWX && size == 2)
+ {
+ meml = adjust_address (mem, QImode, ofs);
+ memh = adjust_address (mem, QImode, ofs+1);
+ if (BYTES_BIG_ENDIAN)
+ tmp = meml, meml = memh, memh = tmp;
+ extl = gen_reg_rtx (DImode);
+ exth = gen_reg_rtx (DImode);
+ emit_insn (gen_zero_extendqidi2 (extl, meml));
+ emit_insn (gen_zero_extendqidi2 (exth, memh));
+ exth = expand_simple_binop (DImode, ASHIFT, exth, GEN_INT (8),
+ NULL, 1, OPTAB_LIB_WIDEN);
+ addr = expand_simple_binop (DImode, IOR, extl, exth,
+ NULL, 1, OPTAB_LIB_WIDEN);
+
+ if (sign && GET_MODE (tgt) != HImode)
+ {
+ addr = gen_lowpart (HImode, addr);
+ emit_insn (gen_extend_insn (tgt, addr, GET_MODE (tgt), HImode, 0));
+ }
+ else
+ {
+ if (GET_MODE (tgt) != DImode)
+ addr = gen_lowpart (GET_MODE (tgt), addr);
+ emit_move_insn (tgt, addr);
+ }
+ return;
+ }
+
meml = gen_reg_rtx (DImode);
memh = gen_reg_rtx (DImode);
addr = gen_reg_rtx (DImode);
mema = force_reg (Pmode, mema);
/* AND addresses cannot be in any alias set, since they may implicitly
- alias surrounding code. Ideally we'd have some alias set that
+ alias surrounding code. Ideally we'd have some alias set that
covered all types except those with alignment 8 or higher. */
tmp = change_address (mem, DImode,
- gen_rtx_AND (DImode,
+ gen_rtx_AND (DImode,
plus_constant (mema, ofs),
GEN_INT (-8)));
set_mem_alias_set (tmp, 0);
emit_move_insn (meml, tmp);
tmp = change_address (mem, DImode,
- gen_rtx_AND (DImode,
+ gen_rtx_AND (DImode,
plus_constant (mema, ofs + size - 1),
GEN_INT (-8)));
set_mem_alias_set (tmp, 0);
/* We must use tgt here for the target. Alpha-vms port fails if we use
addr for the target, because addr is marked as a pointer and combine
- knows that pointers are always sign-extended 32 bit values. */
+ knows that pointers are always sign-extended 32-bit values. */
addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
- addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (48),
+ addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (48),
addr, 1, OPTAB_WIDEN);
}
else
break;
default:
- abort ();
+ gcc_unreachable ();
}
emit_insn (gen_extxl_be (exth, memh, GEN_INT (size*8), addr));
}
break;
default:
- abort();
+ gcc_unreachable ();
}
}
}
if (addr != tgt)
- emit_move_insn (tgt, gen_lowpart(GET_MODE (tgt), addr));
+ emit_move_insn (tgt, gen_lowpart (GET_MODE (tgt), addr));
}
/* Similarly, use ins and msk instructions to perform unaligned stores. */
void
-alpha_expand_unaligned_store (dst, src, size, ofs)
- rtx dst, src;
- HOST_WIDE_INT size, ofs;
+alpha_expand_unaligned_store (rtx dst, rtx src,
+ HOST_WIDE_INT size, HOST_WIDE_INT ofs)
{
rtx dstl, dsth, addr, insl, insh, meml, memh, dsta;
-
+
+ if (TARGET_BWX && size == 2)
+ {
+ if (src != const0_rtx)
+ {
+ dstl = gen_lowpart (QImode, src);
+ dsth = expand_simple_binop (DImode, LSHIFTRT, src, GEN_INT (8),
+ NULL, 1, OPTAB_LIB_WIDEN);
+ dsth = gen_lowpart (QImode, dsth);
+ }
+ else
+ dstl = dsth = const0_rtx;
+
+ meml = adjust_address (dst, QImode, ofs);
+ memh = adjust_address (dst, QImode, ofs+1);
+ if (BYTES_BIG_ENDIAN)
+ addr = meml, meml = memh, memh = addr;
+
+ emit_move_insn (meml, dstl);
+ emit_move_insn (memh, dsth);
+ return;
+ }
+
dstl = gen_reg_rtx (DImode);
dsth = gen_reg_rtx (DImode);
insl = gen_reg_rtx (DImode);
dsta = force_reg (Pmode, dsta);
/* AND addresses cannot be in any alias set, since they may implicitly
- alias surrounding code. Ideally we'd have some alias set that
+ alias surrounding code. Ideally we'd have some alias set that
covered all types except those with alignment 8 or higher. */
meml = change_address (dst, DImode,
- gen_rtx_AND (DImode,
+ gen_rtx_AND (DImode,
plus_constant (dsta, ofs),
GEN_INT (-8)));
set_mem_alias_set (meml, 0);
memh = change_address (dst, DImode,
- gen_rtx_AND (DImode,
+ gen_rtx_AND (DImode,
plus_constant (dsta, ofs + size - 1),
GEN_INT (-8)));
set_mem_alias_set (memh, 0);
emit_insn (gen_mskxl_be (dsth, dsth, GEN_INT (0xffff), addr));
break;
case 4:
- emit_insn (gen_mskxl_be (dsth, dsth, GEN_INT (0xffffffff), addr));
- break;
- case 8:
{
-#if HOST_BITS_PER_WIDE_INT == 32
- rtx msk = immed_double_const (0xffffffff, 0xffffffff, DImode);
-#else
- rtx msk = constm1_rtx;
-#endif
+ rtx msk = immed_double_const (0xffffffff, 0, DImode);
emit_insn (gen_mskxl_be (dsth, dsth, msk, addr));
+ break;
}
+ case 8:
+ emit_insn (gen_mskxl_be (dsth, dsth, constm1_rtx, addr));
break;
}
{
addr = copy_addr_to_reg (plus_constant (dsta, ofs));
- if (src != const0_rtx)
+ if (src != CONST0_RTX (GET_MODE (src)))
{
emit_insn (gen_insxh (insh, gen_lowpart (DImode, src),
GEN_INT (size*8), addr));
emit_insn (gen_insll_le (insl, gen_lowpart (SImode, src), addr));
break;
case 8:
- emit_insn (gen_insql_le (insl, src, addr));
+ emit_insn (gen_insql_le (insl, gen_lowpart (DImode, src), addr));
break;
}
}
emit_insn (gen_mskxl_le (dstl, dstl, GEN_INT (0xffff), addr));
break;
case 4:
- emit_insn (gen_mskxl_le (dstl, dstl, GEN_INT (0xffffffff), addr));
- break;
- case 8:
{
-#if HOST_BITS_PER_WIDE_INT == 32
- rtx msk = immed_double_const (0xffffffff, 0xffffffff, DImode);
-#else
- rtx msk = constm1_rtx;
-#endif
+ rtx msk = immed_double_const (0xffffffff, 0, DImode);
emit_insn (gen_mskxl_le (dstl, dstl, msk, addr));
+ break;
}
+ case 8:
+ emit_insn (gen_mskxl_le (dstl, dstl, constm1_rtx, addr));
break;
}
}
- if (src != const0_rtx)
+ if (src != CONST0_RTX (GET_MODE (src)))
{
dsth = expand_binop (DImode, ior_optab, insh, dsth, dsth, 0, OPTAB_WIDEN);
dstl = expand_binop (DImode, ior_optab, insl, dstl, dstl, 0, OPTAB_WIDEN);
}
-
+
if (WORDS_BIG_ENDIAN)
{
emit_move_insn (meml, dstl);
/* Load an integral number of consecutive unaligned quadwords. */
static void
-alpha_expand_unaligned_load_words (out_regs, smem, words, ofs)
- rtx *out_regs;
- rtx smem;
- HOST_WIDE_INT words, ofs;
+alpha_expand_unaligned_load_words (rtx *out_regs, rtx smem,
+ HOST_WIDE_INT words, HOST_WIDE_INT ofs)
{
rtx const im8 = GEN_INT (-8);
rtx const i64 = GEN_INT (64);
if (ofs != 0)
smem = adjust_address (smem, GET_MODE (smem), ofs);
-
+
/* Load up all of the source data. */
for (i = 0; i < words; ++i)
{
emit_move_insn (data_regs[words], tmp);
/* Extract the half-word fragments. Unfortunately DEC decided to make
- extxh with offset zero a noop instead of zeroing the register, so
+ extxh with offset zero a noop instead of zeroing the register, so
we must take care of that edge condition ourselves with cmov. */
sreg = copy_addr_to_reg (smema);
- areg = expand_binop (DImode, and_optab, sreg, GEN_INT (7), NULL,
+ areg = expand_binop (DImode, and_optab, sreg, GEN_INT (7), NULL,
1, OPTAB_WIDEN);
if (WORDS_BIG_ENDIAN)
emit_move_insn (sreg, plus_constant (sreg, 7));
may be NULL to store zeros. */
static void
-alpha_expand_unaligned_store_words (data_regs, dmem, words, ofs)
- rtx *data_regs;
- rtx dmem;
- HOST_WIDE_INT words, ofs;
+alpha_expand_unaligned_store_words (rtx *data_regs, rtx dmem,
+ HOST_WIDE_INT words, HOST_WIDE_INT ofs)
{
rtx const im8 = GEN_INT (-8);
rtx const i64 = GEN_INT (64);
-#if HOST_BITS_PER_WIDE_INT == 32
- rtx const im1 = immed_double_const (0xffffffff, 0xffffffff, DImode);
-#else
- rtx const im1 = constm1_rtx;
-#endif
rtx ins_tmps[MAX_MOVE_WORDS];
rtx st_tmp_1, st_tmp_2, dreg;
rtx st_addr_1, st_addr_2, dmema;
ins_tmps[i] = gen_reg_rtx(DImode);
st_tmp_1 = gen_reg_rtx(DImode);
st_tmp_2 = gen_reg_rtx(DImode);
-
+
if (ofs != 0)
dmem = adjust_address (dmem, GET_MODE (dmem), ofs);
/* Split and merge the ends with the destination data. */
if (WORDS_BIG_ENDIAN)
{
- emit_insn (gen_mskxl_be (st_tmp_2, st_tmp_2, im1, dreg));
+ emit_insn (gen_mskxl_be (st_tmp_2, st_tmp_2, constm1_rtx, dreg));
emit_insn (gen_mskxh (st_tmp_1, st_tmp_1, i64, dreg));
}
else
{
emit_insn (gen_mskxh (st_tmp_2, st_tmp_2, i64, dreg));
- emit_insn (gen_mskxl_le (st_tmp_1, st_tmp_1, im1, dreg));
+ emit_insn (gen_mskxl_le (st_tmp_1, st_tmp_1, constm1_rtx, dreg));
}
if (data_regs != NULL)
operands[3] is the alignment. */
int
-alpha_expand_block_move (operands)
- rtx operands[];
+alpha_expand_block_move (rtx operands[])
{
rtx bytes_rtx = operands[2];
rtx align_rtx = operands[3];
rtx data_regs[2 * MAX_MOVE_WORDS + 16];
rtx tmp;
unsigned int i, words, ofs, nregs = 0;
-
+
if (orig_bytes <= 0)
return 1;
else if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
src_align = 16;
}
}
-
+
tmp = XEXP (orig_dst, 0);
if (GET_CODE (tmp) == REG)
dst_align = MAX (dst_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
}
}
- /* Load the entire block into registers. */
- if (GET_CODE (XEXP (orig_src, 0)) == ADDRESSOF)
- {
- enum machine_mode mode;
-
- tmp = XEXP (XEXP (orig_src, 0), 0);
-
- /* Don't use the existing register if we're reading more than
- is held in the register. Nor if there is not a mode that
- handles the exact size. */
- mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 1);
- if (mode != BLKmode
- && GET_MODE_SIZE (GET_MODE (tmp)) >= bytes)
- {
- if (mode == TImode)
- {
- data_regs[nregs] = gen_lowpart (DImode, tmp);
- data_regs[nregs + 1] = gen_highpart (DImode, tmp);
- nregs += 2;
- }
- else
- data_regs[nregs++] = gen_lowpart (mode, tmp);
-
- goto src_done;
- }
-
- /* No appropriate mode; fall back on memory. */
- orig_src = replace_equiv_address (orig_src,
- copy_addr_to_reg (XEXP (orig_src, 0)));
- src_align = GET_MODE_BITSIZE (GET_MODE (tmp));
- }
-
ofs = 0;
if (src_align >= 64 && bytes >= 8)
{
ofs += 1;
}
- src_done:
-
- if (nregs > ARRAY_SIZE (data_regs))
- abort ();
+ gcc_assert (nregs <= ARRAY_SIZE (data_regs));
/* Now save it back out again. */
i = 0, ofs = 0;
- if (GET_CODE (XEXP (orig_dst, 0)) == ADDRESSOF)
- {
- enum machine_mode mode;
- tmp = XEXP (XEXP (orig_dst, 0), 0);
-
- mode = mode_for_size (orig_bytes * BITS_PER_UNIT, MODE_INT, 1);
- if (GET_MODE (tmp) == mode)
- {
- if (nregs == 1)
- {
- emit_move_insn (tmp, data_regs[0]);
- i = 1;
- goto dst_done;
- }
-
- else if (nregs == 2 && mode == TImode)
- {
- /* Undo the subregging done above when copying between
- two TImode registers. */
- if (GET_CODE (data_regs[0]) == SUBREG
- && GET_MODE (SUBREG_REG (data_regs[0])) == TImode)
- emit_move_insn (tmp, SUBREG_REG (data_regs[0]));
- else
- {
- rtx seq;
-
- start_sequence ();
- emit_move_insn (gen_lowpart (DImode, tmp), data_regs[0]);
- emit_move_insn (gen_highpart (DImode, tmp), data_regs[1]);
- seq = get_insns ();
- end_sequence ();
-
- emit_no_conflict_block (seq, tmp, data_regs[0],
- data_regs[1], NULL_RTX);
- }
-
- i = 2;
- goto dst_done;
- }
- }
-
- /* ??? If nregs > 1, consider reconstructing the word in regs. */
- /* ??? Optimize mode < dst_mode with strict_low_part. */
-
- /* No appropriate mode; fall back on memory. We can speed things
- up by recognizing extra alignment information. */
- orig_dst = replace_equiv_address (orig_dst,
- copy_addr_to_reg (XEXP (orig_dst, 0)));
- dst_align = GET_MODE_BITSIZE (GET_MODE (tmp));
- }
-
/* Write out the data in whatever chunks reading the source allowed. */
if (dst_align >= 64)
{
else
alpha_expand_unaligned_store_words (data_regs + i, orig_dst,
words, ofs);
-
+
i += words;
ofs += words * 8;
}
ofs += 2;
}
- while (i < nregs && GET_MODE (data_regs[i]) == QImode)
+ /* The remainder must be byte copies. */
+ while (i < nregs)
{
+ gcc_assert (GET_MODE (data_regs[i]) == QImode);
emit_move_insn (adjust_address (orig_dst, QImode, ofs), data_regs[i]);
i++;
ofs += 1;
}
- dst_done:
-
- if (i != nregs)
- abort ();
-
return 1;
}
int
-alpha_expand_block_clear (operands)
- rtx operands[];
+alpha_expand_block_clear (rtx operands[])
{
rtx bytes_rtx = operands[1];
- rtx align_rtx = operands[2];
+ rtx align_rtx = operands[3];
HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
HOST_WIDE_INT bytes = orig_bytes;
HOST_WIDE_INT align = INTVAL (align_rtx) * BITS_PER_UNIT;
rtx orig_dst = operands[0];
rtx tmp;
int i, words, ofs = 0;
-
+
if (orig_bytes <= 0)
return 1;
if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
align = a, alignofs = 2 - c % 2;
}
}
- else if (GET_CODE (tmp) == ADDRESSOF)
- {
- enum machine_mode mode;
-
- mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 1);
- if (GET_MODE (XEXP (tmp, 0)) == mode)
- {
- emit_move_insn (XEXP (tmp, 0), const0_rtx);
- return 1;
- }
-
- /* No appropriate mode; fall back on memory. */
- orig_dst = replace_equiv_address (orig_dst, copy_addr_to_reg (tmp));
- align = GET_MODE_BITSIZE (GET_MODE (XEXP (tmp, 0)));
- }
/* Handle an unaligned prefix first. */
we won't be able to. Downgrade align to match what's left over. */
if (alignofs > 0)
{
- alignofs = alignofs & -alignofs;
- align = MIN (align, alignofs * BITS_PER_UNIT);
+ alignofs = alignofs & -alignofs;
+ align = MIN (align, alignofs * BITS_PER_UNIT);
+ }
+ }
+
+ /* Handle a block of contiguous long-words. */
+
+ if (align >= 64 && bytes >= 8)
+ {
+ words = bytes / 8;
+
+ for (i = 0; i < words; ++i)
+ emit_move_insn (adjust_address (orig_dst, DImode, ofs + i * 8),
+ const0_rtx);
+
+ bytes -= words * 8;
+ ofs += words * 8;
+ }
+
+ /* If the block is large and appropriately aligned, emit a single
+ store followed by a sequence of stq_u insns. */
+
+ if (align >= 32 && bytes > 16)
+ {
+ rtx orig_dsta;
+
+ emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
+ bytes -= 4;
+ ofs += 4;
+
+ orig_dsta = XEXP (orig_dst, 0);
+ if (GET_CODE (orig_dsta) == LO_SUM)
+ orig_dsta = force_reg (Pmode, orig_dsta);
+
+ words = bytes / 8;
+ for (i = 0; i < words; ++i)
+ {
+ rtx mem
+ = change_address (orig_dst, DImode,
+ gen_rtx_AND (DImode,
+ plus_constant (orig_dsta, ofs + i*8),
+ GEN_INT (-8)));
+ set_mem_alias_set (mem, 0);
+ emit_move_insn (mem, const0_rtx);
+ }
+
+ /* Depending on the alignment, the first stq_u may have overlapped
+ with the initial stl, which means that the last stq_u didn't
+ write as much as it would appear. Leave those questionable bytes
+ unaccounted for. */
+ bytes -= words * 8 - 4;
+ ofs += words * 8 - 4;
+ }
+
+ /* Handle a smaller block of aligned words. */
+
+ if ((align >= 64 && bytes == 4)
+ || (align == 32 && bytes >= 4))
+ {
+ words = bytes / 4;
+
+ for (i = 0; i < words; ++i)
+ emit_move_insn (adjust_address (orig_dst, SImode, ofs + i * 4),
+ const0_rtx);
+
+ bytes -= words * 4;
+ ofs += words * 4;
+ }
+
+ /* An unaligned block uses stq_u stores for as many as possible. */
+
+ if (bytes >= 8)
+ {
+ words = bytes / 8;
+
+ alpha_expand_unaligned_store_words (NULL, orig_dst, words, ofs);
+
+ bytes -= words * 8;
+ ofs += words * 8;
+ }
+
+ /* Next clean up any trailing pieces. */
+
+#if HOST_BITS_PER_WIDE_INT >= 64
+ /* Count the number of bits in BYTES for which aligned stores could
+ be emitted. */
+ words = 0;
+ for (i = (TARGET_BWX ? 1 : 4); i * BITS_PER_UNIT <= align ; i <<= 1)
+ if (bytes & i)
+ words += 1;
+
+ /* If we have appropriate alignment (and it wouldn't take too many
+ instructions otherwise), mask out the bytes we need. */
+ if (TARGET_BWX ? words > 2 : bytes > 0)
+ {
+ if (align >= 64)
+ {
+ rtx mem, tmp;
+ HOST_WIDE_INT mask;
+
+ mem = adjust_address (orig_dst, DImode, ofs);
+ set_mem_alias_set (mem, 0);
+
+ mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
+
+ tmp = expand_binop (DImode, and_optab, mem, GEN_INT (mask),
+ NULL_RTX, 1, OPTAB_WIDEN);
+
+ emit_move_insn (mem, tmp);
+ return 1;
+ }
+ else if (align >= 32 && bytes < 4)
+ {
+ rtx mem, tmp;
+ HOST_WIDE_INT mask;
+
+ mem = adjust_address (orig_dst, SImode, ofs);
+ set_mem_alias_set (mem, 0);
+
+ mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
+
+ tmp = expand_binop (SImode, and_optab, mem, GEN_INT (mask),
+ NULL_RTX, 1, OPTAB_WIDEN);
+
+ emit_move_insn (mem, tmp);
+ return 1;
+ }
+ }
+#endif
+
+ if (!TARGET_BWX && bytes >= 4)
+ {
+ alpha_expand_unaligned_store (orig_dst, const0_rtx, 4, ofs);
+ bytes -= 4;
+ ofs += 4;
+ }
+
+ if (bytes >= 2)
+ {
+ if (align >= 16)
+ {
+ do {
+ emit_move_insn (adjust_address (orig_dst, HImode, ofs),
+ const0_rtx);
+ bytes -= 2;
+ ofs += 2;
+ } while (bytes >= 2);
+ }
+ else if (! TARGET_BWX)
+ {
+ alpha_expand_unaligned_store (orig_dst, const0_rtx, 2, ofs);
+ bytes -= 2;
+ ofs += 2;
+ }
+ }
+
+ while (bytes > 0)
+ {
+ emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
+ bytes -= 1;
+ ofs += 1;
+ }
+
+ return 1;
+}
+
+/* Returns a mask so that zap(x, value) == x & mask. */
+
+rtx
+alpha_expand_zap_mask (HOST_WIDE_INT value)
+{
+ rtx result;
+ int i;
+
+ if (HOST_BITS_PER_WIDE_INT >= 64)
+ {
+ HOST_WIDE_INT mask = 0;
+
+ for (i = 7; i >= 0; --i)
+ {
+ mask <<= 8;
+ if (!((value >> i) & 1))
+ mask |= 0xff;
+ }
+
+ result = gen_int_mode (mask, DImode);
+ }
+ else
+ {
+ HOST_WIDE_INT mask_lo = 0, mask_hi = 0;
+
+ gcc_assert (HOST_BITS_PER_WIDE_INT == 32);
+
+ for (i = 7; i >= 4; --i)
+ {
+ mask_hi <<= 8;
+ if (!((value >> i) & 1))
+ mask_hi |= 0xff;
+ }
+
+ for (i = 3; i >= 0; --i)
+ {
+ mask_lo <<= 8;
+ if (!((value >> i) & 1))
+ mask_lo |= 0xff;
+ }
+
+ result = immed_double_const (mask_lo, mask_hi, DImode);
+ }
+
+ return result;
+}
+
+void
+alpha_expand_builtin_vector_binop (rtx (*gen) (rtx, rtx, rtx),
+ enum machine_mode mode,
+ rtx op0, rtx op1, rtx op2)
+{
+ op0 = gen_lowpart (mode, op0);
+
+ if (op1 == const0_rtx)
+ op1 = CONST0_RTX (mode);
+ else
+ op1 = gen_lowpart (mode, op1);
+
+ if (op2 == const0_rtx)
+ op2 = CONST0_RTX (mode);
+ else
+ op2 = gen_lowpart (mode, op2);
+
+ emit_insn ((*gen) (op0, op1, op2));
+}
+
+/* A subroutine of the atomic operation splitters. Jump to LABEL if
+ COND is true. Mark the jump as unlikely to be taken. */
+
+static void
+emit_unlikely_jump (rtx cond, rtx label)
+{
+ rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
+ rtx x;
+
+ x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
+ x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
+ REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
+}
+
+/* A subroutine of the atomic operation splitters. Emit a load-locked
+ instruction in MODE. */
+
+static void
+emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
+{
+ rtx (*fn) (rtx, rtx) = NULL;
+ if (mode == SImode)
+ fn = gen_load_locked_si;
+ else if (mode == DImode)
+ fn = gen_load_locked_di;
+ emit_insn (fn (reg, mem));
+}
+
+/* A subroutine of the atomic operation splitters. Emit a store-conditional
+ instruction in MODE. */
+
+static void
+emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
+{
+ rtx (*fn) (rtx, rtx, rtx) = NULL;
+ if (mode == SImode)
+ fn = gen_store_conditional_si;
+ else if (mode == DImode)
+ fn = gen_store_conditional_di;
+ emit_insn (fn (res, mem, val));
+}
+
+/* A subroutine of the atomic operation splitters. Emit an insxl
+ instruction in MODE. */
+
+static rtx
+emit_insxl (enum machine_mode mode, rtx op1, rtx op2)
+{
+ rtx ret = gen_reg_rtx (DImode);
+ rtx (*fn) (rtx, rtx, rtx);
+
+ if (WORDS_BIG_ENDIAN)
+ {
+ if (mode == QImode)
+ fn = gen_insbl_be;
+ else
+ fn = gen_inswl_be;
+ }
+ else
+ {
+ if (mode == QImode)
+ fn = gen_insbl_le;
+ else
+ fn = gen_inswl_le;
+ }
+ /* The insbl and inswl patterns require a register operand. */
+ op1 = force_reg (mode, op1);
+ emit_insn (fn (ret, op1, op2));
+
+ return ret;
+}
+
+/* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
+ to perform. MEM is the memory on which to operate. VAL is the second
+ operand of the binary operator. BEFORE and AFTER are optional locations to
+ return the value of MEM either before of after the operation. SCRATCH is
+ a scratch register. */
+
+void
+alpha_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
+ rtx before, rtx after, rtx scratch)
+{
+ enum machine_mode mode = GET_MODE (mem);
+ rtx label, x, cond = gen_rtx_REG (DImode, REGNO (scratch));
+
+ emit_insn (gen_memory_barrier ());
+
+ label = gen_label_rtx ();
+ emit_label (label);
+ label = gen_rtx_LABEL_REF (DImode, label);
+
+ if (before == NULL)
+ before = scratch;
+ emit_load_locked (mode, before, mem);
+
+ if (code == NOT)
+ {
+ x = gen_rtx_AND (mode, before, val);
+ emit_insn (gen_rtx_SET (VOIDmode, val, x));
+
+ x = gen_rtx_NOT (mode, val);
+ }
+ else
+ x = gen_rtx_fmt_ee (code, mode, before, val);
+ if (after)
+ emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
+ emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
+
+ emit_store_conditional (mode, cond, mem, scratch);
+
+ x = gen_rtx_EQ (DImode, cond, const0_rtx);
+ emit_unlikely_jump (x, label);
+
+ emit_insn (gen_memory_barrier ());
+}
+
+/* Expand a compare and swap operation. */
+
+void
+alpha_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
+ rtx scratch)
+{
+ enum machine_mode mode = GET_MODE (mem);
+ rtx label1, label2, x, cond = gen_lowpart (DImode, scratch);
+
+ emit_insn (gen_memory_barrier ());
+
+ label1 = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
+ label2 = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
+ emit_label (XEXP (label1, 0));
+
+ emit_load_locked (mode, retval, mem);
+
+ x = gen_lowpart (DImode, retval);
+ if (oldval == const0_rtx)
+ x = gen_rtx_NE (DImode, x, const0_rtx);
+ else
+ {
+ x = gen_rtx_EQ (DImode, x, oldval);
+ emit_insn (gen_rtx_SET (VOIDmode, cond, x));
+ x = gen_rtx_EQ (DImode, cond, const0_rtx);
+ }
+ emit_unlikely_jump (x, label2);
+
+ emit_move_insn (scratch, newval);
+ emit_store_conditional (mode, cond, mem, scratch);
+
+ x = gen_rtx_EQ (DImode, cond, const0_rtx);
+ emit_unlikely_jump (x, label1);
+
+ emit_insn (gen_memory_barrier ());
+ emit_label (XEXP (label2, 0));
+}
+
+void
+alpha_expand_compare_and_swap_12 (rtx dst, rtx mem, rtx oldval, rtx newval)
+{
+ enum machine_mode mode = GET_MODE (mem);
+ rtx addr, align, wdst;
+ rtx (*fn5) (rtx, rtx, rtx, rtx, rtx);
+
+ addr = force_reg (DImode, XEXP (mem, 0));
+ align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-8),
+ NULL_RTX, 1, OPTAB_DIRECT);
+
+ oldval = convert_modes (DImode, mode, oldval, 1);
+ newval = emit_insxl (mode, newval, addr);
+
+ wdst = gen_reg_rtx (DImode);
+ if (mode == QImode)
+ fn5 = gen_sync_compare_and_swapqi_1;
+ else
+ fn5 = gen_sync_compare_and_swaphi_1;
+ emit_insn (fn5 (wdst, addr, oldval, newval, align));
+
+ emit_move_insn (dst, gen_lowpart (mode, wdst));
+}
+
+void
+alpha_split_compare_and_swap_12 (enum machine_mode mode, rtx dest, rtx addr,
+ rtx oldval, rtx newval, rtx align,
+ rtx scratch, rtx cond)
+{
+ rtx label1, label2, mem, width, mask, x;
+
+ mem = gen_rtx_MEM (DImode, align);
+ MEM_VOLATILE_P (mem) = 1;
+
+ emit_insn (gen_memory_barrier ());
+ label1 = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
+ label2 = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
+ emit_label (XEXP (label1, 0));
+
+ emit_load_locked (DImode, scratch, mem);
+
+ width = GEN_INT (GET_MODE_BITSIZE (mode));
+ mask = GEN_INT (mode == QImode ? 0xff : 0xffff);
+ if (WORDS_BIG_ENDIAN)
+ emit_insn (gen_extxl_be (dest, scratch, width, addr));
+ else
+ emit_insn (gen_extxl_le (dest, scratch, width, addr));
+
+ if (oldval == const0_rtx)
+ x = gen_rtx_NE (DImode, dest, const0_rtx);
+ else
+ {
+ x = gen_rtx_EQ (DImode, dest, oldval);
+ emit_insn (gen_rtx_SET (VOIDmode, cond, x));
+ x = gen_rtx_EQ (DImode, cond, const0_rtx);
+ }
+ emit_unlikely_jump (x, label2);
+
+ if (WORDS_BIG_ENDIAN)
+ emit_insn (gen_mskxl_be (scratch, scratch, mask, addr));
+ else
+ emit_insn (gen_mskxl_le (scratch, scratch, mask, addr));
+ emit_insn (gen_iordi3 (scratch, scratch, newval));
+
+ emit_store_conditional (DImode, scratch, mem, scratch);
+
+ x = gen_rtx_EQ (DImode, scratch, const0_rtx);
+ emit_unlikely_jump (x, label1);
+
+ emit_insn (gen_memory_barrier ());
+ emit_label (XEXP (label2, 0));
+}
+
+/* Expand an atomic exchange operation. */
+
+void
+alpha_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
+{
+ enum machine_mode mode = GET_MODE (mem);
+ rtx label, x, cond = gen_lowpart (DImode, scratch);
+
+ label = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
+ emit_label (XEXP (label, 0));
+
+ emit_load_locked (mode, retval, mem);
+ emit_move_insn (scratch, val);
+ emit_store_conditional (mode, cond, mem, scratch);
+
+ x = gen_rtx_EQ (DImode, cond, const0_rtx);
+ emit_unlikely_jump (x, label);
+
+ emit_insn (gen_memory_barrier ());
+}
+
+void
+alpha_expand_lock_test_and_set_12 (rtx dst, rtx mem, rtx val)
+{
+ enum machine_mode mode = GET_MODE (mem);
+ rtx addr, align, wdst;
+ rtx (*fn4) (rtx, rtx, rtx, rtx);
+
+ /* Force the address into a register. */
+ addr = force_reg (DImode, XEXP (mem, 0));
+
+ /* Align it to a multiple of 8. */
+ align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-8),
+ NULL_RTX, 1, OPTAB_DIRECT);
+
+ /* Insert val into the correct byte location within the word. */
+ val = emit_insxl (mode, val, addr);
+
+ wdst = gen_reg_rtx (DImode);
+ if (mode == QImode)
+ fn4 = gen_sync_lock_test_and_setqi_1;
+ else
+ fn4 = gen_sync_lock_test_and_sethi_1;
+ emit_insn (fn4 (wdst, addr, val, align));
+
+ emit_move_insn (dst, gen_lowpart (mode, wdst));
+}
+
+void
+alpha_split_lock_test_and_set_12 (enum machine_mode mode, rtx dest, rtx addr,
+ rtx val, rtx align, rtx scratch)
+{
+ rtx label, mem, width, mask, x;
+
+ mem = gen_rtx_MEM (DImode, align);
+ MEM_VOLATILE_P (mem) = 1;
+
+ label = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
+ emit_label (XEXP (label, 0));
+
+ emit_load_locked (DImode, scratch, mem);
+
+ width = GEN_INT (GET_MODE_BITSIZE (mode));
+ mask = GEN_INT (mode == QImode ? 0xff : 0xffff);
+ if (WORDS_BIG_ENDIAN)
+ {
+ emit_insn (gen_extxl_be (dest, scratch, width, addr));
+ emit_insn (gen_mskxl_be (scratch, scratch, mask, addr));
+ }
+ else
+ {
+ emit_insn (gen_extxl_le (dest, scratch, width, addr));
+ emit_insn (gen_mskxl_le (scratch, scratch, mask, addr));
+ }
+ emit_insn (gen_iordi3 (scratch, scratch, val));
+
+ emit_store_conditional (DImode, scratch, mem, scratch);
+
+ x = gen_rtx_EQ (DImode, scratch, const0_rtx);
+ emit_unlikely_jump (x, label);
+
+ emit_insn (gen_memory_barrier ());
+}
+\f
+/* Adjust the cost of a scheduling dependency. Return the new cost of
+ a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
+
+static int
+alpha_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
+{
+ enum attr_type insn_type, dep_insn_type;
+
+ /* If the dependence is an anti-dependence, there is no cost. For an
+ output dependence, there is sometimes a cost, but it doesn't seem
+ worth handling those few cases. */
+ if (REG_NOTE_KIND (link) != 0)
+ return cost;
+
+ /* If we can't recognize the insns, we can't really do anything. */
+ if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
+ return cost;
+
+ insn_type = get_attr_type (insn);
+ dep_insn_type = get_attr_type (dep_insn);
+
+ /* Bring in the user-defined memory latency. */
+ if (dep_insn_type == TYPE_ILD
+ || dep_insn_type == TYPE_FLD
+ || dep_insn_type == TYPE_LDSYM)
+ cost += alpha_memory_latency-1;
+
+ /* Everything else handled in DFA bypasses now. */
+
+ return cost;
+}
+
+/* The number of instructions that can be issued per cycle. */
+
+static int
+alpha_issue_rate (void)
+{
+ return (alpha_tune == PROCESSOR_EV4 ? 2 : 4);
+}
+
+/* How many alternative schedules to try. This should be as wide as the
+ scheduling freedom in the DFA, but no wider. Making this value too
+ large results extra work for the scheduler.
+
+ For EV4, loads can be issued to either IB0 or IB1, thus we have 2
+ alternative schedules. For EV5, we can choose between E0/E1 and
+ FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
+
+static int
+alpha_multipass_dfa_lookahead (void)
+{
+ return (alpha_tune == PROCESSOR_EV6 ? 4 : 2);
+}
+\f
+/* Machine-specific function data. */
+
+struct machine_function GTY(())
+{
+ /* For unicosmk. */
+ /* List of call information words for calls from this function. */
+ struct rtx_def *first_ciw;
+ struct rtx_def *last_ciw;
+ int ciw_count;
+
+ /* List of deferred case vectors. */
+ struct rtx_def *addr_list;
+
+ /* For OSF. */
+ const char *some_ld_name;
+
+ /* For TARGET_LD_BUGGY_LDGP. */
+ struct rtx_def *gp_save_rtx;
+};
+
+/* How to allocate a 'struct machine_function'. */
+
+static struct machine_function *
+alpha_init_machine_status (void)
+{
+ return ((struct machine_function *)
+ ggc_alloc_cleared (sizeof (struct machine_function)));
+}
+
+/* Functions to save and restore alpha_return_addr_rtx. */
+
+/* Start the ball rolling with RETURN_ADDR_RTX. */
+
+rtx
+alpha_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
+{
+ if (count != 0)
+ return const0_rtx;
+
+ return get_hard_reg_initial_val (Pmode, REG_RA);
+}
+
+/* Return or create a memory slot containing the gp value for the current
+ function. Needed only if TARGET_LD_BUGGY_LDGP. */
+
+rtx
+alpha_gp_save_rtx (void)
+{
+ rtx seq, m = cfun->machine->gp_save_rtx;
+
+ if (m == NULL)
+ {
+ start_sequence ();
+
+ m = assign_stack_local (DImode, UNITS_PER_WORD, BITS_PER_WORD);
+ m = validize_mem (m);
+ emit_move_insn (m, pic_offset_table_rtx);
+
+ seq = get_insns ();
+ end_sequence ();
+
+ /* We used to simply emit the sequence after entry_of_function.
+ However this breaks the CFG if the first instruction in the
+ first block is not the NOTE_INSN_BASIC_BLOCK, for example a
+ label. Emit the sequence properly on the edge. We are only
+ invoked from dw2_build_landing_pads and finish_eh_generation
+ will call commit_edge_insertions thanks to a kludge. */
+ insert_insn_on_edge (seq, single_succ_edge (ENTRY_BLOCK_PTR));
+
+ cfun->machine->gp_save_rtx = m;
+ }
+
+ return m;
+}
+
+static int
+alpha_ra_ever_killed (void)
+{
+ rtx top;
+
+ if (!has_hard_reg_initial_val (Pmode, REG_RA))
+ return (int)df_regs_ever_live_p (REG_RA);
+
+ push_topmost_sequence ();
+ top = get_insns ();
+ pop_topmost_sequence ();
+
+ return reg_set_between_p (gen_rtx_REG (Pmode, REG_RA), top, NULL_RTX);
+}
+
+\f
+/* Return the trap mode suffix applicable to the current
+ instruction, or NULL. */
+
+static const char *
+get_trap_mode_suffix (void)
+{
+ enum attr_trap_suffix s = get_attr_trap_suffix (current_output_insn);
+
+ switch (s)
+ {
+ case TRAP_SUFFIX_NONE:
+ return NULL;
+
+ case TRAP_SUFFIX_SU:
+ if (alpha_fptm >= ALPHA_FPTM_SU)
+ return "su";
+ return NULL;
+
+ case TRAP_SUFFIX_SUI:
+ if (alpha_fptm >= ALPHA_FPTM_SUI)
+ return "sui";
+ return NULL;
+
+ case TRAP_SUFFIX_V_SV:
+ switch (alpha_fptm)
+ {
+ case ALPHA_FPTM_N:
+ return NULL;
+ case ALPHA_FPTM_U:
+ return "v";
+ case ALPHA_FPTM_SU:
+ case ALPHA_FPTM_SUI:
+ return "sv";
+ default:
+ gcc_unreachable ();
+ }
+
+ case TRAP_SUFFIX_V_SV_SVI:
+ switch (alpha_fptm)
+ {
+ case ALPHA_FPTM_N:
+ return NULL;
+ case ALPHA_FPTM_U:
+ return "v";
+ case ALPHA_FPTM_SU:
+ return "sv";
+ case ALPHA_FPTM_SUI:
+ return "svi";
+ default:
+ gcc_unreachable ();
+ }
+ break;
+
+ case TRAP_SUFFIX_U_SU_SUI:
+ switch (alpha_fptm)
+ {
+ case ALPHA_FPTM_N:
+ return NULL;
+ case ALPHA_FPTM_U:
+ return "u";
+ case ALPHA_FPTM_SU:
+ return "su";
+ case ALPHA_FPTM_SUI:
+ return "sui";
+ default:
+ gcc_unreachable ();
+ }
+ break;
+
+ default:
+ gcc_unreachable ();
+ }
+ gcc_unreachable ();
+}
+
+/* Return the rounding mode suffix applicable to the current
+ instruction, or NULL. */
+
+static const char *
+get_round_mode_suffix (void)
+{
+ enum attr_round_suffix s = get_attr_round_suffix (current_output_insn);
+
+ switch (s)
+ {
+ case ROUND_SUFFIX_NONE:
+ return NULL;
+ case ROUND_SUFFIX_NORMAL:
+ switch (alpha_fprm)
+ {
+ case ALPHA_FPRM_NORM:
+ return NULL;
+ case ALPHA_FPRM_MINF:
+ return "m";
+ case ALPHA_FPRM_CHOP:
+ return "c";
+ case ALPHA_FPRM_DYN:
+ return "d";
+ default:
+ gcc_unreachable ();
+ }
+ break;
+
+ case ROUND_SUFFIX_C:
+ return "c";
+
+ default:
+ gcc_unreachable ();
+ }
+ gcc_unreachable ();
+}
+
+/* Locate some local-dynamic symbol still in use by this function
+ so that we can print its name in some movdi_er_tlsldm pattern. */
+
+static int
+get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
+{
+ rtx x = *px;
+
+ if (GET_CODE (x) == SYMBOL_REF
+ && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
+ {
+ cfun->machine->some_ld_name = XSTR (x, 0);
+ return 1;
+ }
+
+ return 0;
+}
+
+static const char *
+get_some_local_dynamic_name (void)
+{
+ rtx insn;
+
+ if (cfun->machine->some_ld_name)
+ return cfun->machine->some_ld_name;
+
+ for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
+ if (INSN_P (insn)
+ && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
+ return cfun->machine->some_ld_name;
+
+ gcc_unreachable ();
+}
+
+/* Print an operand. Recognize special options, documented below. */
+
+void
+print_operand (FILE *file, rtx x, int code)
+{
+ int i;
+
+ switch (code)
+ {
+ case '~':
+ /* Print the assembler name of the current function. */
+ assemble_name (file, alpha_fnname);
+ break;
+
+ case '&':
+ assemble_name (file, get_some_local_dynamic_name ());
+ break;
+
+ case '/':
+ {
+ const char *trap = get_trap_mode_suffix ();
+ const char *round = get_round_mode_suffix ();
+
+ if (trap || round)
+ fprintf (file, (TARGET_AS_SLASH_BEFORE_SUFFIX ? "/%s%s" : "%s%s"),
+ (trap ? trap : ""), (round ? round : ""));
+ break;
+ }
+
+ case ',':
+ /* Generates single precision instruction suffix. */
+ fputc ((TARGET_FLOAT_VAX ? 'f' : 's'), file);
+ break;
+
+ case '-':
+ /* Generates double precision instruction suffix. */
+ fputc ((TARGET_FLOAT_VAX ? 'g' : 't'), file);
+ break;
+
+ case '#':
+ if (alpha_this_literal_sequence_number == 0)
+ alpha_this_literal_sequence_number = alpha_next_sequence_number++;
+ fprintf (file, "%d", alpha_this_literal_sequence_number);
+ break;
+
+ case '*':
+ if (alpha_this_gpdisp_sequence_number == 0)
+ alpha_this_gpdisp_sequence_number = alpha_next_sequence_number++;
+ fprintf (file, "%d", alpha_this_gpdisp_sequence_number);
+ break;
+
+ case 'H':
+ if (GET_CODE (x) == HIGH)
+ output_addr_const (file, XEXP (x, 0));
+ else
+ output_operand_lossage ("invalid %%H value");
+ break;
+
+ case 'J':
+ {
+ const char *lituse;
+
+ if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD_CALL)
+ {
+ x = XVECEXP (x, 0, 0);
+ lituse = "lituse_tlsgd";
+ }
+ else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM_CALL)
+ {
+ x = XVECEXP (x, 0, 0);
+ lituse = "lituse_tlsldm";
+ }
+ else if (GET_CODE (x) == CONST_INT)
+ lituse = "lituse_jsr";
+ else
+ {
+ output_operand_lossage ("invalid %%J value");
+ break;
+ }
+
+ if (x != const0_rtx)
+ fprintf (file, "\t\t!%s!%d", lituse, (int) INTVAL (x));
+ }
+ break;
+
+ case 'j':
+ {
+ const char *lituse;
+
+#ifdef HAVE_AS_JSRDIRECT_RELOCS
+ lituse = "lituse_jsrdirect";
+#else
+ lituse = "lituse_jsr";
+#endif
+
+ gcc_assert (INTVAL (x) != 0);
+ fprintf (file, "\t\t!%s!%d", lituse, (int) INTVAL (x));
+ }
+ break;
+ case 'r':
+ /* If this operand is the constant zero, write it as "$31". */
+ if (GET_CODE (x) == REG)
+ fprintf (file, "%s", reg_names[REGNO (x)]);
+ else if (x == CONST0_RTX (GET_MODE (x)))
+ fprintf (file, "$31");
+ else
+ output_operand_lossage ("invalid %%r value");
+ break;
+
+ case 'R':
+ /* Similar, but for floating-point. */
+ if (GET_CODE (x) == REG)
+ fprintf (file, "%s", reg_names[REGNO (x)]);
+ else if (x == CONST0_RTX (GET_MODE (x)))
+ fprintf (file, "$f31");
+ else
+ output_operand_lossage ("invalid %%R value");
+ break;
+
+ case 'N':
+ /* Write the 1's complement of a constant. */
+ if (GET_CODE (x) != CONST_INT)
+ output_operand_lossage ("invalid %%N value");
+
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
+ break;
+
+ case 'P':
+ /* Write 1 << C, for a constant C. */
+ if (GET_CODE (x) != CONST_INT)
+ output_operand_lossage ("invalid %%P value");
+
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT) 1 << INTVAL (x));
+ break;
+
+ case 'h':
+ /* Write the high-order 16 bits of a constant, sign-extended. */
+ if (GET_CODE (x) != CONST_INT)
+ output_operand_lossage ("invalid %%h value");
+
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) >> 16);
+ break;
+
+ case 'L':
+ /* Write the low-order 16 bits of a constant, sign-extended. */
+ if (GET_CODE (x) != CONST_INT)
+ output_operand_lossage ("invalid %%L value");
+
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC,
+ (INTVAL (x) & 0xffff) - 2 * (INTVAL (x) & 0x8000));
+ break;
+
+ case 'm':
+ /* Write mask for ZAP insn. */
+ if (GET_CODE (x) == CONST_DOUBLE)
+ {
+ HOST_WIDE_INT mask = 0;
+ HOST_WIDE_INT value;
+
+ value = CONST_DOUBLE_LOW (x);
+ for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
+ i++, value >>= 8)
+ if (value & 0xff)
+ mask |= (1 << i);
+
+ value = CONST_DOUBLE_HIGH (x);
+ for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
+ i++, value >>= 8)
+ if (value & 0xff)
+ mask |= (1 << (i + sizeof (int)));
+
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask & 0xff);
+ }
+
+ else if (GET_CODE (x) == CONST_INT)
+ {
+ HOST_WIDE_INT mask = 0, value = INTVAL (x);
+
+ for (i = 0; i < 8; i++, value >>= 8)
+ if (value & 0xff)
+ mask |= (1 << i);
+
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask);
+ }
+ else
+ output_operand_lossage ("invalid %%m value");
+ break;
+
+ case 'M':
+ /* 'b', 'w', 'l', or 'q' as the value of the constant. */
+ if (GET_CODE (x) != CONST_INT
+ || (INTVAL (x) != 8 && INTVAL (x) != 16
+ && INTVAL (x) != 32 && INTVAL (x) != 64))
+ output_operand_lossage ("invalid %%M value");
+
+ fprintf (file, "%s",
+ (INTVAL (x) == 8 ? "b"
+ : INTVAL (x) == 16 ? "w"
+ : INTVAL (x) == 32 ? "l"
+ : "q"));
+ break;
+
+ case 'U':
+ /* Similar, except do it from the mask. */
+ if (GET_CODE (x) == CONST_INT)
+ {
+ HOST_WIDE_INT value = INTVAL (x);
+
+ if (value == 0xff)
+ {
+ fputc ('b', file);
+ break;
+ }
+ if (value == 0xffff)
+ {
+ fputc ('w', file);
+ break;
+ }
+ if (value == 0xffffffff)
+ {
+ fputc ('l', file);
+ break;
+ }
+ if (value == -1)
+ {
+ fputc ('q', file);
+ break;
+ }
+ }
+ else if (HOST_BITS_PER_WIDE_INT == 32
+ && GET_CODE (x) == CONST_DOUBLE
+ && CONST_DOUBLE_LOW (x) == 0xffffffff
+ && CONST_DOUBLE_HIGH (x) == 0)
+ {
+ fputc ('l', file);
+ break;
+ }
+ output_operand_lossage ("invalid %%U value");
+ break;
+
+ case 's':
+ /* Write the constant value divided by 8 for little-endian mode or
+ (56 - value) / 8 for big-endian mode. */
+
+ if (GET_CODE (x) != CONST_INT
+ || (unsigned HOST_WIDE_INT) INTVAL (x) >= (WORDS_BIG_ENDIAN
+ ? 56
+ : 64)
+ || (INTVAL (x) & 7) != 0)
+ output_operand_lossage ("invalid %%s value");
+
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC,
+ WORDS_BIG_ENDIAN
+ ? (56 - INTVAL (x)) / 8
+ : INTVAL (x) / 8);
+ break;
+
+ case 'S':
+ /* Same, except compute (64 - c) / 8 */
+
+ if (GET_CODE (x) != CONST_INT
+ && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64
+ && (INTVAL (x) & 7) != 8)
+ output_operand_lossage ("invalid %%s value");
+
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, (64 - INTVAL (x)) / 8);
+ break;
+
+ case 't':
+ {
+ /* On Unicos/Mk systems: use a DEX expression if the symbol
+ clashes with a register name. */
+ int dex = unicosmk_need_dex (x);
+ if (dex)
+ fprintf (file, "DEX(%d)", dex);
+ else
+ output_addr_const (file, x);
+ }
+ break;
+
+ case 'C': case 'D': case 'c': case 'd':
+ /* Write out comparison name. */
+ {
+ enum rtx_code c = GET_CODE (x);
+
+ if (!COMPARISON_P (x))
+ output_operand_lossage ("invalid %%C value");
+
+ else if (code == 'D')
+ c = reverse_condition (c);
+ else if (code == 'c')
+ c = swap_condition (c);
+ else if (code == 'd')
+ c = swap_condition (reverse_condition (c));
+
+ if (c == LEU)
+ fprintf (file, "ule");
+ else if (c == LTU)
+ fprintf (file, "ult");
+ else if (c == UNORDERED)
+ fprintf (file, "un");
+ else
+ fprintf (file, "%s", GET_RTX_NAME (c));
+ }
+ break;
+
+ case 'E':
+ /* Write the divide or modulus operator. */
+ switch (GET_CODE (x))
+ {
+ case DIV:
+ fprintf (file, "div%s", GET_MODE (x) == SImode ? "l" : "q");
+ break;
+ case UDIV:
+ fprintf (file, "div%su", GET_MODE (x) == SImode ? "l" : "q");
+ break;
+ case MOD:
+ fprintf (file, "rem%s", GET_MODE (x) == SImode ? "l" : "q");
+ break;
+ case UMOD:
+ fprintf (file, "rem%su", GET_MODE (x) == SImode ? "l" : "q");
+ break;
+ default:
+ output_operand_lossage ("invalid %%E value");
+ break;
+ }
+ break;
+
+ case 'A':
+ /* Write "_u" for unaligned access. */
+ if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
+ fprintf (file, "_u");
+ break;
+
+ case 0:
+ if (GET_CODE (x) == REG)
+ fprintf (file, "%s", reg_names[REGNO (x)]);
+ else if (GET_CODE (x) == MEM)
+ output_address (XEXP (x, 0));
+ else if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == UNSPEC)
+ {
+ switch (XINT (XEXP (x, 0), 1))
+ {
+ case UNSPEC_DTPREL:
+ case UNSPEC_TPREL:
+ output_addr_const (file, XVECEXP (XEXP (x, 0), 0, 0));
+ break;
+ default:
+ output_operand_lossage ("unknown relocation unspec");
+ break;
+ }
+ }
+ else
+ output_addr_const (file, x);
+ break;
+
+ default:
+ output_operand_lossage ("invalid %%xn code");
+ }
+}
+
+void
+print_operand_address (FILE *file, rtx addr)
+{
+ int basereg = 31;
+ HOST_WIDE_INT offset = 0;
+
+ if (GET_CODE (addr) == AND)
+ addr = XEXP (addr, 0);
+
+ if (GET_CODE (addr) == PLUS
+ && GET_CODE (XEXP (addr, 1)) == CONST_INT)
+ {
+ offset = INTVAL (XEXP (addr, 1));
+ addr = XEXP (addr, 0);
+ }
+
+ if (GET_CODE (addr) == LO_SUM)
+ {
+ const char *reloc16, *reloclo;
+ rtx op1 = XEXP (addr, 1);
+
+ if (GET_CODE (op1) == CONST && GET_CODE (XEXP (op1, 0)) == UNSPEC)
+ {
+ op1 = XEXP (op1, 0);
+ switch (XINT (op1, 1))
+ {
+ case UNSPEC_DTPREL:
+ reloc16 = NULL;
+ reloclo = (alpha_tls_size == 16 ? "dtprel" : "dtprello");
+ break;
+ case UNSPEC_TPREL:
+ reloc16 = NULL;
+ reloclo = (alpha_tls_size == 16 ? "tprel" : "tprello");
+ break;
+ default:
+ output_operand_lossage ("unknown relocation unspec");
+ return;
+ }
+
+ output_addr_const (file, XVECEXP (op1, 0, 0));
+ }
+ else
+ {
+ reloc16 = "gprel";
+ reloclo = "gprellow";
+ output_addr_const (file, op1);
}
- }
- /* Handle a block of contiguous long-words. */
+ if (offset)
+ fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
- if (align >= 64 && bytes >= 8)
- {
- words = bytes / 8;
+ addr = XEXP (addr, 0);
+ switch (GET_CODE (addr))
+ {
+ case REG:
+ basereg = REGNO (addr);
+ break;
- for (i = 0; i < words; ++i)
- emit_move_insn (adjust_address (orig_dst, DImode, ofs + i * 8),
- const0_rtx);
+ case SUBREG:
+ basereg = subreg_regno (addr);
+ break;
- bytes -= words * 8;
- ofs += words * 8;
- }
+ default:
+ gcc_unreachable ();
+ }
- /* If the block is large and appropriately aligned, emit a single
- store followed by a sequence of stq_u insns. */
+ fprintf (file, "($%d)\t\t!%s", basereg,
+ (basereg == 29 ? reloc16 : reloclo));
+ return;
+ }
- if (align >= 32 && bytes > 16)
+ switch (GET_CODE (addr))
{
- rtx orig_dsta;
+ case REG:
+ basereg = REGNO (addr);
+ break;
- emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
- bytes -= 4;
- ofs += 4;
+ case SUBREG:
+ basereg = subreg_regno (addr);
+ break;
- orig_dsta = XEXP (orig_dst, 0);
- if (GET_CODE (orig_dsta) == LO_SUM)
- orig_dsta = force_reg (Pmode, orig_dsta);
+ case CONST_INT:
+ offset = INTVAL (addr);
+ break;
- words = bytes / 8;
- for (i = 0; i < words; ++i)
- {
- rtx mem
- = change_address (orig_dst, DImode,
- gen_rtx_AND (DImode,
- plus_constant (orig_dsta, ofs + i*8),
- GEN_INT (-8)));
- set_mem_alias_set (mem, 0);
- emit_move_insn (mem, const0_rtx);
- }
+#if TARGET_ABI_OPEN_VMS
+ case SYMBOL_REF:
+ fprintf (file, "%s", XSTR (addr, 0));
+ return;
- /* Depending on the alignment, the first stq_u may have overlapped
- with the initial stl, which means that the last stq_u didn't
- write as much as it would appear. Leave those questionable bytes
- unaccounted for. */
- bytes -= words * 8 - 4;
- ofs += words * 8 - 4;
+ case CONST:
+ gcc_assert (GET_CODE (XEXP (addr, 0)) == PLUS
+ && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF);
+ fprintf (file, "%s+" HOST_WIDE_INT_PRINT_DEC,
+ XSTR (XEXP (XEXP (addr, 0), 0), 0),
+ INTVAL (XEXP (XEXP (addr, 0), 1)));
+ return;
+
+#endif
+ default:
+ gcc_unreachable ();
}
- /* Handle a smaller block of aligned words. */
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC "($%d)", offset, basereg);
+}
+\f
+/* Emit RTL insns to initialize the variable parts of a trampoline at
+ TRAMP. FNADDR is an RTX for the address of the function's pure
+ code. CXT is an RTX for the static chain value for the function.
- if ((align >= 64 && bytes == 4)
- || (align == 32 && bytes >= 4))
- {
- words = bytes / 4;
+ The three offset parameters are for the individual template's
+ layout. A JMPOFS < 0 indicates that the trampoline does not
+ contain instructions at all.
- for (i = 0; i < words; ++i)
- emit_move_insn (adjust_address (orig_dst, SImode, ofs + i * 4),
- const0_rtx);
+ We assume here that a function will be called many more times than
+ its address is taken (e.g., it might be passed to qsort), so we
+ take the trouble to initialize the "hint" field in the JMP insn.
+ Note that the hint field is PC (new) + 4 * bits 13:0. */
- bytes -= words * 4;
- ofs += words * 4;
- }
+void
+alpha_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt,
+ int fnofs, int cxtofs, int jmpofs)
+{
+ rtx addr;
+ /* VMS really uses DImode pointers in memory at this point. */
+ enum machine_mode mode = TARGET_ABI_OPEN_VMS ? Pmode : ptr_mode;
- /* An unaligned block uses stq_u stores for as many as possible. */
+#ifdef POINTERS_EXTEND_UNSIGNED
+ fnaddr = convert_memory_address (mode, fnaddr);
+ cxt = convert_memory_address (mode, cxt);
+#endif
- if (bytes >= 8)
- {
- words = bytes / 8;
+ /* Store function address and CXT. */
+ addr = memory_address (mode, plus_constant (tramp, fnofs));
+ emit_move_insn (gen_rtx_MEM (mode, addr), fnaddr);
+ addr = memory_address (mode, plus_constant (tramp, cxtofs));
+ emit_move_insn (gen_rtx_MEM (mode, addr), cxt);
- alpha_expand_unaligned_store_words (NULL, orig_dst, words, ofs);
+#ifdef ENABLE_EXECUTE_STACK
+ emit_library_call (init_one_libfunc ("__enable_execute_stack"),
+ 0, VOIDmode, 1, tramp, Pmode);
+#endif
- bytes -= words * 8;
- ofs += words * 8;
- }
+ if (jmpofs >= 0)
+ emit_insn (gen_imb ());
+}
+\f
+/* Determine where to put an argument to a function.
+ Value is zero to push the argument on the stack,
+ or a hard register in which to store the argument.
- /* Next clean up any trailing pieces. */
+ MODE is the argument's machine mode.
+ TYPE is the data type of the argument (as a tree).
+ This is null for libcalls where that information may
+ not be available.
+ CUM is a variable of type CUMULATIVE_ARGS which gives info about
+ the preceding args and about the function being called.
+ NAMED is nonzero if this argument is a named parameter
+ (otherwise it is an extra parameter matching an ellipsis).
-#if HOST_BITS_PER_WIDE_INT >= 64
- /* Count the number of bits in BYTES for which aligned stores could
- be emitted. */
- words = 0;
- for (i = (TARGET_BWX ? 1 : 4); i * BITS_PER_UNIT <= align ; i <<= 1)
- if (bytes & i)
- words += 1;
+ On Alpha the first 6 words of args are normally in registers
+ and the rest are pushed. */
- /* If we have appropriate alignment (and it wouldn't take too many
- instructions otherwise), mask out the bytes we need. */
- if (TARGET_BWX ? words > 2 : bytes > 0)
+rtx
+function_arg (CUMULATIVE_ARGS cum, enum machine_mode mode, tree type,
+ int named ATTRIBUTE_UNUSED)
+{
+ int basereg;
+ int num_args;
+
+ /* Don't get confused and pass small structures in FP registers. */
+ if (type && AGGREGATE_TYPE_P (type))
+ basereg = 16;
+ else
{
- if (align >= 64)
- {
- rtx mem, tmp;
- HOST_WIDE_INT mask;
+#ifdef ENABLE_CHECKING
+ /* With alpha_split_complex_arg, we shouldn't see any raw complex
+ values here. */
+ gcc_assert (!COMPLEX_MODE_P (mode));
+#endif
- mem = adjust_address (orig_dst, DImode, ofs);
- set_mem_alias_set (mem, 0);
+ /* Set up defaults for FP operands passed in FP registers, and
+ integral operands passed in integer registers. */
+ if (TARGET_FPREGS && GET_MODE_CLASS (mode) == MODE_FLOAT)
+ basereg = 32 + 16;
+ else
+ basereg = 16;
+ }
- mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
+ /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
+ the three platforms, so we can't avoid conditional compilation. */
+#if TARGET_ABI_OPEN_VMS
+ {
+ if (mode == VOIDmode)
+ return alpha_arg_info_reg_val (cum);
- tmp = expand_binop (DImode, and_optab, mem, GEN_INT (mask),
- NULL_RTX, 1, OPTAB_WIDEN);
+ num_args = cum.num_args;
+ if (num_args >= 6
+ || targetm.calls.must_pass_in_stack (mode, type))
+ return NULL_RTX;
+ }
+#elif TARGET_ABI_UNICOSMK
+ {
+ int size;
- emit_move_insn (mem, tmp);
- return 1;
- }
- else if (align >= 32 && bytes < 4)
+ /* If this is the last argument, generate the call info word (CIW). */
+ /* ??? We don't include the caller's line number in the CIW because
+ I don't know how to determine it if debug infos are turned off. */
+ if (mode == VOIDmode)
{
- rtx mem, tmp;
- HOST_WIDE_INT mask;
+ int i;
+ HOST_WIDE_INT lo;
+ HOST_WIDE_INT hi;
+ rtx ciw;
- mem = adjust_address (orig_dst, SImode, ofs);
- set_mem_alias_set (mem, 0);
+ lo = 0;
- mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
+ for (i = 0; i < cum.num_reg_words && i < 5; i++)
+ if (cum.reg_args_type[i])
+ lo |= (1 << (7 - i));
- tmp = expand_binop (SImode, and_optab, mem, GEN_INT (mask),
- NULL_RTX, 1, OPTAB_WIDEN);
+ if (cum.num_reg_words == 6 && cum.reg_args_type[5])
+ lo |= 7;
+ else
+ lo |= cum.num_reg_words;
- emit_move_insn (mem, tmp);
- return 1;
- }
- }
+#if HOST_BITS_PER_WIDE_INT == 32
+ hi = (cum.num_args << 20) | cum.num_arg_words;
+#else
+ lo = lo | ((HOST_WIDE_INT) cum.num_args << 52)
+ | ((HOST_WIDE_INT) cum.num_arg_words << 32);
+ hi = 0;
#endif
+ ciw = immed_double_const (lo, hi, DImode);
- if (!TARGET_BWX && bytes >= 4)
- {
- alpha_expand_unaligned_store (orig_dst, const0_rtx, 4, ofs);
- bytes -= 4;
- ofs += 4;
- }
-
- if (bytes >= 2)
- {
- if (align >= 16)
- {
- do {
- emit_move_insn (adjust_address (orig_dst, HImode, ofs),
- const0_rtx);
- bytes -= 2;
- ofs += 2;
- } while (bytes >= 2);
+ return gen_rtx_UNSPEC (DImode, gen_rtvec (1, ciw),
+ UNSPEC_UMK_LOAD_CIW);
}
- else if (! TARGET_BWX)
+
+ size = ALPHA_ARG_SIZE (mode, type, named);
+ num_args = cum.num_reg_words;
+ if (cum.force_stack
+ || cum.num_reg_words + size > 6
+ || targetm.calls.must_pass_in_stack (mode, type))
+ return NULL_RTX;
+ else if (type && TYPE_MODE (type) == BLKmode)
{
- alpha_expand_unaligned_store (orig_dst, const0_rtx, 2, ofs);
- bytes -= 2;
- ofs += 2;
+ rtx reg1, reg2;
+
+ reg1 = gen_rtx_REG (DImode, num_args + 16);
+ reg1 = gen_rtx_EXPR_LIST (DImode, reg1, const0_rtx);
+
+ /* The argument fits in two registers. Note that we still need to
+ reserve a register for empty structures. */
+ if (size == 0)
+ return NULL_RTX;
+ else if (size == 1)
+ return gen_rtx_PARALLEL (mode, gen_rtvec (1, reg1));
+ else
+ {
+ reg2 = gen_rtx_REG (DImode, num_args + 17);
+ reg2 = gen_rtx_EXPR_LIST (DImode, reg2, GEN_INT (8));
+ return gen_rtx_PARALLEL (mode, gen_rtvec (2, reg1, reg2));
+ }
}
}
+#elif TARGET_ABI_OSF
+ {
+ if (cum >= 6)
+ return NULL_RTX;
+ num_args = cum;
- while (bytes > 0)
- {
- emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
- bytes -= 1;
- ofs += 1;
+ /* VOID is passed as a special flag for "last argument". */
+ if (type == void_type_node)
+ basereg = 16;
+ else if (targetm.calls.must_pass_in_stack (mode, type))
+ return NULL_RTX;
}
+#else
+#error Unhandled ABI
+#endif
- return 1;
+ return gen_rtx_REG (mode, num_args + basereg);
}
-\f
-/* Adjust the cost of a scheduling dependency. Return the new cost of
- a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
static int
-alpha_adjust_cost (insn, link, dep_insn, cost)
- rtx insn;
- rtx link;
- rtx dep_insn;
- int cost;
+alpha_arg_partial_bytes (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
+ enum machine_mode mode ATTRIBUTE_UNUSED,
+ tree type ATTRIBUTE_UNUSED,
+ bool named ATTRIBUTE_UNUSED)
{
- rtx set, set_src;
- enum attr_type insn_type, dep_insn_type;
+ int words = 0;
- /* If the dependence is an anti-dependence, there is no cost. For an
- output dependence, there is sometimes a cost, but it doesn't seem
- worth handling those few cases. */
+#if TARGET_ABI_OPEN_VMS
+ if (cum->num_args < 6
+ && 6 < cum->num_args + ALPHA_ARG_SIZE (mode, type, named))
+ words = 6 - cum->num_args;
+#elif TARGET_ABI_UNICOSMK
+ /* Never any split arguments. */
+#elif TARGET_ABI_OSF
+ if (*cum < 6 && 6 < *cum + ALPHA_ARG_SIZE (mode, type, named))
+ words = 6 - *cum;
+#else
+#error Unhandled ABI
+#endif
- if (REG_NOTE_KIND (link) != 0)
- return 0;
+ return words * UNITS_PER_WORD;
+}
- /* If we can't recognize the insns, we can't really do anything. */
- if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
- return cost;
- insn_type = get_attr_type (insn);
- dep_insn_type = get_attr_type (dep_insn);
+/* Return true if TYPE must be returned in memory, instead of in registers. */
- /* Bring in the user-defined memory latency. */
- if (dep_insn_type == TYPE_ILD
- || dep_insn_type == TYPE_FLD
- || dep_insn_type == TYPE_LDSYM)
- cost += alpha_memory_latency-1;
+static bool
+alpha_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
+{
+ enum machine_mode mode = VOIDmode;
+ int size;
- switch (alpha_cpu)
+ if (type)
{
- case PROCESSOR_EV4:
- /* On EV4, if INSN is a store insn and DEP_INSN is setting the data
- being stored, we can sometimes lower the cost. */
+ mode = TYPE_MODE (type);
- if ((insn_type == TYPE_IST || insn_type == TYPE_FST)
- && (set = single_set (dep_insn)) != 0
- && GET_CODE (PATTERN (insn)) == SET
- && rtx_equal_p (SET_DEST (set), SET_SRC (PATTERN (insn))))
- {
- switch (dep_insn_type)
- {
- case TYPE_ILD:
- case TYPE_FLD:
- /* No savings here. */
- return cost;
+ /* All aggregates are returned in memory. */
+ if (AGGREGATE_TYPE_P (type))
+ return true;
+ }
- case TYPE_IMUL:
- /* In these cases, we save one cycle. */
- return cost - 1;
+ size = GET_MODE_SIZE (mode);
+ switch (GET_MODE_CLASS (mode))
+ {
+ case MODE_VECTOR_FLOAT:
+ /* Pass all float vectors in memory, like an aggregate. */
+ return true;
- default:
- /* In all other cases, we save two cycles. */
- return MAX (0, cost - 2);
- }
- }
+ case MODE_COMPLEX_FLOAT:
+ /* We judge complex floats on the size of their element,
+ not the size of the whole type. */
+ size = GET_MODE_UNIT_SIZE (mode);
+ break;
- /* Another case that needs adjustment is an arithmetic or logical
- operation. It's cost is usually one cycle, but we default it to
- two in the MD file. The only case that it is actually two is
- for the address in loads, stores, and jumps. */
+ case MODE_INT:
+ case MODE_FLOAT:
+ case MODE_COMPLEX_INT:
+ case MODE_VECTOR_INT:
+ break;
- if (dep_insn_type == TYPE_IADD || dep_insn_type == TYPE_ILOG)
- {
- switch (insn_type)
- {
- case TYPE_ILD:
- case TYPE_IST:
- case TYPE_FLD:
- case TYPE_FST:
- case TYPE_JSR:
- return cost;
- default:
- return 1;
- }
- }
+ default:
+ /* ??? We get called on all sorts of random stuff from
+ aggregate_value_p. We must return something, but it's not
+ clear what's safe to return. Pretend it's a struct I
+ guess. */
+ return true;
+ }
- /* The final case is when a compare feeds into an integer branch;
- the cost is only one cycle in that case. */
+ /* Otherwise types must fit in one register. */
+ return size > UNITS_PER_WORD;
+}
- if (dep_insn_type == TYPE_ICMP && insn_type == TYPE_IBR)
- return 1;
- break;
+/* Return true if TYPE should be passed by invisible reference. */
- case PROCESSOR_EV5:
- /* And the lord DEC saith: "A special bypass provides an effective
- latency of 0 cycles for an ICMP or ILOG insn producing the test
- operand of an IBR or ICMOV insn." */
+static bool
+alpha_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
+ enum machine_mode mode,
+ const_tree type ATTRIBUTE_UNUSED,
+ bool named ATTRIBUTE_UNUSED)
+{
+ return mode == TFmode || mode == TCmode;
+}
- if ((dep_insn_type == TYPE_ICMP || dep_insn_type == TYPE_ILOG)
- && (set = single_set (dep_insn)) != 0)
- {
- /* A branch only has one input. This must be it. */
- if (insn_type == TYPE_IBR)
- return 0;
- /* A conditional move has three, make sure it is the test. */
- if (insn_type == TYPE_ICMOV
- && GET_CODE (set_src = PATTERN (insn)) == SET
- && GET_CODE (set_src = SET_SRC (set_src)) == IF_THEN_ELSE
- && rtx_equal_p (SET_DEST (set), XEXP (set_src, 0)))
- return 0;
- }
+/* Define how to find the value returned by a function. VALTYPE is the
+ data type of the value (as a tree). If the precise function being
+ called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
+ MODE is set instead of VALTYPE for libcalls.
- /* "The multiplier is unable to receive data from IEU bypass paths.
- The instruction issues at the expected time, but its latency is
- increased by the time it takes for the input data to become
- available to the multiplier" -- which happens in pipeline stage
- six, when results are comitted to the register file. */
+ On Alpha the value is found in $0 for integer functions and
+ $f0 for floating-point functions. */
- if (insn_type == TYPE_IMUL)
- {
- switch (dep_insn_type)
- {
- /* These insns produce their results in pipeline stage five. */
- case TYPE_ILD:
- case TYPE_ICMOV:
- case TYPE_IMUL:
- case TYPE_MVI:
- return cost + 1;
-
- /* Other integer insns produce results in pipeline stage four. */
- default:
- return cost + 2;
- }
- }
- break;
+rtx
+function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
+ enum machine_mode mode)
+{
+ unsigned int regnum, dummy;
+ enum mode_class mclass;
+
+ gcc_assert (!valtype || !alpha_return_in_memory (valtype, func));
+
+ if (valtype)
+ mode = TYPE_MODE (valtype);
- case PROCESSOR_EV6:
- /* There is additional latency to move the result of (most) FP
- operations anywhere but the FP register file. */
+ mclass = GET_MODE_CLASS (mode);
+ switch (mclass)
+ {
+ case MODE_INT:
+ PROMOTE_MODE (mode, dummy, valtype);
+ /* FALLTHRU */
- if ((insn_type == TYPE_FST || insn_type == TYPE_FTOI)
- && (dep_insn_type == TYPE_FADD ||
- dep_insn_type == TYPE_FMUL ||
- dep_insn_type == TYPE_FCMOV))
- return cost + 2;
+ case MODE_COMPLEX_INT:
+ case MODE_VECTOR_INT:
+ regnum = 0;
+ break;
+ case MODE_FLOAT:
+ regnum = 32;
break;
+
+ case MODE_COMPLEX_FLOAT:
+ {
+ enum machine_mode cmode = GET_MODE_INNER (mode);
+
+ return gen_rtx_PARALLEL
+ (VOIDmode,
+ gen_rtvec (2,
+ gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 32),
+ const0_rtx),
+ gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 33),
+ GEN_INT (GET_MODE_SIZE (cmode)))));
+ }
+
+ default:
+ gcc_unreachable ();
}
- /* Otherwise, return the default cost. */
- return cost;
+ return gen_rtx_REG (mode, regnum);
}
-/* Function to initialize the issue rate used by the scheduler. */
-static int
-alpha_issue_rate ()
+/* TCmode complex values are passed by invisible reference. We
+ should not split these values. */
+
+static bool
+alpha_split_complex_arg (const_tree type)
{
- return (alpha_cpu == PROCESSOR_EV4 ? 2 : 4);
+ return TYPE_MODE (type) != TCmode;
}
-static int
-alpha_variable_issue (dump, verbose, insn, cim)
- FILE *dump ATTRIBUTE_UNUSED;
- int verbose ATTRIBUTE_UNUSED;
- rtx insn;
- int cim;
+static tree
+alpha_build_builtin_va_list (void)
{
- if (recog_memoized (insn) < 0 || get_attr_type (insn) == TYPE_MULTI)
- return 0;
+ tree base, ofs, space, record, type_decl;
- return cim - 1;
-}
+ if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
+ return ptr_type_node;
-\f
-/* Register global variables and machine-specific functions with the
- garbage collector. */
+ record = (*lang_hooks.types.make_type) (RECORD_TYPE);
+ type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
+ TREE_CHAIN (record) = type_decl;
+ TYPE_NAME (record) = type_decl;
-#if TARGET_ABI_UNICOSMK
-static void
-alpha_init_machine_status (p)
- struct function *p;
-{
- p->machine =
- (struct machine_function *) xcalloc (1, sizeof (struct machine_function));
+ /* C++? SET_IS_AGGR_TYPE (record, 1); */
+
+ /* Dummy field to prevent alignment warnings. */
+ space = build_decl (FIELD_DECL, NULL_TREE, integer_type_node);
+ DECL_FIELD_CONTEXT (space) = record;
+ DECL_ARTIFICIAL (space) = 1;
+ DECL_IGNORED_P (space) = 1;
+
+ ofs = build_decl (FIELD_DECL, get_identifier ("__offset"),
+ integer_type_node);
+ DECL_FIELD_CONTEXT (ofs) = record;
+ TREE_CHAIN (ofs) = space;
+
+ base = build_decl (FIELD_DECL, get_identifier ("__base"),
+ ptr_type_node);
+ DECL_FIELD_CONTEXT (base) = record;
+ TREE_CHAIN (base) = ofs;
+
+ TYPE_FIELDS (record) = base;
+ layout_type (record);
- p->machine->first_ciw = NULL_RTX;
- p->machine->last_ciw = NULL_RTX;
- p->machine->ciw_count = 0;
- p->machine->addr_list = NULL_RTX;
+ va_list_gpr_counter_field = ofs;
+ return record;
}
-static void
-alpha_mark_machine_status (p)
- struct function *p;
+#if TARGET_ABI_OSF
+/* Helper function for alpha_stdarg_optimize_hook. Skip over casts
+ and constant additions. */
+
+static gimple
+va_list_skip_additions (tree lhs)
{
- struct machine_function *machine = p->machine;
+ gimple stmt;
- if (machine)
+ for (;;)
{
- ggc_mark_rtx (machine->first_ciw);
- ggc_mark_rtx (machine->addr_list);
- }
-}
+ enum tree_code code;
-static void
-alpha_free_machine_status (p)
- struct function *p;
-{
- free (p->machine);
- p->machine = NULL;
-}
-#endif /* TARGET_ABI_UNICOSMK */
+ stmt = SSA_NAME_DEF_STMT (lhs);
-/* Functions to save and restore alpha_return_addr_rtx. */
+ if (gimple_code (stmt) == GIMPLE_PHI)
+ return stmt;
-/* Start the ball rolling with RETURN_ADDR_RTX. */
+ if (!is_gimple_assign (stmt)
+ || gimple_assign_lhs (stmt) != lhs)
+ return NULL;
-rtx
-alpha_return_addr (count, frame)
- int count;
- rtx frame ATTRIBUTE_UNUSED;
-{
- if (count != 0)
- return const0_rtx;
+ if (TREE_CODE (gimple_assign_rhs1 (stmt)) != SSA_NAME)
+ return stmt;
+ code = gimple_assign_rhs_code (stmt);
+ if (!CONVERT_EXPR_CODE_P (code)
+ && ((code != PLUS_EXPR && code != POINTER_PLUS_EXPR)
+ || TREE_CODE (gimple_assign_rhs2 (stmt)) != INTEGER_CST
+ || !host_integerp (gimple_assign_rhs2 (stmt), 1)))
+ return stmt;
- return get_hard_reg_initial_val (Pmode, REG_RA);
+ lhs = gimple_assign_rhs1 (stmt);
+ }
}
-/* Return or create a pseudo containing the gp value for the current
- function. Needed only if TARGET_LD_BUGGY_LDGP. */
+/* Check if LHS = RHS statement is
+ LHS = *(ap.__base + ap.__offset + cst)
+ or
+ LHS = *(ap.__base
+ + ((ap.__offset + cst <= 47)
+ ? ap.__offset + cst - 48 : ap.__offset + cst) + cst2).
+ If the former, indicate that GPR registers are needed,
+ if the latter, indicate that FPR registers are needed.
-rtx
-alpha_gp_save_rtx ()
-{
- rtx r = get_hard_reg_initial_val (DImode, 29);
- if (GET_CODE (r) != MEM)
- r = gen_mem_addressof (r, NULL_TREE);
- return r;
-}
+ Also look for LHS = (*ptr).field, where ptr is one of the forms
+ listed above.
-static int
-alpha_ra_ever_killed ()
-{
- rtx top;
+ On alpha, cfun->va_list_gpr_size is used as size of the needed
+ regs and cfun->va_list_fpr_size is a bitmask, bit 0 set if GPR
+ registers are needed and bit 1 set if FPR registers are needed.
+ Return true if va_list references should not be scanned for the
+ current statement. */
- if (!has_hard_reg_initial_val (Pmode, REG_RA))
- return regs_ever_live[REG_RA];
+static bool
+alpha_stdarg_optimize_hook (struct stdarg_info *si, const_gimple stmt)
+{
+ tree base, offset, rhs;
+ int offset_arg = 1;
+ gimple base_stmt;
- push_topmost_sequence ();
- top = get_insns ();
- pop_topmost_sequence ();
+ if (get_gimple_rhs_class (gimple_assign_rhs_code (stmt))
+ != GIMPLE_SINGLE_RHS)
+ return false;
- return reg_set_between_p (gen_rtx_REG (Pmode, REG_RA), top, NULL_RTX);
-}
+ rhs = gimple_assign_rhs1 (stmt);
+ while (handled_component_p (rhs))
+ rhs = TREE_OPERAND (rhs, 0);
+ if (TREE_CODE (rhs) != INDIRECT_REF
+ || TREE_CODE (TREE_OPERAND (rhs, 0)) != SSA_NAME)
+ return false;
-\f
-/* Return the trap mode suffix applicable to the current
- instruction, or NULL. */
+ stmt = va_list_skip_additions (TREE_OPERAND (rhs, 0));
+ if (stmt == NULL
+ || !is_gimple_assign (stmt)
+ || gimple_assign_rhs_code (stmt) != POINTER_PLUS_EXPR)
+ return false;
-static const char *
-get_trap_mode_suffix ()
-{
- enum attr_trap_suffix s = get_attr_trap_suffix (current_output_insn);
+ base = gimple_assign_rhs1 (stmt);
+ if (TREE_CODE (base) == SSA_NAME)
+ {
+ base_stmt = va_list_skip_additions (base);
+ if (base_stmt
+ && is_gimple_assign (base_stmt)
+ && gimple_assign_rhs_code (base_stmt) == COMPONENT_REF)
+ base = gimple_assign_rhs1 (base_stmt);
+ }
- switch (s)
+ if (TREE_CODE (base) != COMPONENT_REF
+ || TREE_OPERAND (base, 1) != TYPE_FIELDS (va_list_type_node))
{
- case TRAP_SUFFIX_NONE:
- return NULL;
+ base = gimple_assign_rhs2 (stmt);
+ if (TREE_CODE (base) == SSA_NAME)
+ {
+ base_stmt = va_list_skip_additions (base);
+ if (base_stmt
+ && is_gimple_assign (base_stmt)
+ && gimple_assign_rhs_code (base_stmt) == COMPONENT_REF)
+ base = gimple_assign_rhs1 (base_stmt);
+ }
- case TRAP_SUFFIX_SU:
- if (alpha_fptm >= ALPHA_FPTM_SU)
- return "su";
- return NULL;
+ if (TREE_CODE (base) != COMPONENT_REF
+ || TREE_OPERAND (base, 1) != TYPE_FIELDS (va_list_type_node))
+ return false;
- case TRAP_SUFFIX_SUI:
- if (alpha_fptm >= ALPHA_FPTM_SUI)
- return "sui";
- return NULL;
+ offset_arg = 0;
+ }
- case TRAP_SUFFIX_V_SV:
- switch (alpha_fptm)
- {
- case ALPHA_FPTM_N:
- return NULL;
- case ALPHA_FPTM_U:
- return "v";
- case ALPHA_FPTM_SU:
- case ALPHA_FPTM_SUI:
- return "sv";
- }
- break;
+ base = get_base_address (base);
+ if (TREE_CODE (base) != VAR_DECL
+ || !bitmap_bit_p (si->va_list_vars, DECL_UID (base)))
+ return false;
- case TRAP_SUFFIX_V_SV_SVI:
- switch (alpha_fptm)
- {
- case ALPHA_FPTM_N:
- return NULL;
- case ALPHA_FPTM_U:
- return "v";
- case ALPHA_FPTM_SU:
- return "sv";
- case ALPHA_FPTM_SUI:
- return "svi";
- }
- break;
+ offset = gimple_op (stmt, 1 + offset_arg);
+ if (TREE_CODE (offset) == SSA_NAME)
+ {
+ gimple offset_stmt = va_list_skip_additions (offset);
- case TRAP_SUFFIX_U_SU_SUI:
- switch (alpha_fptm)
+ if (offset_stmt
+ && gimple_code (offset_stmt) == GIMPLE_PHI)
{
- case ALPHA_FPTM_N:
- return NULL;
- case ALPHA_FPTM_U:
- return "u";
- case ALPHA_FPTM_SU:
- return "su";
- case ALPHA_FPTM_SUI:
- return "sui";
+ HOST_WIDE_INT sub;
+ gimple arg1_stmt, arg2_stmt;
+ tree arg1, arg2;
+ enum tree_code code1, code2;
+
+ if (gimple_phi_num_args (offset_stmt) != 2)
+ goto escapes;
+
+ arg1_stmt
+ = va_list_skip_additions (gimple_phi_arg_def (offset_stmt, 0));
+ arg2_stmt
+ = va_list_skip_additions (gimple_phi_arg_def (offset_stmt, 1));
+ if (arg1_stmt == NULL
+ || !is_gimple_assign (arg1_stmt)
+ || arg2_stmt == NULL
+ || !is_gimple_assign (arg2_stmt))
+ goto escapes;
+
+ code1 = gimple_assign_rhs_code (arg1_stmt);
+ code2 = gimple_assign_rhs_code (arg2_stmt);
+ if (code1 == COMPONENT_REF
+ && (code2 == MINUS_EXPR || code2 == PLUS_EXPR))
+ /* Do nothing. */;
+ else if (code2 == COMPONENT_REF
+ && (code1 == MINUS_EXPR || code1 == PLUS_EXPR))
+ {
+ gimple tem = arg1_stmt;
+ code2 = code1;
+ arg1_stmt = arg2_stmt;
+ arg2_stmt = tem;
+ }
+ else
+ goto escapes;
+
+ if (!host_integerp (gimple_assign_rhs2 (arg2_stmt), 0))
+ goto escapes;
+
+ sub = tree_low_cst (gimple_assign_rhs2 (arg2_stmt), 0);
+ if (code2 == MINUS_EXPR)
+ sub = -sub;
+ if (sub < -48 || sub > -32)
+ goto escapes;
+
+ arg1 = gimple_assign_rhs1 (arg1_stmt);
+ arg2 = gimple_assign_rhs1 (arg2_stmt);
+ if (TREE_CODE (arg2) == SSA_NAME)
+ {
+ arg2_stmt = va_list_skip_additions (arg2);
+ if (arg2_stmt == NULL
+ || !is_gimple_assign (arg2_stmt)
+ || gimple_assign_rhs_code (arg2_stmt) != COMPONENT_REF)
+ goto escapes;
+ arg2 = gimple_assign_rhs1 (arg2_stmt);
+ }
+ if (arg1 != arg2)
+ goto escapes;
+
+ if (TREE_CODE (arg1) != COMPONENT_REF
+ || TREE_OPERAND (arg1, 1) != va_list_gpr_counter_field
+ || get_base_address (arg1) != base)
+ goto escapes;
+
+ /* Need floating point regs. */
+ cfun->va_list_fpr_size |= 2;
+ return false;
}
- break;
- }
- abort ();
+ if (offset_stmt
+ && is_gimple_assign (offset_stmt)
+ && gimple_assign_rhs_code (offset_stmt) == COMPONENT_REF)
+ offset = gimple_assign_rhs1 (offset_stmt);
+ }
+ if (TREE_CODE (offset) != COMPONENT_REF
+ || TREE_OPERAND (offset, 1) != va_list_gpr_counter_field
+ || get_base_address (offset) != base)
+ goto escapes;
+ else
+ /* Need general regs. */
+ cfun->va_list_fpr_size |= 1;
+ return false;
+
+escapes:
+ si->va_list_escapes = true;
+ return false;
}
+#endif
-/* Return the rounding mode suffix applicable to the current
- instruction, or NULL. */
+/* Perform any needed actions needed for a function that is receiving a
+ variable number of arguments. */
-static const char *
-get_round_mode_suffix ()
+static void
+alpha_setup_incoming_varargs (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
+ tree type, int *pretend_size, int no_rtl)
{
- enum attr_round_suffix s = get_attr_round_suffix (current_output_insn);
+ CUMULATIVE_ARGS cum = *pcum;
- switch (s)
+ /* Skip the current argument. */
+ FUNCTION_ARG_ADVANCE (cum, mode, type, 1);
+
+#if TARGET_ABI_UNICOSMK
+ /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
+ arguments on the stack. Unfortunately, it doesn't always store the first
+ one (i.e. the one that arrives in $16 or $f16). This is not a problem
+ with stdargs as we always have at least one named argument there. */
+ if (cum.num_reg_words < 6)
{
- case ROUND_SUFFIX_NONE:
- return NULL;
- case ROUND_SUFFIX_NORMAL:
- switch (alpha_fprm)
+ if (!no_rtl)
{
- case ALPHA_FPRM_NORM:
- return NULL;
- case ALPHA_FPRM_MINF:
- return "m";
- case ALPHA_FPRM_CHOP:
- return "c";
- case ALPHA_FPRM_DYN:
- return "d";
+ emit_insn (gen_umk_mismatch_args (GEN_INT (cum.num_reg_words)));
+ emit_insn (gen_arg_home_umk ());
+ }
+ *pretend_size = 0;
+ }
+#elif TARGET_ABI_OPEN_VMS
+ /* For VMS, we allocate space for all 6 arg registers plus a count.
+
+ However, if NO registers need to be saved, don't allocate any space.
+ This is not only because we won't need the space, but because AP
+ includes the current_pretend_args_size and we don't want to mess up
+ any ap-relative addresses already made. */
+ if (cum.num_args < 6)
+ {
+ if (!no_rtl)
+ {
+ emit_move_insn (gen_rtx_REG (DImode, 1), virtual_incoming_args_rtx);
+ emit_insn (gen_arg_home ());
+ }
+ *pretend_size = 7 * UNITS_PER_WORD;
+ }
+#else
+ /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
+ only push those that are remaining. However, if NO registers need to
+ be saved, don't allocate any space. This is not only because we won't
+ need the space, but because AP includes the current_pretend_args_size
+ and we don't want to mess up any ap-relative addresses already made.
+
+ If we are not to use the floating-point registers, save the integer
+ registers where we would put the floating-point registers. This is
+ not the most efficient way to implement varargs with just one register
+ class, but it isn't worth doing anything more efficient in this rare
+ case. */
+ if (cum >= 6)
+ return;
+
+ if (!no_rtl)
+ {
+ int count;
+ alias_set_type set = get_varargs_alias_set ();
+ rtx tmp;
+
+ count = cfun->va_list_gpr_size / UNITS_PER_WORD;
+ if (count > 6 - cum)
+ count = 6 - cum;
+
+ /* Detect whether integer registers or floating-point registers
+ are needed by the detected va_arg statements. See above for
+ how these values are computed. Note that the "escape" value
+ is VA_LIST_MAX_FPR_SIZE, which is 255, which has both of
+ these bits set. */
+ gcc_assert ((VA_LIST_MAX_FPR_SIZE & 3) == 3);
+
+ if (cfun->va_list_fpr_size & 1)
+ {
+ tmp = gen_rtx_MEM (BLKmode,
+ plus_constant (virtual_incoming_args_rtx,
+ (cum + 6) * UNITS_PER_WORD));
+ MEM_NOTRAP_P (tmp) = 1;
+ set_mem_alias_set (tmp, set);
+ move_block_from_reg (16 + cum, tmp, count);
}
- break;
- case ROUND_SUFFIX_C:
- return "c";
- }
- abort ();
+ if (cfun->va_list_fpr_size & 2)
+ {
+ tmp = gen_rtx_MEM (BLKmode,
+ plus_constant (virtual_incoming_args_rtx,
+ cum * UNITS_PER_WORD));
+ MEM_NOTRAP_P (tmp) = 1;
+ set_mem_alias_set (tmp, set);
+ move_block_from_reg (16 + cum + TARGET_FPREGS*32, tmp, count);
+ }
+ }
+ *pretend_size = 12 * UNITS_PER_WORD;
+#endif
}
-/* Print an operand. Recognize special options, documented below. */
-
-void
-print_operand (file, x, code)
- FILE *file;
- rtx x;
- int code;
+static void
+alpha_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
{
- int i;
+ HOST_WIDE_INT offset;
+ tree t, offset_field, base_field;
- switch (code)
+ if (TREE_CODE (TREE_TYPE (valist)) == ERROR_MARK)
+ return;
+
+ if (TARGET_ABI_UNICOSMK)
+ std_expand_builtin_va_start (valist, nextarg);
+
+ /* For Unix, TARGET_SETUP_INCOMING_VARARGS moves the starting address base
+ up by 48, storing fp arg registers in the first 48 bytes, and the
+ integer arg registers in the next 48 bytes. This is only done,
+ however, if any integer registers need to be stored.
+
+ If no integer registers need be stored, then we must subtract 48
+ in order to account for the integer arg registers which are counted
+ in argsize above, but which are not actually stored on the stack.
+ Must further be careful here about structures straddling the last
+ integer argument register; that futzes with pretend_args_size,
+ which changes the meaning of AP. */
+
+ if (NUM_ARGS < 6)
+ offset = TARGET_ABI_OPEN_VMS ? UNITS_PER_WORD : 6 * UNITS_PER_WORD;
+ else
+ offset = -6 * UNITS_PER_WORD + crtl->args.pretend_args_size;
+
+ if (TARGET_ABI_OPEN_VMS)
{
- case '~':
- /* Print the assembler name of the current function. */
- assemble_name (file, alpha_fnname);
- break;
+ nextarg = plus_constant (nextarg, offset);
+ nextarg = plus_constant (nextarg, NUM_ARGS * UNITS_PER_WORD);
+ t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist,
+ make_tree (ptr_type_node, nextarg));
+ TREE_SIDE_EFFECTS (t) = 1;
- case '/':
- {
- const char *trap = get_trap_mode_suffix ();
- const char *round = get_round_mode_suffix ();
+ expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
+ }
+ else
+ {
+ base_field = TYPE_FIELDS (TREE_TYPE (valist));
+ offset_field = TREE_CHAIN (base_field);
- if (trap || round)
- fprintf (file, (TARGET_AS_SLASH_BEFORE_SUFFIX ? "/%s%s" : "%s%s"),
- (trap ? trap : ""), (round ? round : ""));
- break;
- }
+ base_field = build3 (COMPONENT_REF, TREE_TYPE (base_field),
+ valist, base_field, NULL_TREE);
+ offset_field = build3 (COMPONENT_REF, TREE_TYPE (offset_field),
+ valist, offset_field, NULL_TREE);
- case ',':
- /* Generates single precision instruction suffix. */
- fputc ((TARGET_FLOAT_VAX ? 'f' : 's'), file);
- break;
+ t = make_tree (ptr_type_node, virtual_incoming_args_rtx);
+ t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
+ size_int (offset));
+ t = build2 (MODIFY_EXPR, TREE_TYPE (base_field), base_field, t);
+ TREE_SIDE_EFFECTS (t) = 1;
+ expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
- case '-':
- /* Generates double precision instruction suffix. */
- fputc ((TARGET_FLOAT_VAX ? 'g' : 't'), file);
- break;
+ t = build_int_cst (NULL_TREE, NUM_ARGS * UNITS_PER_WORD);
+ t = build2 (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field, t);
+ TREE_SIDE_EFFECTS (t) = 1;
+ expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
+ }
+}
- case '#':
- if (alpha_this_literal_sequence_number == 0)
- alpha_this_literal_sequence_number = alpha_next_sequence_number++;
- fprintf (file, "%d", alpha_this_literal_sequence_number);
- break;
+static tree
+alpha_gimplify_va_arg_1 (tree type, tree base, tree offset,
+ gimple_seq *pre_p)
+{
+ tree type_size, ptr_type, addend, t, addr;
+ gimple_seq internal_post;
- case '*':
- if (alpha_this_gpdisp_sequence_number == 0)
- alpha_this_gpdisp_sequence_number = alpha_next_sequence_number++;
- fprintf (file, "%d", alpha_this_gpdisp_sequence_number);
- break;
+ /* If the type could not be passed in registers, skip the block
+ reserved for the registers. */
+ if (targetm.calls.must_pass_in_stack (TYPE_MODE (type), type))
+ {
+ t = build_int_cst (TREE_TYPE (offset), 6*8);
+ gimplify_assign (offset,
+ build2 (MAX_EXPR, TREE_TYPE (offset), offset, t),
+ pre_p);
+ }
- case 'H':
- if (GET_CODE (x) == HIGH)
- output_addr_const (file, XEXP (x, 0));
- else
- output_operand_lossage ("invalid %%H value");
- break;
+ addend = offset;
+ ptr_type = build_pointer_type (type);
- case 'J':
- if (GET_CODE (x) == CONST_INT)
- {
- if (INTVAL (x) != 0)
- fprintf (file, "\t\t!lituse_jsr!%d", (int) INTVAL (x));
- }
- else
- output_operand_lossage ("invalid %%J value");
- break;
+ if (TREE_CODE (type) == COMPLEX_TYPE)
+ {
+ tree real_part, imag_part, real_temp;
- case 'r':
- /* If this operand is the constant zero, write it as "$31". */
- if (GET_CODE (x) == REG)
- fprintf (file, "%s", reg_names[REGNO (x)]);
- else if (x == CONST0_RTX (GET_MODE (x)))
- fprintf (file, "$31");
- else
- output_operand_lossage ("invalid %%r value");
- break;
+ real_part = alpha_gimplify_va_arg_1 (TREE_TYPE (type), base,
+ offset, pre_p);
- case 'R':
- /* Similar, but for floating-point. */
- if (GET_CODE (x) == REG)
- fprintf (file, "%s", reg_names[REGNO (x)]);
- else if (x == CONST0_RTX (GET_MODE (x)))
- fprintf (file, "$f31");
- else
- output_operand_lossage ("invalid %%R value");
- break;
+ /* Copy the value into a new temporary, lest the formal temporary
+ be reused out from under us. */
+ real_temp = get_initialized_tmp_var (real_part, pre_p, NULL);
- case 'N':
- /* Write the 1's complement of a constant. */
- if (GET_CODE (x) != CONST_INT)
- output_operand_lossage ("invalid %%N value");
+ imag_part = alpha_gimplify_va_arg_1 (TREE_TYPE (type), base,
+ offset, pre_p);
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
- break;
+ return build2 (COMPLEX_EXPR, type, real_temp, imag_part);
+ }
+ else if (TREE_CODE (type) == REAL_TYPE)
+ {
+ tree fpaddend, cond, fourtyeight;
- case 'P':
- /* Write 1 << C, for a constant C. */
- if (GET_CODE (x) != CONST_INT)
- output_operand_lossage ("invalid %%P value");
+ fourtyeight = build_int_cst (TREE_TYPE (addend), 6*8);
+ fpaddend = fold_build2 (MINUS_EXPR, TREE_TYPE (addend),
+ addend, fourtyeight);
+ cond = fold_build2 (LT_EXPR, boolean_type_node, addend, fourtyeight);
+ addend = fold_build3 (COND_EXPR, TREE_TYPE (addend), cond,
+ fpaddend, addend);
+ }
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT) 1 << INTVAL (x));
- break;
+ /* Build the final address and force that value into a temporary. */
+ addr = build2 (POINTER_PLUS_EXPR, ptr_type, fold_convert (ptr_type, base),
+ fold_convert (sizetype, addend));
+ internal_post = NULL;
+ gimplify_expr (&addr, pre_p, &internal_post, is_gimple_val, fb_rvalue);
+ gimple_seq_add_seq (pre_p, internal_post);
- case 'h':
- /* Write the high-order 16 bits of a constant, sign-extended. */
- if (GET_CODE (x) != CONST_INT)
- output_operand_lossage ("invalid %%h value");
+ /* Update the offset field. */
+ type_size = TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type));
+ if (type_size == NULL || TREE_OVERFLOW (type_size))
+ t = size_zero_node;
+ else
+ {
+ t = size_binop (PLUS_EXPR, type_size, size_int (7));
+ t = size_binop (TRUNC_DIV_EXPR, t, size_int (8));
+ t = size_binop (MULT_EXPR, t, size_int (8));
+ }
+ t = fold_convert (TREE_TYPE (offset), t);
+ gimplify_assign (offset, build2 (PLUS_EXPR, TREE_TYPE (offset), offset, t),
+ pre_p);
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) >> 16);
- break;
+ return build_va_arg_indirect_ref (addr);
+}
- case 'L':
- /* Write the low-order 16 bits of a constant, sign-extended. */
- if (GET_CODE (x) != CONST_INT)
- output_operand_lossage ("invalid %%L value");
+static tree
+alpha_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
+ gimple_seq *post_p)
+{
+ tree offset_field, base_field, offset, base, t, r;
+ bool indirect;
- fprintf (file, HOST_WIDE_INT_PRINT_DEC,
- (INTVAL (x) & 0xffff) - 2 * (INTVAL (x) & 0x8000));
- break;
+ if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
+ return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
- case 'm':
- /* Write mask for ZAP insn. */
- if (GET_CODE (x) == CONST_DOUBLE)
- {
- HOST_WIDE_INT mask = 0;
- HOST_WIDE_INT value;
+ base_field = TYPE_FIELDS (va_list_type_node);
+ offset_field = TREE_CHAIN (base_field);
+ base_field = build3 (COMPONENT_REF, TREE_TYPE (base_field),
+ valist, base_field, NULL_TREE);
+ offset_field = build3 (COMPONENT_REF, TREE_TYPE (offset_field),
+ valist, offset_field, NULL_TREE);
- value = CONST_DOUBLE_LOW (x);
- for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
- i++, value >>= 8)
- if (value & 0xff)
- mask |= (1 << i);
+ /* Pull the fields of the structure out into temporaries. Since we never
+ modify the base field, we can use a formal temporary. Sign-extend the
+ offset field so that it's the proper width for pointer arithmetic. */
+ base = get_formal_tmp_var (base_field, pre_p);
- value = CONST_DOUBLE_HIGH (x);
- for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
- i++, value >>= 8)
- if (value & 0xff)
- mask |= (1 << (i + sizeof (int)));
+ t = fold_convert (lang_hooks.types.type_for_size (64, 0), offset_field);
+ offset = get_initialized_tmp_var (t, pre_p, NULL);
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask & 0xff);
- }
+ indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
+ if (indirect)
+ type = build_pointer_type (type);
- else if (GET_CODE (x) == CONST_INT)
- {
- HOST_WIDE_INT mask = 0, value = INTVAL (x);
+ /* Find the value. Note that this will be a stable indirection, or
+ a composite of stable indirections in the case of complex. */
+ r = alpha_gimplify_va_arg_1 (type, base, offset, pre_p);
- for (i = 0; i < 8; i++, value >>= 8)
- if (value & 0xff)
- mask |= (1 << i);
+ /* Stuff the offset temporary back into its field. */
+ gimplify_assign (unshare_expr (offset_field),
+ fold_convert (TREE_TYPE (offset_field), offset), pre_p);
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask);
- }
- else
- output_operand_lossage ("invalid %%m value");
- break;
+ if (indirect)
+ r = build_va_arg_indirect_ref (r);
- case 'M':
- /* 'b', 'w', 'l', or 'q' as the value of the constant. */
- if (GET_CODE (x) != CONST_INT
- || (INTVAL (x) != 8 && INTVAL (x) != 16
- && INTVAL (x) != 32 && INTVAL (x) != 64))
- output_operand_lossage ("invalid %%M value");
+ return r;
+}
+\f
+/* Builtins. */
+
+enum alpha_builtin
+{
+ ALPHA_BUILTIN_CMPBGE,
+ ALPHA_BUILTIN_EXTBL,
+ ALPHA_BUILTIN_EXTWL,
+ ALPHA_BUILTIN_EXTLL,
+ ALPHA_BUILTIN_EXTQL,
+ ALPHA_BUILTIN_EXTWH,
+ ALPHA_BUILTIN_EXTLH,
+ ALPHA_BUILTIN_EXTQH,
+ ALPHA_BUILTIN_INSBL,
+ ALPHA_BUILTIN_INSWL,
+ ALPHA_BUILTIN_INSLL,
+ ALPHA_BUILTIN_INSQL,
+ ALPHA_BUILTIN_INSWH,
+ ALPHA_BUILTIN_INSLH,
+ ALPHA_BUILTIN_INSQH,
+ ALPHA_BUILTIN_MSKBL,
+ ALPHA_BUILTIN_MSKWL,
+ ALPHA_BUILTIN_MSKLL,
+ ALPHA_BUILTIN_MSKQL,
+ ALPHA_BUILTIN_MSKWH,
+ ALPHA_BUILTIN_MSKLH,
+ ALPHA_BUILTIN_MSKQH,
+ ALPHA_BUILTIN_UMULH,
+ ALPHA_BUILTIN_ZAP,
+ ALPHA_BUILTIN_ZAPNOT,
+ ALPHA_BUILTIN_AMASK,
+ ALPHA_BUILTIN_IMPLVER,
+ ALPHA_BUILTIN_RPCC,
+ ALPHA_BUILTIN_THREAD_POINTER,
+ ALPHA_BUILTIN_SET_THREAD_POINTER,
+
+ /* TARGET_MAX */
+ ALPHA_BUILTIN_MINUB8,
+ ALPHA_BUILTIN_MINSB8,
+ ALPHA_BUILTIN_MINUW4,
+ ALPHA_BUILTIN_MINSW4,
+ ALPHA_BUILTIN_MAXUB8,
+ ALPHA_BUILTIN_MAXSB8,
+ ALPHA_BUILTIN_MAXUW4,
+ ALPHA_BUILTIN_MAXSW4,
+ ALPHA_BUILTIN_PERR,
+ ALPHA_BUILTIN_PKLB,
+ ALPHA_BUILTIN_PKWB,
+ ALPHA_BUILTIN_UNPKBL,
+ ALPHA_BUILTIN_UNPKBW,
+
+ /* TARGET_CIX */
+ ALPHA_BUILTIN_CTTZ,
+ ALPHA_BUILTIN_CTLZ,
+ ALPHA_BUILTIN_CTPOP,
+
+ ALPHA_BUILTIN_max
+};
- fprintf (file, "%s",
- (INTVAL (x) == 8 ? "b"
- : INTVAL (x) == 16 ? "w"
- : INTVAL (x) == 32 ? "l"
- : "q"));
- break;
+static unsigned int const code_for_builtin[ALPHA_BUILTIN_max] = {
+ CODE_FOR_builtin_cmpbge,
+ CODE_FOR_builtin_extbl,
+ CODE_FOR_builtin_extwl,
+ CODE_FOR_builtin_extll,
+ CODE_FOR_builtin_extql,
+ CODE_FOR_builtin_extwh,
+ CODE_FOR_builtin_extlh,
+ CODE_FOR_builtin_extqh,
+ CODE_FOR_builtin_insbl,
+ CODE_FOR_builtin_inswl,
+ CODE_FOR_builtin_insll,
+ CODE_FOR_builtin_insql,
+ CODE_FOR_builtin_inswh,
+ CODE_FOR_builtin_inslh,
+ CODE_FOR_builtin_insqh,
+ CODE_FOR_builtin_mskbl,
+ CODE_FOR_builtin_mskwl,
+ CODE_FOR_builtin_mskll,
+ CODE_FOR_builtin_mskql,
+ CODE_FOR_builtin_mskwh,
+ CODE_FOR_builtin_msklh,
+ CODE_FOR_builtin_mskqh,
+ CODE_FOR_umuldi3_highpart,
+ CODE_FOR_builtin_zap,
+ CODE_FOR_builtin_zapnot,
+ CODE_FOR_builtin_amask,
+ CODE_FOR_builtin_implver,
+ CODE_FOR_builtin_rpcc,
+ CODE_FOR_load_tp,
+ CODE_FOR_set_tp,
+
+ /* TARGET_MAX */
+ CODE_FOR_builtin_minub8,
+ CODE_FOR_builtin_minsb8,
+ CODE_FOR_builtin_minuw4,
+ CODE_FOR_builtin_minsw4,
+ CODE_FOR_builtin_maxub8,
+ CODE_FOR_builtin_maxsb8,
+ CODE_FOR_builtin_maxuw4,
+ CODE_FOR_builtin_maxsw4,
+ CODE_FOR_builtin_perr,
+ CODE_FOR_builtin_pklb,
+ CODE_FOR_builtin_pkwb,
+ CODE_FOR_builtin_unpkbl,
+ CODE_FOR_builtin_unpkbw,
+
+ /* TARGET_CIX */
+ CODE_FOR_ctzdi2,
+ CODE_FOR_clzdi2,
+ CODE_FOR_popcountdi2
+};
- case 'U':
- /* Similar, except do it from the mask. */
- if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xff)
- fprintf (file, "b");
- else if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xffff)
- fprintf (file, "w");
- else if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xffffffff)
- fprintf (file, "l");
-#if HOST_BITS_PER_WIDE_INT == 32
- else if (GET_CODE (x) == CONST_DOUBLE
- && CONST_DOUBLE_HIGH (x) == 0
- && CONST_DOUBLE_LOW (x) == -1)
- fprintf (file, "l");
- else if (GET_CODE (x) == CONST_DOUBLE
- && CONST_DOUBLE_HIGH (x) == -1
- && CONST_DOUBLE_LOW (x) == -1)
- fprintf (file, "q");
-#else
- else if (GET_CODE (x) == CONST_INT && INTVAL (x) == -1)
- fprintf (file, "q");
- else if (GET_CODE (x) == CONST_DOUBLE
- && CONST_DOUBLE_HIGH (x) == 0
- && CONST_DOUBLE_LOW (x) == -1)
- fprintf (file, "q");
-#endif
- else
- output_operand_lossage ("invalid %%U value");
- break;
+struct alpha_builtin_def
+{
+ const char *name;
+ enum alpha_builtin code;
+ unsigned int target_mask;
+ bool is_const;
+};
- case 's':
- /* Write the constant value divided by 8 for little-endian mode or
- (56 - value) / 8 for big-endian mode. */
+static struct alpha_builtin_def const zero_arg_builtins[] = {
+ { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER, 0, true },
+ { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC, 0, false }
+};
- if (GET_CODE (x) != CONST_INT
- || (unsigned HOST_WIDE_INT) INTVAL (x) >= (WORDS_BIG_ENDIAN
- ? 56
- : 64)
- || (INTVAL (x) & 7) != 0)
- output_operand_lossage ("invalid %%s value");
+static struct alpha_builtin_def const one_arg_builtins[] = {
+ { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK, 0, true },
+ { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB, MASK_MAX, true },
+ { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB, MASK_MAX, true },
+ { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL, MASK_MAX, true },
+ { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW, MASK_MAX, true },
+ { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ, MASK_CIX, true },
+ { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ, MASK_CIX, true },
+ { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP, MASK_CIX, true }
+};
- fprintf (file, HOST_WIDE_INT_PRINT_DEC,
- WORDS_BIG_ENDIAN
- ? (56 - INTVAL (x)) / 8
- : INTVAL (x) / 8);
- break;
+static struct alpha_builtin_def const two_arg_builtins[] = {
+ { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE, 0, true },
+ { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL, 0, true },
+ { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL, 0, true },
+ { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL, 0, true },
+ { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL, 0, true },
+ { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH, 0, true },
+ { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH, 0, true },
+ { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH, 0, true },
+ { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL, 0, true },
+ { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL, 0, true },
+ { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL, 0, true },
+ { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL, 0, true },
+ { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH, 0, true },
+ { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH, 0, true },
+ { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH, 0, true },
+ { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL, 0, true },
+ { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL, 0, true },
+ { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL, 0, true },
+ { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL, 0, true },
+ { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH, 0, true },
+ { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH, 0, true },
+ { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH, 0, true },
+ { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH, 0, true },
+ { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP, 0, true },
+ { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT, 0, true },
+ { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8, MASK_MAX, true },
+ { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8, MASK_MAX, true },
+ { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4, MASK_MAX, true },
+ { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4, MASK_MAX, true },
+ { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8, MASK_MAX, true },
+ { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8, MASK_MAX, true },
+ { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4, MASK_MAX, true },
+ { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4, MASK_MAX, true },
+ { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR, MASK_MAX, true }
+};
- case 'S':
- /* Same, except compute (64 - c) / 8 */
+static GTY(()) tree alpha_v8qi_u;
+static GTY(()) tree alpha_v8qi_s;
+static GTY(()) tree alpha_v4hi_u;
+static GTY(()) tree alpha_v4hi_s;
- if (GET_CODE (x) != CONST_INT
- && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64
- && (INTVAL (x) & 7) != 8)
- output_operand_lossage ("invalid %%s value");
+/* Helper function of alpha_init_builtins. Add the COUNT built-in
+ functions pointed to by P, with function type FTYPE. */
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, (64 - INTVAL (x)) / 8);
- break;
+static void
+alpha_add_builtins (const struct alpha_builtin_def *p, size_t count,
+ tree ftype)
+{
+ tree decl;
+ size_t i;
- case 't':
+ for (i = 0; i < count; ++i, ++p)
+ if ((target_flags & p->target_mask) == p->target_mask)
{
- /* On Unicos/Mk systems: use a DEX expression if the symbol
- clashes with a register name. */
- int dex = unicosmk_need_dex (x);
- if (dex)
- fprintf (file, "DEX(%d)", dex);
- else
- output_addr_const (file, x);
+ decl = add_builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
+ NULL, NULL);
+ if (p->is_const)
+ TREE_READONLY (decl) = 1;
+ TREE_NOTHROW (decl) = 1;
}
- break;
+}
- case 'C': case 'D': case 'c': case 'd':
- /* Write out comparison name. */
- {
- enum rtx_code c = GET_CODE (x);
- if (GET_RTX_CLASS (c) != '<')
- output_operand_lossage ("invalid %%C value");
+static void
+alpha_init_builtins (void)
+{
+ tree dimode_integer_type_node;
+ tree ftype, decl;
+
+ dimode_integer_type_node = lang_hooks.types.type_for_mode (DImode, 0);
- else if (code == 'D')
- c = reverse_condition (c);
- else if (code == 'c')
- c = swap_condition (c);
- else if (code == 'd')
- c = swap_condition (reverse_condition (c));
+ ftype = build_function_type (dimode_integer_type_node, void_list_node);
+ alpha_add_builtins (zero_arg_builtins, ARRAY_SIZE (zero_arg_builtins),
+ ftype);
- if (c == LEU)
- fprintf (file, "ule");
- else if (c == LTU)
- fprintf (file, "ult");
- else if (c == UNORDERED)
- fprintf (file, "un");
- else
- fprintf (file, "%s", GET_RTX_NAME (c));
- }
- break;
+ ftype = build_function_type_list (dimode_integer_type_node,
+ dimode_integer_type_node, NULL_TREE);
+ alpha_add_builtins (one_arg_builtins, ARRAY_SIZE (one_arg_builtins),
+ ftype);
- case 'E':
- /* Write the divide or modulus operator. */
- switch (GET_CODE (x))
- {
- case DIV:
- fprintf (file, "div%s", GET_MODE (x) == SImode ? "l" : "q");
- break;
- case UDIV:
- fprintf (file, "div%su", GET_MODE (x) == SImode ? "l" : "q");
- break;
- case MOD:
- fprintf (file, "rem%s", GET_MODE (x) == SImode ? "l" : "q");
- break;
- case UMOD:
- fprintf (file, "rem%su", GET_MODE (x) == SImode ? "l" : "q");
- break;
- default:
- output_operand_lossage ("invalid %%E value");
- break;
- }
- break;
+ ftype = build_function_type_list (dimode_integer_type_node,
+ dimode_integer_type_node,
+ dimode_integer_type_node, NULL_TREE);
+ alpha_add_builtins (two_arg_builtins, ARRAY_SIZE (two_arg_builtins),
+ ftype);
- case 'A':
- /* Write "_u" for unaligned access. */
- if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
- fprintf (file, "_u");
- break;
+ ftype = build_function_type (ptr_type_node, void_list_node);
+ decl = add_builtin_function ("__builtin_thread_pointer", ftype,
+ ALPHA_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
+ NULL, NULL);
+ TREE_NOTHROW (decl) = 1;
- case 0:
- if (GET_CODE (x) == REG)
- fprintf (file, "%s", reg_names[REGNO (x)]);
- else if (GET_CODE (x) == MEM)
- output_address (XEXP (x, 0));
- else
- output_addr_const (file, x);
- break;
+ ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
+ decl = add_builtin_function ("__builtin_set_thread_pointer", ftype,
+ ALPHA_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
+ NULL, NULL);
+ TREE_NOTHROW (decl) = 1;
- default:
- output_operand_lossage ("invalid %%xn code");
- }
+ alpha_v8qi_u = build_vector_type (unsigned_intQI_type_node, 8);
+ alpha_v8qi_s = build_vector_type (intQI_type_node, 8);
+ alpha_v4hi_u = build_vector_type (unsigned_intHI_type_node, 4);
+ alpha_v4hi_s = build_vector_type (intHI_type_node, 4);
}
-void
-print_operand_address (file, addr)
- FILE *file;
- rtx addr;
+/* Expand an expression EXP that calls a built-in function,
+ with result going to TARGET if that's convenient
+ (and in mode MODE if that's convenient).
+ SUBTARGET may be used as the target for computing one of EXP's operands.
+ IGNORE is nonzero if the value is to be ignored. */
+
+static rtx
+alpha_expand_builtin (tree exp, rtx target,
+ rtx subtarget ATTRIBUTE_UNUSED,
+ enum machine_mode mode ATTRIBUTE_UNUSED,
+ int ignore ATTRIBUTE_UNUSED)
{
- int basereg = 31;
- HOST_WIDE_INT offset = 0;
+#define MAX_ARGS 2
- if (GET_CODE (addr) == AND)
- addr = XEXP (addr, 0);
+ tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
+ unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
+ tree arg;
+ call_expr_arg_iterator iter;
+ enum insn_code icode;
+ rtx op[MAX_ARGS], pat;
+ int arity;
+ bool nonvoid;
- if (GET_CODE (addr) == PLUS
- && GET_CODE (XEXP (addr, 1)) == CONST_INT)
+ if (fcode >= ALPHA_BUILTIN_max)
+ internal_error ("bad builtin fcode");
+ icode = code_for_builtin[fcode];
+ if (icode == 0)
+ internal_error ("bad builtin fcode");
+
+ nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
+
+ arity = 0;
+ FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
{
- offset = INTVAL (XEXP (addr, 1));
- addr = XEXP (addr, 0);
+ const struct insn_operand_data *insn_op;
+
+ if (arg == error_mark_node)
+ return NULL_RTX;
+ if (arity > MAX_ARGS)
+ return NULL_RTX;
+
+ insn_op = &insn_data[icode].operand[arity + nonvoid];
+
+ op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0);
+
+ if (!(*insn_op->predicate) (op[arity], insn_op->mode))
+ op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
+ arity++;
}
- if (GET_CODE (addr) == LO_SUM)
+ if (nonvoid)
{
- output_addr_const (file, XEXP (addr, 1));
- if (offset)
- {
- fputc ('+', file);
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
- }
-
- addr = XEXP (addr, 0);
- if (GET_CODE (addr) == REG)
- basereg = REGNO (addr);
- else if (GET_CODE (addr) == SUBREG
- && GET_CODE (SUBREG_REG (addr)) == REG)
- basereg = subreg_regno (addr);
- else
- abort ();
+ enum machine_mode tmode = insn_data[icode].operand[0].mode;
+ if (!target
+ || GET_MODE (target) != tmode
+ || !(*insn_data[icode].operand[0].predicate) (target, tmode))
+ target = gen_reg_rtx (tmode);
+ }
- fprintf (file, "($%d)\t\t!%s", basereg,
- (basereg == 29 ? "gprel" : "gprellow"));
- return;
+ switch (arity)
+ {
+ case 0:
+ pat = GEN_FCN (icode) (target);
+ break;
+ case 1:
+ if (nonvoid)
+ pat = GEN_FCN (icode) (target, op[0]);
+ else
+ pat = GEN_FCN (icode) (op[0]);
+ break;
+ case 2:
+ pat = GEN_FCN (icode) (target, op[0], op[1]);
+ break;
+ default:
+ gcc_unreachable ();
}
+ if (!pat)
+ return NULL_RTX;
+ emit_insn (pat);
- if (GET_CODE (addr) == REG)
- basereg = REGNO (addr);
- else if (GET_CODE (addr) == SUBREG
- && GET_CODE (SUBREG_REG (addr)) == REG)
- basereg = subreg_regno (addr);
- else if (GET_CODE (addr) == CONST_INT)
- offset = INTVAL (addr);
+ if (nonvoid)
+ return target;
else
- abort ();
-
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
- fprintf (file, "($%d)", basereg);
+ return const0_rtx;
}
-\f
-/* Emit RTL insns to initialize the variable parts of a trampoline at
- TRAMP. FNADDR is an RTX for the address of the function's pure
- code. CXT is an RTX for the static chain value for the function.
-
- The three offset parameters are for the individual template's
- layout. A JMPOFS < 0 indicates that the trampoline does not
- contain instructions at all.
-
- We assume here that a function will be called many more times than
- its address is taken (e.g., it might be passed to qsort), so we
- take the trouble to initialize the "hint" field in the JMP insn.
- Note that the hint field is PC (new) + 4 * bits 13:0. */
-void
-alpha_initialize_trampoline (tramp, fnaddr, cxt, fnofs, cxtofs, jmpofs)
- rtx tramp, fnaddr, cxt;
- int fnofs, cxtofs, jmpofs;
-{
- rtx temp, temp1, addr;
- /* VMS really uses DImode pointers in memory at this point. */
- enum machine_mode mode = TARGET_ABI_OPEN_VMS ? Pmode : ptr_mode;
-#ifdef POINTERS_EXTEND_UNSIGNED
- fnaddr = convert_memory_address (mode, fnaddr);
- cxt = convert_memory_address (mode, cxt);
+/* Several bits below assume HWI >= 64 bits. This should be enforced
+ by config.gcc. */
+#if HOST_BITS_PER_WIDE_INT < 64
+# error "HOST_WIDE_INT too small"
#endif
- /* Store function address and CXT. */
- addr = memory_address (mode, plus_constant (tramp, fnofs));
- emit_move_insn (gen_rtx_MEM (mode, addr), fnaddr);
- addr = memory_address (mode, plus_constant (tramp, cxtofs));
- emit_move_insn (gen_rtx_MEM (mode, addr), cxt);
-
- /* This has been disabled since the hint only has a 32k range, and in
- no existing OS is the stack within 32k of the text segment. */
- if (0 && jmpofs >= 0)
- {
- /* Compute hint value. */
- temp = force_operand (plus_constant (tramp, jmpofs+4), NULL_RTX);
- temp = expand_binop (DImode, sub_optab, fnaddr, temp, temp, 1,
- OPTAB_WIDEN);
- temp = expand_shift (RSHIFT_EXPR, Pmode, temp,
- build_int_2 (2, 0), NULL_RTX, 1);
- temp = expand_and (SImode, gen_lowpart (SImode, temp),
- GEN_INT (0x3fff), 0);
-
- /* Merge in the hint. */
- addr = memory_address (SImode, plus_constant (tramp, jmpofs));
- temp1 = force_reg (SImode, gen_rtx_MEM (SImode, addr));
- temp1 = expand_and (SImode, temp1, GEN_INT (0xffffc000), NULL_RTX);
- temp1 = expand_binop (SImode, ior_optab, temp1, temp, temp1, 1,
- OPTAB_WIDEN);
- emit_move_insn (gen_rtx_MEM (SImode, addr), temp1);
- }
-
-#ifdef TRANSFER_FROM_TRAMPOLINE
- emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
- 0, VOIDmode, 1, addr, Pmode);
-#endif
+/* Fold the builtin for the CMPBGE instruction. This is a vector comparison
+ with an 8-bit output vector. OPINT contains the integer operands; bit N
+ of OP_CONST is set if OPINT[N] is valid. */
- if (jmpofs >= 0)
- emit_insn (gen_imb ());
+static tree
+alpha_fold_builtin_cmpbge (unsigned HOST_WIDE_INT opint[], long op_const)
+{
+ if (op_const == 3)
+ {
+ int i, val;
+ for (i = 0, val = 0; i < 8; ++i)
+ {
+ unsigned HOST_WIDE_INT c0 = (opint[0] >> (i * 8)) & 0xff;
+ unsigned HOST_WIDE_INT c1 = (opint[1] >> (i * 8)) & 0xff;
+ if (c0 >= c1)
+ val |= 1 << i;
+ }
+ return build_int_cst (long_integer_type_node, val);
+ }
+ else if (op_const == 2 && opint[1] == 0)
+ return build_int_cst (long_integer_type_node, 0xff);
+ return NULL;
}
-\f
-/* Determine where to put an argument to a function.
- Value is zero to push the argument on the stack,
- or a hard register in which to store the argument.
- MODE is the argument's machine mode.
- TYPE is the data type of the argument (as a tree).
- This is null for libcalls where that information may
- not be available.
- CUM is a variable of type CUMULATIVE_ARGS which gives info about
- the preceding args and about the function being called.
- NAMED is nonzero if this argument is a named parameter
- (otherwise it is an extra parameter matching an ellipsis).
+/* Fold the builtin for the ZAPNOT instruction. This is essentially a
+ specialized form of an AND operation. Other byte manipulation instructions
+ are defined in terms of this instruction, so this is also used as a
+ subroutine for other builtins.
- On Alpha the first 6 words of args are normally in registers
- and the rest are pushed. */
+ OP contains the tree operands; OPINT contains the extracted integer values.
+ Bit N of OP_CONST it set if OPINT[N] is valid. OP may be null if only
+ OPINT may be considered. */
-rtx
-function_arg (cum, mode, type, named)
- CUMULATIVE_ARGS cum;
- enum machine_mode mode;
- tree type;
- int named ATTRIBUTE_UNUSED;
+static tree
+alpha_fold_builtin_zapnot (tree *op, unsigned HOST_WIDE_INT opint[],
+ long op_const)
{
- int basereg;
- int num_args;
+ if (op_const & 2)
+ {
+ unsigned HOST_WIDE_INT mask = 0;
+ int i;
- /* Set up defaults for FP operands passed in FP registers, and
- integral operands passed in integer registers. */
- if (TARGET_FPREGS
- && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
- || GET_MODE_CLASS (mode) == MODE_FLOAT))
- basereg = 32 + 16;
- else
- basereg = 16;
+ for (i = 0; i < 8; ++i)
+ if ((opint[1] >> i) & 1)
+ mask |= (unsigned HOST_WIDE_INT)0xff << (i * 8);
- /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
- the three platforms, so we can't avoid conditional compilation. */
-#if TARGET_ABI_OPEN_VMS
- {
- if (mode == VOIDmode)
- return alpha_arg_info_reg_val (cum);
+ if (op_const & 1)
+ return build_int_cst (long_integer_type_node, opint[0] & mask);
- num_args = cum.num_args;
- if (num_args >= 6 || MUST_PASS_IN_STACK (mode, type))
- return NULL_RTX;
+ if (op)
+ return fold_build2 (BIT_AND_EXPR, long_integer_type_node, op[0],
+ build_int_cst (long_integer_type_node, mask));
}
-#else
-#if TARGET_ABI_UNICOSMK
+ else if ((op_const & 1) && opint[0] == 0)
+ return build_int_cst (long_integer_type_node, 0);
+ return NULL;
+}
+
+/* Fold the builtins for the EXT family of instructions. */
+
+static tree
+alpha_fold_builtin_extxx (tree op[], unsigned HOST_WIDE_INT opint[],
+ long op_const, unsigned HOST_WIDE_INT bytemask,
+ bool is_high)
+{
+ long zap_const = 2;
+ tree *zap_op = NULL;
+
+ if (op_const & 2)
{
- int size;
+ unsigned HOST_WIDE_INT loc;
- /* If this is the last argument, generate the call info word (CIW). */
- /* ??? We don't include the caller's line number in the CIW because
- I don't know how to determine it if debug infos are turned off. */
- if (mode == VOIDmode)
+ loc = opint[1] & 7;
+ if (BYTES_BIG_ENDIAN)
+ loc ^= 7;
+ loc *= 8;
+
+ if (loc != 0)
{
- int i;
- HOST_WIDE_INT lo;
- HOST_WIDE_INT hi;
- rtx ciw;
+ if (op_const & 1)
+ {
+ unsigned HOST_WIDE_INT temp = opint[0];
+ if (is_high)
+ temp <<= loc;
+ else
+ temp >>= loc;
+ opint[0] = temp;
+ zap_const = 3;
+ }
+ }
+ else
+ zap_op = op;
+ }
+
+ opint[1] = bytemask;
+ return alpha_fold_builtin_zapnot (zap_op, opint, zap_const);
+}
- lo = 0;
+/* Fold the builtins for the INS family of instructions. */
- for (i = 0; i < cum.num_reg_words && i < 5; i++)
- if (cum.reg_args_type[i])
- lo |= (1 << (7 - i));
+static tree
+alpha_fold_builtin_insxx (tree op[], unsigned HOST_WIDE_INT opint[],
+ long op_const, unsigned HOST_WIDE_INT bytemask,
+ bool is_high)
+{
+ if ((op_const & 1) && opint[0] == 0)
+ return build_int_cst (long_integer_type_node, 0);
- if (cum.num_reg_words == 6 && cum.reg_args_type[5])
- lo |= 7;
- else
- lo |= cum.num_reg_words;
+ if (op_const & 2)
+ {
+ unsigned HOST_WIDE_INT temp, loc, byteloc;
+ tree *zap_op = NULL;
-#if HOST_BITS_PER_WIDE_INT == 32
- hi = (cum.num_args << 20) | cum.num_arg_words;
-#else
- lo = lo | ((HOST_WIDE_INT) cum.num_args << 52)
- | ((HOST_WIDE_INT) cum.num_arg_words << 32);
- hi = 0;
-#endif
- ciw = immed_double_const (lo, hi, DImode);
+ loc = opint[1] & 7;
+ if (BYTES_BIG_ENDIAN)
+ loc ^= 7;
+ bytemask <<= loc;
- return gen_rtx_UNSPEC (DImode, gen_rtvec (1, ciw),
- UNSPEC_UMK_LOAD_CIW);
+ temp = opint[0];
+ if (is_high)
+ {
+ byteloc = (64 - (loc * 8)) & 0x3f;
+ if (byteloc == 0)
+ zap_op = op;
+ else
+ temp >>= byteloc;
+ bytemask >>= 8;
}
-
- size = ALPHA_ARG_SIZE (mode, type, named);
- num_args = cum.num_reg_words;
- if (MUST_PASS_IN_STACK (mode, type)
- || cum.num_reg_words + size > 6 || cum.force_stack)
- return NULL_RTX;
- else if (type && TYPE_MODE (type) == BLKmode)
+ else
{
- rtx reg1, reg2;
-
- reg1 = gen_rtx_REG (DImode, num_args + 16);
- reg1 = gen_rtx_EXPR_LIST (DImode, reg1, const0_rtx);
-
- /* The argument fits in two registers. Note that we still need to
- reserve a register for empty structures. */
- if (size == 0)
- return NULL_RTX;
- else if (size == 1)
- return gen_rtx_PARALLEL (mode, gen_rtvec (1, reg1));
+ byteloc = loc * 8;
+ if (byteloc == 0)
+ zap_op = op;
else
- {
- reg2 = gen_rtx_REG (DImode, num_args + 17);
- reg2 = gen_rtx_EXPR_LIST (DImode, reg2, GEN_INT (8));
- return gen_rtx_PARALLEL (mode, gen_rtvec (2, reg1, reg2));
- }
+ temp <<= byteloc;
}
+
+ opint[0] = temp;
+ opint[1] = bytemask;
+ return alpha_fold_builtin_zapnot (zap_op, opint, op_const);
}
-#else
+
+ return NULL;
+}
+
+static tree
+alpha_fold_builtin_mskxx (tree op[], unsigned HOST_WIDE_INT opint[],
+ long op_const, unsigned HOST_WIDE_INT bytemask,
+ bool is_high)
+{
+ if (op_const & 2)
{
- if (cum >= 6)
- return NULL_RTX;
- num_args = cum;
+ unsigned HOST_WIDE_INT loc;
- /* VOID is passed as a special flag for "last argument". */
- if (type == void_type_node)
- basereg = 16;
- else if (MUST_PASS_IN_STACK (mode, type))
- return NULL_RTX;
- else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum, mode, type, named))
- basereg = 16;
+ loc = opint[1] & 7;
+ if (BYTES_BIG_ENDIAN)
+ loc ^= 7;
+ bytemask <<= loc;
+
+ if (is_high)
+ bytemask >>= 8;
+
+ opint[1] = bytemask ^ 0xff;
+ }
+
+ return alpha_fold_builtin_zapnot (op, opint, op_const);
+}
+
+static tree
+alpha_fold_builtin_umulh (unsigned HOST_WIDE_INT opint[], long op_const)
+{
+ switch (op_const)
+ {
+ case 3:
+ {
+ unsigned HOST_WIDE_INT l;
+ HOST_WIDE_INT h;
+
+ mul_double (opint[0], 0, opint[1], 0, &l, &h);
+
+#if HOST_BITS_PER_WIDE_INT > 64
+# error fixme
+#endif
+
+ return build_int_cst (long_integer_type_node, h);
+ }
+
+ case 1:
+ opint[1] = opint[0];
+ /* FALLTHRU */
+ case 2:
+ /* Note that (X*1) >> 64 == 0. */
+ if (opint[1] == 0 || opint[1] == 1)
+ return build_int_cst (long_integer_type_node, 0);
+ break;
}
-#endif /* TARGET_ABI_UNICOSMK */
-#endif /* TARGET_ABI_OPEN_VMS */
+ return NULL;
+}
- return gen_rtx_REG (mode, num_args + basereg);
+static tree
+alpha_fold_vector_minmax (enum tree_code code, tree op[], tree vtype)
+{
+ tree op0 = fold_convert (vtype, op[0]);
+ tree op1 = fold_convert (vtype, op[1]);
+ tree val = fold_build2 (code, vtype, op0, op1);
+ return fold_build1 (VIEW_CONVERT_EXPR, long_integer_type_node, val);
}
-tree
-alpha_build_va_list ()
+static tree
+alpha_fold_builtin_perr (unsigned HOST_WIDE_INT opint[], long op_const)
{
- tree base, ofs, record, type_decl;
+ unsigned HOST_WIDE_INT temp = 0;
+ int i;
- if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
- return ptr_type_node;
+ if (op_const != 3)
+ return NULL;
- record = make_lang_type (RECORD_TYPE);
- type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
- TREE_CHAIN (record) = type_decl;
- TYPE_NAME (record) = type_decl;
+ for (i = 0; i < 8; ++i)
+ {
+ unsigned HOST_WIDE_INT a = (opint[0] >> (i * 8)) & 0xff;
+ unsigned HOST_WIDE_INT b = (opint[1] >> (i * 8)) & 0xff;
+ if (a >= b)
+ temp += a - b;
+ else
+ temp += b - a;
+ }
- /* C++? SET_IS_AGGR_TYPE (record, 1); */
+ return build_int_cst (long_integer_type_node, temp);
+}
- ofs = build_decl (FIELD_DECL, get_identifier ("__offset"),
- integer_type_node);
- DECL_FIELD_CONTEXT (ofs) = record;
+static tree
+alpha_fold_builtin_pklb (unsigned HOST_WIDE_INT opint[], long op_const)
+{
+ unsigned HOST_WIDE_INT temp;
- base = build_decl (FIELD_DECL, get_identifier ("__base"),
- ptr_type_node);
- DECL_FIELD_CONTEXT (base) = record;
- TREE_CHAIN (base) = ofs;
+ if (op_const == 0)
+ return NULL;
- TYPE_FIELDS (record) = base;
- layout_type (record);
+ temp = opint[0] & 0xff;
+ temp |= (opint[0] >> 24) & 0xff00;
- return record;
+ return build_int_cst (long_integer_type_node, temp);
}
-void
-alpha_va_start (stdarg_p, valist, nextarg)
- int stdarg_p;
- tree valist;
- rtx nextarg ATTRIBUTE_UNUSED;
+static tree
+alpha_fold_builtin_pkwb (unsigned HOST_WIDE_INT opint[], long op_const)
{
- HOST_WIDE_INT offset;
- tree t, offset_field, base_field;
+ unsigned HOST_WIDE_INT temp;
- if (TREE_CODE (TREE_TYPE (valist)) == ERROR_MARK)
- return;
+ if (op_const == 0)
+ return NULL;
- if (TARGET_ABI_UNICOSMK)
- std_expand_builtin_va_start (stdarg_p, valist, nextarg);
+ temp = opint[0] & 0xff;
+ temp |= (opint[0] >> 8) & 0xff00;
+ temp |= (opint[0] >> 16) & 0xff0000;
+ temp |= (opint[0] >> 24) & 0xff000000;
- /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
- up by 48, storing fp arg registers in the first 48 bytes, and the
- integer arg registers in the next 48 bytes. This is only done,
- however, if any integer registers need to be stored.
+ return build_int_cst (long_integer_type_node, temp);
+}
- If no integer registers need be stored, then we must subtract 48
- in order to account for the integer arg registers which are counted
- in argsize above, but which are not actually stored on the stack. */
+static tree
+alpha_fold_builtin_unpkbl (unsigned HOST_WIDE_INT opint[], long op_const)
+{
+ unsigned HOST_WIDE_INT temp;
- if (NUM_ARGS <= 5 + stdarg_p)
- offset = TARGET_ABI_OPEN_VMS ? UNITS_PER_WORD : 6 * UNITS_PER_WORD;
- else
- offset = -6 * UNITS_PER_WORD;
+ if (op_const == 0)
+ return NULL;
- if (TARGET_ABI_OPEN_VMS)
- {
- nextarg = plus_constant (nextarg, offset);
- nextarg = plus_constant (nextarg, NUM_ARGS * UNITS_PER_WORD);
- t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
- make_tree (ptr_type_node, nextarg));
- TREE_SIDE_EFFECTS (t) = 1;
+ temp = opint[0] & 0xff;
+ temp |= (opint[0] & 0xff00) << 24;
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
- }
- else
- {
- base_field = TYPE_FIELDS (TREE_TYPE (valist));
- offset_field = TREE_CHAIN (base_field);
+ return build_int_cst (long_integer_type_node, temp);
+}
- base_field = build (COMPONENT_REF, TREE_TYPE (base_field),
- valist, base_field);
- offset_field = build (COMPONENT_REF, TREE_TYPE (offset_field),
- valist, offset_field);
+static tree
+alpha_fold_builtin_unpkbw (unsigned HOST_WIDE_INT opint[], long op_const)
+{
+ unsigned HOST_WIDE_INT temp;
- t = make_tree (ptr_type_node, virtual_incoming_args_rtx);
- t = build (PLUS_EXPR, ptr_type_node, t, build_int_2 (offset, 0));
- t = build (MODIFY_EXPR, TREE_TYPE (base_field), base_field, t);
- TREE_SIDE_EFFECTS (t) = 1;
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
+ if (op_const == 0)
+ return NULL;
- t = build_int_2 (NUM_ARGS * UNITS_PER_WORD, 0);
- t = build (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field, t);
- TREE_SIDE_EFFECTS (t) = 1;
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
- }
+ temp = opint[0] & 0xff;
+ temp |= (opint[0] & 0x0000ff00) << 8;
+ temp |= (opint[0] & 0x00ff0000) << 16;
+ temp |= (opint[0] & 0xff000000) << 24;
+
+ return build_int_cst (long_integer_type_node, temp);
}
-rtx
-alpha_va_arg (valist, type)
- tree valist, type;
+static tree
+alpha_fold_builtin_cttz (unsigned HOST_WIDE_INT opint[], long op_const)
{
- rtx addr;
- tree t, type_size, rounded_size;
- tree offset_field, base_field, addr_tree, addend;
- tree wide_type, wide_ofs;
- int indirect = 0;
+ unsigned HOST_WIDE_INT temp;
- if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
- return std_expand_builtin_va_arg (valist, type);
+ if (op_const == 0)
+ return NULL;
- if (type == error_mark_node
- || (type_size = TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type))) == NULL
- || TREE_OVERFLOW (type_size))
- rounded_size = size_zero_node;
+ if (opint[0] == 0)
+ temp = 64;
else
- rounded_size = fold (build (MULT_EXPR, sizetype,
- fold (build (TRUNC_DIV_EXPR, sizetype,
- fold (build (PLUS_EXPR, sizetype,
- type_size,
- size_int (7))),
- size_int (8))),
- size_int (8)));
-
- base_field = TYPE_FIELDS (TREE_TYPE (valist));
- offset_field = TREE_CHAIN (base_field);
+ temp = exact_log2 (opint[0] & -opint[0]);
- base_field = build (COMPONENT_REF, TREE_TYPE (base_field),
- valist, base_field);
- offset_field = build (COMPONENT_REF, TREE_TYPE (offset_field),
- valist, offset_field);
+ return build_int_cst (long_integer_type_node, temp);
+}
- /* If the type could not be passed in registers, skip the block
- reserved for the registers. */
- if (MUST_PASS_IN_STACK (TYPE_MODE (type), type))
- {
- t = build (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field,
- build (MAX_EXPR, TREE_TYPE (offset_field),
- offset_field, build_int_2 (6*8, 0)));
- TREE_SIDE_EFFECTS (t) = 1;
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
- }
+static tree
+alpha_fold_builtin_ctlz (unsigned HOST_WIDE_INT opint[], long op_const)
+{
+ unsigned HOST_WIDE_INT temp;
- wide_type = make_signed_type (64);
- wide_ofs = save_expr (build1 (CONVERT_EXPR, wide_type, offset_field));
+ if (op_const == 0)
+ return NULL;
- addend = wide_ofs;
+ if (opint[0] == 0)
+ temp = 64;
+ else
+ temp = 64 - floor_log2 (opint[0]) - 1;
- if (TYPE_MODE (type) == TFmode || TYPE_MODE (type) == TCmode)
- {
- indirect = 1;
- rounded_size = size_int (UNITS_PER_WORD);
- }
- else if (FLOAT_TYPE_P (type))
- {
- tree fpaddend, cond;
+ return build_int_cst (long_integer_type_node, temp);
+}
- fpaddend = fold (build (PLUS_EXPR, TREE_TYPE (addend),
- addend, build_int_2 (-6*8, 0)));
+static tree
+alpha_fold_builtin_ctpop (unsigned HOST_WIDE_INT opint[], long op_const)
+{
+ unsigned HOST_WIDE_INT temp, op;
- cond = fold (build (LT_EXPR, integer_type_node,
- wide_ofs, build_int_2 (6*8, 0)));
+ if (op_const == 0)
+ return NULL;
- addend = fold (build (COND_EXPR, TREE_TYPE (addend), cond,
- fpaddend, addend));
- }
+ op = opint[0];
+ temp = 0;
+ while (op)
+ temp++, op &= op - 1;
- addr_tree = build (PLUS_EXPR, TREE_TYPE (base_field),
- base_field, addend);
+ return build_int_cst (long_integer_type_node, temp);
+}
- addr = expand_expr (addr_tree, NULL_RTX, Pmode, EXPAND_NORMAL);
- addr = copy_to_reg (addr);
+/* Fold one of our builtin functions. */
- t = build (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field,
- build (PLUS_EXPR, TREE_TYPE (offset_field),
- offset_field, rounded_size));
- TREE_SIDE_EFFECTS (t) = 1;
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
+static tree
+alpha_fold_builtin (tree fndecl, tree arglist, bool ignore ATTRIBUTE_UNUSED)
+{
+ tree op[MAX_ARGS], t;
+ unsigned HOST_WIDE_INT opint[MAX_ARGS];
+ long op_const = 0, arity = 0;
- if (indirect)
+ for (t = arglist; t ; t = TREE_CHAIN (t), ++arity)
{
- addr = force_reg (Pmode, addr);
- addr = gen_rtx_MEM (Pmode, addr);
+ tree arg = TREE_VALUE (t);
+ if (arg == error_mark_node)
+ return NULL;
+ if (arity >= MAX_ARGS)
+ return NULL;
+
+ op[arity] = arg;
+ opint[arity] = 0;
+ if (TREE_CODE (arg) == INTEGER_CST)
+ {
+ op_const |= 1L << arity;
+ opint[arity] = int_cst_value (arg);
+ }
}
- return addr;
+ switch (DECL_FUNCTION_CODE (fndecl))
+ {
+ case ALPHA_BUILTIN_CMPBGE:
+ return alpha_fold_builtin_cmpbge (opint, op_const);
+
+ case ALPHA_BUILTIN_EXTBL:
+ return alpha_fold_builtin_extxx (op, opint, op_const, 0x01, false);
+ case ALPHA_BUILTIN_EXTWL:
+ return alpha_fold_builtin_extxx (op, opint, op_const, 0x03, false);
+ case ALPHA_BUILTIN_EXTLL:
+ return alpha_fold_builtin_extxx (op, opint, op_const, 0x0f, false);
+ case ALPHA_BUILTIN_EXTQL:
+ return alpha_fold_builtin_extxx (op, opint, op_const, 0xff, false);
+ case ALPHA_BUILTIN_EXTWH:
+ return alpha_fold_builtin_extxx (op, opint, op_const, 0x03, true);
+ case ALPHA_BUILTIN_EXTLH:
+ return alpha_fold_builtin_extxx (op, opint, op_const, 0x0f, true);
+ case ALPHA_BUILTIN_EXTQH:
+ return alpha_fold_builtin_extxx (op, opint, op_const, 0xff, true);
+
+ case ALPHA_BUILTIN_INSBL:
+ return alpha_fold_builtin_insxx (op, opint, op_const, 0x01, false);
+ case ALPHA_BUILTIN_INSWL:
+ return alpha_fold_builtin_insxx (op, opint, op_const, 0x03, false);
+ case ALPHA_BUILTIN_INSLL:
+ return alpha_fold_builtin_insxx (op, opint, op_const, 0x0f, false);
+ case ALPHA_BUILTIN_INSQL:
+ return alpha_fold_builtin_insxx (op, opint, op_const, 0xff, false);
+ case ALPHA_BUILTIN_INSWH:
+ return alpha_fold_builtin_insxx (op, opint, op_const, 0x03, true);
+ case ALPHA_BUILTIN_INSLH:
+ return alpha_fold_builtin_insxx (op, opint, op_const, 0x0f, true);
+ case ALPHA_BUILTIN_INSQH:
+ return alpha_fold_builtin_insxx (op, opint, op_const, 0xff, true);
+
+ case ALPHA_BUILTIN_MSKBL:
+ return alpha_fold_builtin_mskxx (op, opint, op_const, 0x01, false);
+ case ALPHA_BUILTIN_MSKWL:
+ return alpha_fold_builtin_mskxx (op, opint, op_const, 0x03, false);
+ case ALPHA_BUILTIN_MSKLL:
+ return alpha_fold_builtin_mskxx (op, opint, op_const, 0x0f, false);
+ case ALPHA_BUILTIN_MSKQL:
+ return alpha_fold_builtin_mskxx (op, opint, op_const, 0xff, false);
+ case ALPHA_BUILTIN_MSKWH:
+ return alpha_fold_builtin_mskxx (op, opint, op_const, 0x03, true);
+ case ALPHA_BUILTIN_MSKLH:
+ return alpha_fold_builtin_mskxx (op, opint, op_const, 0x0f, true);
+ case ALPHA_BUILTIN_MSKQH:
+ return alpha_fold_builtin_mskxx (op, opint, op_const, 0xff, true);
+
+ case ALPHA_BUILTIN_UMULH:
+ return alpha_fold_builtin_umulh (opint, op_const);
+
+ case ALPHA_BUILTIN_ZAP:
+ opint[1] ^= 0xff;
+ /* FALLTHRU */
+ case ALPHA_BUILTIN_ZAPNOT:
+ return alpha_fold_builtin_zapnot (op, opint, op_const);
+
+ case ALPHA_BUILTIN_MINUB8:
+ return alpha_fold_vector_minmax (MIN_EXPR, op, alpha_v8qi_u);
+ case ALPHA_BUILTIN_MINSB8:
+ return alpha_fold_vector_minmax (MIN_EXPR, op, alpha_v8qi_s);
+ case ALPHA_BUILTIN_MINUW4:
+ return alpha_fold_vector_minmax (MIN_EXPR, op, alpha_v4hi_u);
+ case ALPHA_BUILTIN_MINSW4:
+ return alpha_fold_vector_minmax (MIN_EXPR, op, alpha_v4hi_s);
+ case ALPHA_BUILTIN_MAXUB8:
+ return alpha_fold_vector_minmax (MAX_EXPR, op, alpha_v8qi_u);
+ case ALPHA_BUILTIN_MAXSB8:
+ return alpha_fold_vector_minmax (MAX_EXPR, op, alpha_v8qi_s);
+ case ALPHA_BUILTIN_MAXUW4:
+ return alpha_fold_vector_minmax (MAX_EXPR, op, alpha_v4hi_u);
+ case ALPHA_BUILTIN_MAXSW4:
+ return alpha_fold_vector_minmax (MAX_EXPR, op, alpha_v4hi_s);
+
+ case ALPHA_BUILTIN_PERR:
+ return alpha_fold_builtin_perr (opint, op_const);
+ case ALPHA_BUILTIN_PKLB:
+ return alpha_fold_builtin_pklb (opint, op_const);
+ case ALPHA_BUILTIN_PKWB:
+ return alpha_fold_builtin_pkwb (opint, op_const);
+ case ALPHA_BUILTIN_UNPKBL:
+ return alpha_fold_builtin_unpkbl (opint, op_const);
+ case ALPHA_BUILTIN_UNPKBW:
+ return alpha_fold_builtin_unpkbw (opint, op_const);
+
+ case ALPHA_BUILTIN_CTTZ:
+ return alpha_fold_builtin_cttz (opint, op_const);
+ case ALPHA_BUILTIN_CTLZ:
+ return alpha_fold_builtin_ctlz (opint, op_const);
+ case ALPHA_BUILTIN_CTPOP:
+ return alpha_fold_builtin_ctpop (opint, op_const);
+
+ case ALPHA_BUILTIN_AMASK:
+ case ALPHA_BUILTIN_IMPLVER:
+ case ALPHA_BUILTIN_RPCC:
+ case ALPHA_BUILTIN_THREAD_POINTER:
+ case ALPHA_BUILTIN_SET_THREAD_POINTER:
+ /* None of these are foldable at compile-time. */
+ default:
+ return NULL;
+ }
}
\f
/* This page contains routines that are used to determine what the function
/* These variables are used for communication between the following functions.
They indicate various things about the current function being compiled
that are used to tell what kind of prologue, epilogue and procedure
- descriptior to generate. */
+ descriptor to generate. */
/* Nonzero if we need a stack procedure. */
enum alpha_procedure_types {PT_NULL = 0, PT_REGISTER = 1, PT_STACK = 2};
/* Compute register masks for saved registers. */
static void
-alpha_sa_mask (imaskP, fmaskP)
- unsigned long *imaskP;
- unsigned long *fmaskP;
+alpha_sa_mask (unsigned long *imaskP, unsigned long *fmaskP)
{
unsigned long imask = 0;
unsigned long fmask = 0;
unsigned int i;
- /* Irritatingly, there are two kinds of thunks -- those created with
- ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go through
- the regular part of the compiler. In the ASM_OUTPUT_MI_THUNK case
- we don't have valid register life info, but assemble_start_function
- wants to output .frame and .mask directives. */
- if (current_function_is_thunk && !no_new_pseudos)
+ /* When outputting a thunk, we don't have valid register life info,
+ but assemble_start_function wants to output .frame and .mask
+ directives. */
+ if (cfun->is_thunk)
{
*imaskP = 0;
*fmaskP = 0;
}
if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
- imask |= (1L << HARD_FRAME_POINTER_REGNUM);
+ imask |= (1UL << HARD_FRAME_POINTER_REGNUM);
/* One for every register we have to save. */
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
if (! fixed_regs[i] && ! call_used_regs[i]
- && regs_ever_live[i] && i != REG_RA
+ && df_regs_ever_live_p (i) && i != REG_RA
&& (!TARGET_ABI_UNICOSMK || i != HARD_FRAME_POINTER_REGNUM))
{
if (i < 32)
- imask |= (1L << i);
+ imask |= (1UL << i);
else
- fmask |= (1L << (i - 32));
+ fmask |= (1UL << (i - 32));
}
/* We need to restore these for the handler. */
- if (current_function_calls_eh_return)
- for (i = 0; ; ++i)
- {
- unsigned regno = EH_RETURN_DATA_REGNO (i);
- if (regno == INVALID_REGNUM)
- break;
- imask |= 1L << regno;
- }
-
+ if (crtl->calls_eh_return)
+ {
+ for (i = 0; ; ++i)
+ {
+ unsigned regno = EH_RETURN_DATA_REGNO (i);
+ if (regno == INVALID_REGNUM)
+ break;
+ imask |= 1UL << regno;
+ }
+ }
+
/* If any register spilled, then spill the return address also. */
/* ??? This is required by the Digital stack unwind specification
and isn't needed if we're doing Dwarf2 unwinding. */
if (imask || fmask || alpha_ra_ever_killed ())
- imask |= (1L << REG_RA);
+ imask |= (1UL << REG_RA);
*imaskP = imask;
*fmaskP = fmask;
}
int
-alpha_sa_size ()
+alpha_sa_size (void)
{
unsigned long mask[2];
int sa_size = 0;
alpha_procedure_type
= (sa_size || get_frame_size() != 0
- || current_function_outgoing_args_size || current_function_varargs
- || current_function_stdarg || current_function_calls_alloca
+ || crtl->outgoing_args_size
+ || cfun->stdarg || cfun->calls_alloca
|| frame_pointer_needed)
? PT_STACK : PT_REGISTER;
vms_base_regno
= (frame_pointer_needed
- || current_function_has_nonlocal_label
+ || cfun->has_nonlocal_label
|| alpha_procedure_type == PT_STACK
- || current_function_outgoing_args_size)
+ || crtl->outgoing_args_size)
? REG_PV : HARD_FRAME_POINTER_REGNUM;
/* If we want to copy PV into FP, we need to find some register
vms_save_fp_regno = -1;
if (vms_base_regno == HARD_FRAME_POINTER_REGNUM)
for (i = 0; i < 32; i++)
- if (! fixed_regs[i] && call_used_regs[i] && ! regs_ever_live[i])
+ if (! fixed_regs[i] && call_used_regs[i] && ! df_regs_ever_live_p (i))
vms_save_fp_regno = i;
if (vms_save_fp_regno == -1 && alpha_procedure_type == PT_REGISTER)
return sa_size * 8;
}
+/* Define the offset between two registers, one to be eliminated,
+ and the other its replacement, at the start of a routine. */
+
+HOST_WIDE_INT
+alpha_initial_elimination_offset (unsigned int from,
+ unsigned int to ATTRIBUTE_UNUSED)
+{
+ HOST_WIDE_INT ret;
+
+ ret = alpha_sa_size ();
+ ret += ALPHA_ROUND (crtl->outgoing_args_size);
+
+ switch (from)
+ {
+ case FRAME_POINTER_REGNUM:
+ break;
+
+ case ARG_POINTER_REGNUM:
+ ret += (ALPHA_ROUND (get_frame_size ()
+ + crtl->args.pretend_args_size)
+ - crtl->args.pretend_args_size);
+ break;
+
+ default:
+ gcc_unreachable ();
+ }
+
+ return ret;
+}
+
int
-alpha_pv_save_size ()
+alpha_pv_save_size (void)
{
alpha_sa_size ();
return alpha_procedure_type == PT_STACK ? 8 : 0;
}
int
-alpha_using_fp ()
+alpha_using_fp (void)
{
alpha_sa_size ();
return vms_unwind_regno == HARD_FRAME_POINTER_REGNUM;
#endif
static int
-find_lo_sum (px, data)
- rtx *px;
- void *data ATTRIBUTE_UNUSED;
+find_lo_sum_using_gp (rtx *px, void *data ATTRIBUTE_UNUSED)
+{
+ return GET_CODE (*px) == LO_SUM && XEXP (*px, 0) == pic_offset_table_rtx;
+}
+
+int
+alpha_find_lo_sum_using_gp (rtx insn)
{
- return GET_CODE (*px) == LO_SUM;
+ return for_each_rtx (&PATTERN (insn), find_lo_sum_using_gp, NULL) > 0;
}
static int
-alpha_does_function_need_gp ()
+alpha_does_function_need_gp (void)
{
rtx insn;
if (! TARGET_ABI_OSF)
return 0;
- if (TARGET_PROFILING_NEEDS_GP && current_function_profile)
+ /* We need the gp to load the address of __mcount. */
+ if (TARGET_PROFILING_NEEDS_GP && crtl->profile)
+ return 1;
+
+ /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
+ if (cfun->is_thunk)
return 1;
- if (current_function_is_thunk)
+ /* The nonlocal receiver pattern assumes that the gp is valid for
+ the nested function. Reasonable because it's almost always set
+ correctly already. For the cases where that's wrong, make sure
+ the nested function loads its gp on entry. */
+ if (crtl->has_nonlocal_goto)
return 1;
- /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
+ /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
Even if we are a static function, we still need to do this in case
our address is taken and passed to something like qsort. */
for (; insn; insn = NEXT_INSN (insn))
if (INSN_P (insn)
+ && ! JUMP_TABLE_DATA_P (insn)
&& GET_CODE (PATTERN (insn)) != USE
- && GET_CODE (PATTERN (insn)) != CLOBBER)
- {
- enum attr_type type = get_attr_type (insn);
- if (type == TYPE_LDSYM || type == TYPE_JSR)
- return 1;
- if (TARGET_EXPLICIT_RELOCS
- && for_each_rtx (&PATTERN (insn), find_lo_sum, NULL) > 0)
- return 1;
- }
+ && GET_CODE (PATTERN (insn)) != CLOBBER
+ && get_attr_usegp (insn))
+ return 1;
return 0;
}
-/* Write a version stamp. Don't write anything if we are running as a
- cross-compiler. Otherwise, use the versions in /usr/include/stamp.h. */
-
-#ifdef HAVE_STAMP_H
-#include <stamp.h>
-#endif
-
-void
-alpha_write_verstamp (file)
- FILE *file ATTRIBUTE_UNUSED;
-{
-#ifdef MS_STAMP
- fprintf (file, "\t.verstamp %d %d\n", MS_STAMP, LS_STAMP);
-#endif
-}
\f
/* Helper function to set RTX_FRAME_RELATED_P on instructions, including
sequences. */
static rtx
-set_frame_related_p ()
+set_frame_related_p (void)
{
- rtx seq = gen_sequence ();
+ rtx seq = get_insns ();
+ rtx insn;
+
end_sequence ();
- if (GET_CODE (seq) == SEQUENCE)
+ if (!seq)
+ return NULL_RTX;
+
+ if (INSN_P (seq))
{
- int i = XVECLEN (seq, 0);
- while (--i >= 0)
- RTX_FRAME_RELATED_P (XVECEXP (seq, 0, i)) = 1;
- return emit_insn (seq);
+ insn = seq;
+ while (insn != NULL_RTX)
+ {
+ RTX_FRAME_RELATED_P (insn) = 1;
+ insn = NEXT_INSN (insn);
+ }
+ seq = emit_insn (seq);
}
else
{
seq = emit_insn (seq);
RTX_FRAME_RELATED_P (seq) = 1;
- return seq;
}
+ return seq;
}
#define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
+/* Generates a store with the proper unwind info attached. VALUE is
+ stored at BASE_REG+BASE_OFS. If FRAME_BIAS is nonzero, then BASE_REG
+ contains SP+FRAME_BIAS, and that is the unwind info that should be
+ generated. If FRAME_REG != VALUE, then VALUE is being stored on
+ behalf of FRAME_REG, and FRAME_REG should be present in the unwind. */
+
+static void
+emit_frame_store_1 (rtx value, rtx base_reg, HOST_WIDE_INT frame_bias,
+ HOST_WIDE_INT base_ofs, rtx frame_reg)
+{
+ rtx addr, mem, insn;
+
+ addr = plus_constant (base_reg, base_ofs);
+ mem = gen_rtx_MEM (DImode, addr);
+ set_mem_alias_set (mem, alpha_sr_alias_set);
+
+ insn = emit_move_insn (mem, value);
+ RTX_FRAME_RELATED_P (insn) = 1;
+
+ if (frame_bias || value != frame_reg)
+ {
+ if (frame_bias)
+ {
+ addr = plus_constant (stack_pointer_rtx, frame_bias + base_ofs);
+ mem = gen_rtx_MEM (DImode, addr);
+ }
+
+ REG_NOTES (insn)
+ = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
+ gen_rtx_SET (VOIDmode, mem, frame_reg),
+ REG_NOTES (insn));
+ }
+}
+
+static void
+emit_frame_store (unsigned int regno, rtx base_reg,
+ HOST_WIDE_INT frame_bias, HOST_WIDE_INT base_ofs)
+{
+ rtx reg = gen_rtx_REG (DImode, regno);
+ emit_frame_store_1 (reg, base_reg, frame_bias, base_ofs, reg);
+}
+
/* Write function prologue. */
/* On vms we have two kinds of functions:
simply allocate stack without saving registers. */
void
-alpha_expand_prologue ()
+alpha_expand_prologue (void)
{
/* Registers to save. */
unsigned long imask = 0;
HOST_WIDE_INT frame_size;
/* Offset from base reg to register save area. */
HOST_WIDE_INT reg_offset;
- rtx sa_reg, mem;
+ rtx sa_reg;
int i;
sa_size = alpha_sa_size ();
frame_size = get_frame_size ();
if (TARGET_ABI_OPEN_VMS)
- frame_size = ALPHA_ROUND (sa_size
+ frame_size = ALPHA_ROUND (sa_size
+ (alpha_procedure_type == PT_STACK ? 8 : 0)
+ frame_size
- + current_function_pretend_args_size);
+ + crtl->args.pretend_args_size);
else if (TARGET_ABI_UNICOSMK)
/* We have to allocate space for the DSIB if we generate a frame. */
frame_size = ALPHA_ROUND (sa_size
+ (alpha_procedure_type == PT_STACK ? 48 : 0))
+ ALPHA_ROUND (frame_size
- + current_function_outgoing_args_size);
+ + crtl->outgoing_args_size);
else
- frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
+ frame_size = (ALPHA_ROUND (crtl->outgoing_args_size)
+ sa_size
+ ALPHA_ROUND (frame_size
- + current_function_pretend_args_size));
+ + crtl->args.pretend_args_size));
if (TARGET_ABI_OPEN_VMS)
reg_offset = 8;
else
- reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
+ reg_offset = ALPHA_ROUND (crtl->outgoing_args_size);
alpha_sa_mask (&imask, &fmask);
the call to mcount ourselves, rather than having the linker do it
magically in response to -pg. Since _mcount has special linkage,
don't represent the call as a call. */
- if (TARGET_PROFILING_NEEDS_GP && current_function_profile)
+ if (TARGET_PROFILING_NEEDS_GP && crtl->profile)
emit_insn (gen_prologue_mcount ());
if (TARGET_ABI_UNICOSMK)
4096 bytes (we can probably get away without the latter test) and
every 8192 bytes in between. If the frame size is > 32768, we
do this in a loop. Otherwise, we generate the explicit probe
- instructions.
+ instructions.
Note that we are only allowed to adjust sp once in the prologue. */
{
if (frame_size > 4096)
{
- int probed = 4096;
+ int probed;
- do
+ for (probed = 4096; probed < frame_size; probed += 8192)
emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
? -probed + 64
: -probed)));
- while ((probed += 8192) < frame_size);
/* We only have to do this probe if we aren't saving registers. */
- if (sa_size == 0 && probed + 4096 < frame_size)
+ if (sa_size == 0 && frame_size > probed - 4096)
emit_insn (gen_probe_stack (GEN_INT (-frame_size)));
}
/* For NT stack unwind (done by 'reverse execution'), it's
not OK to take the result of a loop, even though the value
is already in ptr, so we reload it via a single operation
- and subtract it to sp.
+ and subtract it to sp.
Yes, that's correct -- we have to reload the whole constant
- into a temporary via ldah+lda then subtract from sp. To
- ensure we get ldah+lda, we use a special pattern. */
+ into a temporary via ldah+lda then subtract from sp. */
HOST_WIDE_INT lo, hi;
lo = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
hi = frame_size - lo;
emit_move_insn (ptr, GEN_INT (hi));
- emit_insn (gen_nt_lda (ptr, GEN_INT (lo)));
+ emit_insn (gen_adddi3 (ptr, ptr, GEN_INT (lo)));
seq = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
ptr));
}
if (!TARGET_ABI_UNICOSMK)
{
+ HOST_WIDE_INT sa_bias = 0;
+
/* Cope with very large offsets to the register save area. */
sa_reg = stack_pointer_rtx;
if (reg_offset + sa_size > 0x8000)
{
int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
- HOST_WIDE_INT bias;
+ rtx sa_bias_rtx;
if (low + sa_size <= 0x8000)
- bias = reg_offset - low, reg_offset = low;
- else
- bias = reg_offset, reg_offset = 0;
+ sa_bias = reg_offset - low, reg_offset = low;
+ else
+ sa_bias = reg_offset, reg_offset = 0;
sa_reg = gen_rtx_REG (DImode, 24);
- FRP (emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx,
- GEN_INT (bias))));
+ sa_bias_rtx = GEN_INT (sa_bias);
+
+ if (add_operand (sa_bias_rtx, DImode))
+ emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx, sa_bias_rtx));
+ else
+ {
+ emit_move_insn (sa_reg, sa_bias_rtx);
+ emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx, sa_reg));
+ }
}
-
+
/* Save regs in stack order. Beginning with VMS PV. */
if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
- {
- mem = gen_rtx_MEM (DImode, stack_pointer_rtx);
- set_mem_alias_set (mem, alpha_sr_alias_set);
- FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_PV)));
- }
+ emit_frame_store (REG_PV, stack_pointer_rtx, 0, 0);
/* Save register RA next. */
- if (imask & (1L << REG_RA))
+ if (imask & (1UL << REG_RA))
{
- mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
- set_mem_alias_set (mem, alpha_sr_alias_set);
- FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA)));
- imask &= ~(1L << REG_RA);
+ emit_frame_store (REG_RA, sa_reg, sa_bias, reg_offset);
+ imask &= ~(1UL << REG_RA);
reg_offset += 8;
}
/* Now save any other registers required to be saved. */
- for (i = 0; i < 32; i++)
- if (imask & (1L << i))
+ for (i = 0; i < 31; i++)
+ if (imask & (1UL << i))
{
- mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
- set_mem_alias_set (mem, alpha_sr_alias_set);
- FRP (emit_move_insn (mem, gen_rtx_REG (DImode, i)));
+ emit_frame_store (i, sa_reg, sa_bias, reg_offset);
reg_offset += 8;
}
- for (i = 0; i < 32; i++)
- if (fmask & (1L << i))
+ for (i = 0; i < 31; i++)
+ if (fmask & (1UL << i))
{
- mem = gen_rtx_MEM (DFmode, plus_constant (sa_reg, reg_offset));
- set_mem_alias_set (mem, alpha_sr_alias_set);
- FRP (emit_move_insn (mem, gen_rtx_REG (DFmode, i+32)));
+ emit_frame_store (i+32, sa_reg, sa_bias, reg_offset);
reg_offset += 8;
}
}
reg_offset = -56;
for (i = 9; i < 15; i++)
- if (imask & (1L << i))
+ if (imask & (1UL << i))
{
- mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx,
- reg_offset));
- set_mem_alias_set (mem, alpha_sr_alias_set);
- FRP (emit_move_insn (mem, gen_rtx_REG (DImode, i)));
+ emit_frame_store (i, hard_frame_pointer_rtx, 0, reg_offset);
reg_offset -= 8;
}
for (i = 2; i < 10; i++)
- if (fmask & (1L << i))
+ if (fmask & (1UL << i))
{
- mem = gen_rtx_MEM (DFmode, plus_constant (hard_frame_pointer_rtx,
- reg_offset));
- set_mem_alias_set (mem, alpha_sr_alias_set);
- FRP (emit_move_insn (mem, gen_rtx_REG (DFmode, i+32)));
+ emit_frame_store (i+32, hard_frame_pointer_rtx, 0, reg_offset);
reg_offset -= 8;
}
}
FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
/* If we have to allocate space for outgoing args, do it now. */
- if (current_function_outgoing_args_size != 0)
- FRP (emit_move_insn
- (stack_pointer_rtx,
- plus_constant (hard_frame_pointer_rtx,
- - (ALPHA_ROUND
- (current_function_outgoing_args_size)))));
+ if (crtl->outgoing_args_size != 0)
+ {
+ rtx seq
+ = emit_move_insn (stack_pointer_rtx,
+ plus_constant
+ (hard_frame_pointer_rtx,
+ - (ALPHA_ROUND
+ (crtl->outgoing_args_size))));
+
+ /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
+ if ! frame_pointer_needed. Setting the bit will change the CFA
+ computation rule to use sp again, which would be wrong if we had
+ frame_pointer_needed, as this means sp might move unpredictably
+ later on.
+
+ Also, note that
+ frame_pointer_needed
+ => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
+ and
+ crtl->outgoing_args_size != 0
+ => alpha_procedure_type != PT_NULL,
+
+ so when we are not setting the bit here, we are guaranteed to
+ have emitted an FRP frame pointer update just before. */
+ RTX_FRAME_RELATED_P (seq) = ! frame_pointer_needed;
+ }
}
else if (!TARGET_ABI_UNICOSMK)
{
(clobber:BLK (scratch)), but this doesn't work for fp insns. So we
have to prevent all such scheduling with a blockage.
- Linux, on the other hand, never bothered to implement OSF/1's
+ Linux, on the other hand, never bothered to implement OSF/1's
exception handling, and so doesn't care about such things. Anyone
planning to use dwarf2 frame-unwind info can also omit the blockage. */
emit_insn (gen_blockage ());
}
+/* Count the number of .file directives, so that .loc is up to date. */
+int num_source_filenames = 0;
+
/* Output the textual info surrounding the prologue. */
void
-alpha_start_function (file, fnname, decl)
- FILE *file;
- const char *fnname;
- tree decl ATTRIBUTE_UNUSED;
+alpha_start_function (FILE *file, const char *fnname,
+ tree decl ATTRIBUTE_UNUSED)
{
unsigned long imask = 0;
unsigned long fmask = 0;
/* Stack space needed for pushing registers clobbered by us. */
HOST_WIDE_INT sa_size;
/* Complete stack size needed. */
- HOST_WIDE_INT frame_size;
+ unsigned HOST_WIDE_INT frame_size;
+ /* The maximum debuggable frame size (512 Kbytes using Tru64 as). */
+ unsigned HOST_WIDE_INT max_frame_size = TARGET_ABI_OSF && !TARGET_GAS
+ ? 524288
+ : 1UL << 31;
/* Offset from base reg to register save area. */
HOST_WIDE_INT reg_offset;
char *entry_label = (char *) alloca (strlen (fnname) + 6);
frame_size = get_frame_size ();
if (TARGET_ABI_OPEN_VMS)
- frame_size = ALPHA_ROUND (sa_size
+ frame_size = ALPHA_ROUND (sa_size
+ (alpha_procedure_type == PT_STACK ? 8 : 0)
+ frame_size
- + current_function_pretend_args_size);
+ + crtl->args.pretend_args_size);
else if (TARGET_ABI_UNICOSMK)
frame_size = ALPHA_ROUND (sa_size
+ (alpha_procedure_type == PT_STACK ? 48 : 0))
+ ALPHA_ROUND (frame_size
- + current_function_outgoing_args_size);
+ + crtl->outgoing_args_size);
else
- frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
+ frame_size = (ALPHA_ROUND (crtl->outgoing_args_size)
+ sa_size
+ ALPHA_ROUND (frame_size
- + current_function_pretend_args_size));
+ + crtl->args.pretend_args_size));
if (TARGET_ABI_OPEN_VMS)
reg_offset = 8;
else
- reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
+ reg_offset = ALPHA_ROUND (crtl->outgoing_args_size);
alpha_sa_mask (&imask, &fmask);
ASM_OUTPUT_SOURCE_FILENAME (file,
DECL_SOURCE_FILE (current_function_decl));
#endif
-#ifdef ASM_OUTPUT_SOURCE_LINE
+#ifdef SDB_OUTPUT_SOURCE_LINE
if (debug_info_level != DINFO_LEVEL_TERSE)
- ASM_OUTPUT_SOURCE_LINE (file,
+ SDB_OUTPUT_SOURCE_LINE (file,
DECL_SOURCE_LINE (current_function_decl));
#endif
}
Otherwise, do it here. */
if (TARGET_ABI_OSF
&& ! alpha_function_needs_gp
- && ! current_function_is_thunk)
+ && ! cfun->is_thunk)
{
putc ('$', file);
assemble_name (file, fnname);
}
/* Set up offsets to alpha virtual arg/local debugging pointer. */
- alpha_auto_offset = -frame_size + current_function_pretend_args_size;
+ alpha_auto_offset = -frame_size + crtl->args.pretend_args_size;
alpha_arg_offset = -frame_size + 48;
/* Describe our frame. If the frame size is larger than an integer,
if (TARGET_ABI_UNICOSMK)
;
else if (TARGET_ABI_OPEN_VMS)
- {
- fprintf (file, "\t.frame $%d,", vms_unwind_regno);
- fprintf (file, HOST_WIDE_INT_PRINT_DEC,
- frame_size >= ((HOST_WIDE_INT) 1 << 31) ? 0 : frame_size);
- fputs (",$26,", file);
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, reg_offset);
- fputs ("\n", file);
- }
+ fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26,"
+ HOST_WIDE_INT_PRINT_DEC "\n",
+ vms_unwind_regno,
+ frame_size >= (1UL << 31) ? 0 : frame_size,
+ reg_offset);
else if (!flag_inhibit_size_directive)
- {
- fprintf (file, "\t.frame $%d,",
- (frame_pointer_needed
- ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM));
- fprintf (file, HOST_WIDE_INT_PRINT_DEC,
- frame_size >= (1l << 31) ? 0 : frame_size);
- fprintf (file, ",$26,%d\n", current_function_pretend_args_size);
- }
+ fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26,%d\n",
+ (frame_pointer_needed
+ ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM),
+ frame_size >= max_frame_size ? 0 : frame_size,
+ crtl->args.pretend_args_size);
/* Describe which registers were spilled. */
if (TARGET_ABI_UNICOSMK)
if (imask)
/* ??? Does VMS care if mask contains ra? The old code didn't
set it, so I don't here. */
- fprintf (file, "\t.mask 0x%lx,0\n", imask & ~(1L << REG_RA));
+ fprintf (file, "\t.mask 0x%lx,0\n", imask & ~(1UL << REG_RA));
if (fmask)
fprintf (file, "\t.fmask 0x%lx,0\n", fmask);
if (alpha_procedure_type == PT_REGISTER)
{
if (imask)
{
- fprintf (file, "\t.mask 0x%lx,", imask);
- fprintf (file, HOST_WIDE_INT_PRINT_DEC,
- frame_size >= (1l << 31) ? 0 : reg_offset - frame_size);
- putc ('\n', file);
+ fprintf (file, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", imask,
+ frame_size >= max_frame_size ? 0 : reg_offset - frame_size);
for (i = 0; i < 32; ++i)
- if (imask & (1L << i))
+ if (imask & (1UL << i))
reg_offset += 8;
}
if (fmask)
- {
- fprintf (file, "\t.fmask 0x%lx,", fmask);
- fprintf (file, HOST_WIDE_INT_PRINT_DEC,
- frame_size >= (1l << 31) ? 0 : reg_offset - frame_size);
- putc ('\n', file);
- }
+ fprintf (file, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", fmask,
+ frame_size >= max_frame_size ? 0 : reg_offset - frame_size);
}
#if TARGET_ABI_OPEN_VMS
- /* Ifdef'ed cause readonly_section and link_section are only
- available then. */
- readonly_section ();
+ /* Ifdef'ed cause link_section are only available then. */
+ switch_to_section (readonly_data_section);
fprintf (file, "\t.align 3\n");
assemble_name (file, fnname); fputs ("..na:\n", file);
fputs ("\t.ascii \"", file);
assemble_name (file, fnname);
fputs ("\\0\"\n", file);
-
- link_section ();
- fprintf (file, "\t.align 3\n");
- fputs ("\t.name ", file);
- assemble_name (file, fnname);
- fputs ("..na\n", file);
- ASM_OUTPUT_LABEL (file, fnname);
- fprintf (file, "\t.pdesc ");
- assemble_name (file, fnname);
- fprintf (file, "..en,%s\n",
- alpha_procedure_type == PT_STACK ? "stack"
- : alpha_procedure_type == PT_REGISTER ? "reg" : "null");
alpha_need_linkage (fnname, 1);
- text_section ();
+ switch_to_section (text_section);
#endif
}
/* Emit the .prologue note at the scheduled end of the prologue. */
static void
-alpha_output_function_end_prologue (file)
- FILE *file;
+alpha_output_function_end_prologue (FILE *file)
{
if (TARGET_ABI_UNICOSMK)
;
fputs ("\t.prologue 0\n", file);
else if (!flag_inhibit_size_directive)
fprintf (file, "\t.prologue %d\n",
- alpha_function_needs_gp || current_function_is_thunk);
+ alpha_function_needs_gp || cfun->is_thunk);
}
/* Write function epilogue. */
-/* ??? At some point we will want to support full unwind, and so will
+/* ??? At some point we will want to support full unwind, and so will
need to mark the epilogue as well. At the moment, we just confuse
dwarf2out. */
#undef FRP
#define FRP(exp) exp
void
-alpha_expand_epilogue ()
+alpha_expand_epilogue (void)
{
/* Registers to save. */
unsigned long imask = 0;
frame_size = get_frame_size ();
if (TARGET_ABI_OPEN_VMS)
- frame_size = ALPHA_ROUND (sa_size
+ frame_size = ALPHA_ROUND (sa_size
+ (alpha_procedure_type == PT_STACK ? 8 : 0)
+ frame_size
- + current_function_pretend_args_size);
+ + crtl->args.pretend_args_size);
else if (TARGET_ABI_UNICOSMK)
frame_size = ALPHA_ROUND (sa_size
+ (alpha_procedure_type == PT_STACK ? 48 : 0))
+ ALPHA_ROUND (frame_size
- + current_function_outgoing_args_size);
+ + crtl->outgoing_args_size);
else
- frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
+ frame_size = (ALPHA_ROUND (crtl->outgoing_args_size)
+ sa_size
+ ALPHA_ROUND (frame_size
- + current_function_pretend_args_size));
+ + crtl->args.pretend_args_size));
if (TARGET_ABI_OPEN_VMS)
{
reg_offset = 0;
}
else
- reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
+ reg_offset = ALPHA_ROUND (crtl->outgoing_args_size);
alpha_sa_mask (&imask, &fmask);
fp_offset = 0;
sa_reg = stack_pointer_rtx;
- if (current_function_calls_eh_return)
+ if (crtl->calls_eh_return)
eh_ofs = EH_RETURN_STACKADJ_RTX;
else
eh_ofs = NULL_RTX;
if (low + sa_size <= 0x8000)
bias = reg_offset - low, reg_offset = low;
- else
+ else
bias = reg_offset, reg_offset = 0;
sa_reg = gen_rtx_REG (DImode, 22);
FRP (emit_move_insn (sa_reg, sa_reg_exp));
}
-
+
/* Restore registers in order, excepting a true frame pointer. */
mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA), mem));
reg_offset += 8;
- imask &= ~(1L << REG_RA);
+ imask &= ~(1UL << REG_RA);
- for (i = 0; i < 32; ++i)
- if (imask & (1L << i))
+ for (i = 0; i < 31; ++i)
+ if (imask & (1UL << i))
{
if (i == HARD_FRAME_POINTER_REGNUM && fp_is_frame_pointer)
fp_offset = reg_offset;
reg_offset += 8;
}
- for (i = 0; i < 32; ++i)
- if (fmask & (1L << i))
+ for (i = 0; i < 31; ++i)
+ if (fmask & (1UL << i))
{
mem = gen_rtx_MEM (DFmode, plus_constant(sa_reg, reg_offset));
set_mem_alias_set (mem, alpha_sr_alias_set);
reg_offset = -56;
for (i = 9; i < 15; i++)
- if (imask & (1L << i))
+ if (imask & (1UL << i))
{
mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx,
reg_offset));
}
for (i = 2; i < 10; i++)
- if (fmask & (1L << i))
+ if (fmask & (1UL << i))
{
mem = gen_rtx_MEM (DFmode, plus_constant(hard_frame_pointer_rtx,
reg_offset));
register so as not to interfere with a potential fp restore,
which must be consecutive with an SP restore. */
if (frame_size < 32768
- && ! (TARGET_ABI_UNICOSMK && current_function_calls_alloca))
+ && ! (TARGET_ABI_UNICOSMK && cfun->calls_alloca))
sp_adj2 = GEN_INT (frame_size);
else if (TARGET_ABI_UNICOSMK)
{
else
{
rtx tmp = gen_rtx_REG (DImode, 23);
- FRP (sp_adj2 = alpha_emit_set_const (tmp, DImode, frame_size, 3));
+ FRP (sp_adj2 = alpha_emit_set_const (tmp, DImode, frame_size,
+ 3, false));
if (!sp_adj2)
{
/* We can't drop new things to memory this late, afaik,
so build it up by pieces. */
FRP (sp_adj2 = alpha_emit_set_long_const (tmp, frame_size,
-(frame_size < 0)));
- if (!sp_adj2)
- abort ();
+ gcc_assert (sp_adj2);
}
}
FRP (emit_move_insn (stack_pointer_rtx,
gen_rtx_PLUS (DImode, sp_adj1, sp_adj2)));
}
- else
+ else
{
if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_REGISTER)
{
emit_insn (gen_blockage ());
FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
- hard_frame_pointer_rtx, GEN_INT (-1))));
+ hard_frame_pointer_rtx, constm1_rtx)));
}
}
}
-
+\f
/* Output the rest of the textual info surrounding the epilogue. */
void
-alpha_end_function (file, fnname, decl)
- FILE *file;
- const char *fnname;
- tree decl ATTRIBUTE_UNUSED;
+alpha_end_function (FILE *file, const char *fnname, tree decl ATTRIBUTE_UNUSED)
{
+ rtx insn;
+
+ /* We output a nop after noreturn calls at the very end of the function to
+ ensure that the return address always remains in the caller's code range,
+ as not doing so might confuse unwinding engines. */
+ insn = get_last_insn ();
+ if (!INSN_P (insn))
+ insn = prev_active_insn (insn);
+ if (insn && GET_CODE (insn) == CALL_INSN)
+ output_asm_insn (get_insn_template (CODE_FOR_nop, NULL), NULL);
+
+#if TARGET_ABI_OSF
+ if (cfun->is_thunk)
+ free_after_compilation (cfun);
+#endif
+
+#if TARGET_ABI_OPEN_VMS
+ alpha_write_linkage (file, fnname, decl);
+#endif
+
/* End the function. */
if (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive)
{
}
inside_function = FALSE;
- /* Show that we know this function if it is called again.
-
- Don't do this for global functions in object files destined for a
- shared library because the function may be overridden by the application
- or other libraries. Similarly, don't do this for weak functions.
-
- Don't do this for functions not defined in the .text section, as
- otherwise it's not unlikely that the destination is out of range
- for a direct branch. */
-
- if (!DECL_WEAK (current_function_decl)
- && (!flag_pic || !TREE_PUBLIC (current_function_decl))
- && decl_in_text_section (current_function_decl))
- SYMBOL_REF_FLAG (XEXP (DECL_RTL (current_function_decl), 0)) = 1;
-
/* Output jump tables and the static subroutine information block. */
if (TARGET_ABI_UNICOSMK)
{
}
}
-/* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
+#if TARGET_ABI_OSF
+/* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
In order to avoid the hordes of differences between generated code
with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
Not sure why this idea hasn't been explored before... */
-void
-alpha_output_mi_thunk_osf (file, thunk_fndecl, delta, function)
- FILE *file;
- tree thunk_fndecl ATTRIBUTE_UNUSED;
- HOST_WIDE_INT delta;
- tree function;
+static void
+alpha_output_mi_thunk_osf (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+ HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
+ tree function)
{
HOST_WIDE_INT hi, lo;
- rtx this, insn, funexp;
+ rtx this_rtx, insn, funexp;
+
+ gcc_assert (cfun->is_thunk);
/* We always require a valid GP. */
emit_insn (gen_prologue_ldgp ());
- emit_note (NULL, NOTE_INSN_PROLOGUE_END);
+ emit_note (NOTE_INSN_PROLOGUE_END);
/* Find the "this" pointer. If the function returns a structure,
the structure return pointer is in $16. */
- if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function))))
- this = gen_rtx_REG (Pmode, 17);
+ if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
+ this_rtx = gen_rtx_REG (Pmode, 17);
else
- this = gen_rtx_REG (Pmode, 16);
+ this_rtx = gen_rtx_REG (Pmode, 16);
/* Add DELTA. When possible we use ldah+lda. Otherwise load the
entire constant for the add. */
if (hi + lo == delta)
{
if (hi)
- emit_insn (gen_adddi3 (this, this, GEN_INT (hi)));
+ emit_insn (gen_adddi3 (this_rtx, this_rtx, GEN_INT (hi)));
if (lo)
- emit_insn (gen_adddi3 (this, this, GEN_INT (lo)));
+ emit_insn (gen_adddi3 (this_rtx, this_rtx, GEN_INT (lo)));
}
else
{
rtx tmp = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 0),
delta, -(delta < 0));
- emit_insn (gen_adddi3 (this, this, tmp));
+ emit_insn (gen_adddi3 (this_rtx, this_rtx, tmp));
+ }
+
+ /* Add a delta stored in the vtable at VCALL_OFFSET. */
+ if (vcall_offset)
+ {
+ rtx tmp, tmp2;
+
+ tmp = gen_rtx_REG (Pmode, 0);
+ emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
+
+ lo = ((vcall_offset & 0xffff) ^ 0x8000) - 0x8000;
+ hi = (((vcall_offset - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000;
+ if (hi + lo == vcall_offset)
+ {
+ if (hi)
+ emit_insn (gen_adddi3 (tmp, tmp, GEN_INT (hi)));
+ }
+ else
+ {
+ tmp2 = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 1),
+ vcall_offset, -(vcall_offset < 0));
+ emit_insn (gen_adddi3 (tmp, tmp, tmp2));
+ lo = 0;
+ }
+ if (lo)
+ tmp2 = gen_rtx_PLUS (Pmode, tmp, GEN_INT (lo));
+ else
+ tmp2 = tmp;
+ emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp2));
+
+ emit_insn (gen_adddi3 (this_rtx, this_rtx, tmp));
}
/* Generate a tail call to the target function. */
instruction scheduling worth while. Note that use_thunk calls
assemble_start_function and assemble_end_function. */
insn = get_insns ();
+ insn_locators_alloc ();
shorten_branches (insn);
final_start_function (insn, file, 1);
- final (insn, file, 1, 0);
+ final (insn, file, 1);
final_end_function ();
}
+#endif /* TARGET_ABI_OSF */
\f
/* Debugging support. */
int sdb_label_count = 0;
-/* Next label # for each statement. */
-
-static int sym_lineno = 0;
-
-/* Count the number of .file directives, so that .loc is up to date. */
-
-static int num_source_filenames = 0;
-
/* Name of the file containing the current function. */
static const char *current_function_file = "";
/* Emit a new filename to a stream. */
void
-alpha_output_filename (stream, name)
- FILE *stream;
- const char *name;
+alpha_output_filename (FILE *stream, const char *name)
{
static int first_time = TRUE;
- char ltext_label_name[100];
if (first_time)
{
}
else if (write_symbols == DBX_DEBUG)
- {
- ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
- fprintf (stream, "%s", ASM_STABS_OP);
- output_quoted_string (stream, name);
- fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
- }
+ /* dbxout.c will emit an appropriate .stabs directive. */
+ return;
else if (name != current_function_file
&& strcmp (name, current_function_file) != 0)
fprintf (stream, "\t.file\t%d ", num_source_filenames);
}
- output_quoted_string (stream, name);
- fprintf (stream, "\n");
- }
-}
-\f
-/* Emit a linenumber to a stream. */
-
-void
-alpha_output_lineno (stream, line)
- FILE *stream;
- int line;
-{
- if (write_symbols == DBX_DEBUG)
- {
- /* mips-tfile doesn't understand .stabd directives. */
- ++sym_lineno;
- fprintf (stream, "$LM%d:\n%s%d,0,%d,$LM%d\n",
- sym_lineno, ASM_STABN_OP, N_SLINE, line, sym_lineno);
+ output_quoted_string (stream, name);
+ fprintf (stream, "\n");
}
- else
- fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line);
}
\f
/* Structure to show the current status of registers and memory. */
} used, defd;
};
-static void summarize_insn PARAMS ((rtx, struct shadow_summary *, int));
-static void alpha_handle_trap_shadows PARAMS ((rtx));
-
/* Summary the effects of expression X on the machine. Update SUM, a pointer
to the summary structure. SET is nonzero if the insn is setting the
object, otherwise zero. */
static void
-summarize_insn (x, sum, set)
- rtx x;
- struct shadow_summary *sum;
- int set;
+summarize_insn (rtx x, struct shadow_summary *sum, int set)
{
const char *format_ptr;
int i, j;
case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
- case SQRT: case FFS:
+ case SQRT: case FFS:
summarize_insn (XEXP (x, 0), sum, 0);
break;
break;
default:
- abort ();
+ gcc_unreachable ();
}
}
}
(d) The trap shadow may not include any branch instructions. */
static void
-alpha_handle_trap_shadows (insns)
- rtx insns;
+alpha_handle_trap_shadows (void)
{
struct shadow_summary shadow;
int trap_pending, exception_nesting;
shadow.used.fp = 0;
shadow.used.mem = 0;
shadow.defd = shadow.used;
-
- for (i = insns; i ; i = NEXT_INSN (i))
+
+ for (i = get_insns (); i ; i = NEXT_INSN (i))
{
if (GET_CODE (i) == NOTE)
{
- switch (NOTE_LINE_NUMBER (i))
+ switch (NOTE_KIND (i))
{
case NOTE_INSN_EH_REGION_BEG:
exception_nesting++;
switch (GET_CODE (i))
{
case INSN:
- /* Annoyingly, get_attr_trap will abort on these. */
+ /* Annoyingly, get_attr_trap will die on these. */
if (GET_CODE (PATTERN (i)) == USE
|| GET_CODE (PATTERN (i)) == CLOBBER)
break;
|| (sum.defd.mem & shadow.used.mem))
{
/* (a) would be violated (also takes care of (b)) */
- if (get_attr_trap (i) == TRAP_YES
- && ((sum.defd.i & sum.used.i)
- || (sum.defd.fp & sum.used.fp)))
- abort ();
+ gcc_assert (get_attr_trap (i) != TRAP_YES
+ || (!(sum.defd.i & sum.used.i)
+ && !(sum.defd.fp & sum.used.fp)));
goto close_shadow;
}
goto close_shadow;
default:
- abort ();
+ gcc_unreachable ();
}
}
else
}
\f
/* Alpha can only issue instruction groups simultaneously if they are
- suitibly aligned. This is very processor-specific. */
+ suitably aligned. This is very processor-specific. */
+/* There are a number of entries in alphaev4_insn_pipe and alphaev5_insn_pipe
+ that are marked "fake". These instructions do not exist on that target,
+ but it is possible to see these insns with deranged combinations of
+ command-line options, such as "-mtune=ev4 -mmax". Instead of aborting,
+ choose a result at random. */
enum alphaev4_pipe {
EV4_STOP = 0,
EV5_FM = 64
};
-static enum alphaev4_pipe alphaev4_insn_pipe PARAMS ((rtx));
-static enum alphaev5_pipe alphaev5_insn_pipe PARAMS ((rtx));
-static rtx alphaev4_next_group PARAMS ((rtx, int *, int *));
-static rtx alphaev5_next_group PARAMS ((rtx, int *, int *));
-static rtx alphaev4_next_nop PARAMS ((int *));
-static rtx alphaev5_next_nop PARAMS ((int *));
-
-static void alpha_align_insns
- PARAMS ((rtx, unsigned int, rtx (*)(rtx, int *, int *), rtx (*)(int *)));
-
static enum alphaev4_pipe
-alphaev4_insn_pipe (insn)
- rtx insn;
+alphaev4_insn_pipe (rtx insn)
{
if (recog_memoized (insn) < 0)
return EV4_STOP;
switch (get_attr_type (insn))
{
case TYPE_ILD:
+ case TYPE_LDSYM:
case TYPE_FLD:
+ case TYPE_LD_L:
return EV4_IBX;
- case TYPE_LDSYM:
case TYPE_IADD:
case TYPE_ILOG:
case TYPE_ICMOV:
case TYPE_ICMP:
- case TYPE_IST:
case TYPE_FST:
case TYPE_SHIFT:
case TYPE_IMUL:
case TYPE_FBR:
+ case TYPE_MVI: /* fake */
return EV4_IB0;
+ case TYPE_IST:
case TYPE_MISC:
case TYPE_IBR:
case TYPE_JSR:
+ case TYPE_CALLPAL:
case TYPE_FCPYS:
case TYPE_FCMOV:
case TYPE_FADD:
case TYPE_FDIV:
case TYPE_FMUL:
+ case TYPE_ST_C:
+ case TYPE_MB:
+ case TYPE_FSQRT: /* fake */
+ case TYPE_FTOI: /* fake */
+ case TYPE_ITOF: /* fake */
return EV4_IB1;
default:
- abort ();
+ gcc_unreachable ();
}
}
static enum alphaev5_pipe
-alphaev5_insn_pipe (insn)
- rtx insn;
+alphaev5_insn_pipe (rtx insn)
{
if (recog_memoized (insn) < 0)
return EV5_STOP;
case TYPE_IMUL:
case TYPE_MISC:
case TYPE_MVI:
+ case TYPE_LD_L:
+ case TYPE_ST_C:
+ case TYPE_MB:
+ case TYPE_FTOI: /* fake */
+ case TYPE_ITOF: /* fake */
return EV5_E0;
case TYPE_IBR:
case TYPE_JSR:
+ case TYPE_CALLPAL:
return EV5_E1;
case TYPE_FCPYS:
case TYPE_FCMOV:
case TYPE_FADD:
case TYPE_FDIV:
+ case TYPE_FSQRT: /* fake */
return EV5_FA;
case TYPE_FMUL:
return EV5_FM;
default:
- abort();
+ gcc_unreachable ();
}
}
-/* IN_USE is a mask of the slots currently filled within the insn group.
+/* IN_USE is a mask of the slots currently filled within the insn group.
The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
- the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
+ the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
LEN is, of course, the length of the group in bytes. */
static rtx
-alphaev4_next_group (insn, pin_use, plen)
- rtx insn;
- int *pin_use, *plen;
+alphaev4_next_group (rtx insn, int *pin_use, int *plen)
{
int len, in_use;
if (in_use)
goto done;
- /* If this is a completely unrecognized insn, its an asm.
+ /* If this is a completely unrecognized insn, it's an asm.
We don't know how long it is, so record length as -1 to
signal a needed realignment. */
if (recog_memoized (insn) < 0)
break;
default:
- abort();
+ gcc_unreachable ();
}
len += 4;
-
+
/* Haifa doesn't do well scheduling branches. */
if (GET_CODE (insn) == JUMP_INSN)
goto next_and_done;
return insn;
}
-/* IN_USE is a mask of the slots currently filled within the insn group.
+/* IN_USE is a mask of the slots currently filled within the insn group.
The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
- the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
+ the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
LEN is, of course, the length of the group in bytes. */
static rtx
-alphaev5_next_group (insn, pin_use, plen)
- rtx insn;
- int *pin_use, *plen;
+alphaev5_next_group (rtx insn, int *pin_use, int *plen)
{
int len, in_use;
if (in_use)
goto done;
- /* If this is a completely unrecognized insn, its an asm.
+ /* If this is a completely unrecognized insn, it's an asm.
We don't know how long it is, so record length as -1 to
signal a needed realignment. */
if (recog_memoized (insn) < 0)
len = get_attr_length (insn);
goto next_and_done;
- /* ??? Most of the places below, we would like to abort, as
- it would indicate an error either in Haifa, or in the
- scheduling description. Unfortunately, Haifa never
- schedules the last instruction of the BB, so we don't
- have an accurate TI bit to go off. */
+ /* ??? Most of the places below, we would like to assert never
+ happen, as it would indicate an error either in Haifa, or
+ in the scheduling description. Unfortunately, Haifa never
+ schedules the last instruction of the BB, so we don't have
+ an accurate TI bit to go off. */
case EV5_E01:
if (in_use & EV5_E0)
{
break;
default:
- abort();
+ gcc_unreachable ();
}
len += 4;
-
+
/* Haifa doesn't do well scheduling branches. */
/* ??? If this is predicted not-taken, slotting continues, except
that no more IBR, FBR, or JSR insns may be slotted. */
}
static rtx
-alphaev4_next_nop (pin_use)
- int *pin_use;
+alphaev4_next_nop (int *pin_use)
{
int in_use = *pin_use;
rtx nop;
}
static rtx
-alphaev5_next_nop (pin_use)
- int *pin_use;
+alphaev5_next_nop (int *pin_use)
{
int in_use = *pin_use;
rtx nop;
/* The instruction group alignment main loop. */
static void
-alpha_align_insns (insns, max_align, next_group, next_nop)
- rtx insns;
- unsigned int max_align;
- rtx (*next_group) PARAMS ((rtx, int *, int *));
- rtx (*next_nop) PARAMS ((int *));
+alpha_align_insns (unsigned int max_align,
+ rtx (*next_group) (rtx, int *, int *),
+ rtx (*next_nop) (int *))
{
/* ALIGN is the known alignment for the insn group. */
unsigned int align;
/* OFS is the offset of the current insn in the insn group. */
int ofs;
- int prev_in_use, in_use, len;
+ int prev_in_use, in_use, len, ldgp;
rtx i, next;
/* Let shorten branches care for assigning alignments to code labels. */
- shorten_branches (insns);
+ shorten_branches (get_insns ());
if (align_functions < 4)
align = 4;
align = max_align;
ofs = prev_in_use = 0;
- i = insns;
+ i = get_insns ();
if (GET_CODE (i) == NOTE)
i = next_nonnote_insn (i);
+ ldgp = alpha_function_needs_gp ? 8 : 0;
+
while (i)
{
next = (*next_group) (i, &in_use, &len);
else if (ofs & (new_align-1))
ofs = (ofs | (new_align-1)) + 1;
- if (len != 0)
- abort();
+ gcc_assert (!len);
}
/* Handle complex instructions special. */
}
}
+ /* We may not insert padding inside the initial ldgp sequence. */
+ else if (ldgp > 0)
+ ldgp -= len;
+
/* If the group won't fit in the same INT16 as the previous,
we need to add padding to keep the group together. Rather
than simply leaving the insn filling to the assembler, we
int nop_count = (align - ofs) / 4;
rtx where;
- /* Insert nops before labels, branches, and calls to truely merge
+ /* Insert nops before labels, branches, and calls to truly merge
the execution of the nops with the previous instruction group. */
where = prev_nonnote_insn (i);
if (where)
else
where = i;
- do
+ do
emit_insn_before ((*next_nop)(&prev_in_use), where);
while (--nop_count);
ofs = 0;
i = next;
}
}
+
+/* Insert an unop between a noreturn function call and GP load. */
+
+static void
+alpha_pad_noreturn (void)
+{
+ rtx insn, next;
+
+ for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
+ {
+ if (!CALL_P (insn)
+ || !find_reg_note (insn, REG_NORETURN, NULL_RTX))
+ continue;
+
+ next = next_active_insn (insn);
+
+ if (next)
+ {
+ rtx pat = PATTERN (next);
+
+ if (GET_CODE (pat) == SET
+ && GET_CODE (SET_SRC (pat)) == UNSPEC_VOLATILE
+ && XINT (SET_SRC (pat), 1) == UNSPECV_LDGP1)
+ emit_insn_after (gen_unop (), insn);
+ }
+ }
+}
\f
/* Machine dependent reorg pass. */
-void
-alpha_reorg (insns)
- rtx insns;
+static void
+alpha_reorg (void)
{
+ /* Workaround for a linker error that triggers when an
+ exception handler immediatelly follows a noreturn function.
+
+ The instruction stream from an object file:
+
+ 54: 00 40 5b 6b jsr ra,(t12),58 <__func+0x58>
+ 58: 00 00 ba 27 ldah gp,0(ra)
+ 5c: 00 00 bd 23 lda gp,0(gp)
+ 60: 00 00 7d a7 ldq t12,0(gp)
+ 64: 00 40 5b 6b jsr ra,(t12),68 <__func+0x68>
+
+ was converted in the final link pass to:
+
+ fdb24: a0 03 40 d3 bsr ra,fe9a8 <_called_func+0x8>
+ fdb28: 00 00 fe 2f unop
+ fdb2c: 00 00 fe 2f unop
+ fdb30: 30 82 7d a7 ldq t12,-32208(gp)
+ fdb34: 00 40 5b 6b jsr ra,(t12),fdb38 <__func+0x68>
+
+ GP load instructions were wrongly cleared by the linker relaxation
+ pass. This workaround prevents removal of GP loads by inserting
+ an unop instruction between a noreturn function call and
+ exception handler prologue. */
+
+ if (current_function_has_exception_handlers ())
+ alpha_pad_noreturn ();
+
if (alpha_tp != ALPHA_TP_PROG || flag_exceptions)
- alpha_handle_trap_shadows (insns);
+ alpha_handle_trap_shadows ();
/* Due to the number of extra trapb insns, don't bother fixing up
alignment when trap precision is instruction. Moreover, we can
&& alpha_tp != ALPHA_TP_INSN
&& flag_schedule_insns_after_reload)
{
- if (alpha_cpu == PROCESSOR_EV4)
- alpha_align_insns (insns, 8, alphaev4_next_group, alphaev4_next_nop);
- else if (alpha_cpu == PROCESSOR_EV5)
- alpha_align_insns (insns, 16, alphaev5_next_group, alphaev5_next_nop);
+ if (alpha_tune == PROCESSOR_EV4)
+ alpha_align_insns (8, alphaev4_next_group, alphaev4_next_nop);
+ else if (alpha_tune == PROCESSOR_EV5)
+ alpha_align_insns (16, alphaev5_next_group, alphaev5_next_nop);
}
}
\f
-/* Check a floating-point value for validity for a particular machine mode. */
-
-static const char * const float_strings[] =
-{
- /* These are for FLOAT_VAX. */
- "1.70141173319264430e+38", /* 2^127 (2^24 - 1) / 2^24 */
- "-1.70141173319264430e+38",
- "2.93873587705571877e-39", /* 2^-128 */
- "-2.93873587705571877e-39",
- /* These are for the default broken IEEE mode, which traps
- on infinity or denormal numbers. */
- "3.402823466385288598117e+38", /* 2^128 (1 - 2^-24) */
- "-3.402823466385288598117e+38",
- "1.1754943508222875079687e-38", /* 2^-126 */
- "-1.1754943508222875079687e-38",
-};
+#if !TARGET_ABI_UNICOSMK
-static REAL_VALUE_TYPE float_values[8];
-static int inited_float_values = 0;
+#ifdef HAVE_STAMP_H
+#include <stamp.h>
+#endif
-int
-check_float_value (mode, d, overflow)
- enum machine_mode mode;
- REAL_VALUE_TYPE *d;
- int overflow ATTRIBUTE_UNUSED;
+static void
+alpha_file_start (void)
{
+#ifdef OBJECT_FORMAT_ELF
+ /* If emitting dwarf2 debug information, we cannot generate a .file
+ directive to start the file, as it will conflict with dwarf2out
+ file numbers. So it's only useful when emitting mdebug output. */
+ targetm.file_start_file_directive = (write_symbols == DBX_DEBUG);
+#endif
- if (TARGET_IEEE || TARGET_IEEE_CONFORMANT || TARGET_IEEE_WITH_INEXACT)
- return 0;
+ default_file_start ();
+#ifdef MS_STAMP
+ fprintf (asm_out_file, "\t.verstamp %d %d\n", MS_STAMP, LS_STAMP);
+#endif
- if (inited_float_values == 0)
- {
- int i;
- for (i = 0; i < 8; i++)
- float_values[i] = REAL_VALUE_ATOF (float_strings[i], DFmode);
+ fputs ("\t.set noreorder\n", asm_out_file);
+ fputs ("\t.set volatile\n", asm_out_file);
+ if (!TARGET_ABI_OPEN_VMS)
+ fputs ("\t.set noat\n", asm_out_file);
+ if (TARGET_EXPLICIT_RELOCS)
+ fputs ("\t.set nomacro\n", asm_out_file);
+ if (TARGET_SUPPORT_ARCH | TARGET_BWX | TARGET_MAX | TARGET_FIX | TARGET_CIX)
+ {
+ const char *arch;
+
+ if (alpha_cpu == PROCESSOR_EV6 || TARGET_FIX || TARGET_CIX)
+ arch = "ev6";
+ else if (TARGET_MAX)
+ arch = "pca56";
+ else if (TARGET_BWX)
+ arch = "ev56";
+ else if (alpha_cpu == PROCESSOR_EV5)
+ arch = "ev5";
+ else
+ arch = "ev4";
- inited_float_values = 1;
+ fprintf (asm_out_file, "\t.arch %s\n", arch);
}
+}
+#endif
- if (mode == SFmode)
- {
- REAL_VALUE_TYPE r;
- REAL_VALUE_TYPE *fvptr;
+#ifdef OBJECT_FORMAT_ELF
+/* Since we don't have a .dynbss section, we should not allow global
+ relocations in the .rodata section. */
- if (TARGET_FLOAT_VAX)
- fvptr = &float_values[0];
- else
- fvptr = &float_values[4];
+static int
+alpha_elf_reloc_rw_mask (void)
+{
+ return flag_pic ? 3 : 2;
+}
- memcpy (&r, d, sizeof (REAL_VALUE_TYPE));
- if (REAL_VALUES_LESS (fvptr[0], r))
- {
- memcpy (d, &fvptr[0], sizeof (REAL_VALUE_TYPE));
- return 1;
- }
- else if (REAL_VALUES_LESS (r, fvptr[1]))
- {
- memcpy (d, &fvptr[1], sizeof (REAL_VALUE_TYPE));
- return 1;
- }
- else if (REAL_VALUES_LESS (dconst0, r)
- && REAL_VALUES_LESS (r, fvptr[2]))
- {
- memcpy (d, &dconst0, sizeof (REAL_VALUE_TYPE));
- return 1;
- }
- else if (REAL_VALUES_LESS (r, dconst0)
- && REAL_VALUES_LESS (fvptr[3], r))
- {
- memcpy (d, &dconst0, sizeof (REAL_VALUE_TYPE));
- return 1;
- }
- }
+/* Return a section for X. The only special thing we do here is to
+ honor small data. */
- return 0;
+static section *
+alpha_elf_select_rtx_section (enum machine_mode mode, rtx x,
+ unsigned HOST_WIDE_INT align)
+{
+ if (TARGET_SMALL_DATA && GET_MODE_SIZE (mode) <= g_switch_value)
+ /* ??? Consider using mergeable sdata sections. */
+ return sdata_section;
+ else
+ return default_elf_select_rtx_section (mode, x, align);
+}
+
+static unsigned int
+alpha_elf_section_type_flags (tree decl, const char *name, int reloc)
+{
+ unsigned int flags = 0;
+
+ if (strcmp (name, ".sdata") == 0
+ || strncmp (name, ".sdata.", 7) == 0
+ || strncmp (name, ".gnu.linkonce.s.", 16) == 0
+ || strcmp (name, ".sbss") == 0
+ || strncmp (name, ".sbss.", 6) == 0
+ || strncmp (name, ".gnu.linkonce.sb.", 17) == 0)
+ flags = SECTION_SMALL;
+
+ flags |= default_section_type_flags (decl, name, reloc);
+ return flags;
}
+#endif /* OBJECT_FORMAT_ELF */
\f
+/* Structure to collect function names for final output in link section. */
+/* Note that items marked with GTY can't be ifdef'ed out. */
+
+enum links_kind {KIND_UNUSED, KIND_LOCAL, KIND_EXTERN};
+enum reloc_kind {KIND_LINKAGE, KIND_CODEADDR};
+
+struct alpha_links GTY(())
+{
+ int num;
+ rtx linkage;
+ enum links_kind lkind;
+ enum reloc_kind rkind;
+};
+
+struct alpha_funcs GTY(())
+{
+ int num;
+ splay_tree GTY ((param1_is (char *), param2_is (struct alpha_links *)))
+ links;
+};
+
+static GTY ((param1_is (char *), param2_is (struct alpha_links *)))
+ splay_tree alpha_links_tree;
+static GTY ((param1_is (tree), param2_is (struct alpha_funcs *)))
+ splay_tree alpha_funcs_tree;
+
+static GTY(()) int alpha_funcs_num;
+
#if TARGET_ABI_OPEN_VMS
/* Return the VMS argument type corresponding to MODE. */
enum avms_arg_type
-alpha_arg_type (mode)
- enum machine_mode mode;
+alpha_arg_type (enum machine_mode mode)
{
switch (mode)
{
register value. */
rtx
-alpha_arg_info_reg_val (cum)
- CUMULATIVE_ARGS cum;
+alpha_arg_info_reg_val (CUMULATIVE_ARGS cum)
{
unsigned HOST_WIDE_INT regval = cum.num_args;
int i;
return GEN_INT (regval);
}
\f
-#include <splay-tree.h>
-
-/* Structure to collect function names for final output
- in link section. */
-
-enum links_kind {KIND_UNUSED, KIND_LOCAL, KIND_EXTERN};
-
-struct alpha_links
-{
- rtx linkage;
- enum links_kind kind;
-};
-
-static splay_tree alpha_links;
-
-static int mark_alpha_links_node PARAMS ((splay_tree_node, void *));
-static void mark_alpha_links PARAMS ((void *));
-static int alpha_write_one_linkage PARAMS ((splay_tree_node, void *));
-
-/* Protect alpha_links from garbage collection. */
-
-static int
-mark_alpha_links_node (node, data)
- splay_tree_node node;
- void *data ATTRIBUTE_UNUSED;
-{
- struct alpha_links *links = (struct alpha_links *) node->value;
- ggc_mark_rtx (links->linkage);
- return 0;
-}
-
-static void
-mark_alpha_links (ptr)
- void *ptr;
-{
- splay_tree tree = *(splay_tree *) ptr;
- splay_tree_foreach (tree, mark_alpha_links_node, NULL);
-}
-
/* Make (or fake) .linkage entry for function call.
IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
Return an SYMBOL_REF rtx for the linkage. */
rtx
-alpha_need_linkage (name, is_local)
- const char *name;
- int is_local;
+alpha_need_linkage (const char *name, int is_local)
{
splay_tree_node node;
struct alpha_links *al;
if (name[0] == '*')
name++;
- if (alpha_links)
+ if (is_local)
+ {
+ struct alpha_funcs *cfaf;
+
+ if (!alpha_funcs_tree)
+ alpha_funcs_tree = splay_tree_new_ggc ((splay_tree_compare_fn)
+ splay_tree_compare_pointers);
+
+ cfaf = (struct alpha_funcs *) ggc_alloc (sizeof (struct alpha_funcs));
+
+ cfaf->links = 0;
+ cfaf->num = ++alpha_funcs_num;
+
+ splay_tree_insert (alpha_funcs_tree,
+ (splay_tree_key) current_function_decl,
+ (splay_tree_value) cfaf);
+ }
+
+ if (alpha_links_tree)
{
/* Is this name already defined? */
- node = splay_tree_lookup (alpha_links, (splay_tree_key) name);
+ node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
if (node)
{
al = (struct alpha_links *) node->value;
if (is_local)
{
/* Defined here but external assumed. */
- if (al->kind == KIND_EXTERN)
- al->kind = KIND_LOCAL;
+ if (al->lkind == KIND_EXTERN)
+ al->lkind = KIND_LOCAL;
}
else
{
/* Used here but unused assumed. */
- if (al->kind == KIND_UNUSED)
- al->kind = KIND_LOCAL;
+ if (al->lkind == KIND_UNUSED)
+ al->lkind = KIND_LOCAL;
}
return al->linkage;
}
}
else
- {
- alpha_links = splay_tree_new ((splay_tree_compare_fn) strcmp,
- (splay_tree_delete_key_fn) free,
- (splay_tree_delete_key_fn) free);
- ggc_add_root (&alpha_links, 1, 1, mark_alpha_links);
- }
+ alpha_links_tree = splay_tree_new_ggc ((splay_tree_compare_fn) strcmp);
- al = (struct alpha_links *) xmalloc (sizeof (struct alpha_links));
- name = xstrdup (name);
+ al = (struct alpha_links *) ggc_alloc (sizeof (struct alpha_links));
+ name = ggc_strdup (name);
/* Assume external if no definition. */
- al->kind = (is_local ? KIND_UNUSED : KIND_EXTERN);
+ al->lkind = (is_local ? KIND_UNUSED : KIND_EXTERN);
/* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
get_identifier (name);
/* Construct a SYMBOL_REF for us to call. */
{
size_t name_len = strlen (name);
- char *linksym = alloca (name_len + 6);
+ char *linksym = XALLOCAVEC (char, name_len + 6);
linksym[0] = '$';
memcpy (linksym + 1, name, name_len);
memcpy (linksym + 1 + name_len, "..lk", 5);
ggc_alloc_string (linksym, name_len + 5));
}
- splay_tree_insert (alpha_links, (splay_tree_key) name,
+ splay_tree_insert (alpha_links_tree, (splay_tree_key) name,
(splay_tree_value) al);
return al->linkage;
}
+rtx
+alpha_use_linkage (rtx linkage, tree cfundecl, int lflag, int rflag)
+{
+ splay_tree_node cfunnode;
+ struct alpha_funcs *cfaf;
+ struct alpha_links *al;
+ const char *name = XSTR (linkage, 0);
+
+ cfaf = (struct alpha_funcs *) 0;
+ al = (struct alpha_links *) 0;
+
+ cfunnode = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) cfundecl);
+ cfaf = (struct alpha_funcs *) cfunnode->value;
+
+ if (cfaf->links)
+ {
+ splay_tree_node lnode;
+
+ /* Is this name already defined? */
+
+ lnode = splay_tree_lookup (cfaf->links, (splay_tree_key) name);
+ if (lnode)
+ al = (struct alpha_links *) lnode->value;
+ }
+ else
+ cfaf->links = splay_tree_new_ggc ((splay_tree_compare_fn) strcmp);
+
+ if (!al)
+ {
+ size_t name_len;
+ size_t buflen;
+ char buf [512];
+ char *linksym;
+ splay_tree_node node = 0;
+ struct alpha_links *anl;
+
+ if (name[0] == '*')
+ name++;
+
+ name_len = strlen (name);
+
+ al = (struct alpha_links *) ggc_alloc (sizeof (struct alpha_links));
+ al->num = cfaf->num;
+
+ node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
+ if (node)
+ {
+ anl = (struct alpha_links *) node->value;
+ al->lkind = anl->lkind;
+ }
+
+ sprintf (buf, "$%d..%s..lk", cfaf->num, name);
+ buflen = strlen (buf);
+ linksym = XALLOCAVEC (char, buflen + 1);
+ memcpy (linksym, buf, buflen + 1);
+
+ al->linkage = gen_rtx_SYMBOL_REF
+ (Pmode, ggc_alloc_string (linksym, buflen + 1));
+
+ splay_tree_insert (cfaf->links, (splay_tree_key) name,
+ (splay_tree_value) al);
+ }
+
+ if (rflag)
+ al->rkind = KIND_CODEADDR;
+ else
+ al->rkind = KIND_LINKAGE;
+
+ if (lflag)
+ return gen_rtx_MEM (Pmode, plus_constant (al->linkage, 8));
+ else
+ return al->linkage;
+}
+
static int
-alpha_write_one_linkage (node, data)
- splay_tree_node node;
- void *data;
+alpha_write_one_linkage (splay_tree_node node, void *data)
{
const char *const name = (const char *) node->key;
- struct alpha_links *links = (struct alpha_links *) node->value;
+ struct alpha_links *link = (struct alpha_links *) node->value;
FILE *stream = (FILE *) data;
- if (links->kind == KIND_UNUSED
- || ! TREE_SYMBOL_REFERENCED (get_identifier (name)))
- return 0;
-
- fprintf (stream, "$%s..lk:\n", name);
- if (links->kind == KIND_LOCAL)
+ fprintf (stream, "$%d..%s..lk:\n", link->num, name);
+ if (link->rkind == KIND_CODEADDR)
{
- /* Local and used, build linkage pair. */
- fprintf (stream, "\t.quad %s..en\n", name);
- fprintf (stream, "\t.quad %s\n", name);
+ if (link->lkind == KIND_LOCAL)
+ {
+ /* Local and used */
+ fprintf (stream, "\t.quad %s..en\n", name);
+ }
+ else
+ {
+ /* External and used, request code address. */
+ fprintf (stream, "\t.code_address %s\n", name);
+ }
}
else
{
- /* External and used, request linkage pair. */
- fprintf (stream, "\t.linkage %s\n", name);
+ if (link->lkind == KIND_LOCAL)
+ {
+ /* Local and used, build linkage pair. */
+ fprintf (stream, "\t.quad %s..en\n", name);
+ fprintf (stream, "\t.quad %s\n", name);
+ }
+ else
+ {
+ /* External and used, request linkage pair. */
+ fprintf (stream, "\t.linkage %s\n", name);
+ }
}
return 0;
}
-void
-alpha_write_linkage (stream)
- FILE *stream;
+static void
+alpha_write_linkage (FILE *stream, const char *funname, tree fundecl)
{
- if (alpha_links)
+ splay_tree_node node;
+ struct alpha_funcs *func;
+
+ fprintf (stream, "\t.link\n");
+ fprintf (stream, "\t.align 3\n");
+ in_section = NULL;
+
+ node = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) fundecl);
+ func = (struct alpha_funcs *) node->value;
+
+ fputs ("\t.name ", stream);
+ assemble_name (stream, funname);
+ fputs ("..na\n", stream);
+ ASM_OUTPUT_LABEL (stream, funname);
+ fprintf (stream, "\t.pdesc ");
+ assemble_name (stream, funname);
+ fprintf (stream, "..en,%s\n",
+ alpha_procedure_type == PT_STACK ? "stack"
+ : alpha_procedure_type == PT_REGISTER ? "reg" : "null");
+
+ if (func->links)
{
- readonly_section ();
- fprintf (stream, "\t.align 3\n");
- splay_tree_foreach (alpha_links, alpha_write_one_linkage, stream);
+ splay_tree_foreach (func->links, alpha_write_one_linkage, stream);
+ /* splay_tree_delete (func->links); */
}
}
#define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
static unsigned int
-vms_section_type_flags (decl, name, reloc)
- tree decl;
- const char *name;
- int reloc;
+vms_section_type_flags (tree decl, const char *name, int reloc)
{
unsigned int flags = default_section_type_flags (decl, name, reloc);
the section; 0 if the default should be used. */
static void
-vms_asm_named_section (name, flags)
- const char *name;
- unsigned int flags;
+vms_asm_named_section (const char *name, unsigned int flags,
+ tree decl ATTRIBUTE_UNUSED)
{
fputc ('\n', asm_out_file);
fprintf (asm_out_file, ".section\t%s", name);
/* Record an element in the table of global constructors. SYMBOL is
a SYMBOL_REF of the function to be called; PRIORITY is a number
- between 0 and MAX_INIT_PRIORITY.
+ between 0 and MAX_INIT_PRIORITY.
Differs from default_ctors_section_asm_out_constructor in that the
width of the .ctors entry is always 64 bits, rather than the 32 bits
used by a normal pointer. */
static void
-vms_asm_out_constructor (symbol, priority)
- rtx symbol;
- int priority ATTRIBUTE_UNUSED;
+vms_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
{
- ctors_section ();
+ switch_to_section (ctors_section);
assemble_align (BITS_PER_WORD);
assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
}
static void
-vms_asm_out_destructor (symbol, priority)
- rtx symbol;
- int priority ATTRIBUTE_UNUSED;
+vms_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
{
- dtors_section ();
+ switch_to_section (dtors_section);
assemble_align (BITS_PER_WORD);
assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
}
#else
rtx
-alpha_need_linkage (name, is_local)
- const char *name ATTRIBUTE_UNUSED;
- int is_local ATTRIBUTE_UNUSED;
+alpha_need_linkage (const char *name ATTRIBUTE_UNUSED,
+ int is_local ATTRIBUTE_UNUSED)
{
return NULL_RTX;
}
-#endif /* TARGET_ABI_OPEN_VMS */
-\f
-#if TARGET_ABI_UNICOSMK
-
-static void unicosmk_output_module_name PARAMS ((FILE *));
-static void unicosmk_output_default_externs PARAMS ((FILE *));
-static void unicosmk_output_dex PARAMS ((FILE *));
-static void unicosmk_output_externs PARAMS ((FILE *));
-static void unicosmk_output_addr_vec PARAMS ((FILE *, rtx));
-static const char *unicosmk_ssib_name PARAMS ((void));
-static int unicosmk_special_name PARAMS ((const char *));
-
-/* Define the offset between two registers, one to be eliminated, and the
- other its replacement, at the start of a routine. */
-
-int
-unicosmk_initial_elimination_offset (from, to)
- int from;
- int to;
+rtx
+alpha_use_linkage (rtx linkage ATTRIBUTE_UNUSED,
+ tree cfundecl ATTRIBUTE_UNUSED,
+ int lflag ATTRIBUTE_UNUSED,
+ int rflag ATTRIBUTE_UNUSED)
{
- int fixed_size;
-
- fixed_size = alpha_sa_size();
- if (fixed_size != 0)
- fixed_size += 48;
-
- if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
- return -fixed_size;
- else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
- return 0;
- else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
- return (ALPHA_ROUND (current_function_outgoing_args_size)
- + ALPHA_ROUND (get_frame_size()));
- else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
- return (ALPHA_ROUND (fixed_size)
- + ALPHA_ROUND (get_frame_size()
- + current_function_outgoing_args_size));
- else
- abort ();
+ return NULL_RTX;
}
-/* Output the module name for .ident and .end directives. We have to strip
- directories and add make sure that the module name starts with a letter
- or '$'. */
-
-static void
-unicosmk_output_module_name (file)
- FILE *file;
-{
- const char *name;
-
- /* Strip directories. */
-
- name = strrchr (main_input_filename, '/');
- if (name)
- ++name;
- else
- name = main_input_filename;
-
- /* CAM only accepts module names that start with a letter or '$'. We
- prefix the module name with a '$' if necessary. */
-
- if (!ISALPHA (*name))
- fprintf (file, "$%s", name);
- else
- fputs (name, file);
-}
+#endif /* TARGET_ABI_OPEN_VMS */
+\f
+#if TARGET_ABI_UNICOSMK
-/* Output text that to appear at the beginning of an assembler file. */
+/* This evaluates to true if we do not know how to pass TYPE solely in
+ registers. This is the case for all arguments that do not fit in two
+ registers. */
-void
-unicosmk_asm_file_start (file)
- FILE *file;
+static bool
+unicosmk_must_pass_in_stack (enum machine_mode mode, const_tree type)
{
- int i;
-
- fputs ("\t.ident\t", file);
- unicosmk_output_module_name (file);
- fputs ("\n\n", file);
-
- /* The Unicos/Mk assembler uses different register names. Instead of trying
- to support them, we simply use micro definitions. */
-
- /* CAM has different register names: rN for the integer register N and fN
- for the floating-point register N. Instead of trying to use these in
- alpha.md, we define the symbols $N and $fN to refer to the appropriate
- register. */
-
- for (i = 0; i < 32; ++i)
- fprintf (file, "$%d <- r%d\n", i, i);
-
- for (i = 0; i < 32; ++i)
- fprintf (file, "$f%d <- f%d\n", i, i);
-
- putc ('\n', file);
-
- /* The .align directive fill unused space with zeroes which does not work
- in code sections. We define the macro 'gcc@code@align' which uses nops
- instead. Note that it assumes that code sections always have the
- biggest possible alignment since . refers to the current offset from
- the beginning of the section. */
-
- fputs ("\t.macro gcc@code@align n\n", file);
- fputs ("gcc@n@bytes = 1 << n\n", file);
- fputs ("gcc@here = . % gcc@n@bytes\n", file);
- fputs ("\t.if ne, gcc@here, 0\n", file);
- fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", file);
- fputs ("\tbis r31,r31,r31\n", file);
- fputs ("\t.endr\n", file);
- fputs ("\t.endif\n", file);
- fputs ("\t.endm gcc@code@align\n\n", file);
+ if (type == NULL)
+ return false;
- /* Output extern declarations which should always be visible. */
- unicosmk_output_default_externs (file);
+ if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
+ return true;
+ if (TREE_ADDRESSABLE (type))
+ return true;
- /* Open a dummy section. We always need to be inside a section for the
- section-switching code to work correctly.
- ??? This should be a module id or something like that. I still have to
- figure out what the rules for those are. */
- fputs ("\n\t.psect\t$SG00000,data\n", file);
+ return ALPHA_ARG_SIZE (mode, type, 0) > 2;
}
-/* Output text to appear at the end of an assembler file. This includes all
- pending extern declarations and DEX expressions. */
+/* Define the offset between two registers, one to be eliminated, and the
+ other its replacement, at the start of a routine. */
-void
-unicosmk_asm_file_end (file)
- FILE *file;
+int
+unicosmk_initial_elimination_offset (int from, int to)
{
- fputs ("\t.endp\n\n", file);
+ int fixed_size;
- /* Output all pending externs. */
+ fixed_size = alpha_sa_size();
+ if (fixed_size != 0)
+ fixed_size += 48;
- unicosmk_output_externs (file);
+ if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
+ return -fixed_size;
+ else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
+ return 0;
+ else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
+ return (ALPHA_ROUND (crtl->outgoing_args_size)
+ + ALPHA_ROUND (get_frame_size()));
+ else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
+ return (ALPHA_ROUND (fixed_size)
+ + ALPHA_ROUND (get_frame_size()
+ + crtl->outgoing_args_size));
+ else
+ gcc_unreachable ();
+}
- /* Output dex definitions used for functions whose names conflict with
- register names. */
+/* Output the module name for .ident and .end directives. We have to strip
+ directories and add make sure that the module name starts with a letter
+ or '$'. */
- unicosmk_output_dex (file);
+static void
+unicosmk_output_module_name (FILE *file)
+{
+ const char *name = lbasename (main_input_filename);
+ unsigned len = strlen (name);
+ char *clean_name = alloca (len + 2);
+ char *ptr = clean_name;
- fputs ("\t.end\t", file);
- unicosmk_output_module_name (file);
- putc ('\n', file);
+ /* CAM only accepts module names that start with a letter or '$'. We
+ prefix the module name with a '$' if necessary. */
+
+ if (!ISALPHA (*name))
+ *ptr++ = '$';
+ memcpy (ptr, name, len + 1);
+ clean_symbol_name (clean_name);
+ fputs (clean_name, file);
}
/* Output the definition of a common variable. */
void
-unicosmk_output_common (file, name, size, align)
- FILE *file;
- const char *name;
- int size;
- int align;
+unicosmk_output_common (FILE *file, const char *name, int size, int align)
{
tree name_tree;
printf ("T3E__: common %s\n", name);
- common_section ();
+ in_section = NULL;
fputs("\t.endp\n\n\t.psect ", file);
assemble_name(file, name);
fprintf(file, ",%d,common\n", floor_log2 (align / BITS_PER_UNIT));
#define SECTION_MAIN (SECTION_PUBLIC << 1)
static int current_section_align;
+/* A get_unnamed_section callback for switching to the text section. */
+
+static void
+unicosmk_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED)
+{
+ static int count = 0;
+ fprintf (asm_out_file, "\t.endp\n\n\t.psect\tgcc@text___%d,code\n", count++);
+}
+
+/* A get_unnamed_section callback for switching to the data section. */
+
+static void
+unicosmk_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED)
+{
+ static int count = 1;
+ fprintf (asm_out_file, "\t.endp\n\n\t.psect\tgcc@data___%d,data\n", count++);
+}
+
+/* Implement TARGET_ASM_INIT_SECTIONS.
+
+ The Cray assembler is really weird with respect to sections. It has only
+ named sections and you can't reopen a section once it has been closed.
+ This means that we have to generate unique names whenever we want to
+ reenter the text or the data section. */
+
+static void
+unicosmk_init_sections (void)
+{
+ text_section = get_unnamed_section (SECTION_CODE,
+ unicosmk_output_text_section_asm_op,
+ NULL);
+ data_section = get_unnamed_section (SECTION_WRITE,
+ unicosmk_output_data_section_asm_op,
+ NULL);
+ readonly_data_section = data_section;
+}
+
static unsigned int
-unicosmk_section_type_flags (decl, name, reloc)
- tree decl;
- const char *name;
- int reloc ATTRIBUTE_UNUSED;
+unicosmk_section_type_flags (tree decl, const char *name,
+ int reloc ATTRIBUTE_UNUSED)
{
unsigned int flags = default_section_type_flags (decl, name, reloc);
/* Generate a section name for decl and associate it with the
declaration. */
-void
-unicosmk_unique_section (decl, reloc)
- tree decl;
- int reloc ATTRIBUTE_UNUSED;
+static void
+unicosmk_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
{
const char *name;
int len;
- if (!decl)
- abort ();
+ gcc_assert (decl);
name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
- STRIP_NAME_ENCODING (name, name);
+ name = default_strip_name_encoding (name);
len = strlen (name);
if (TREE_CODE (decl) == FUNCTION_DECL)
{
char *string;
- /* It is essential that we prefix the section name here because
- otherwise the section names generated for constructors and
+ /* It is essential that we prefix the section name here because
+ otherwise the section names generated for constructors and
destructors confuse collect2. */
string = alloca (len + 6);
the section; 0 if the default should be used. */
static void
-unicosmk_asm_named_section (name, flags)
- const char *name;
- unsigned int flags;
+unicosmk_asm_named_section (const char *name, unsigned int flags,
+ tree decl ATTRIBUTE_UNUSED)
{
const char *kind;
}
static void
-unicosmk_insert_attributes (decl, attr_ptr)
- tree decl;
- tree *attr_ptr ATTRIBUTE_UNUSED;
+unicosmk_insert_attributes (tree decl, tree *attr_ptr ATTRIBUTE_UNUSED)
{
if (DECL_P (decl)
&& (TREE_PUBLIC (decl) || TREE_CODE (decl) == FUNCTION_DECL))
- UNIQUE_SECTION (decl, 0);
+ unicosmk_unique_section (decl, 0);
}
/* Output an alignment directive. We have to use the macro 'gcc@code@align'
in code sections because .align fill unused space with zeroes. */
-
+
void
-unicosmk_output_align (file, align)
- FILE *file;
- int align;
+unicosmk_output_align (FILE *file, int align)
{
if (inside_function)
fprintf (file, "\tgcc@code@align\t%d\n", align);
does not allow data definitions in code sections. */
void
-unicosmk_defer_case_vector (lab, vec)
- rtx lab;
- rtx vec;
+unicosmk_defer_case_vector (rtx lab, rtx vec)
{
struct machine_function *machine = cfun->machine;
-
+
vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
machine->addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec,
- machine->addr_list);
+ machine->addr_list);
}
/* Output a case vector. */
static void
-unicosmk_output_addr_vec (file, vec)
- FILE *file;
- rtx vec;
+unicosmk_output_addr_vec (FILE *file, rtx vec)
{
rtx lab = XEXP (vec, 0);
rtx body = XEXP (vec, 1);
int vlen = XVECLEN (body, 0);
int idx;
- ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (lab));
+ (*targetm.asm_out.internal_label) (file, "L", CODE_LABEL_NUMBER (lab));
for (idx = 0; idx < vlen; idx++)
{
/* Output current function's deferred case vectors. */
static void
-unicosmk_output_deferred_case_vectors (file)
- FILE *file;
+unicosmk_output_deferred_case_vectors (FILE *file)
{
struct machine_function *machine = cfun->machine;
rtx t;
if (machine->addr_list == NULL_RTX)
return;
- data_section ();
+ switch_to_section (data_section);
for (t = machine->addr_list; t; t = XEXP (t, 1))
unicosmk_output_addr_vec (file, XEXP (t, 0));
}
-/* Set up the dynamic subprogram information block (DSIB) and update the
- frame pointer register ($15) for subroutines which have a frame. If the
+/* Generate the name of the SSIB section for the current function. */
+
+#define SSIB_PREFIX "__SSIB_"
+#define SSIB_PREFIX_LEN 7
+
+static const char *
+unicosmk_ssib_name (void)
+{
+ /* This is ok since CAM won't be able to deal with names longer than that
+ anyway. */
+
+ static char name[256];
+
+ rtx x;
+ const char *fnname;
+ int len;
+
+ x = DECL_RTL (cfun->decl);
+ gcc_assert (GET_CODE (x) == MEM);
+ x = XEXP (x, 0);
+ gcc_assert (GET_CODE (x) == SYMBOL_REF);
+ fnname = XSTR (x, 0);
+
+ len = strlen (fnname);
+ if (len + SSIB_PREFIX_LEN > 255)
+ len = 255 - SSIB_PREFIX_LEN;
+
+ strcpy (name, SSIB_PREFIX);
+ strncpy (name + SSIB_PREFIX_LEN, fnname, len);
+ name[len + SSIB_PREFIX_LEN] = 0;
+
+ return name;
+}
+
+/* Set up the dynamic subprogram information block (DSIB) and update the
+ frame pointer register ($15) for subroutines which have a frame. If the
subroutine doesn't have a frame, simply increment $15. */
static void
-unicosmk_gen_dsib (imaskP)
- unsigned long * imaskP;
+unicosmk_gen_dsib (unsigned long *imaskP)
{
if (alpha_procedure_type == PT_STACK)
{
mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 56));
set_mem_alias_set (mem, alpha_sr_alias_set);
FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA)));
- (*imaskP) &= ~(1L << REG_RA);
+ (*imaskP) &= ~(1UL << REG_RA);
/* Save the old frame pointer. */
mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 48));
set_mem_alias_set (mem, alpha_sr_alias_set);
FRP (emit_move_insn (mem, hard_frame_pointer_rtx));
- (*imaskP) &= ~(1L << HARD_FRAME_POINTER_REGNUM);
+ (*imaskP) &= ~(1UL << HARD_FRAME_POINTER_REGNUM);
emit_insn (gen_blockage ());
have a frame. */
FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
- hard_frame_pointer_rtx, GEN_INT (1))));
+ hard_frame_pointer_rtx, const1_rtx)));
}
}
-#define SSIB_PREFIX "__SSIB_"
-#define SSIB_PREFIX_LEN 7
-
-/* Generate the name of the SSIB section for the current function. */
-
-static const char *
-unicosmk_ssib_name ()
-{
- /* This is ok since CAM won't be able to deal with names longer than that
- anyway. */
-
- static char name[256];
-
- rtx x;
- const char *fnname;
- int len;
-
- x = DECL_RTL (cfun->decl);
- if (GET_CODE (x) != MEM)
- abort ();
- x = XEXP (x, 0);
- if (GET_CODE (x) != SYMBOL_REF)
- abort ();
- fnname = XSTR (x, 0);
- STRIP_NAME_ENCODING (fnname, fnname);
-
- len = strlen (fnname);
- if (len + SSIB_PREFIX_LEN > 255)
- len = 255 - SSIB_PREFIX_LEN;
-
- strcpy (name, SSIB_PREFIX);
- strncpy (name + SSIB_PREFIX_LEN, fnname, len);
- name[len + SSIB_PREFIX_LEN] = 0;
-
- return name;
-}
-
/* Output the static subroutine information block for the current
function. */
static void
-unicosmk_output_ssib (file, fnname)
- FILE *file;
- const char *fnname;
+unicosmk_output_ssib (FILE *file, const char *fnname)
{
int len;
int i;
rtx ciw;
struct machine_function *machine = cfun->machine;
- ssib_section ();
+ in_section = NULL;
fprintf (file, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix,
unicosmk_ssib_name ());
for (x = machine->first_ciw; x; x = XEXP (x, 1))
{
ciw = XEXP (x, 0);
- fprintf (file, "\t.quad\t");
#if HOST_BITS_PER_WIDE_INT == 32
- fprintf (file, HOST_WIDE_INT_PRINT_DOUBLE_HEX,
+ fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX "\n",
CONST_DOUBLE_HIGH (ciw), CONST_DOUBLE_LOW (ciw));
#else
- fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (ciw));
+ fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n", INTVAL (ciw));
#endif
- fprintf (file, "\n");
}
}
X is a CONST_INT or CONST_DOUBLE representing the CIW. */
rtx
-unicosmk_add_call_info_word (x)
- rtx x;
+unicosmk_add_call_info_word (rtx x)
{
rtx node;
struct machine_function *machine = cfun->machine;
++machine->ciw_count;
return GEN_INT (machine->ciw_count
- + strlen (current_function_name)/8 + 5);
-}
-
-static char unicosmk_section_buf[100];
-
-char *
-unicosmk_text_section ()
-{
- static int count = 0;
- sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
- count++);
- return unicosmk_section_buf;
-}
-
-char *
-unicosmk_data_section ()
-{
- static int count = 1;
- sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
- count++);
- return unicosmk_section_buf;
+ + strlen (current_function_name ())/8 + 5);
}
/* The Cray assembler doesn't accept extern declarations for symbols which
/* List of identifiers for which an extern declaration might have to be
emitted. */
+/* FIXME: needs to use GC, so it can be saved and restored for PCH. */
struct unicosmk_extern_list
{
/* Output extern declarations which are required for every asm file. */
static void
-unicosmk_output_default_externs (file)
- FILE *file;
+unicosmk_output_default_externs (FILE *file)
{
static const char *const externs[] =
{ "__T3E_MISMATCH" };
referenced but not defined. */
static void
-unicosmk_output_externs (file)
- FILE *file;
+unicosmk_output_externs (FILE *file)
{
struct unicosmk_extern_list *p;
const char *real_name;
len = strlen (user_label_prefix);
for (p = unicosmk_extern_head; p != 0; p = p->next)
{
- /* We have to strip the encoding and possibly remove user_label_prefix
+ /* We have to strip the encoding and possibly remove user_label_prefix
from the identifier in order to handle -fleading-underscore and
explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
- STRIP_NAME_ENCODING (real_name, p->name);
+ real_name = default_strip_name_encoding (p->name);
if (len && p->name[0] == '*'
&& !memcmp (real_name, user_label_prefix, len))
real_name += len;
-
+
name_tree = get_identifier (real_name);
if (! TREE_ASM_WRITTEN (name_tree))
{
}
}
}
-
+
/* Record an extern. */
void
-unicosmk_add_extern (name)
- const char *name;
+unicosmk_add_extern (const char *name)
{
struct unicosmk_extern_list *p;
p = (struct unicosmk_extern_list *)
- permalloc (sizeof (struct unicosmk_extern_list));
+ xmalloc (sizeof (struct unicosmk_extern_list));
p->next = unicosmk_extern_head;
p->name = name;
unicosmk_extern_head = p;
/* Structure to collect identifiers which have been replaced by DEX
expressions. */
+/* FIXME: needs to use GC, so it can be saved and restored for PCH. */
struct unicosmk_dex {
struct unicosmk_dex *next;
const char *name;
};
-/* List of identifiers which have been replaced by DEX expressions. The DEX
+/* List of identifiers which have been replaced by DEX expressions. The DEX
number is determined by the position in the list. */
-static struct unicosmk_dex *unicosmk_dex_list = NULL;
+static struct unicosmk_dex *unicosmk_dex_list = NULL;
/* The number of elements in the DEX list. */
/* Check if NAME must be replaced by a DEX expression. */
static int
-unicosmk_special_name (name)
- const char *name;
+unicosmk_special_name (const char *name)
{
if (name[0] == '*')
++name;
otherwise. */
static int
-unicosmk_need_dex (x)
- rtx x;
+unicosmk_need_dex (rtx x)
{
struct unicosmk_dex *dex;
const char *name;
int i;
-
+
if (GET_CODE (x) != SYMBOL_REF)
return 0;
return i;
--i;
}
-
- dex = (struct unicosmk_dex *) permalloc (sizeof (struct unicosmk_dex));
+
+ dex = (struct unicosmk_dex *) xmalloc (sizeof (struct unicosmk_dex));
dex->name = name;
dex->next = unicosmk_dex_list;
unicosmk_dex_list = dex;
/* Output the DEX definitions for this file. */
static void
-unicosmk_output_dex (file)
- FILE *file;
+unicosmk_output_dex (FILE *file)
{
struct unicosmk_dex *dex;
int i;
putc ('\n', file);
--i;
}
-
+
fprintf (file, "\t.dexend\n");
}
+/* Output text that to appear at the beginning of an assembler file. */
+
+static void
+unicosmk_file_start (void)
+{
+ int i;
+
+ fputs ("\t.ident\t", asm_out_file);
+ unicosmk_output_module_name (asm_out_file);
+ fputs ("\n\n", asm_out_file);
+
+ /* The Unicos/Mk assembler uses different register names. Instead of trying
+ to support them, we simply use micro definitions. */
+
+ /* CAM has different register names: rN for the integer register N and fN
+ for the floating-point register N. Instead of trying to use these in
+ alpha.md, we define the symbols $N and $fN to refer to the appropriate
+ register. */
+
+ for (i = 0; i < 32; ++i)
+ fprintf (asm_out_file, "$%d <- r%d\n", i, i);
+
+ for (i = 0; i < 32; ++i)
+ fprintf (asm_out_file, "$f%d <- f%d\n", i, i);
+
+ putc ('\n', asm_out_file);
+
+ /* The .align directive fill unused space with zeroes which does not work
+ in code sections. We define the macro 'gcc@code@align' which uses nops
+ instead. Note that it assumes that code sections always have the
+ biggest possible alignment since . refers to the current offset from
+ the beginning of the section. */
+
+ fputs ("\t.macro gcc@code@align n\n", asm_out_file);
+ fputs ("gcc@n@bytes = 1 << n\n", asm_out_file);
+ fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file);
+ fputs ("\t.if ne, gcc@here, 0\n", asm_out_file);
+ fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file);
+ fputs ("\tbis r31,r31,r31\n", asm_out_file);
+ fputs ("\t.endr\n", asm_out_file);
+ fputs ("\t.endif\n", asm_out_file);
+ fputs ("\t.endm gcc@code@align\n\n", asm_out_file);
+
+ /* Output extern declarations which should always be visible. */
+ unicosmk_output_default_externs (asm_out_file);
+
+ /* Open a dummy section. We always need to be inside a section for the
+ section-switching code to work correctly.
+ ??? This should be a module id or something like that. I still have to
+ figure out what the rules for those are. */
+ fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file);
+}
+
+/* Output text to appear at the end of an assembler file. This includes all
+ pending extern declarations and DEX expressions. */
+
+static void
+unicosmk_file_end (void)
+{
+ fputs ("\t.endp\n\n", asm_out_file);
+
+ /* Output all pending externs. */
+
+ unicosmk_output_externs (asm_out_file);
+
+ /* Output dex definitions used for functions whose names conflict with
+ register names. */
+
+ unicosmk_output_dex (asm_out_file);
+
+ fputs ("\t.end\t", asm_out_file);
+ unicosmk_output_module_name (asm_out_file);
+ putc ('\n', asm_out_file);
+}
+
#else
static void
-unicosmk_output_deferred_case_vectors (file)
- FILE *file ATTRIBUTE_UNUSED;
+unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED)
{}
static void
-unicosmk_gen_dsib (imaskP)
- unsigned long * imaskP ATTRIBUTE_UNUSED;
+unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED)
{}
static void
-unicosmk_output_ssib (file, fnname)
- FILE * file ATTRIBUTE_UNUSED;
- const char * fnname ATTRIBUTE_UNUSED;
+unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED,
+ const char * fnname ATTRIBUTE_UNUSED)
{}
rtx
-unicosmk_add_call_info_word (x)
- rtx x ATTRIBUTE_UNUSED;
+unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED)
{
return NULL_RTX;
}
static int
-unicosmk_need_dex (x)
- rtx x ATTRIBUTE_UNUSED;
+unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED)
{
return 0;
}
#endif /* TARGET_ABI_UNICOSMK */
+
+static void
+alpha_init_libfuncs (void)
+{
+ if (TARGET_ABI_UNICOSMK)
+ {
+ /* Prevent gcc from generating calls to __divsi3. */
+ set_optab_libfunc (sdiv_optab, SImode, 0);
+ set_optab_libfunc (udiv_optab, SImode, 0);
+
+ /* Use the functions provided by the system library
+ for DImode integer division. */
+ set_optab_libfunc (sdiv_optab, DImode, "$sldiv");
+ set_optab_libfunc (udiv_optab, DImode, "$uldiv");
+ }
+ else if (TARGET_ABI_OPEN_VMS)
+ {
+ /* Use the VMS runtime library functions for division and
+ remainder. */
+ set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
+ set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
+ set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
+ set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
+ set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
+ set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
+ set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
+ set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
+ }
+}
+
+\f
+/* Initialize the GCC target structure. */
+#if TARGET_ABI_OPEN_VMS
+# undef TARGET_ATTRIBUTE_TABLE
+# define TARGET_ATTRIBUTE_TABLE vms_attribute_table
+# undef TARGET_SECTION_TYPE_FLAGS
+# define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
+#endif
+
+#undef TARGET_IN_SMALL_DATA_P
+#define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
+
+#if TARGET_ABI_UNICOSMK
+# undef TARGET_INSERT_ATTRIBUTES
+# define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
+# undef TARGET_SECTION_TYPE_FLAGS
+# define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
+# undef TARGET_ASM_UNIQUE_SECTION
+# define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
+#undef TARGET_ASM_FUNCTION_RODATA_SECTION
+#define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
+# undef TARGET_ASM_GLOBALIZE_LABEL
+# define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
+# undef TARGET_MUST_PASS_IN_STACK
+# define TARGET_MUST_PASS_IN_STACK unicosmk_must_pass_in_stack
+#endif
+
+#undef TARGET_ASM_ALIGNED_HI_OP
+#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
+#undef TARGET_ASM_ALIGNED_DI_OP
+#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
+
+/* Default unaligned ops are provided for ELF systems. To get unaligned
+ data for non-ELF systems, we have to turn off auto alignment. */
+#ifndef OBJECT_FORMAT_ELF
+#undef TARGET_ASM_UNALIGNED_HI_OP
+#define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
+#undef TARGET_ASM_UNALIGNED_SI_OP
+#define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
+#undef TARGET_ASM_UNALIGNED_DI_OP
+#define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
+#endif
+
+#ifdef OBJECT_FORMAT_ELF
+#undef TARGET_ASM_RELOC_RW_MASK
+#define TARGET_ASM_RELOC_RW_MASK alpha_elf_reloc_rw_mask
+#undef TARGET_ASM_SELECT_RTX_SECTION
+#define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
+#undef TARGET_SECTION_TYPE_FLAGS
+#define TARGET_SECTION_TYPE_FLAGS alpha_elf_section_type_flags
+#endif
+
+#undef TARGET_ASM_FUNCTION_END_PROLOGUE
+#define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
+
+#undef TARGET_INIT_LIBFUNCS
+#define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
+
+#if TARGET_ABI_UNICOSMK
+#undef TARGET_ASM_FILE_START
+#define TARGET_ASM_FILE_START unicosmk_file_start
+#undef TARGET_ASM_FILE_END
+#define TARGET_ASM_FILE_END unicosmk_file_end
+#else
+#undef TARGET_ASM_FILE_START
+#define TARGET_ASM_FILE_START alpha_file_start
+#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
+#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
+#endif
+
+#undef TARGET_SCHED_ADJUST_COST
+#define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
+#undef TARGET_SCHED_ISSUE_RATE
+#define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
+#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
+#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
+ alpha_multipass_dfa_lookahead
+
+#undef TARGET_HAVE_TLS
+#define TARGET_HAVE_TLS HAVE_AS_TLS
+
+#undef TARGET_INIT_BUILTINS
+#define TARGET_INIT_BUILTINS alpha_init_builtins
+#undef TARGET_EXPAND_BUILTIN
+#define TARGET_EXPAND_BUILTIN alpha_expand_builtin
+#undef TARGET_FOLD_BUILTIN
+#define TARGET_FOLD_BUILTIN alpha_fold_builtin
+
+#undef TARGET_FUNCTION_OK_FOR_SIBCALL
+#define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
+#undef TARGET_CANNOT_COPY_INSN_P
+#define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
+#undef TARGET_CANNOT_FORCE_CONST_MEM
+#define TARGET_CANNOT_FORCE_CONST_MEM alpha_cannot_force_const_mem
+
+#if TARGET_ABI_OSF
+#undef TARGET_ASM_OUTPUT_MI_THUNK
+#define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
+#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
+#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
+#undef TARGET_STDARG_OPTIMIZE_HOOK
+#define TARGET_STDARG_OPTIMIZE_HOOK alpha_stdarg_optimize_hook
+#endif
+
+#undef TARGET_RTX_COSTS
+#define TARGET_RTX_COSTS alpha_rtx_costs
+#undef TARGET_ADDRESS_COST
+#define TARGET_ADDRESS_COST hook_int_rtx_bool_0
+
+#undef TARGET_MACHINE_DEPENDENT_REORG
+#define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
+
+#undef TARGET_PROMOTE_FUNCTION_ARGS
+#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
+#undef TARGET_PROMOTE_FUNCTION_RETURN
+#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
+#undef TARGET_PROMOTE_PROTOTYPES
+#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_false
+#undef TARGET_RETURN_IN_MEMORY
+#define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
+#undef TARGET_PASS_BY_REFERENCE
+#define TARGET_PASS_BY_REFERENCE alpha_pass_by_reference
+#undef TARGET_SETUP_INCOMING_VARARGS
+#define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
+#undef TARGET_STRICT_ARGUMENT_NAMING
+#define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
+#undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
+#define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
+#undef TARGET_SPLIT_COMPLEX_ARG
+#define TARGET_SPLIT_COMPLEX_ARG alpha_split_complex_arg
+#undef TARGET_GIMPLIFY_VA_ARG_EXPR
+#define TARGET_GIMPLIFY_VA_ARG_EXPR alpha_gimplify_va_arg
+#undef TARGET_ARG_PARTIAL_BYTES
+#define TARGET_ARG_PARTIAL_BYTES alpha_arg_partial_bytes
+
+#undef TARGET_SECONDARY_RELOAD
+#define TARGET_SECONDARY_RELOAD alpha_secondary_reload
+
+#undef TARGET_SCALAR_MODE_SUPPORTED_P
+#define TARGET_SCALAR_MODE_SUPPORTED_P alpha_scalar_mode_supported_p
+#undef TARGET_VECTOR_MODE_SUPPORTED_P
+#define TARGET_VECTOR_MODE_SUPPORTED_P alpha_vector_mode_supported_p
+
+#undef TARGET_BUILD_BUILTIN_VA_LIST
+#define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
+
+#undef TARGET_EXPAND_BUILTIN_VA_START
+#define TARGET_EXPAND_BUILTIN_VA_START alpha_va_start
+
+/* The Alpha architecture does not require sequential consistency. See
+ http://www.cs.umd.edu/~pugh/java/memoryModel/AlphaReordering.html
+ for an example of how it can be violated in practice. */
+#undef TARGET_RELAXED_ORDERING
+#define TARGET_RELAXED_ORDERING true
+
+#undef TARGET_DEFAULT_TARGET_FLAGS
+#define TARGET_DEFAULT_TARGET_FLAGS \
+ (TARGET_DEFAULT | TARGET_CPU_DEFAULT | TARGET_DEFAULT_EXPLICIT_RELOCS)
+#undef TARGET_HANDLE_OPTION
+#define TARGET_HANDLE_OPTION alpha_handle_option
+
+#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
+#undef TARGET_MANGLE_TYPE
+#define TARGET_MANGLE_TYPE alpha_mangle_type
+#endif
+
+struct gcc_target targetm = TARGET_INITIALIZER;
+
+\f
+#include "gt-alpha.h"
projects / msp430-gcc.git / blobdiff