;; Machine description of the Argonaut ARC cpu for GNU C compiler
-;; Copyright (C) 1994, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+;; Copyright (C) 1994, 1997, 1998, 1999, 2000, 2004, 2005, 2007, 2008
+;; Free Software Foundation, Inc.
-;; This file is part of GNU CC.
+;; This file is part of GCC.
-;; GNU CC is free software; you can redistribute it and/or modify
+;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
+;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
-;; GNU CC is distributed in the hope that it will be useful,
+;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
;; conditionalizing instructions. It saves having to scan the rtl to see if
;; it uses or alters the condition codes.
-;; USE: This insn uses the condition codes (eg: a conditional branch).
+;; USE: This insn uses the condition codes (e.g.: a conditional branch).
;; CANUSE: This insn can use the condition codes (for conditional execution).
;; SET: All condition codes are set by this insn.
;; SET_ZN: the Z and N flags are set by this insn.
(eq_attr "in_delay_slot" "true")
(eq_attr "in_delay_slot" "true")])
\f
-;; Function units of the ARC
+;; Scheduling description for the ARC
-;; (define_function_unit {name} {num-units} {n-users} {test}
-;; {ready-delay} {issue-delay} [{conflict-list}])
+(define_cpu_unit "branch")
+
+(define_insn_reservation "any_insn" 1 (eq_attr "type" "!load,compare,branch")
+ "nothing")
;; 1) A conditional jump cannot immediately follow the insn setting the flags.
;; This isn't a complete solution as it doesn't come with guarantees. That
;; is done in the branch patterns and in arc_print_operand. This exists to
;; avoid inserting a nop when we can.
-(define_function_unit "compare" 1 0 (eq_attr "type" "compare") 2 2 [(eq_attr "type" "branch")])
+
+(define_insn_reservation "compare" 1 (eq_attr "type" "compare")
+ "nothing,branch")
+
+(define_insn_reservation "branch" 1 (eq_attr "type" "branch")
+ "branch")
;; 2) References to loaded registers should wait a cycle.
;; Memory with load-delay of 1 (i.e., 2 cycle load).
-(define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
-;; Units that take one cycle do not need to be specified.
+(define_insn_reservation "memory" 2 (eq_attr "type" "load")
+ "nothing")
\f
;; Move instructions.
case 3 :
return \"st%V0 %1,%0\;st%V0 %R1,%R0\";
default:
- abort();
+ gcc_unreachable ();
}
}"
[(set_attr "type" "move,move,load,store")
;{
; /* Flow doesn't understand that this is effectively a DFmode move.
; It doesn't know that all of `operands[0]' is set. */
-; emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
+; emit_clobber (operands[0]);
;
; /* Emit insns that movsi_insn can handle. */
; emit_insn (gen_movsi (operand_subword (operands[0], 0, 0, DImode),
"
{
/* Everything except mem = const or mem = mem can be done easily. */
-
-#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
- if (GET_CODE (operands[1]) == CONST_DOUBLE)
- operands[1] = force_const_mem (SFmode, operands[1]);
-#endif
-
if (GET_CODE (operands[0]) == MEM)
operands[1] = force_reg (SFmode, operands[1]);
}")
"
{
/* Everything except mem = const or mem = mem can be done easily. */
-
-#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
- if (GET_CODE (operands[1]) == CONST_DOUBLE)
- operands[1] = force_const_mem (DFmode, operands[1]);
-#endif
-
if (GET_CODE (operands[0]) == MEM)
operands[1] = force_reg (DFmode, operands[1]);
}")
case 3 :
return \"st%V0 %1,%0\;st%V0 %R1,%R0\";
default:
- abort();
+ gcc_unreachable ();
}
}"
[(set_attr "type" "move,move,load,store")
;{
; /* Flow doesn't understand that this is effectively a DFmode move.
; It doesn't know that all of `operands[0]' is set. */
-; emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
+; emit_clobber (operands[0]);
;
; /* Emit insns that movsi_insn can handle. */
; emit_insn (gen_movsi (operand_subword (operands[0], 0, 0, DFmode),
= gen_rtx_REG (SELECT_CC_MODE (code, arc_compare_op0, arc_compare_op1),
61);
- operands[1] = gen_rtx (code, VOIDmode, ccreg, const0_rtx);
+ operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
}")
;(define_expand "movdicc"
; = gen_rtx_REG (SELECT_CC_MODE (code, arc_compare_op0, arc_compare_op1),
; 61);
;
-; operands[1] = gen_rtx (code, VOIDmode, ccreg, const0_rtx);
+; operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
;}")
(define_expand "movsfcc"
= gen_rtx_REG (SELECT_CC_MODE (code, arc_compare_op0, arc_compare_op1),
61);
- operands[1] = gen_rtx (code, VOIDmode, ccreg, const0_rtx);
+ operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
}")
;(define_expand "movdfcc"
; = gen_rtx_REG (SELECT_CC_MODE (code, arc_compare_op0, arc_compare_op1),
; 61);
;
-; operands[1] = gen_rtx (code, VOIDmode, ccreg, const0_rtx);
+; operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
;}")
(define_insn "*movsicc_insn"
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