;; -*- Mode: Scheme -*-
;; Machine description for GNU compiler,
;; for ATMEL AVR micro controllers.
-;; Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+;; Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2007, 2008,
+;; 2009 Free Software Foundation, Inc.
;; Contributed by Denis Chertykov (denisc@overta.ru)
-;; This file is part of GNU CC.
+;; This file is part of GCC.
-;; GNU CC is free software; you can redistribute it and/or modify
+;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
+;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
-;; GNU CC is distributed in the hope that it will be useful,
+;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
;; Special characters after '%':
;; A No effect (add 0).
;; j Branch condition.
;; k Reverse branch condition.
;; o Displacement for (mem (plus (reg) (const_int))) operands.
-;; ~ Output 'r' if not AVR_MEGA.
+;; p POST_INC or PRE_DEC address as a pointer (X, Y, Z)
+;; r POST_INC or PRE_DEC address as a register (r26, r28, r30)
+;; ~ Output 'r' if not AVR_HAVE_JMP_CALL.
+;; ! Output 'e' if AVR_HAVE_EIJMP_EICALL.
;; UNSPEC usage:
;; 0 Length of a string, see "strlenhi".
-;; 1 Read from a word address in program memory, see "casesi".
-
+;; 1 Jump by register pair Z or by table addressed by Z, see "casesi".
+
+(define_constants
+ [(REG_X 26)
+ (REG_Y 28)
+ (REG_Z 30)
+ (REG_W 24)
+ (REG_SP 32)
+ (TMP_REGNO 0) ; temporary register r0
+ (ZERO_REGNO 1) ; zero register r1
+
+ (SREG_ADDR 0x5F)
+ (RAMPZ_ADDR 0x5B)
+
+ (UNSPEC_STRLEN 0)
+ (UNSPEC_INDEX_JMP 1)
+ (UNSPEC_SEI 2)
+ (UNSPEC_CLI 3)
+
+ (UNSPECV_PROLOGUE_SAVES 0)
+ (UNSPECV_EPILOGUE_RESTORES 1)
+ (UNSPECV_WRITE_SP_IRQ_ON 2)
+ (UNSPECV_WRITE_SP_IRQ_OFF 3)
+ (UNSPECV_GOTO_RECEIVER 4)])
+
+(include "predicates.md")
+(include "constraints.md")
+
;; Condition code settings.
(define_attr "cc" "none,set_czn,set_zn,set_n,compare,clobber"
(const_string "none"))
-(define_attr "type" "branch,branch1,arith"
+(define_attr "type" "branch,branch1,arith,xcall"
(const_string "arith"))
-(define_attr "mcu_enhanced" "yes,no"
- (const (if_then_else (symbol_ref "AVR_ENHANCED")
+(define_attr "mcu_have_movw" "yes,no"
+ (const (if_then_else (symbol_ref "AVR_HAVE_MOVW")
(const_string "yes")
(const_string "no"))))
(define_attr "mcu_mega" "yes,no"
- (const (if_then_else (symbol_ref "AVR_MEGA")
+ (const (if_then_else (symbol_ref "AVR_HAVE_JMP_CALL")
(const_string "yes")
(const_string "no"))))
(le (minus (pc) (match_dup 0))
(const_int 2043)))
(const_int 3)
- (const_int 4)))]
+ (const_int 4)))
+ (eq_attr "type" "xcall")
+ (if_then_else (eq_attr "mcu_mega" "no")
+ (const_int 1)
+ (const_int 2))]
(const_int 2)))
-(define_insn "*pop1"
- [(set (reg:HI 32) (plus:HI (reg:HI 32) (const_int 1)))]
- ""
- "pop __tmp_reg__"
- [(set_attr "length" "1")])
+;; Define mode iterator
+(define_mode_iterator QISI [(QI "") (HI "") (SI "")])
-(define_insn "*pop2"
- [(set (reg:HI 32) (plus:HI (reg:HI 32) (const_int 2)))]
+;;========================================================================
+;; The following is used by nonlocal_goto and setjmp.
+;; The receiver pattern will create no instructions since internally
+;; virtual_stack_vars = hard_frame_pointer + 1 so the RTL become R28=R28
+;; This avoids creating add/sub offsets in frame_pointer save/resore.
+;; The 'null' receiver also avoids problems with optimisation
+;; not recognising incoming jmp and removing code that resets frame_pointer.
+;; The code derived from builtins.c.
+
+(define_expand "nonlocal_goto_receiver"
+ [(set (reg:HI REG_Y)
+ (unspec_volatile:HI [(const_int 0)] UNSPECV_GOTO_RECEIVER))]
""
- "pop __tmp_reg__
- pop __tmp_reg__"
- [(set_attr "length" "2")])
+ {
+ emit_move_insn (virtual_stack_vars_rtx,
+ gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx,
+ gen_int_mode (STARTING_FRAME_OFFSET,
+ Pmode)));
+ /* This might change the hard frame pointer in ways that aren't
+ apparent to early optimization passes, so force a clobber. */
+ emit_clobber (hard_frame_pointer_rtx);
+ DONE;
+ })
+
-(define_insn "*pop3"
- [(set (reg:HI 32) (plus:HI (reg:HI 32) (const_int 3)))]
- ""
- "pop __tmp_reg__
- pop __tmp_reg__
- pop __tmp_reg__"
- [(set_attr "length" "3")])
+;; Defining nonlocal_goto_receiver means we must also define this.
+;; even though its function is identical to that in builtins.c
-(define_insn "*pop4"
- [(set (reg:HI 32) (plus:HI (reg:HI 32) (const_int 4)))]
+(define_expand "nonlocal_goto"
+ [
+ (use (match_operand 0 "general_operand"))
+ (use (match_operand 1 "general_operand"))
+ (use (match_operand 2 "general_operand"))
+ (use (match_operand 3 "general_operand"))
+ ]
""
- "pop __tmp_reg__
- pop __tmp_reg__
- pop __tmp_reg__
- pop __tmp_reg__"
- [(set_attr "length" "4")])
+{
+ rtx r_label = copy_to_reg (operands[1]);
+ rtx r_fp = operands[3];
+ rtx r_sp = operands[2];
+
+ emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
+
+ emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
+
+ emit_move_insn (hard_frame_pointer_rtx, r_fp);
+ emit_stack_restore (SAVE_NONLOCAL, r_sp, NULL_RTX);
+
+ emit_use (hard_frame_pointer_rtx);
+ emit_use (stack_pointer_rtx);
+
+ emit_indirect_jump (r_label);
+
+ DONE;
+})
-(define_insn "*pop5"
- [(set (reg:HI 32) (plus:HI (reg:HI 32) (const_int 5)))]
- ""
- "pop __tmp_reg__
- pop __tmp_reg__
- pop __tmp_reg__
- pop __tmp_reg__
- pop __tmp_reg__"
- [(set_attr "length" "5")])
(define_insn "*pushqi"
- [(set (mem:QI (post_dec (reg:HI 32)))
- (match_operand:QI 0 "nonmemory_operand" "r,L"))]
- "(operands[0] == const0_rtx || register_operand (operands[0], QImode))"
+ [(set (mem:QI (post_dec (reg:HI REG_SP)))
+ (match_operand:QI 0 "reg_or_0_operand" "r,L"))]
+ ""
"@
push %0
push __zero_reg__"
(define_insn "*pushhi"
- [(set (mem:HI (post_dec (reg:HI 32)))
- (match_operand:HI 0 "nonmemory_operand" "r,L"))]
- "(operands[0] == const0_rtx || register_operand (operands[0], HImode))"
+ [(set (mem:HI (post_dec (reg:HI REG_SP)))
+ (match_operand:HI 0 "reg_or_0_operand" "r,L"))]
+ ""
"@
push %B0\;push %A0
push __zero_reg__\;push __zero_reg__"
[(set_attr "length" "2,2")])
(define_insn "*pushsi"
- [(set (mem:SI (post_dec (reg:HI 32)))
- (match_operand:SI 0 "nonmemory_operand" "r,L"))]
- "(operands[0] == const0_rtx || register_operand (operands[0], SImode))"
+ [(set (mem:SI (post_dec (reg:HI REG_SP)))
+ (match_operand:SI 0 "reg_or_0_operand" "r,L"))]
+ ""
"@
push %D0\;push %C0\;push %B0\;push %A0
push __zero_reg__\;push __zero_reg__\;push __zero_reg__\;push __zero_reg__"
[(set_attr "length" "4,4")])
(define_insn "*pushsf"
- [(set (mem:SF (post_dec (reg:HI 32)))
+ [(set (mem:SF (post_dec (reg:HI REG_SP)))
(match_operand:SF 0 "register_operand" "r"))]
""
"push %D0
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(match_operand:QI 1 "general_operand" ""))]
""
- "/* One of the ops has to be in a register */
+ "/* One of the ops has to be in a register. */
if (!register_operand(operand0, QImode)
&& ! (register_operand(operand1, QImode) || const0_rtx == operand1))
operands[1] = copy_to_mode_reg(QImode, operand1);
(define_peephole2
[(match_scratch:QI 2 "d")
- (set (match_operand:QI 0 "register_operand" "")
+ (set (match_operand:QI 0 "l_register_operand" "")
(match_operand:QI 1 "immediate_operand" ""))]
"(operands[1] != const0_rtx
- && test_hard_reg_class (NO_LD_REGS, operands[0]))"
+ && operands[1] != const1_rtx
+ && operands[1] != constm1_rtx)"
[(parallel [(set (match_dup 0) (match_dup 1))
(clobber (match_dup 2))])]
- "if (!avr_peep2_scratch_safe (operands[2]))
- FAIL;")
+ "")
;;============================================================================
;; move word (16 bit)
""
"
{
- /* One of the ops has to be in a register */
+ /* One of the ops has to be in a register. */
if (!register_operand(operand0, HImode)
&& !(register_operand(operand1, HImode) || const0_rtx == operands[1]))
{
}
}")
+(define_insn "*movhi_sp"
+ [(set (match_operand:HI 0 "register_operand" "=q,r")
+ (match_operand:HI 1 "register_operand" "r,q"))]
+ "((stack_register_operand(operands[0], HImode) && register_operand (operands[1], HImode))
+ || (register_operand (operands[0], HImode) && stack_register_operand(operands[1], HImode)))"
+ "* return output_movhi (insn, operands, NULL);"
+ [(set_attr "length" "5,2")
+ (set_attr "cc" "none,none")])
+
+(define_insn "movhi_sp_r_irq_off"
+ [(set (match_operand:HI 0 "stack_register_operand" "=q")
+ (unspec_volatile:HI [(match_operand:HI 1 "register_operand" "r")]
+ UNSPECV_WRITE_SP_IRQ_OFF))]
+ ""
+ "out __SP_H__, %B1
+ out __SP_L__, %A1"
+ [(set_attr "length" "2")
+ (set_attr "cc" "none")])
+
+(define_insn "movhi_sp_r_irq_on"
+ [(set (match_operand:HI 0 "stack_register_operand" "=q")
+ (unspec_volatile:HI [(match_operand:HI 1 "register_operand" "r")]
+ UNSPECV_WRITE_SP_IRQ_ON))]
+ ""
+ "cli
+ out __SP_H__, %B1
+ sei
+ out __SP_L__, %A1"
+ [(set_attr "length" "4")
+ (set_attr "cc" "none")])
(define_peephole2
[(match_scratch:QI 2 "d")
- (set (match_operand:HI 0 "register_operand" "")
- (match_operand:HI 1 "immediate_operand" ""))]
- "(operands[1] != const0_rtx
- && test_hard_reg_class (NO_LD_REGS, operands[0]))"
+ (set (match_operand:HI 0 "l_register_operand" "")
+ (match_operand:HI 1 "immediate_operand" ""))]
+ "(operands[1] != const0_rtx
+ && operands[1] != constm1_rtx)"
[(parallel [(set (match_dup 0) (match_dup 1))
(clobber (match_dup 2))])]
- "if (!avr_peep2_scratch_safe (operands[2]))
- FAIL;")
+ "")
;; '*' because it is not used in rtl generation, only in above peephole
(define_insn "*reload_inhi"
[(set_attr "length" "2,6,7,2,6,5,2")
(set_attr "cc" "none,clobber,clobber,none,clobber,none,none")])
+(define_peephole2 ; movw
+ [(set (match_operand:QI 0 "even_register_operand" "")
+ (match_operand:QI 1 "even_register_operand" ""))
+ (set (match_operand:QI 2 "odd_register_operand" "")
+ (match_operand:QI 3 "odd_register_operand" ""))]
+ "(AVR_HAVE_MOVW
+ && REGNO (operands[0]) == REGNO (operands[2]) - 1
+ && REGNO (operands[1]) == REGNO (operands[3]) - 1)"
+ [(set (match_dup 4) (match_dup 5))]
+ {
+ operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
+ operands[5] = gen_rtx_REG (HImode, REGNO (operands[1]));
+ })
+
+(define_peephole2 ; movw_r
+ [(set (match_operand:QI 0 "odd_register_operand" "")
+ (match_operand:QI 1 "odd_register_operand" ""))
+ (set (match_operand:QI 2 "even_register_operand" "")
+ (match_operand:QI 3 "even_register_operand" ""))]
+ "(AVR_HAVE_MOVW
+ && REGNO (operands[2]) == REGNO (operands[0]) - 1
+ && REGNO (operands[3]) == REGNO (operands[1]) - 1)"
+ [(set (match_dup 4) (match_dup 5))]
+ {
+ operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));
+ operands[5] = gen_rtx_REG (HImode, REGNO (operands[3]));
+ })
+
;;==========================================================================
;; move double word (32 bit)
-(define_peephole2
+(define_peephole2 ; movsi_lreg_const
[(match_scratch:QI 2 "d")
- (set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "immediate_operand" ""))]
+ (set (match_operand:SI 0 "l_register_operand" "")
+ (match_operand:SI 1 "immediate_operand" ""))
+ (match_dup 2)]
"(operands[1] != const0_rtx
- && test_hard_reg_class (NO_LD_REGS, operands[0]))"
+ && operands[1] != constm1_rtx)"
[(parallel [(set (match_dup 0) (match_dup 1))
(clobber (match_dup 2))])]
- "if (!avr_peep2_scratch_safe (operands[2]))
- FAIL;")
+ "")
;; '*' because it is not used in rtl generation.
(define_insn "*reload_insi"
;;=========================================================================
;; move string (like memcpy)
+;; implement as RTL loop
-(define_expand "movstrhi"
+(define_expand "movmemhi"
[(parallel [(set (match_operand:BLK 0 "memory_operand" "")
- (match_operand:BLK 1 "memory_operand" ""))
- (use (match_operand:HI 2 "const_int_operand" ""))
- (use (match_operand:HI 3 "const_int_operand" ""))
- (clobber (match_dup 4))
- (clobber (match_dup 5))
- (clobber (match_dup 6))])]
+ (match_operand:BLK 1 "memory_operand" ""))
+ (use (match_operand:HI 2 "const_int_operand" ""))
+ (use (match_operand:HI 3 "const_int_operand" ""))])]
""
"{
- rtx addr0, addr1;
- int cnt8;
+ int prob;
+ HOST_WIDE_INT count;
+ enum machine_mode mode;
+ rtx label = gen_label_rtx ();
+ rtx loop_reg;
+ rtx jump;
+
+ /* Copy pointers into new psuedos - they will be changed. */
+ rtx addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
+ rtx addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
+
+ /* Create rtx for tmp register - we use this as scratch. */
+ rtx tmp_reg_rtx = gen_rtx_REG (QImode, TMP_REGNO);
if (GET_CODE (operands[2]) != CONST_INT)
FAIL;
- cnt8 = byte_immediate_operand (operands[2], GET_MODE (operands[2]));
- operands[2] = copy_to_mode_reg (cnt8 ? QImode : HImode, operands[2]);
- operands[4] = operands[2];
-
- addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
- addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
- operands[5] = addr0;
- operands[6] = addr1;
+ count = INTVAL (operands[2]);
+ if (count <= 0)
+ FAIL;
- operands[0] = gen_rtx (MEM, BLKmode, addr0);
- operands[1] = gen_rtx (MEM, BLKmode, addr1);
+ /* Work out branch probability for latter use. */
+ prob = REG_BR_PROB_BASE - REG_BR_PROB_BASE / count;
+
+ /* See if constant fit 8 bits. */
+ mode = (count < 0x100) ? QImode : HImode;
+ /* Create loop counter register. */
+ loop_reg = copy_to_mode_reg (mode, gen_int_mode (count, mode));
+
+ /* Now create RTL code for move loop. */
+ /* Label at top of loop. */
+ emit_label (label);
+
+ /* Move one byte into scratch and inc pointer. */
+ emit_move_insn (tmp_reg_rtx, gen_rtx_MEM (QImode, addr1));
+ emit_move_insn (addr1, gen_rtx_PLUS (Pmode, addr1, const1_rtx));
+
+ /* Move to mem and inc pointer. */
+ emit_move_insn (gen_rtx_MEM (QImode, addr0), tmp_reg_rtx);
+ emit_move_insn (addr0, gen_rtx_PLUS (Pmode, addr0, const1_rtx));
+
+ /* Decrement count. */
+ emit_move_insn (loop_reg, gen_rtx_PLUS (mode, loop_reg, constm1_rtx));
+
+ /* Compare with zero and jump if not equal. */
+ emit_cmp_and_jump_insns (loop_reg, const0_rtx, NE, NULL_RTX, mode, 1,
+ label);
+ /* Set jump probability based on loop count. */
+ jump = get_last_insn ();
+ REG_NOTES (jump) = gen_rtx_EXPR_LIST (REG_BR_PROB,
+ GEN_INT (prob),
+ REG_NOTES (jump));
+ DONE;
}")
-(define_insn "*movstrqi_insn"
- [(set (mem:BLK (match_operand:HI 0 "register_operand" "e"))
- (mem:BLK (match_operand:HI 1 "register_operand" "e")))
- (use (match_operand:QI 2 "register_operand" "r"))
- (use (match_operand:QI 3 "const_int_operand" "i"))
- (clobber (match_dup 2))
- (clobber (match_dup 0))
- (clobber (match_dup 1))]
- ""
- "ld __tmp_reg__,%a1+
- st %a0+,__tmp_reg__
- dec %2
- brne .-8"
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
+;; =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2
+;; memset (%0, %2, %1)
-(define_insn "*movstrhi"
- [(set (mem:BLK (match_operand:HI 0 "register_operand" "e,e"))
- (mem:BLK (match_operand:HI 1 "register_operand" "e,e")))
- (use (match_operand:HI 2 "register_operand" "!w,d"))
- (use (match_operand:HI 3 "const_int_operand" ""))
- (clobber (match_dup 2))
- (clobber (match_dup 0))
- (clobber (match_dup 1))]
- ""
- "*{
- if (which_alternative==0)
- return (AS2 (ld,__tmp_reg__,%a1+) CR_TAB
- AS2 (st,%a0+,__tmp_reg__) CR_TAB
- AS2 (sbiw,%A2,1) CR_TAB
- AS1 (brne,.-8));
- else
- return (AS2 (ld,__tmp_reg__,%a1+) CR_TAB
- AS2 (st,%a0+,__tmp_reg__) CR_TAB
- AS2 (subi,%A2,1) CR_TAB
- AS2 (sbci,%B2,0) CR_TAB
- AS1 (brne,.-10));
-}"
- [(set_attr "length" "4,5")
- (set_attr "cc" "clobber,clobber")])
-
-;; =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0
-;; memset (%0, 0, %1)
-
-(define_expand "clrstrhi"
+(define_expand "setmemhi"
[(parallel [(set (match_operand:BLK 0 "memory_operand" "")
- (const_int 0))
+ (match_operand 2 "const_int_operand" ""))
(use (match_operand:HI 1 "const_int_operand" ""))
- (use (match_operand:HI 2 "const_int_operand" "n"))
- (clobber (match_dup 3))
- (clobber (match_dup 4))])]
+ (use (match_operand:HI 3 "const_int_operand" "n"))
+ (clobber (match_scratch:HI 4 ""))
+ (clobber (match_dup 5))])]
""
"{
rtx addr0;
int cnt8;
+ enum machine_mode mode;
+
+ /* If value to set is not zero, use the library routine. */
+ if (operands[2] != const0_rtx)
+ FAIL;
if (GET_CODE (operands[1]) != CONST_INT)
FAIL;
cnt8 = byte_immediate_operand (operands[1], GET_MODE (operands[1]));
- operands[1] = copy_to_mode_reg (cnt8 ? QImode : HImode, operands[1]);
- operands[3] = operands[1];
-
+ mode = cnt8 ? QImode : HImode;
+ operands[5] = gen_rtx_SCRATCH (mode);
+ operands[1] = copy_to_mode_reg (mode,
+ gen_int_mode (INTVAL (operands[1]), mode));
addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
- operands[4] = addr0;
-
- operands[0] = gen_rtx (MEM, BLKmode, addr0);
+ operands[0] = gen_rtx_MEM (BLKmode, addr0);
}")
-(define_insn "*clrstrqi"
+(define_insn "*clrmemqi"
[(set (mem:BLK (match_operand:HI 0 "register_operand" "e"))
(const_int 0))
(use (match_operand:QI 1 "register_operand" "r"))
(use (match_operand:QI 2 "const_int_operand" "n"))
- (clobber (match_dup 1))
- (clobber (match_dup 0))]
+ (clobber (match_scratch:HI 3 "=0"))
+ (clobber (match_scratch:QI 4 "=&1"))]
""
"st %a0+,__zero_reg__
dec %1
[(set_attr "length" "3")
(set_attr "cc" "clobber")])
-(define_insn "*clrstrhi"
+(define_insn "*clrmemhi"
[(set (mem:BLK (match_operand:HI 0 "register_operand" "e,e"))
(const_int 0))
(use (match_operand:HI 1 "register_operand" "!w,d"))
(use (match_operand:HI 2 "const_int_operand" "n,n"))
- (clobber (match_dup 1))
- (clobber (match_dup 0))]
+ (clobber (match_scratch:HI 3 "=0,0"))
+ (clobber (match_scratch:HI 4 "=&1,&1"))]
""
"*{
if (which_alternative==0)
[(set (match_dup 4)
(unspec:HI [(match_operand:BLK 1 "memory_operand" "")
(match_operand:QI 2 "const_int_operand" "")
- (match_operand:HI 3 "immediate_operand" "")] 0))
+ (match_operand:HI 3 "immediate_operand" "")]
+ UNSPEC_STRLEN))
(set (match_dup 4) (plus:HI (match_dup 4)
(const_int -1)))
(set (match_operand:HI 0 "register_operand" "")
if (! (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0))
FAIL;
addr = copy_to_mode_reg (Pmode, XEXP (operands[1],0));
- operands[1] = gen_rtx (MEM, BLKmode, addr);
+ operands[1] = gen_rtx_MEM (BLKmode, addr);
operands[5] = addr;
operands[4] = gen_reg_rtx (HImode);
}")
[(set (match_operand:HI 0 "register_operand" "=e")
(unspec:HI [(mem:BLK (match_operand:HI 1 "register_operand" "%0"))
(const_int 0)
- (match_operand:HI 2 "immediate_operand" "i")] 0))]
+ (match_operand:HI 2 "immediate_operand" "i")]
+ UNSPEC_STRLEN))]
""
"ld __tmp_reg__,%a0+
tst __tmp_reg__
[(set_attr "length" "2")
(set_attr "cc" "set_n")])
-(define_insn "*addhi3_zero_extend2"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (plus:HI
- (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
- (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
- ""
- "add %0,%2
- mov %B0,__zero_reg__
- adc %B0,__zero_reg__"
- [(set_attr "length" "3")
- (set_attr "cc" "set_n")])
+(define_insn "*addhi3_sp_R_pc2"
+ [(set (match_operand:HI 1 "stack_register_operand" "=q")
+ (plus:HI (match_operand:HI 2 "stack_register_operand" "q")
+ (match_operand:HI 0 "avr_sp_immediate_operand" "R")))]
+ "AVR_2_BYTE_PC"
+ "*{
+ if (CONST_INT_P (operands[0]))
+ {
+ switch(INTVAL (operands[0]))
+ {
+ case -6:
+ return \"rcall .\" CR_TAB
+ \"rcall .\" CR_TAB
+ \"rcall .\";
+ case -5:
+ return \"rcall .\" CR_TAB
+ \"rcall .\" CR_TAB
+ \"push __tmp_reg__\";
+ case -4:
+ return \"rcall .\" CR_TAB
+ \"rcall .\";
+ case -3:
+ return \"rcall .\" CR_TAB
+ \"push __tmp_reg__\";
+ case -2:
+ return \"rcall .\";
+ case -1:
+ return \"push __tmp_reg__\";
+ case 0:
+ return \"\";
+ case 1:
+ return \"pop __tmp_reg__\";
+ case 2:
+ return \"pop __tmp_reg__\" CR_TAB
+ \"pop __tmp_reg__\";
+ case 3:
+ return \"pop __tmp_reg__\" CR_TAB
+ \"pop __tmp_reg__\" CR_TAB
+ \"pop __tmp_reg__\";
+ case 4:
+ return \"pop __tmp_reg__\" CR_TAB
+ \"pop __tmp_reg__\" CR_TAB
+ \"pop __tmp_reg__\" CR_TAB
+ \"pop __tmp_reg__\";
+ case 5:
+ return \"pop __tmp_reg__\" CR_TAB
+ \"pop __tmp_reg__\" CR_TAB
+ \"pop __tmp_reg__\" CR_TAB
+ \"pop __tmp_reg__\" CR_TAB
+ \"pop __tmp_reg__\";
+ }
+ }
+ return \"bug\";
+ }"
+ [(set (attr "length")
+ (cond [(eq (const_int -6) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
+ (eq (const_int -5) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
+ (eq (const_int -4) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
+ (eq (const_int -3) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
+ (eq (const_int -2) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
+ (eq (const_int -1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
+ (eq (const_int 0) (symbol_ref "INTVAL (operands[0])")) (const_int 0)
+ (eq (const_int 1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
+ (eq (const_int 2) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
+ (eq (const_int 3) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
+ (eq (const_int 4) (symbol_ref "INTVAL (operands[0])")) (const_int 4)
+ (eq (const_int 5) (symbol_ref "INTVAL (operands[0])")) (const_int 5)]
+ (const_int 0)))])
+
+(define_insn "*addhi3_sp_R_pc3"
+ [(set (match_operand:HI 1 "stack_register_operand" "=q")
+ (plus:HI (match_operand:HI 2 "stack_register_operand" "q")
+ (match_operand:QI 0 "avr_sp_immediate_operand" "R")))]
+ "AVR_3_BYTE_PC"
+ "*{
+ if (CONST_INT_P (operands[0]))
+ {
+ switch(INTVAL (operands[0]))
+ {
+ case -6:
+ return \"rcall .\" CR_TAB
+ \"rcall .\";
+ case -5:
+ return \"rcall .\" CR_TAB
+ \"push __tmp_reg__\" CR_TAB
+ \"push __tmp_reg__\";
+ case -4:
+ return \"rcall .\" CR_TAB
+ \"push __tmp_reg__\";
+ case -3:
+ return \"rcall .\";
+ case -2:
+ return \"push __tmp_reg__\" CR_TAB
+ \"push __tmp_reg__\";
+ case -1:
+ return \"push __tmp_reg__\";
+ case 0:
+ return \"\";
+ case 1:
+ return \"pop __tmp_reg__\";
+ case 2:
+ return \"pop __tmp_reg__\" CR_TAB
+ \"pop __tmp_reg__\";
+ case 3:
+ return \"pop __tmp_reg__\" CR_TAB
+ \"pop __tmp_reg__\" CR_TAB
+ \"pop __tmp_reg__\";
+ case 4:
+ return \"pop __tmp_reg__\" CR_TAB
+ \"pop __tmp_reg__\" CR_TAB
+ \"pop __tmp_reg__\" CR_TAB
+ \"pop __tmp_reg__\";
+ case 5:
+ return \"pop __tmp_reg__\" CR_TAB
+ \"pop __tmp_reg__\" CR_TAB
+ \"pop __tmp_reg__\" CR_TAB
+ \"pop __tmp_reg__\" CR_TAB
+ \"pop __tmp_reg__\";
+ }
+ }
+ return \"bug\";
+ }"
+ [(set (attr "length")
+ (cond [(eq (const_int -6) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
+ (eq (const_int -5) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
+ (eq (const_int -4) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
+ (eq (const_int -3) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
+ (eq (const_int -2) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
+ (eq (const_int -1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
+ (eq (const_int 0) (symbol_ref "INTVAL (operands[0])")) (const_int 0)
+ (eq (const_int 1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
+ (eq (const_int 2) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
+ (eq (const_int 3) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
+ (eq (const_int 4) (symbol_ref "INTVAL (operands[0])")) (const_int 4)
+ (eq (const_int 5) (symbol_ref "INTVAL (operands[0])")) (const_int 5)]
+ (const_int 0)))])
(define_insn "*addhi3"
[(set (match_operand:HI 0 "register_operand" "=r,!w,!w,d,r,r")
(match_operand:QI 2 "register_operand" "")))]
""
"{
- if (!AVR_ENHANCED)
+ if (!AVR_HAVE_MUL)
{
emit_insn (gen_mulqi3_call (operands[0], operands[1], operands[2]));
DONE;
[(set (match_operand:QI 0 "register_operand" "=r")
(mult:QI (match_operand:QI 1 "register_operand" "r")
(match_operand:QI 2 "register_operand" "r")))]
- "AVR_ENHANCED"
+ "AVR_HAVE_MUL"
"mul %1,%2
mov %0,r0
clr r1"
(define_insn "*mulqi3_call"
[(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
(clobber (reg:QI 22))]
- "!AVR_ENHANCED"
+ "!AVR_HAVE_MUL"
"%~call __mulqi3"
- [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
- (const_int 1)
- (const_int 2)))
+ [(set_attr "type" "xcall")
(set_attr "cc" "clobber")])
(define_insn "mulqihi3"
[(set (match_operand:HI 0 "register_operand" "=r")
(mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "d"))
(sign_extend:HI (match_operand:QI 2 "register_operand" "d"))))]
- "AVR_ENHANCED"
+ "AVR_HAVE_MUL"
"muls %1,%2
movw %0,r0
clr r1"
[(set (match_operand:HI 0 "register_operand" "=r")
(mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
- "AVR_ENHANCED"
+ "AVR_HAVE_MUL"
"mul %1,%2
movw %0,r0
clr r1"
""
"
{
- if (!AVR_ENHANCED)
+ if (!AVR_HAVE_MUL)
{
emit_insn (gen_mulhi3_call (operands[0], operands[1], operands[2]));
DONE;
[(set (match_operand:HI 0 "register_operand" "=&r")
(mult:HI (match_operand:HI 1 "register_operand" "r")
(match_operand:HI 2 "register_operand" "r")))]
- "AVR_ENHANCED"
+ "AVR_HAVE_MUL"
"mul %A1,%A2
movw %0,r0
mul %A1,%B2
[(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
(clobber (reg:HI 22))
(clobber (reg:QI 21))]
- "!AVR_ENHANCED"
+ "!AVR_HAVE_MUL"
"%~call __mulhi3"
- [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
- (const_int 1)
- (const_int 2)))
+ [(set_attr "type" "xcall")
(set_attr "cc" "clobber")])
;; Operand 2 (reg:SI 18) not clobbered on the enhanced core.
(clobber (reg:HI 26))
(clobber (reg:HI 30))])
(set (match_operand:SI 0 "register_operand" "") (reg:SI 22))]
- "AVR_ENHANCED"
+ "AVR_HAVE_MUL"
"")
(define_insn "*mulsi3_call"
[(set (reg:SI 22) (mult:SI (reg:SI 22) (reg:SI 18)))
(clobber (reg:HI 26))
(clobber (reg:HI 30))]
- "AVR_ENHANCED"
+ "AVR_HAVE_MUL"
"%~call __mulsi3"
- [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
- (const_int 1)
- (const_int 2)))
+ [(set_attr "type" "xcall")
(set_attr "cc" "clobber")])
; / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / %
(clobber (reg:QI 23))]
""
"%~call __divmodqi4"
- [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
- (const_int 1)
- (const_int 2)))
+ [(set_attr "type" "xcall")
(set_attr "cc" "clobber")])
(define_expand "udivmodqi4"
(clobber (reg:QI 23))]
""
"%~call __udivmodqi4"
- [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
- (const_int 1)
- (const_int 2)))
+ [(set_attr "type" "xcall")
(set_attr "cc" "clobber")])
(define_expand "divmodhi4"
(clobber (reg:QI 21))]
""
"%~call __divmodhi4"
- [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
- (const_int 1)
- (const_int 2)))
+ [(set_attr "type" "xcall")
(set_attr "cc" "clobber")])
(define_expand "udivmodhi4"
(clobber (reg:QI 21))]
""
"%~call __udivmodhi4"
- [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
- (const_int 1)
- (const_int 2)))
+ [(set_attr "type" "xcall")
(set_attr "cc" "clobber")])
(define_expand "divmodsi4"
(clobber (reg:HI 30))]
""
"%~call __divmodsi4"
- [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
- (const_int 1)
- (const_int 2)))
+ [(set_attr "type" "xcall")
(set_attr "cc" "clobber")])
(define_expand "udivmodsi4"
(clobber (reg:HI 30))]
""
"%~call __udivmodsi4"
- [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
- (const_int 1)
- (const_int 2)))
+ [(set_attr "type" "xcall")
(set_attr "cc" "clobber")])
;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
return \"bug\";
}"
[(set_attr "length" "4,4")
- (set_attr "cc" "set_n,set_n")])
+ (set_attr "cc" "set_n,clobber")])
+
+(define_peephole2 ; andi
+ [(set (match_operand:QI 0 "d_register_operand" "")
+ (and:QI (match_dup 0)
+ (match_operand:QI 1 "const_int_operand" "")))
+ (set (match_dup 0)
+ (and:QI (match_dup 0)
+ (match_operand:QI 2 "const_int_operand" "")))]
+ ""
+ [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
+ {
+ operands[1] = GEN_INT (INTVAL (operands[1]) & INTVAL (operands[2]));
+ })
;;|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
;; ior
[(set_attr "length" "4")
(set_attr "cc" "set_n")])
+;; swap swap swap swap swap swap swap swap swap swap swap swap swap swap swap
+;; swap
+
+(define_expand "rotlqi3"
+ [(set (match_operand:QI 0 "register_operand" "")
+ (rotate:QI (match_operand:QI 1 "register_operand" "")
+ (match_operand:QI 2 "const_int_operand" "")))]
+ ""
+ "
+{
+ if (INTVAL (operands[2]) != 4)
+ FAIL;
+}")
+
+(define_insn "*rotlqi3_4"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (rotate:QI (match_operand:QI 1 "register_operand" "0")
+ (const_int 4)))]
+ ""
+ "swap %0"
+ [(set_attr "length" "1")
+ (set_attr "cc" "none")])
+
+(define_expand "rotlhi3"
+ [(set (match_operand:HI 0 "register_operand" "")
+ (rotate:HI (match_operand:HI 1 "register_operand" "")
+ (match_operand:HI 2 "const_int_operand" "")))]
+ ""
+ "
+{
+ if (INTVAL (operands[2]) != 8)
+ FAIL;
+}")
+
+(define_insn_and_split "*rotlhi3_8"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (rotate:HI (match_operand:HI 1 "register_operand" "r")
+ (const_int 8)))]
+ ""
+ "mov __tmp_reg__,%A0
+ mov %A0,%B0
+ mov %B0, __tmp_reg__"
+ "reload_completed
+ && REGNO (operands[0]) != REGNO (operands[1])"
+ [(set (match_dup 2) (match_dup 5))
+ (set (match_dup 3) (match_dup 4))]
+ "operands[2] = gen_lowpart (QImode, operands[0]);
+ operands[3] = gen_highpart (QImode, operands[0]);
+
+ operands[4] = gen_lowpart (QImode, operands[1]);
+ operands[5] = gen_highpart (QImode, operands[1]);"
+ [(set_attr "length" "3")
+ (set_attr "cc" "none")])
+
+(define_expand "rotlsi3"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (rotate:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "const_int_operand" "")))]
+ ""
+ "
+{
+ if (INTVAL (operands[2]) != 8
+ || INTVAL (operands[2]) != 16
+ || INTVAL (operands[2]) != 24)
+ FAIL;
+}")
+
+(define_insn_and_split "*rotlsi3_16"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (rotate:SI (match_operand:SI 1 "register_operand" "r")
+ (const_int 16)))]
+ ""
+ "{mov __tmp_reg__,%A1\;mov %A0,%C1\;mov %C0, __tmp_reg__\;mov __tmp_reg__,%B1\;mov %B0,%D1\;mov %D0, __tmp_reg__|movw __tmp_reg__,%A1\;movw %A0,%C1\;movw %C0, __tmp_reg__\;clr __zero_reg__}"
+ "reload_completed
+ && REGNO (operands[0]) != REGNO (operands[1])"
+ [(set (match_dup 2) (match_dup 5))
+ (set (match_dup 3) (match_dup 4))]
+ "unsigned int si_lo_off = subreg_lowpart_offset (HImode, SImode);
+ unsigned int si_hi_off = subreg_highpart_offset (HImode, SImode);
+
+ operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, si_lo_off);
+ operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, si_hi_off);
+
+ operands[4] = simplify_gen_subreg (HImode, operands[1], SImode, si_lo_off);
+ operands[5] = simplify_gen_subreg (HImode, operands[1], SImode, si_hi_off);
+
+ if (REGNO (operands[0]) == REGNO(operands[1]) + 2)
+ {
+ emit_move_insn (operands[3], operands[4]);
+ DONE;
+ }
+ else if (REGNO (operands[0]) == REGNO(operands[1]) - 2)
+ {
+ emit_move_insn (operands[2], operands[5]);
+ DONE;
+ }"
+ [(set (attr "length") (if_then_else (eq_attr "mcu_have_movw" "yes")
+ (const_int 4)
+ (const_int 6)))
+ (set (attr "cc") (if_then_else (eq_attr "mcu_have_movw" "yes")
+ (const_string "clobber")
+ (const_string "none")))])
+
+(define_insn_and_split "*rotlsi3_8"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (rotate:SI (match_operand:SI 1 "register_operand" "r")
+ (const_int 8)))]
+ ""
+ "mov __tmp_reg__,%D1
+ mov %D0,%C1
+ mov %C0,%B1
+ mov %B0,%A1
+ mov %A0, __tmp_reg__"
+ "reload_completed
+ && REGNO (operands[0]) != REGNO (operands[1])"
+ [(const_int 0)]
+ "unsigned int si_lo_off = subreg_lowpart_offset (HImode, SImode);
+ unsigned int si_hi_off = subreg_highpart_offset (HImode, SImode);
+ unsigned int hi_lo_off = subreg_lowpart_offset (QImode, HImode);
+ unsigned int hi_hi_off = subreg_highpart_offset (QImode, HImode);
+
+ operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, si_lo_off);
+ operands[4] = simplify_gen_subreg (HImode, operands[0], SImode, si_hi_off);
+ operands[3] = simplify_gen_subreg (QImode, operands[2], HImode, hi_hi_off);
+ operands[2] = simplify_gen_subreg (QImode, operands[2], HImode, hi_lo_off);
+ operands[5] = simplify_gen_subreg (QImode, operands[4], HImode, hi_hi_off);
+ operands[4] = simplify_gen_subreg (QImode, operands[4], HImode, hi_lo_off);
+
+ operands[6] = simplify_gen_subreg (HImode, operands[1], SImode, si_lo_off);
+ operands[8] = simplify_gen_subreg (HImode, operands[1], SImode, si_hi_off);
+ operands[7] = simplify_gen_subreg (QImode, operands[6], HImode, hi_hi_off);
+ operands[6] = simplify_gen_subreg (QImode, operands[6], HImode, hi_lo_off);
+ operands[9] = simplify_gen_subreg (QImode, operands[8], HImode, hi_hi_off);
+ operands[8] = simplify_gen_subreg (QImode, operands[8], HImode, hi_lo_off);
+
+ if (REGNO (operands[0]) < REGNO(operands[1]))
+ {
+ emit_move_insn (operands[2], operands[9]);
+ emit_move_insn (operands[3], operands[6]);
+ emit_move_insn (operands[4], operands[7]);
+ emit_move_insn (operands[5], operands[8]);
+ }
+ else
+ {
+ emit_move_insn (operands[5], operands[8]);
+ emit_move_insn (operands[2], operands[9]);
+ emit_move_insn (operands[4], operands[7]);
+ emit_move_insn (operands[3], operands[6]);
+ }
+ DONE;"
+ [(set_attr "length" "5")
+ (set_attr "cc" "none")])
+
+(define_insn_and_split "*rotlsi3_24"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (rotate:SI (match_operand:SI 1 "register_operand" "r")
+ (const_int 24)))]
+ ""
+ "mov __tmp_reg__,%A1
+ mov %A0,%B1
+ mov %B0,%C1
+ mov %C0,%D1
+ mov %D0, __tmp_reg__"
+ "reload_completed
+ && REGNO (operands[0]) != REGNO (operands[1])"
+ [(const_int 0)]
+ "unsigned int si_lo_off = subreg_lowpart_offset (HImode, SImode);
+ unsigned int si_hi_off = subreg_highpart_offset (HImode, SImode);
+ unsigned int hi_lo_off = subreg_lowpart_offset (QImode, HImode);
+ unsigned int hi_hi_off = subreg_highpart_offset (QImode, HImode);
+
+ operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, si_lo_off);
+ operands[4] = simplify_gen_subreg (HImode, operands[0], SImode, si_hi_off);
+ operands[3] = simplify_gen_subreg (QImode, operands[2], HImode, hi_hi_off);
+ operands[2] = simplify_gen_subreg (QImode, operands[2], HImode, hi_lo_off);
+ operands[5] = simplify_gen_subreg (QImode, operands[4], HImode, hi_hi_off);
+ operands[4] = simplify_gen_subreg (QImode, operands[4], HImode, hi_lo_off);
+
+ operands[6] = simplify_gen_subreg (HImode, operands[1], SImode, si_lo_off);
+ operands[8] = simplify_gen_subreg (HImode, operands[1], SImode, si_hi_off);
+ operands[7] = simplify_gen_subreg (QImode, operands[6], HImode, hi_hi_off);
+ operands[6] = simplify_gen_subreg (QImode, operands[6], HImode, hi_lo_off);
+ operands[9] = simplify_gen_subreg (QImode, operands[8], HImode, hi_hi_off);
+ operands[8] = simplify_gen_subreg (QImode, operands[8], HImode, hi_lo_off);
+
+ if (REGNO (operands[0]) < REGNO(operands[1]))
+ {
+ emit_move_insn (operands[2], operands[7]);
+ emit_move_insn (operands[5], operands[6]);
+ emit_move_insn (operands[3], operands[8]);
+ emit_move_insn (operands[4], operands[9]);
+ }
+ else
+ {
+ emit_move_insn (operands[5], operands[6]);
+ emit_move_insn (operands[4], operands[9]);
+ emit_move_insn (operands[3], operands[8]);
+ emit_move_insn (operands[2], operands[7]);
+ }
+ DONE;"
+ [(set_attr "length" "5")
+ (set_attr "cc" "none")])
+
;;<< << << << << << << << << << << << << << << << << << << << << << << << << <<
;; arithmetic shift left
-(define_insn "ashlqi3"
- [(set (match_operand:QI 0 "register_operand" "=r,r,r,!d,r,r")
- (ashift:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0")
- (match_operand:QI 2 "general_operand" "r,P,K,n,n,Qm")))]
+(define_expand "ashlqi3"
+ [(set (match_operand:QI 0 "register_operand" "")
+ (ashift:QI (match_operand:QI 1 "register_operand" "")
+ (match_operand:QI 2 "general_operand" "")))]
+ ""
+ "")
+
+(define_split ; ashlqi3_const4
+ [(set (match_operand:QI 0 "d_register_operand" "")
+ (ashift:QI (match_dup 0)
+ (const_int 4)))]
+ ""
+ [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
+ (set (match_dup 0) (and:QI (match_dup 0) (const_int -16)))]
+ "")
+
+(define_split ; ashlqi3_const5
+ [(set (match_operand:QI 0 "d_register_operand" "")
+ (ashift:QI (match_dup 0)
+ (const_int 5)))]
+ ""
+ [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
+ (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 1)))
+ (set (match_dup 0) (and:QI (match_dup 0) (const_int -32)))]
+ "")
+
+(define_split ; ashlqi3_const6
+ [(set (match_operand:QI 0 "d_register_operand" "")
+ (ashift:QI (match_dup 0)
+ (const_int 6)))]
+ ""
+ [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
+ (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 2)))
+ (set (match_dup 0) (and:QI (match_dup 0) (const_int -64)))]
+ "")
+
+(define_insn "*ashlqi3"
+ [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
+ (ashift:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
+ (match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
""
"* return ashlqi3_out (insn, operands, NULL);"
- [(set_attr "length" "5,1,2,4,6,9")
- (set_attr "cc" "clobber,set_czn,set_czn,set_czn,set_czn,clobber")])
+ [(set_attr "length" "5,0,1,2,4,6,9")
+ (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
(define_insn "ashlhi3"
- [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
- (ashift:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0,0")
- (match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
+ [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
+ (ashift:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
+ (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
""
"* return ashlhi3_out (insn, operands, NULL);"
- [(set_attr "length" "6,2,2,4,10,10")
- (set_attr "cc" "clobber,set_n,clobber,set_n,clobber,clobber")])
+ [(set_attr "length" "6,0,2,2,4,10,10")
+ (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
(define_insn "ashlsi3"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
- (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r,0,0,0")
- (match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
+ (ashift:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
+ (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
""
"* return ashlsi3_out (insn, operands, NULL);"
- [(set_attr "length" "8,4,4,8,10,12")
- (set_attr "cc" "clobber,set_n,clobber,set_n,clobber,clobber")])
+ [(set_attr "length" "8,0,4,4,8,10,12")
+ (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
;; Optimize if a scratch register from LD_REGS happens to be available.
+(define_peephole2 ; ashlqi3_l_const4
+ [(set (match_operand:QI 0 "l_register_operand" "")
+ (ashift:QI (match_dup 0)
+ (const_int 4)))
+ (match_scratch:QI 1 "d")]
+ ""
+ [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
+ (set (match_dup 1) (const_int -16))
+ (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
+ "")
+
+(define_peephole2 ; ashlqi3_l_const5
+ [(set (match_operand:QI 0 "l_register_operand" "")
+ (ashift:QI (match_dup 0)
+ (const_int 5)))
+ (match_scratch:QI 1 "d")]
+ ""
+ [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
+ (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 1)))
+ (set (match_dup 1) (const_int -32))
+ (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
+ "")
+
+(define_peephole2 ; ashlqi3_l_const6
+ [(set (match_operand:QI 0 "l_register_operand" "")
+ (ashift:QI (match_dup 0)
+ (const_int 6)))
+ (match_scratch:QI 1 "d")]
+ ""
+ [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
+ (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 2)))
+ (set (match_dup 1) (const_int -64))
+ (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
+ "")
+
(define_peephole2
[(match_scratch:QI 3 "d")
(set (match_operand:HI 0 "register_operand" "")
""
[(parallel [(set (match_dup 0) (ashift:HI (match_dup 1) (match_dup 2)))
(clobber (match_dup 3))])]
- "if (!avr_peep2_scratch_safe (operands[3]))
- FAIL;")
+ "")
(define_insn "*ashlhi3_const"
- [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
- (ashift:HI (match_operand:HI 1 "register_operand" "0,r,0,0")
- (match_operand:QI 2 "const_int_operand" "P,O,K,n")))
- (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
+ [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
+ (ashift:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
+ (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
"reload_completed"
"* return ashlhi3_out (insn, operands, NULL);"
- [(set_attr "length" "2,2,4,10")
- (set_attr "cc" "set_n,clobber,set_n,clobber")])
+ [(set_attr "length" "0,2,2,4,10")
+ (set_attr "cc" "none,set_n,clobber,set_n,clobber")])
(define_peephole2
[(match_scratch:QI 3 "d")
""
[(parallel [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
(clobber (match_dup 3))])]
- "if (!avr_peep2_scratch_safe (operands[3]))
- FAIL;")
+ "")
(define_insn "*ashlsi3_const"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r")
- (ashift:SI (match_operand:SI 1 "register_operand" "0,r,0")
- (match_operand:QI 2 "const_int_operand" "P,O,n")))
- (clobber (match_scratch:QI 3 "=X,X,&d"))]
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
+ (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
+ (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
"reload_completed"
"* return ashlsi3_out (insn, operands, NULL);"
- [(set_attr "length" "4,4,10")
- (set_attr "cc" "set_n,clobber,clobber")])
+ [(set_attr "length" "0,4,4,10")
+ (set_attr "cc" "none,set_n,clobber,clobber")])
;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
;; arithmetic shift right
(define_insn "ashrqi3"
- [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
- (ashiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0")
- (match_operand:QI 2 "general_operand" "r,P,K,n,Qm")))]
+ [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
+ (ashiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0")
+ (match_operand:QI 2 "general_operand" "r,L,P,K,n,Qm")))]
""
"* return ashrqi3_out (insn, operands, NULL);"
- [(set_attr "length" "5,1,2,5,9")
- (set_attr "cc" "clobber,clobber,clobber,clobber,clobber")])
+ [(set_attr "length" "5,0,1,2,5,9")
+ (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber")])
(define_insn "ashrhi3"
- [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
- (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0,0")
- (match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
+ [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
+ (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
+ (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
""
"* return ashrhi3_out (insn, operands, NULL);"
- [(set_attr "length" "6,2,4,4,10,10")
- (set_attr "cc" "clobber,clobber,set_n,clobber,clobber,clobber")])
+ [(set_attr "length" "6,0,2,4,4,10,10")
+ (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
(define_insn "ashrsi3"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0,0,0")
- (match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
+ (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
""
"* return ashrsi3_out (insn, operands, NULL);"
- [(set_attr "length" "8,4,6,8,10,12")
- (set_attr "cc" "clobber,clobber,set_n,clobber,clobber,clobber")])
+ [(set_attr "length" "8,0,4,6,8,10,12")
+ (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
;; Optimize if a scratch register from LD_REGS happens to be available.
""
[(parallel [(set (match_dup 0) (ashiftrt:HI (match_dup 1) (match_dup 2)))
(clobber (match_dup 3))])]
- "if (!avr_peep2_scratch_safe (operands[3]))
- FAIL;")
+ "")
(define_insn "*ashrhi3_const"
- [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
- (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,r,0,0")
- (match_operand:QI 2 "const_int_operand" "P,O,K,n")))
- (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
+ [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
+ (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
+ (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
"reload_completed"
"* return ashrhi3_out (insn, operands, NULL);"
- [(set_attr "length" "2,4,4,10")
- (set_attr "cc" "clobber,set_n,clobber,clobber")])
+ [(set_attr "length" "0,2,4,4,10")
+ (set_attr "cc" "none,clobber,set_n,clobber,clobber")])
(define_peephole2
[(match_scratch:QI 3 "d")
""
[(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (match_dup 2)))
(clobber (match_dup 3))])]
- "if (!avr_peep2_scratch_safe (operands[3]))
- FAIL;")
+ "")
(define_insn "*ashrsi3_const"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,r,0")
- (match_operand:QI 2 "const_int_operand" "P,O,n")))
- (clobber (match_scratch:QI 3 "=X,X,&d"))]
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
+ (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
"reload_completed"
"* return ashrsi3_out (insn, operands, NULL);"
- [(set_attr "length" "4,4,10")
- (set_attr "cc" "clobber,set_n,clobber")])
+ [(set_attr "length" "0,4,4,10")
+ (set_attr "cc" "none,clobber,set_n,clobber")])
;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
;; logical shift right
-(define_insn "lshrqi3"
- [(set (match_operand:QI 0 "register_operand" "=r,r,r,!d,r,r")
- (lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0")
- (match_operand:QI 2 "general_operand" "r,P,K,n,n,Qm")))]
+(define_expand "lshrqi3"
+ [(set (match_operand:QI 0 "register_operand" "")
+ (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
+ (match_operand:QI 2 "general_operand" "")))]
+ ""
+ "")
+
+(define_split ; lshrqi3_const4
+ [(set (match_operand:QI 0 "d_register_operand" "")
+ (lshiftrt:QI (match_dup 0)
+ (const_int 4)))]
+ ""
+ [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
+ (set (match_dup 0) (and:QI (match_dup 0) (const_int 15)))]
+ "")
+
+(define_split ; lshrqi3_const5
+ [(set (match_operand:QI 0 "d_register_operand" "")
+ (lshiftrt:QI (match_dup 0)
+ (const_int 5)))]
+ ""
+ [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
+ (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 1)))
+ (set (match_dup 0) (and:QI (match_dup 0) (const_int 7)))]
+ "")
+
+(define_split ; lshrqi3_const6
+ [(set (match_operand:QI 0 "d_register_operand" "")
+ (lshiftrt:QI (match_dup 0)
+ (const_int 6)))]
+ ""
+ [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
+ (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 2)))
+ (set (match_dup 0) (and:QI (match_dup 0) (const_int 3)))]
+ "")
+
+(define_insn "*lshrqi3"
+ [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
+ (lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
+ (match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
""
"* return lshrqi3_out (insn, operands, NULL);"
- [(set_attr "length" "5,1,2,4,6,9")
- (set_attr "cc" "clobber,set_czn,set_czn,set_czn,set_czn,clobber")])
+ [(set_attr "length" "5,0,1,2,4,6,9")
+ (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
(define_insn "lshrhi3"
- [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
- (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0,0")
- (match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
+ [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
+ (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
+ (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
""
"* return lshrhi3_out (insn, operands, NULL);"
- [(set_attr "length" "6,2,2,4,10,10")
- (set_attr "cc" "clobber,clobber,clobber,clobber,clobber,clobber")])
+ [(set_attr "length" "6,0,2,2,4,10,10")
+ (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
(define_insn "lshrsi3"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0,0,0")
- (match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
+ (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
""
"* return lshrsi3_out (insn, operands, NULL);"
- [(set_attr "length" "8,4,4,8,10,12")
- (set_attr "cc" "clobber,clobber,clobber,clobber,clobber,clobber")])
+ [(set_attr "length" "8,0,4,4,8,10,12")
+ (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
;; Optimize if a scratch register from LD_REGS happens to be available.
+(define_peephole2 ; lshrqi3_l_const4
+ [(set (match_operand:QI 0 "l_register_operand" "")
+ (lshiftrt:QI (match_dup 0)
+ (const_int 4)))
+ (match_scratch:QI 1 "d")]
+ ""
+ [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
+ (set (match_dup 1) (const_int 15))
+ (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
+ "")
+
+(define_peephole2 ; lshrqi3_l_const5
+ [(set (match_operand:QI 0 "l_register_operand" "")
+ (lshiftrt:QI (match_dup 0)
+ (const_int 5)))
+ (match_scratch:QI 1 "d")]
+ ""
+ [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
+ (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 1)))
+ (set (match_dup 1) (const_int 7))
+ (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
+ "")
+
+(define_peephole2 ; lshrqi3_l_const6
+ [(set (match_operand:QI 0 "l_register_operand" "")
+ (lshiftrt:QI (match_dup 0)
+ (const_int 6)))
+ (match_scratch:QI 1 "d")]
+ ""
+ [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
+ (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 2)))
+ (set (match_dup 1) (const_int 3))
+ (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
+ "")
+
(define_peephole2
[(match_scratch:QI 3 "d")
(set (match_operand:HI 0 "register_operand" "")
""
[(parallel [(set (match_dup 0) (lshiftrt:HI (match_dup 1) (match_dup 2)))
(clobber (match_dup 3))])]
- "if (!avr_peep2_scratch_safe (operands[3]))
- FAIL;")
+ "")
(define_insn "*lshrhi3_const"
- [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
- (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,r,0,0")
- (match_operand:QI 2 "const_int_operand" "P,O,K,n")))
- (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
+ [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
+ (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
+ (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
"reload_completed"
"* return lshrhi3_out (insn, operands, NULL);"
- [(set_attr "length" "2,2,4,10")
- (set_attr "cc" "clobber,clobber,clobber,clobber")])
+ [(set_attr "length" "0,2,2,4,10")
+ (set_attr "cc" "none,clobber,clobber,clobber,clobber")])
(define_peephole2
[(match_scratch:QI 3 "d")
""
[(parallel [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (match_dup 2)))
(clobber (match_dup 3))])]
- "if (!avr_peep2_scratch_safe (operands[3]))
- FAIL;")
+ "")
(define_insn "*lshrsi3_const"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,r,0")
- (match_operand:QI 2 "const_int_operand" "P,O,n")))
- (clobber (match_scratch:QI 3 "=X,X,&d"))]
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
+ (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
"reload_completed"
"* return lshrsi3_out (insn, operands, NULL);"
- [(set_attr "length" "4,4,10")
- (set_attr "cc" "clobber,clobber,clobber")])
+ [(set_attr "length" "0,4,4,10")
+ (set_attr "cc" "none,clobber,clobber,clobber")])
;; abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x)
;; abs
[(set_attr_alternative "length"
[(const_int 7)
(const_int 8)
- (if_then_else (eq_attr "mcu_enhanced" "yes")
+ (if_then_else (eq_attr "mcu_have_movw" "yes")
(const_int 7)
(const_int 8))])
(set_attr "cc" "set_czn,set_n,set_czn")])
{mov %A0,%A1\;mov %B0,%B1|movw %A0,%A1}\;clr %C0\;sbrc %B0,7\;com %C0\;mov %D0,%C0"
[(set_attr_alternative "length"
[(const_int 4)
- (if_then_else (eq_attr "mcu_enhanced" "yes")
+ (if_then_else (eq_attr "mcu_have_movw" "yes")
(const_int 5)
(const_int 6))])
(set_attr "cc" "set_n,set_n")])
;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
;; zero extend
-(define_insn "zero_extendqihi2"
- [(set (match_operand:HI 0 "register_operand" "=r,r")
- (zero_extend:HI (match_operand:QI 1 "register_operand" "0,*r")))]
+(define_insn_and_split "zero_extendqihi2"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
""
- "@
- clr %B0
- mov %A0,%A1\;clr %B0"
- [(set_attr "length" "1,2")
- (set_attr "cc" "set_n,set_n")])
+ "#"
+ "reload_completed"
+ [(set (match_dup 2) (match_dup 1))
+ (set (match_dup 3) (const_int 0))]
+ "unsigned int low_off = subreg_lowpart_offset (QImode, HImode);
+ unsigned int high_off = subreg_highpart_offset (QImode, HImode);
+
+ operands[2] = simplify_gen_subreg (QImode, operands[0], HImode, low_off);
+ operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, high_off);
+ ")
-(define_insn "zero_extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (zero_extend:SI (match_operand:QI 1 "register_operand" "0,*r")))]
+(define_insn_and_split "zero_extendqisi2"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
""
- "@
- clr %B0\;clr %C0\;clr %D0
- mov %A0,%A1\;clr %B0\;clr %C0\;clr %D0"
- [(set_attr "length" "3,4")
- (set_attr "cc" "set_n,set_n")])
+ "#"
+ "reload_completed"
+ [(set (match_dup 2) (zero_extend:HI (match_dup 1)))
+ (set (match_dup 3) (const_int 0))]
+ "unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
+ unsigned int high_off = subreg_highpart_offset (HImode, SImode);
+
+ operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
+ operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
+ ")
-(define_insn "zero_extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "=r,&r")
- (zero_extend:SI (match_operand:HI 1 "register_operand" "0,*r")))]
+(define_insn_and_split "zero_extendhisi2"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
""
- "@
- clr %C0\;clr %D0
- {mov %A0,%A1\;mov %B0,%B1|movw %A0,%A1}\;clr %C0\;clr %D0"
- [(set_attr_alternative "length"
- [(const_int 2)
- (if_then_else (eq_attr "mcu_enhanced" "yes")
- (const_int 3)
- (const_int 4))])
- (set_attr "cc" "set_n,set_n")])
+ "#"
+ "reload_completed"
+ [(set (match_dup 2) (match_dup 1))
+ (set (match_dup 3) (const_int 0))]
+ "unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
+ unsigned int high_off = subreg_highpart_offset (HImode, SImode);
+
+ operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
+ operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
+ ")
+
+(define_insn_and_split "zero_extendqidi2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
+ ""
+ "#"
+ "reload_completed"
+ [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
+ (set (match_dup 3) (const_int 0))]
+ "unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
+ unsigned int high_off = subreg_highpart_offset (SImode, DImode);
+
+ operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
+ operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
+ ")
+
+(define_insn_and_split "zero_extendhidi2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
+ ""
+ "#"
+ "reload_completed"
+ [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
+ (set (match_dup 3) (const_int 0))]
+ "unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
+ unsigned int high_off = subreg_highpart_offset (SImode, DImode);
+
+ operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
+ operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
+ ")
+
+(define_insn_and_split "zero_extendsidi2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
+ ""
+ "#"
+ "reload_completed"
+ [(set (match_dup 2) (match_dup 1))
+ (set (match_dup 3) (const_int 0))]
+ "unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
+ unsigned int high_off = subreg_highpart_offset (SImode, DImode);
+
+ operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
+ operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
+ ")
;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=>
;; compare
[(set_attr "cc" "compare")
(set_attr "length" "1")])
-(define_insn "*negated_tstqi"
+(define_insn "*reversed_tstqi"
[(set (cc0)
- (neg:QI (match_operand:QI 0 "register_operand" "r")))]
+ (compare (const_int 0)
+ (match_operand:QI 0 "register_operand" "r")))]
""
"cp __zero_reg__,%0"
[(set_attr "cc" "compare")
[(set_attr "cc" "compare,compare")
(set_attr "length" "1,2")])
-(define_insn "*negated_tsthi"
+(define_insn "*reversed_tsthi"
[(set (cc0)
- (neg:HI (match_operand:HI 0 "register_operand" "r")))]
+ (compare (const_int 0)
+ (match_operand:HI 0 "register_operand" "r")))]
""
"cp __zero_reg__,%A0
cpc __zero_reg__,%B0"
[(set_attr "cc" "compare")
(set_attr "length" "4")])
-(define_insn "*negated_tstsi"
+(define_insn "*reversed_tstsi"
[(set (cc0)
- (neg:SI (match_operand:SI 0 "register_operand" "r")))]
+ (compare (const_int 0)
+ (match_operand:SI 0 "register_operand" "r")))]
""
"cp __zero_reg__,%A0
cpc __zero_reg__,%B0
[(set (cc0)
(compare (sign_extend:HI
(match_operand:QI 0 "register_operand" "d"))
- (match_operand:HI 1 "immediate_operand" "M")))]
- ""
+ (match_operand:HI 1 "const_int_operand" "n")))]
+ "INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) <= 127"
"cpi %0,lo8(%1)"
[(set_attr "cc" "compare")
(set_attr "length" "1")])
[(set_attr "cc" "compare,compare,compare,compare,compare")
(set_attr "length" "4,4,7,5,8")])
+; Optimize negated tests into reverse compare if overflow is undefined.
+(define_insn_and_split "negated_tst<mode>"
+ [(set (cc0)
+ (neg:QISI (match_operand:QISI 0 "register_operand")))]
+
+ "(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
+ "#"
+ ""
+ [(set (cc0)
+ (compare (const_int 0)
+ (match_dup 0)))]
+ "")
+
;; ----------------------------------------------------------------------
;; JUMP INSTRUCTIONS
;; ----------------------------------------------------------------------
""
"")
+;; Test a single bit in a QI/HI/SImode register.
(define_insn "*sbrx_branch"
[(set (pc)
(if_then_else
- (match_operator 0 "comparison_operator"
- [(zero_extract
+ (match_operator 0 "eqne_operator"
+ [(zero_extract:HI
(match_operand:QI 1 "register_operand" "r")
(const_int 1)
- (match_operand 2 "immediate_operand" "n"))
+ (match_operand 2 "const_int_operand" "n"))
(const_int 0)])
(label_ref (match_operand 3 "" ""))
(pc)))]
- "(GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)"
- "* {
- int comp = ((get_attr_length (insn) == 4)
- ? reverse_condition (GET_CODE (operands[0]))
- : GET_CODE (operands[0]));
- if (comp == EQ)
- output_asm_insn (AS2 (sbrs,%1,%2), operands);
- else
- output_asm_insn (AS2 (sbrc,%1,%2), operands);
- if (get_attr_length (insn) != 4)
- return AS1 (rjmp,%3);
- return (AS1 (rjmp,.+4) CR_TAB
- AS1 (jmp,%3));
- }"
+ ""
+ "* return avr_out_sbxx_branch (insn, operands);"
[(set (attr "length")
(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
(le (minus (pc) (match_dup 3)) (const_int 2046)))
(const_int 4))))
(set_attr "cc" "clobber")])
-(define_insn "*sbrx_and_branchsi"
+(define_insn "*sbrx_and_branchhi"
[(set (pc)
(if_then_else
- (match_operator 0 "comparison_operator"
- [(and:SI
- (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "immediate_operand" "n"))
+ (match_operator 0 "eqne_operator"
+ [(and:HI
+ (match_operand:HI 1 "register_operand" "r")
+ (match_operand:HI 2 "single_one_operand" "n"))
(const_int 0)])
(label_ref (match_operand 3 "" ""))
(pc)))]
- "(GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)
- && mask_one_bit_p(INTVAL (operands[2]))"
- "* {
- int comp = ((get_attr_length (insn) == 4)
- ? reverse_condition (GET_CODE (operands[0]))
- : GET_CODE (operands[0]));
- int bit = mask_one_bit_p(INTVAL (operands[2])) - 1;
- static char buf[] = \"sbrc %A1,0\";
- buf[3] = (comp == EQ ? 's' : 'c');
- buf[6] = bit / 8 + 'A';
- buf[9] = bit % 8 + '0';
- output_asm_insn (buf, operands);
-
- if (get_attr_length (insn) != 4)
- return AS1 (rjmp,%3);
- return (AS1 (rjmp,.+4) CR_TAB
- AS1 (jmp,%3));
- }"
+ ""
+ "* return avr_out_sbxx_branch (insn, operands);"
[(set (attr "length")
(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
(le (minus (pc) (match_dup 3)) (const_int 2046)))
(const_int 4))))
(set_attr "cc" "clobber")])
-(define_insn "*sbrx_and_branchhi"
+(define_insn "*sbrx_and_branchsi"
[(set (pc)
(if_then_else
- (match_operator 0 "comparison_operator"
- [(and:HI
- (match_operand:HI 1 "register_operand" "r")
- (match_operand:HI 2 "immediate_operand" "n"))
+ (match_operator 0 "eqne_operator"
+ [(and:SI
+ (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "single_one_operand" "n"))
(const_int 0)])
(label_ref (match_operand 3 "" ""))
(pc)))]
- "(GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)
- && mask_one_bit_p(INTVAL (operands[2]))"
- "* {
- int comp = ((get_attr_length (insn) == 4)
- ? reverse_condition (GET_CODE (operands[0]))
- : GET_CODE (operands[0]));
- int bit = mask_one_bit_p(INTVAL (operands[2])) - 1;
- static char buf[] = \"sbrc %A1,0\";
- buf[3] = (comp == EQ ? 's' : 'c');
- buf[6] = bit / 8 + 'A';
- buf[9] = bit % 8 + '0';
- output_asm_insn (buf, operands);
-
- if (get_attr_length (insn) != 4)
- return AS1 (rjmp,%3);
- return (AS1 (rjmp,.+4) CR_TAB
- AS1 (jmp,%3));
- }"
+ ""
+ "* return avr_out_sbxx_branch (insn, operands);"
[(set (attr "length")
(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
(le (minus (pc) (match_dup 3)) (const_int 2046)))
(const_int 4))))
(set_attr "cc" "clobber")])
+;; Convert sign tests to bit 7/15/31 tests that match the above insns.
+(define_peephole2
+ [(set (cc0) (match_operand:QI 0 "register_operand" ""))
+ (set (pc) (if_then_else (ge (cc0) (const_int 0))
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
+ ""
+ [(set (pc) (if_then_else (eq (zero_extract:HI (match_dup 0)
+ (const_int 1)
+ (const_int 7))
+ (const_int 0))
+ (label_ref (match_dup 1))
+ (pc)))]
+ "")
+
+(define_peephole2
+ [(set (cc0) (match_operand:QI 0 "register_operand" ""))
+ (set (pc) (if_then_else (lt (cc0) (const_int 0))
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
+ ""
+ [(set (pc) (if_then_else (ne (zero_extract:HI (match_dup 0)
+ (const_int 1)
+ (const_int 7))
+ (const_int 0))
+ (label_ref (match_dup 1))
+ (pc)))]
+ "")
+
+(define_peephole2
+ [(set (cc0) (match_operand:HI 0 "register_operand" ""))
+ (set (pc) (if_then_else (ge (cc0) (const_int 0))
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
+ ""
+ [(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768))
+ (const_int 0))
+ (label_ref (match_dup 1))
+ (pc)))]
+ "")
+
+(define_peephole2
+ [(set (cc0) (match_operand:HI 0 "register_operand" ""))
+ (set (pc) (if_then_else (lt (cc0) (const_int 0))
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
+ ""
+ [(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768))
+ (const_int 0))
+ (label_ref (match_dup 1))
+ (pc)))]
+ "")
+
+(define_peephole2
+ [(set (cc0) (match_operand:SI 0 "register_operand" ""))
+ (set (pc) (if_then_else (ge (cc0) (const_int 0))
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
+ ""
+ [(set (pc) (if_then_else (eq (and:SI (match_dup 0) (match_dup 2))
+ (const_int 0))
+ (label_ref (match_dup 1))
+ (pc)))]
+ "operands[2] = GEN_INT (-2147483647 - 1);")
+
+(define_peephole2
+ [(set (cc0) (match_operand:SI 0 "register_operand" ""))
+ (set (pc) (if_then_else (lt (cc0) (const_int 0))
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
+ ""
+ [(set (pc) (if_then_else (ne (and:SI (match_dup 0) (match_dup 2))
+ (const_int 0))
+ (label_ref (match_dup 1))
+ (pc)))]
+ "operands[2] = GEN_INT (-2147483647 - 1);")
+
;; ************************************************************************
;; Implementation of conditional jumps here.
;; Compare with 0 (test) jumps
(define_insn "branch"
[(set (pc)
- (if_then_else (match_operator 1 "comparison_operator"
+ (if_then_else (match_operator 1 "simple_comparison_operator"
[(cc0)
(const_int 0)])
(label_ref (match_operand 0 "" ""))
(pc)))]
- "! (GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GTU
- || GET_CODE (operands[1]) == LE || GET_CODE (operands[1]) == LEU)"
+ ""
"*
return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
[(set_attr "type" "branch")
(define_insn "difficult_branch"
[(set (pc)
- (if_then_else (match_operator 1 "comparison_operator"
+ (if_then_else (match_operator 1 "difficult_comparison_operator"
[(cc0)
(const_int 0)])
(label_ref (match_operand 0 "" ""))
(pc)))]
- "(GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GTU
- || GET_CODE (operands[1]) == LE || GET_CODE (operands[1]) == LEU)"
+ ""
"*
return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
[(set_attr "type" "branch1")
(define_insn "rvbranch"
[(set (pc)
- (if_then_else (match_operator 1 "comparison_operator" [(cc0)
- (const_int 0)])
+ (if_then_else (match_operator 1 "simple_comparison_operator"
+ [(cc0)
+ (const_int 0)])
(pc)
(label_ref (match_operand 0 "" ""))))]
- "! (GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GTU
- || GET_CODE (operands[1]) == LE || GET_CODE (operands[1]) == LEU)"
+ ""
"*
return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
[(set_attr "type" "branch1")
(define_insn "difficult_rvbranch"
[(set (pc)
- (if_then_else (match_operator 1 "comparison_operator" [(cc0)
- (const_int 0)])
+ (if_then_else (match_operator 1 "difficult_comparison_operator"
+ [(cc0)
+ (const_int 0)])
(pc)
(label_ref (match_operand 0 "" ""))))]
- "(GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GTU
- || GET_CODE (operands[1]) == LE || GET_CODE (operands[1]) == LEU)"
+ ""
"*
return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
[(set_attr "type" "branch")
(label_ref (match_operand 0 "" "")))]
""
"*{
- if (AVR_MEGA && get_attr_length (insn) != 1)
+ if (AVR_HAVE_JMP_CALL && get_attr_length (insn) != 1)
return AS1 (jmp,%0);
return AS1 (rjmp,%0);
}"
[(set (attr "length")
- (if_then_else (and (ge (minus (pc) (match_dup 0)) (const_int -2047))
- (le (minus (pc) (match_dup 0)) (const_int 2047)))
- (const_int 1)
- (const_int 2)))
+ (if_then_else (match_operand 0 "symbol_ref_operand" "")
+ (if_then_else (eq_attr "mcu_mega" "no")
+ (const_int 1)
+ (const_int 2))
+ (if_then_else (and (ge (minus (pc) (match_dup 0)) (const_int -2047))
+ (le (minus (pc) (match_dup 0)) (const_int 2047)))
+ (const_int 1)
+ (const_int 2))))
(set_attr "cc" "none")])
;; call
"")
(define_insn "call_insn"
- [(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "!z,*r,i"))
- (match_operand:HI 1 "general_operand" "X,X,X"))]
+ [(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "!z,*r,s,n"))
+ (match_operand:HI 1 "general_operand" "X,X,X,X"))]
;; We don't need in saving Z register because r30,r31 is a call used registers
;; Operand 1 not used on the AVR.
"(register_operand (operands[0], HImode) || CONSTANT_P (operands[0]))"
"*{
if (which_alternative==0)
- return \"icall\";
+ return \"%!icall\";
else if (which_alternative==1)
{
- if (AVR_ENHANCED)
+ if (AVR_HAVE_MOVW)
return (AS2 (movw, r30, %0) CR_TAB
- \"icall\");
+ \"%!icall\");
else
return (AS2 (mov, r30, %A0) CR_TAB
AS2 (mov, r31, %B0) CR_TAB
- \"icall\");
+ \"%!icall\");
}
- return AS1(%~call,%c0);
+ else if (which_alternative==2)
+ return AS1(%~call,%c0);
+ return (AS2 (ldi,r30,lo8(%0)) CR_TAB
+ AS2 (ldi,r31,hi8(%0)) CR_TAB
+ \"%!icall\");
}"
- [(set_attr "cc" "clobber,clobber,clobber")
+ [(set_attr "cc" "clobber,clobber,clobber,clobber")
(set_attr_alternative "length"
[(const_int 1)
- (if_then_else (eq_attr "mcu_enhanced" "yes")
+ (if_then_else (eq_attr "mcu_have_movw" "yes")
(const_int 2)
(const_int 3))
(if_then_else (eq_attr "mcu_mega" "yes")
(const_int 2)
- (const_int 1))])])
+ (const_int 1))
+ (const_int 3)])])
(define_insn "call_value_insn"
- [(set (match_operand 0 "register_operand" "=r,r,r")
- (call (mem:HI (match_operand:HI 1 "nonmemory_operand" "!z,*r,i"))
+ [(set (match_operand 0 "register_operand" "=r,r,r,r")
+ (call (mem:HI (match_operand:HI 1 "nonmemory_operand" "!z,*r,s,n"))
;; We don't need in saving Z register because r30,r31 is a call used registers
- (match_operand:HI 2 "general_operand" "X,X,X")))]
+ (match_operand:HI 2 "general_operand" "X,X,X,X")))]
;; Operand 2 not used on the AVR.
"(register_operand (operands[0], VOIDmode) || CONSTANT_P (operands[0]))"
- "*
-{
+ "*{
if (which_alternative==0)
- return \"icall\";
+ return \"%!icall\";
else if (which_alternative==1)
{
- if (AVR_ENHANCED)
+ if (AVR_HAVE_MOVW)
return (AS2 (movw, r30, %1) CR_TAB
- \"icall\");
+ \"%!icall\");
else
return (AS2 (mov, r30, %A1) CR_TAB
AS2 (mov, r31, %B1) CR_TAB
- \"icall\");
+ \"%!icall\");
}
- return AS1(%~call,%c1);
+ else if (which_alternative==2)
+ return AS1(%~call,%c1);
+ return (AS2 (ldi, r30, lo8(%1)) CR_TAB
+ AS2 (ldi, r31, hi8(%1)) CR_TAB
+ \"%!icall\");
}"
- [(set_attr "cc" "clobber,clobber,clobber")
+ [(set_attr "cc" "clobber,clobber,clobber,clobber")
(set_attr_alternative "length"
[(const_int 1)
- (if_then_else (eq_attr "mcu_enhanced" "yes")
+ (if_then_else (eq_attr "mcu_have_movw" "yes")
(const_int 2)
(const_int 3))
(if_then_else (eq_attr "mcu_mega" "yes")
(const_int 2)
- (const_int 1))])])
+ (const_int 1))
+ (const_int 3)])])
(define_insn "nop"
[(const_int 0)]
; indirect jump
(define_insn "indirect_jump"
[(set (pc) (match_operand:HI 0 "register_operand" "!z,*r"))]
- ""
+ "!AVR_HAVE_EIJMP_EICALL"
"@
ijmp
push %A0\;push %B0\;ret"
[(set_attr "length" "1,3")
(set_attr "cc" "none,none")])
+(define_insn "*indirect_jump_avr6"
+ [(set (pc) (match_operand:HI 0 "register_operand" "z"))]
+ "AVR_HAVE_EIJMP_EICALL"
+ "eijmp"
+ [(set_attr "length" "1")
+ (set_attr "cc" "none")])
+
;; table jump
;; Table made from "rjmp" instructions for <=8K devices.
(define_insn "*tablejump_rjmp"
- [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "!z,*r")] 1))
+ [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "!z,*r")]
+ UNSPEC_INDEX_JMP))
(use (label_ref (match_operand 1 "" "")))
(clobber (match_dup 0))]
- "!AVR_MEGA"
+ "(!AVR_HAVE_JMP_CALL) && (!AVR_HAVE_EIJMP_EICALL)"
"@
ijmp
push %A0\;push %B0\;ret"
;; Not a prologue, but similar idea - move the common piece of code to libgcc.
(define_insn "*tablejump_lib"
- [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")] 1))
+ [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
+ UNSPEC_INDEX_JMP))
(use (label_ref (match_operand 1 "" "")))
(clobber (match_dup 0))]
- "AVR_MEGA && TARGET_CALL_PROLOGUES"
+ "AVR_HAVE_JMP_CALL && TARGET_CALL_PROLOGUES"
"jmp __tablejump2__"
[(set_attr "length" "2")
(set_attr "cc" "clobber")])
(define_insn "*tablejump_enh"
- [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")] 1))
+ [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
+ UNSPEC_INDEX_JMP))
(use (label_ref (match_operand 1 "" "")))
(clobber (match_dup 0))]
- "AVR_MEGA && AVR_ENHANCED"
+ "AVR_HAVE_JMP_CALL && AVR_HAVE_LPMX"
"lsl r30
rol r31
lpm __tmp_reg__,Z+
lpm r31,Z
mov r30,__tmp_reg__
- ijmp"
+ %!ijmp"
[(set_attr "length" "6")
(set_attr "cc" "clobber")])
(define_insn "*tablejump"
- [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")] 1))
+ [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
+ UNSPEC_INDEX_JMP))
(use (label_ref (match_operand 1 "" "")))
(clobber (match_dup 0))]
- "AVR_MEGA"
+ "AVR_HAVE_JMP_CALL && !AVR_HAVE_EIJMP_EICALL"
"lsl r30
rol r31
lpm
(set (match_dup 6)
(plus:HI (match_dup 6) (label_ref (match_operand:HI 3 "" ""))))
- (parallel [(set (pc) (unspec:HI [(match_dup 6)] 1))
+ (parallel [(set (pc) (unspec:HI [(match_dup 6)] UNSPEC_INDEX_JMP))
(use (label_ref (match_dup 3)))
(clobber (match_dup 6))])]
""
;; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-;; This instructin sets Z flag
+;; This instruction sets Z flag
(define_insn "sez"
[(set (cc0) (const_int 0))]
[(set_attr "length" "1")
(set_attr "cc" "compare")])
+;; Clear/set/test a single bit in I/O address space.
+
+(define_insn "*cbi"
+ [(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
+ (and:QI (mem:QI (match_dup 0))
+ (match_operand:QI 1 "single_zero_operand" "n")))]
+ "(optimize > 0)"
+{
+ operands[2] = GEN_INT (exact_log2 (~INTVAL (operands[1]) & 0xff));
+ return AS2 (cbi,%0-0x20,%2);
+}
+ [(set_attr "length" "1")
+ (set_attr "cc" "none")])
+
+(define_insn "*sbi"
+ [(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
+ (ior:QI (mem:QI (match_dup 0))
+ (match_operand:QI 1 "single_one_operand" "n")))]
+ "(optimize > 0)"
+{
+ operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
+ return AS2 (sbi,%0-0x20,%2);
+}
+ [(set_attr "length" "1")
+ (set_attr "cc" "none")])
+
+;; Lower half of the I/O space - use sbic/sbis directly.
+(define_insn "*sbix_branch"
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "eqne_operator"
+ [(zero_extract:HI
+ (mem:QI (match_operand 1 "low_io_address_operand" "n"))
+ (const_int 1)
+ (match_operand 2 "const_int_operand" "n"))
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ "(optimize > 0)"
+ "* return avr_out_sbxx_branch (insn, operands);"
+ [(set (attr "length")
+ (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
+ (le (minus (pc) (match_dup 3)) (const_int 2046)))
+ (const_int 2)
+ (if_then_else (eq_attr "mcu_mega" "no")
+ (const_int 2)
+ (const_int 4))))
+ (set_attr "cc" "clobber")])
+
+;; Tests of bit 7 are pessimized to sign tests, so we need this too...
+(define_insn "*sbix_branch_bit7"
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "gelt_operator"
+ [(mem:QI (match_operand 1 "low_io_address_operand" "n"))
+ (const_int 0)])
+ (label_ref (match_operand 2 "" ""))
+ (pc)))]
+ "(optimize > 0)"
+{
+ operands[3] = operands[2];
+ operands[2] = GEN_INT (7);
+ return avr_out_sbxx_branch (insn, operands);
+}
+ [(set (attr "length")
+ (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
+ (le (minus (pc) (match_dup 2)) (const_int 2046)))
+ (const_int 2)
+ (if_then_else (eq_attr "mcu_mega" "no")
+ (const_int 2)
+ (const_int 4))))
+ (set_attr "cc" "clobber")])
+
+;; Upper half of the I/O space - read port to __tmp_reg__ and use sbrc/sbrs.
+(define_insn "*sbix_branch_tmp"
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "eqne_operator"
+ [(zero_extract:HI
+ (mem:QI (match_operand 1 "high_io_address_operand" "n"))
+ (const_int 1)
+ (match_operand 2 "const_int_operand" "n"))
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ "(optimize > 0)"
+ "* return avr_out_sbxx_branch (insn, operands);"
+ [(set (attr "length")
+ (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
+ (le (minus (pc) (match_dup 3)) (const_int 2045)))
+ (const_int 3)
+ (if_then_else (eq_attr "mcu_mega" "no")
+ (const_int 3)
+ (const_int 5))))
+ (set_attr "cc" "clobber")])
+
+(define_insn "*sbix_branch_tmp_bit7"
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "gelt_operator"
+ [(mem:QI (match_operand 1 "high_io_address_operand" "n"))
+ (const_int 0)])
+ (label_ref (match_operand 2 "" ""))
+ (pc)))]
+ "(optimize > 0)"
+{
+ operands[3] = operands[2];
+ operands[2] = GEN_INT (7);
+ return avr_out_sbxx_branch (insn, operands);
+}
+ [(set (attr "length")
+ (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
+ (le (minus (pc) (match_dup 2)) (const_int 2045)))
+ (const_int 3)
+ (if_then_else (eq_attr "mcu_mega" "no")
+ (const_int 3)
+ (const_int 5))))
+ (set_attr "cc" "clobber")])
;; ************************* Peepholes ********************************
(define_peephole
- [(set (match_operand:SI 0 "register_operand" "")
+ [(set (match_operand:SI 0 "d_register_operand" "")
(plus:SI (match_dup 0)
(const_int -1)))
(parallel
[(set (cc0)
(compare (match_dup 0)
(const_int -1)))
- (clobber (match_operand:QI 1 "register_operand" ""))])
+ (clobber (match_operand:QI 1 "d_register_operand" ""))])
(set (pc)
(if_then_else (ne (cc0) (const_int 0))
(label_ref (match_operand 2 "" ""))
(pc)))]
- "(test_hard_reg_class (LD_REGS, operands[0])
- && test_hard_reg_class (LD_REGS, operands[1]))"
+ ""
"*
{
CC_STATUS_INIT;
}")
(define_peephole
- [(set (match_operand:HI 0 "register_operand" "")
+ [(set (match_operand:HI 0 "d_register_operand" "")
(plus:HI (match_dup 0)
(const_int -1)))
(parallel
[(set (cc0)
(compare (match_dup 0)
(const_int 65535)))
- (clobber (match_operand:QI 1 "register_operand" ""))])
+ (clobber (match_operand:QI 1 "d_register_operand" ""))])
(set (pc)
(if_then_else (ne (cc0) (const_int 0))
(label_ref (match_operand 2 "" ""))
(pc)))]
- "(test_hard_reg_class (LD_REGS, operands[0])
- && test_hard_reg_class (LD_REGS, operands[1]))"
+ ""
"*
{
CC_STATUS_INIT;
}")
(define_peephole
- [(set (match_operand:QI 0 "register_operand" "")
+ [(set (match_operand:QI 0 "d_register_operand" "")
(plus:QI (match_dup 0)
(const_int -1)))
(set (cc0)
(if_then_else (ne (cc0) (const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))]
- "test_hard_reg_class (LD_REGS, operands[0])"
+ ""
"*
{
CC_STATUS_INIT;
return (AS1 (brcs,.+4) CR_TAB
AS1 (jmp,%1));
}")
-
-(define_peephole
- [(set (cc0) (match_operand:QI 0 "register_operand" ""))
- (set (pc)
- (if_then_else (lt (cc0) (const_int 0))
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- "jump_over_one_insn_p (insn, operands[1])"
- "sbrs %0,7")
-
-(define_peephole
- [(set (cc0) (match_operand:QI 0 "register_operand" ""))
- (set (pc)
- (if_then_else (ge (cc0) (const_int 0))
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- "jump_over_one_insn_p (insn, operands[1])"
- "sbrc %0,7")
-
-(define_peephole
- [(set (cc0) (match_operand:HI 0 "register_operand" ""))
- (set (pc)
- (if_then_else (lt (cc0) (const_int 0))
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- "jump_over_one_insn_p (insn, operands[1])"
- "sbrs %B0,7")
-
-(define_peephole
- [(set (cc0) (match_operand:HI 0 "register_operand" ""))
- (set (pc)
- (if_then_else (ge (cc0) (const_int 0))
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- "jump_over_one_insn_p (insn, operands[1])"
- "sbrc %B0,7")
-
-(define_peephole
- [(set (cc0) (match_operand:SI 0 "register_operand" ""))
- (set (pc)
- (if_then_else (lt (cc0) (const_int 0))
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- "jump_over_one_insn_p (insn, operands[1])"
- "sbrs %D0,7")
-
-(define_peephole
- [(set (cc0) (match_operand:SI 0 "register_operand" ""))
- (set (pc)
- (if_then_else (ge (cc0) (const_int 0))
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- "jump_over_one_insn_p (insn, operands[1])"
- "sbrc %D0,7")
(define_peephole
[(set (cc0) (match_operand:QI 0 "register_operand" ""))
(pc)))]
"jump_over_one_insn_p (insn, operands[2])"
"cpse %0,%1")
+
+;;pppppppppppppppppppppppppppppppppppppppppppppppppppp
+;;prologue/epilogue support instructions
+
+(define_insn "popqi"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (mem:QI (post_inc (reg:HI REG_SP))))]
+ ""
+ "pop %0"
+ [(set_attr "cc" "none")
+ (set_attr "length" "1")])
+
+(define_insn "pophi"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (mem:HI (post_inc (reg:HI REG_SP))))]
+ ""
+ "pop %A0\;pop %B0"
+ [(set_attr "cc" "none")
+ (set_attr "length" "2")])
+
+;; Enable Interrupts
+(define_insn "enable_interrupt"
+ [(unspec [(const_int 0)] UNSPEC_SEI)]
+ ""
+ "sei"
+ [(set_attr "length" "1")
+ (set_attr "cc" "none")
+ ])
+
+;; Disable Interrupts
+(define_insn "disable_interrupt"
+ [(unspec [(const_int 0)] UNSPEC_CLI)]
+ ""
+ "cli"
+ [(set_attr "length" "1")
+ (set_attr "cc" "none")
+ ])
+
+;; Library prologue saves
+(define_insn "call_prologue_saves"
+ [(unspec_volatile:HI [(const_int 0)] UNSPECV_PROLOGUE_SAVES)
+ (match_operand:HI 0 "immediate_operand" "")
+ (set (reg:HI REG_SP) (minus:HI
+ (reg:HI REG_SP)
+ (match_operand:HI 1 "immediate_operand" "")))
+ (use (reg:HI REG_X))
+ (clobber (reg:HI REG_Z))]
+ ""
+ "ldi r30,lo8(gs(1f))
+ ldi r31,hi8(gs(1f))
+ %~jmp __prologue_saves__+((18 - %0) * 2)
+1:"
+ [(set_attr_alternative "length"
+ [(if_then_else (eq_attr "mcu_mega" "yes")
+ (const_int 6)
+ (const_int 5))])
+ (set_attr "cc" "clobber")
+ ])
+
+; epilogue restores using library
+(define_insn "epilogue_restores"
+ [(unspec_volatile:QI [(const_int 0)] UNSPECV_EPILOGUE_RESTORES)
+ (set (reg:HI REG_Y ) (plus:HI
+ (reg:HI REG_Y)
+ (match_operand:HI 0 "immediate_operand" "")))
+ (set (reg:HI REG_SP) (reg:HI REG_Y))
+ (clobber (reg:QI REG_Z))]
+ ""
+ "ldi r30, lo8(%0)
+ %~jmp __epilogue_restores__ + ((18 - %0) * 2)"
+ [(set_attr_alternative "length"
+ [(if_then_else (eq_attr "mcu_mega" "yes")
+ (const_int 3)
+ (const_int 2))])
+ (set_attr "cc" "clobber")
+ ])
+
+; return
+(define_insn "return"
+ [(return)]
+ "reload_completed && avr_simple_epilogue ()"
+ "ret"
+ [(set_attr "cc" "none")
+ (set_attr "length" "1")])
+
+(define_insn "return_from_epilogue"
+ [(return)]
+ "(reload_completed
+ && cfun->machine
+ && !(cfun->machine->is_interrupt || cfun->machine->is_signal)
+ && !cfun->machine->is_naked)"
+ "ret"
+ [(set_attr "cc" "none")
+ (set_attr "length" "1")])
+
+(define_insn "return_from_interrupt_epilogue"
+ [(return)]
+ "(reload_completed
+ && cfun->machine
+ && (cfun->machine->is_interrupt || cfun->machine->is_signal)
+ && !cfun->machine->is_naked)"
+ "reti"
+ [(set_attr "cc" "none")
+ (set_attr "length" "1")])
+
+(define_insn "return_from_naked_epilogue"
+ [(return)]
+ "(reload_completed
+ && cfun->machine
+ && cfun->machine->is_naked)"
+ ""
+ [(set_attr "cc" "none")
+ (set_attr "length" "0")])
+
+(define_expand "prologue"
+ [(const_int 0)]
+ ""
+ "
+ {
+ expand_prologue ();
+ DONE;
+ }")
+
+(define_expand "epilogue"
+ [(const_int 0)]
+ ""
+ "
+ {
+ expand_epilogue ();
+ DONE;
+ }")
projects / msp430-gcc.git / blobdiff