;; Mips.md Machine Description for MIPS based processors
;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-;; 1999, 2000, 2001 Free Software Foundation, Inc.
+;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
+;; Free Software Foundation, Inc.
;; Contributed by A. Lichnewsky, lich@inria.inria.fr
;; Changes by Michael Meissner, meissner@osf.org
-;; 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
+;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
;; Brendan Eich, brendan@microunity.com.
-;; This file is part of GNU CC.
+;; This file is part of GCC.
-;; GNU CC is free software; you can redistribute it and/or modify
+;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
+;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
-;; GNU CC is distributed in the hope that it will be useful,
+;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;; ??? Currently does not have define_function_unit support for the R8000.
-;; Must include new entries for fmadd in addition to existing entries.
-
-;; UNSPEC values used in mips.md
-;; Number USE
-;; 0 movsi_ul
-;; 1 movsi_usw, get_fnaddr
-;; 2 reload_in*, reload_out* : sets delay on HILO register
-;; 3 eh_set_return
-;; 20 builtin_setjmp_setup
-;; 111 movdi_usd
-;;
-;; UNSPEC_VOLATILE values
-;; 0 blockage
-;; 2 loadgp
-;; 3 builtin_longjmp
-;; 4 exception_receiver
-;; 10 consttable_qi
-;; 11 consttable_hi
-;; 12 consttable_si
-;; 13 consttable_di
-;; 14 consttable_sf
-;; 15 consttable_df
-;; 16 align_2
-;; 17 align_4
-;; 18 align_8
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_constants
+ [(UNSPEC_LOAD_LOW 0)
+ (UNSPEC_LOAD_HIGH 1)
+ (UNSPEC_STORE_WORD 2)
+ (UNSPEC_GET_FNADDR 3)
+ (UNSPEC_BLOCKAGE 4)
+ (UNSPEC_CPRESTORE 5)
+ (UNSPEC_RESTORE_GP 6)
+ (UNSPEC_EH_RETURN 7)
+ (UNSPEC_CONSTTABLE_INT 8)
+ (UNSPEC_CONSTTABLE_FLOAT 9)
+ (UNSPEC_ALIGN 14)
+ (UNSPEC_HIGH 17)
+ (UNSPEC_LOAD_LEFT 18)
+ (UNSPEC_LOAD_RIGHT 19)
+ (UNSPEC_STORE_LEFT 20)
+ (UNSPEC_STORE_RIGHT 21)
+ (UNSPEC_LOADGP 22)
+ (UNSPEC_LOAD_CALL 23)
+ (UNSPEC_LOAD_GOT 24)
+ (UNSPEC_GP 25)
+ (UNSPEC_MFHI 26)
+ (UNSPEC_MTHI 27)
+ (UNSPEC_SET_HILO 28)
+ (UNSPEC_TLS_LDM 29)
+ (UNSPEC_TLS_GET_TP 30)
+ (UNSPEC_MFHC1 31)
+ (UNSPEC_MTHC1 32)
+ (UNSPEC_CLEAR_HAZARD 33)
+ (UNSPEC_RDHWR 34)
+ (UNSPEC_SYNCI 35)
+ (UNSPEC_SYNC 36)
+ (UNSPEC_COMPARE_AND_SWAP 37)
+ (UNSPEC_COMPARE_AND_SWAP_12 38)
+ (UNSPEC_SYNC_OLD_OP 39)
+ (UNSPEC_SYNC_NEW_OP 40)
+ (UNSPEC_SYNC_NEW_OP_12 41)
+ (UNSPEC_SYNC_OLD_OP_12 42)
+ (UNSPEC_SYNC_EXCHANGE 43)
+ (UNSPEC_SYNC_EXCHANGE_12 44)
+ (UNSPEC_MEMORY_BARRIER 45)
+ (UNSPEC_SET_GOT_VERSION 46)
+ (UNSPEC_UPDATE_GOT_VERSION 47)
+ (UNSPEC_COPYGP 48)
+
+ (UNSPEC_ADDRESS_FIRST 100)
+
+ (TLS_GET_TP_REGNUM 3)
+ (GOT_VERSION_REGNUM 79)
+
+ ;; For MIPS Paired-Singled Floating Point Instructions.
+
+ (UNSPEC_MOVE_TF_PS 200)
+ (UNSPEC_C 201)
+
+ ;; MIPS64/MIPS32R2 alnv.ps
+ (UNSPEC_ALNV_PS 202)
+
+ ;; MIPS-3D instructions
+ (UNSPEC_CABS 203)
+
+ (UNSPEC_ADDR_PS 204)
+ (UNSPEC_CVT_PW_PS 205)
+ (UNSPEC_CVT_PS_PW 206)
+ (UNSPEC_MULR_PS 207)
+ (UNSPEC_ABS_PS 208)
+
+ (UNSPEC_RSQRT1 209)
+ (UNSPEC_RSQRT2 210)
+ (UNSPEC_RECIP1 211)
+ (UNSPEC_RECIP2 212)
+ (UNSPEC_SINGLE_CC 213)
+ (UNSPEC_SCC 214)
+
+ ;; MIPS DSP ASE Revision 0.98 3/24/2005
+ (UNSPEC_ADDQ 300)
+ (UNSPEC_ADDQ_S 301)
+ (UNSPEC_SUBQ 302)
+ (UNSPEC_SUBQ_S 303)
+ (UNSPEC_ADDSC 304)
+ (UNSPEC_ADDWC 305)
+ (UNSPEC_MODSUB 306)
+ (UNSPEC_RADDU_W_QB 307)
+ (UNSPEC_ABSQ_S 308)
+ (UNSPEC_PRECRQ_QB_PH 309)
+ (UNSPEC_PRECRQ_PH_W 310)
+ (UNSPEC_PRECRQ_RS_PH_W 311)
+ (UNSPEC_PRECRQU_S_QB_PH 312)
+ (UNSPEC_PRECEQ_W_PHL 313)
+ (UNSPEC_PRECEQ_W_PHR 314)
+ (UNSPEC_PRECEQU_PH_QBL 315)
+ (UNSPEC_PRECEQU_PH_QBR 316)
+ (UNSPEC_PRECEQU_PH_QBLA 317)
+ (UNSPEC_PRECEQU_PH_QBRA 318)
+ (UNSPEC_PRECEU_PH_QBL 319)
+ (UNSPEC_PRECEU_PH_QBR 320)
+ (UNSPEC_PRECEU_PH_QBLA 321)
+ (UNSPEC_PRECEU_PH_QBRA 322)
+ (UNSPEC_SHLL 323)
+ (UNSPEC_SHLL_S 324)
+ (UNSPEC_SHRL_QB 325)
+ (UNSPEC_SHRA_PH 326)
+ (UNSPEC_SHRA_R 327)
+ (UNSPEC_MULEU_S_PH_QBL 328)
+ (UNSPEC_MULEU_S_PH_QBR 329)
+ (UNSPEC_MULQ_RS_PH 330)
+ (UNSPEC_MULEQ_S_W_PHL 331)
+ (UNSPEC_MULEQ_S_W_PHR 332)
+ (UNSPEC_DPAU_H_QBL 333)
+ (UNSPEC_DPAU_H_QBR 334)
+ (UNSPEC_DPSU_H_QBL 335)
+ (UNSPEC_DPSU_H_QBR 336)
+ (UNSPEC_DPAQ_S_W_PH 337)
+ (UNSPEC_DPSQ_S_W_PH 338)
+ (UNSPEC_MULSAQ_S_W_PH 339)
+ (UNSPEC_DPAQ_SA_L_W 340)
+ (UNSPEC_DPSQ_SA_L_W 341)
+ (UNSPEC_MAQ_S_W_PHL 342)
+ (UNSPEC_MAQ_S_W_PHR 343)
+ (UNSPEC_MAQ_SA_W_PHL 344)
+ (UNSPEC_MAQ_SA_W_PHR 345)
+ (UNSPEC_BITREV 346)
+ (UNSPEC_INSV 347)
+ (UNSPEC_REPL_QB 348)
+ (UNSPEC_REPL_PH 349)
+ (UNSPEC_CMP_EQ 350)
+ (UNSPEC_CMP_LT 351)
+ (UNSPEC_CMP_LE 352)
+ (UNSPEC_CMPGU_EQ_QB 353)
+ (UNSPEC_CMPGU_LT_QB 354)
+ (UNSPEC_CMPGU_LE_QB 355)
+ (UNSPEC_PICK 356)
+ (UNSPEC_PACKRL_PH 357)
+ (UNSPEC_EXTR_W 358)
+ (UNSPEC_EXTR_R_W 359)
+ (UNSPEC_EXTR_RS_W 360)
+ (UNSPEC_EXTR_S_H 361)
+ (UNSPEC_EXTP 362)
+ (UNSPEC_EXTPDP 363)
+ (UNSPEC_SHILO 364)
+ (UNSPEC_MTHLIP 365)
+ (UNSPEC_WRDSP 366)
+ (UNSPEC_RDDSP 367)
+
+ ;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
+ (UNSPEC_ABSQ_S_QB 400)
+ (UNSPEC_ADDU_PH 401)
+ (UNSPEC_ADDU_S_PH 402)
+ (UNSPEC_ADDUH_QB 403)
+ (UNSPEC_ADDUH_R_QB 404)
+ (UNSPEC_APPEND 405)
+ (UNSPEC_BALIGN 406)
+ (UNSPEC_CMPGDU_EQ_QB 407)
+ (UNSPEC_CMPGDU_LT_QB 408)
+ (UNSPEC_CMPGDU_LE_QB 409)
+ (UNSPEC_DPA_W_PH 410)
+ (UNSPEC_DPS_W_PH 411)
+ (UNSPEC_MADD 412)
+ (UNSPEC_MADDU 413)
+ (UNSPEC_MSUB 414)
+ (UNSPEC_MSUBU 415)
+ (UNSPEC_MUL_PH 416)
+ (UNSPEC_MUL_S_PH 417)
+ (UNSPEC_MULQ_RS_W 418)
+ (UNSPEC_MULQ_S_PH 419)
+ (UNSPEC_MULQ_S_W 420)
+ (UNSPEC_MULSA_W_PH 421)
+ (UNSPEC_MULT 422)
+ (UNSPEC_MULTU 423)
+ (UNSPEC_PRECR_QB_PH 424)
+ (UNSPEC_PRECR_SRA_PH_W 425)
+ (UNSPEC_PRECR_SRA_R_PH_W 426)
+ (UNSPEC_PREPEND 427)
+ (UNSPEC_SHRA_QB 428)
+ (UNSPEC_SHRA_R_QB 429)
+ (UNSPEC_SHRL_PH 430)
+ (UNSPEC_SUBU_PH 431)
+ (UNSPEC_SUBU_S_PH 432)
+ (UNSPEC_SUBUH_QB 433)
+ (UNSPEC_SUBUH_R_QB 434)
+ (UNSPEC_ADDQH_PH 435)
+ (UNSPEC_ADDQH_R_PH 436)
+ (UNSPEC_ADDQH_W 437)
+ (UNSPEC_ADDQH_R_W 438)
+ (UNSPEC_SUBQH_PH 439)
+ (UNSPEC_SUBQH_R_PH 440)
+ (UNSPEC_SUBQH_W 441)
+ (UNSPEC_SUBQH_R_W 442)
+ (UNSPEC_DPAX_W_PH 443)
+ (UNSPEC_DPSX_W_PH 444)
+ (UNSPEC_DPAQX_S_W_PH 445)
+ (UNSPEC_DPAQX_SA_W_PH 446)
+ (UNSPEC_DPSQX_S_W_PH 447)
+ (UNSPEC_DPSQX_SA_W_PH 448)
+
+ ;; ST Microelectronics Loongson-2E/2F.
+ (UNSPEC_LOONGSON_PAVG 500)
+ (UNSPEC_LOONGSON_PCMPEQ 501)
+ (UNSPEC_LOONGSON_PCMPGT 502)
+ (UNSPEC_LOONGSON_PEXTR 503)
+ (UNSPEC_LOONGSON_PINSR_0 504)
+ (UNSPEC_LOONGSON_PINSR_1 505)
+ (UNSPEC_LOONGSON_PINSR_2 506)
+ (UNSPEC_LOONGSON_PINSR_3 507)
+ (UNSPEC_LOONGSON_PMADD 508)
+ (UNSPEC_LOONGSON_PMOVMSK 509)
+ (UNSPEC_LOONGSON_PMULHU 510)
+ (UNSPEC_LOONGSON_PMULH 511)
+ (UNSPEC_LOONGSON_PMULL 512)
+ (UNSPEC_LOONGSON_PMULU 513)
+ (UNSPEC_LOONGSON_PASUBUB 514)
+ (UNSPEC_LOONGSON_BIADD 515)
+ (UNSPEC_LOONGSON_PSADBH 516)
+ (UNSPEC_LOONGSON_PSHUFH 517)
+ (UNSPEC_LOONGSON_PUNPCKH 518)
+ (UNSPEC_LOONGSON_PUNPCKL 519)
+ (UNSPEC_LOONGSON_PADDD 520)
+ (UNSPEC_LOONGSON_PSUBD 521)
+
+ ;; Used in loongson2ef.md
+ (UNSPEC_LOONGSON_ALU1_TURN_ENABLED_INSN 530)
+ (UNSPEC_LOONGSON_ALU2_TURN_ENABLED_INSN 531)
+ (UNSPEC_LOONGSON_FALU1_TURN_ENABLED_INSN 532)
+ (UNSPEC_LOONGSON_FALU2_TURN_ENABLED_INSN 533)
+
+ (UNSPEC_MIPS_CACHE 600)
+ (UNSPEC_R10K_CACHE_BARRIER 601)
+ ]
+)
+
+(include "predicates.md")
+(include "constraints.md")
\f
-
;; ....................
;;
;; Attributes
;;
;; ....................
+(define_attr "got" "unset,xgot_high,load"
+ (const_string "unset"))
+
+;; For jal instructions, this attribute is DIRECT when the target address
+;; is symbolic and INDIRECT when it is a register.
+(define_attr "jal" "unset,direct,indirect"
+ (const_string "unset"))
+
+;; This attribute is YES if the instruction is a jal macro (not a
+;; real jal instruction).
+;;
+;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
+;; an instruction to restore $gp. Direct jals are also macros for
+;; flag_pic && !TARGET_ABSOLUTE_ABICALLS because they first load
+;; the target address into a register.
+(define_attr "jal_macro" "no,yes"
+ (cond [(eq_attr "jal" "direct")
+ (symbol_ref "TARGET_CALL_CLOBBERED_GP
+ || (flag_pic && !TARGET_ABSOLUTE_ABICALLS)")
+ (eq_attr "jal" "indirect")
+ (symbol_ref "TARGET_CALL_CLOBBERED_GP")]
+ (const_string "no")))
+
+;; Classification of moves, extensions and truncations. Most values
+;; are as for "type" (see below) but there are also the following
+;; move-specific values:
+;;
+;; constN move an N-constraint integer into a MIPS16 register
+;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed
+;; to produce a sign-extended DEST, even if SRC is not
+;; properly sign-extended
+;; andi a single ANDI instruction
+;; loadpool move a constant into a MIPS16 register by loading it
+;; from the pool
+;; shift_shift a shift left followed by a shift right
+;; lui_movf an LUI followed by a MOVF (for d<-z CC moves)
+;;
+;; This attribute is used to determine the instruction's length and
+;; scheduling type. For doubleword moves, the attribute always describes
+;; the split instructions; in some cases, it is more appropriate for the
+;; scheduling type to be "multi" instead.
+(define_attr "move_type"
+ "unknown,load,fpload,store,fpstore,mtc,mfc,mthilo,mfhilo,move,fmove,
+ const,constN,signext,sll0,andi,loadpool,shift_shift,lui_movf"
+ (const_string "unknown"))
+
+;; Main data type used by the insn
+(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"
+ (const_string "unknown"))
+
+;; True if the main data type is twice the size of a word.
+(define_attr "dword_mode" "no,yes"
+ (cond [(and (eq_attr "mode" "DI,DF")
+ (eq (symbol_ref "TARGET_64BIT") (const_int 0)))
+ (const_string "yes")
+
+ (and (eq_attr "mode" "TI,TF")
+ (ne (symbol_ref "TARGET_64BIT") (const_int 0)))
+ (const_string "yes")]
+ (const_string "no")))
+
;; Classification of each insn.
;; branch conditional branch
;; jump unconditional jump
;; call unconditional call
;; load load instruction(s)
+;; fpload floating point load
+;; fpidxload floating point indexed load
;; store store instruction(s)
-;; move data movement within same register set
-;; xfer transfer to/from coprocessor
-;; hilo transfer of hi/lo registers
-;; arith integer arithmetic instruction
-;; darith double precision integer arithmetic instructions
-;; imul integer multiply
-;; idiv integer divide
-;; icmp integer compare
+;; fpstore floating point store
+;; fpidxstore floating point indexed store
+;; prefetch memory prefetch (register + offset)
+;; prefetchx memory indexed prefetch (register + register)
+;; condmove conditional moves
+;; mtc transfer to coprocessor
+;; mfc transfer from coprocessor
+;; mthilo transfer to hi/lo registers
+;; mfhilo transfer from hi/lo registers
+;; const load constant
+;; arith integer arithmetic instructions
+;; logical integer logical instructions
+;; shift integer shift instructions
+;; slt set less than instructions
+;; signext sign extend instructions
+;; clz the clz and clo instructions
+;; pop the pop instruction
+;; trap trap if instructions
+;; imul integer multiply 2 operands
+;; imul3 integer multiply 3 operands
+;; imul3nc integer multiply 3 operands without clobbering HI/LO
+;; imadd integer multiply-add
+;; idiv integer divide 2 operands
+;; idiv3 integer divide 3 operands
+;; move integer register move ({,D}ADD{,U} with rt = 0)
+;; fmove floating point register move
;; fadd floating point add/subtract
;; fmul floating point multiply
;; fmadd floating point multiply-add
;; fdiv floating point divide
+;; frdiv floating point reciprocal divide
+;; frdiv1 floating point reciprocal divide step 1
+;; frdiv2 floating point reciprocal divide step 2
;; fabs floating point absolute value
;; fneg floating point negation
;; fcmp floating point compare
;; fcvt floating point convert
;; fsqrt floating point square root
+;; frsqrt floating point reciprocal square root
+;; frsqrt1 floating point reciprocal square root step1
+;; frsqrt2 floating point reciprocal square root step2
;; multi multiword sequence (or user asm statements)
;; nop no operation
-
+;; ghost an instruction that produces no real code
(define_attr "type"
- "unknown,branch,jump,call,load,store,move,xfer,hilo,arith,darith,imul,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop"
+ "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
+ prefetch,prefetchx,condmove,mtc,mfc,mthilo,mfhilo,const,arith,logical,
+ shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
+ fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
+ frsqrt,frsqrt1,frsqrt2,multi,nop,ghost"
+ (cond [(eq_attr "jal" "!unset") (const_string "call")
+ (eq_attr "got" "load") (const_string "load")
+
+ ;; If a doubleword move uses these expensive instructions,
+ ;; it is usually better to schedule them in the same way
+ ;; as the singleword form, rather than as "multi".
+ (eq_attr "move_type" "load") (const_string "load")
+ (eq_attr "move_type" "fpload") (const_string "fpload")
+ (eq_attr "move_type" "store") (const_string "store")
+ (eq_attr "move_type" "fpstore") (const_string "fpstore")
+ (eq_attr "move_type" "mtc") (const_string "mtc")
+ (eq_attr "move_type" "mfc") (const_string "mfc")
+ (eq_attr "move_type" "mthilo") (const_string "mthilo")
+ (eq_attr "move_type" "mfhilo") (const_string "mfhilo")
+
+ ;; These types of move are always single insns.
+ (eq_attr "move_type" "fmove") (const_string "fmove")
+ (eq_attr "move_type" "loadpool") (const_string "load")
+ (eq_attr "move_type" "signext") (const_string "signext")
+ (eq_attr "move_type" "sll0") (const_string "shift")
+ (eq_attr "move_type" "andi") (const_string "logical")
+
+ ;; These types of move are always split.
+ (eq_attr "move_type" "constN,shift_shift")
+ (const_string "multi")
+
+ ;; These types of move are split for doubleword modes only.
+ (and (eq_attr "move_type" "move,const")
+ (eq_attr "dword_mode" "yes"))
+ (const_string "multi")
+ (eq_attr "move_type" "move") (const_string "move")
+ (eq_attr "move_type" "const") (const_string "const")]
+ ;; We classify "lui_movf" as "unknown" rather than "multi"
+ ;; because we don't split it. FIXME: we should split instead.
+ (const_string "unknown")))
+
+;; Mode for conversion types (fcvt)
+;; I2S integer to float single (SI/DI to SF)
+;; I2D integer to float double (SI/DI to DF)
+;; S2I float to integer (SF to SI/DI)
+;; D2I float to integer (DF to SI/DI)
+;; D2S double to float single
+;; S2D float single to double
+
+(define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
(const_string "unknown"))
-;; Main data type used by the insn
-(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))
-
-;; Length (in # of bytes). A conditional branch is allowed only to a
-;; location within a signed 18-bit offset of the delay slot. If that
-;; provides too smal a range, we use the `j' instruction. This
-;; instruction takes a 28-bit value, but that value is not an offset.
-;; Instead, it's bitwise-ored with the high-order four bits of the
-;; instruction in the delay slot, which means it cannot be used to
-;; cross a 256MB boundary. We could fall back back on the jr,
-;; instruction which allows full access to the entire address space,
-;; but we do not do so at present.
+;; Is this an extended instruction in mips16 mode?
+(define_attr "extended_mips16" "no,yes"
+ (if_then_else (ior (eq_attr "move_type" "sll0")
+ (eq_attr "type" "branch")
+ (eq_attr "jal" "direct"))
+ (const_string "yes")
+ (const_string "no")))
+;; Length of instruction in bytes.
(define_attr "length" ""
- (cond [(eq_attr "type" "branch")
- (cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4))))
- (const_int 131072))
- (const_int 4)]
- (const_int 12))]
- (const_int 4)))
+ (cond [(and (eq_attr "extended_mips16" "yes")
+ (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
+ (const_int 8)
+
+ ;; Direct branch instructions have a range of [-0x40000,0x3fffc].
+ ;; If a branch is outside this range, we have a choice of two
+ ;; sequences. For PIC, an out-of-range branch like:
+ ;;
+ ;; bne r1,r2,target
+ ;; dslot
+ ;;
+ ;; becomes the equivalent of:
+ ;;
+ ;; beq r1,r2,1f
+ ;; dslot
+ ;; la $at,target
+ ;; jr $at
+ ;; nop
+ ;; 1:
+ ;;
+ ;; where the load address can be up to three instructions long
+ ;; (lw, nop, addiu).
+ ;;
+ ;; The non-PIC case is similar except that we use a direct
+ ;; jump instead of an la/jr pair. Since the target of this
+ ;; jump is an absolute 28-bit bit address (the other bits
+ ;; coming from the address of the delay slot) this form cannot
+ ;; cross a 256MB boundary. We could provide the option of
+ ;; using la/jr in this case too, but we do not do so at
+ ;; present.
+ ;;
+ ;; Note that this value does not account for the delay slot
+ ;; instruction, whose length is added separately. If the RTL
+ ;; pattern has no explicit delay slot, mips_adjust_insn_length
+ ;; will add the length of the implicit nop. The values for
+ ;; forward and backward branches will be different as well.
+ (eq_attr "type" "branch")
+ (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
+ (le (minus (pc) (match_dup 1)) (const_int 131068)))
+ (const_int 4)
+ (ne (symbol_ref "flag_pic") (const_int 0))
+ (const_int 24)
+ ] (const_int 12))
+
+ ;; "Ghost" instructions occupy no space.
+ (eq_attr "type" "ghost")
+ (const_int 0)
+
+ (eq_attr "got" "load")
+ (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
+ (const_int 8)
+ (const_int 4))
+ (eq_attr "got" "xgot_high")
+ (const_int 8)
+
+ ;; In general, constant-pool loads are extended instructions.
+ (eq_attr "move_type" "loadpool")
+ (const_int 8)
+
+ ;; LUI_MOVFs are decomposed into two separate instructions.
+ (eq_attr "move_type" "lui_movf")
+ (const_int 8)
+
+ ;; SHIFT_SHIFTs are decomposed into two separate instructions.
+ ;; They are extended instructions on MIPS16 targets.
+ (eq_attr "move_type" "shift_shift")
+ (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
+ (const_int 16)
+ (const_int 8))
+
+ ;; Check for doubleword moves that are decomposed into two
+ ;; instructions.
+ (and (eq_attr "move_type" "mtc,mfc,mthilo,mfhilo,move")
+ (eq_attr "dword_mode" "yes"))
+ (const_int 8)
+
+ ;; Doubleword CONST{,N} moves are split into two word
+ ;; CONST{,N} moves.
+ (and (eq_attr "move_type" "const,constN")
+ (eq_attr "dword_mode" "yes"))
+ (symbol_ref "mips_split_const_insns (operands[1]) * 4")
+
+ ;; Otherwise, constants, loads and stores are handled by external
+ ;; routines.
+ (eq_attr "move_type" "const,constN")
+ (symbol_ref "mips_const_insns (operands[1]) * 4")
+ (eq_attr "move_type" "load,fpload")
+ (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
+ (eq_attr "move_type" "store,fpstore")
+ (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")
+
+ ;; In the worst case, a call macro will take 8 instructions:
+ ;;
+ ;; lui $25,%call_hi(FOO)
+ ;; addu $25,$25,$28
+ ;; lw $25,%call_lo(FOO)($25)
+ ;; nop
+ ;; jalr $25
+ ;; nop
+ ;; lw $gp,X($sp)
+ ;; nop
+ (eq_attr "jal_macro" "yes")
+ (const_int 32)
+
+ ;; Various VR4120 errata require a nop to be inserted after a macc
+ ;; instruction. The assembler does this for us, so account for
+ ;; the worst-case length here.
+ (and (eq_attr "type" "imadd")
+ (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
+ (const_int 8)
+
+ ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
+ ;; the result of the second one is missed. The assembler should work
+ ;; around this by inserting a nop after the first dmult.
+ (and (eq_attr "type" "imul,imul3")
+ (and (eq_attr "mode" "DI")
+ (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
+ (const_int 8)
+
+ (eq_attr "type" "idiv,idiv3")
+ (symbol_ref "mips_idiv_insns () * 4")
+ ] (const_int 4)))
;; Attribute describing the processor. This attribute must match exactly
;; with the processor_type enumeration in mips.h.
-
-;; Attribute describing the processor
-;; (define_attr "cpu" "default,r3000,r6000,r4000"
-;; (const
-;; (cond [(eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R3000")) (const_string "r3000")
-;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R4000")) (const_string "r4000")
-;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R6000")) (const_string "r6000")]
-;; (const_string "default"))))
-
-;; ??? Fix everything that tests this attribute.
(define_attr "cpu"
- "default,r3000,r3900,r6000,r4000,r4100,r4300,r4600,r4650,r5000,r8000,r4kc,r5kc,r20kc"
- (const (symbol_ref "mips_cpu_attr")))
-
-;; Does the instruction have a mandatory delay slot?
-;; The 3900, is (mostly) mips1, but does not have a mandatory load delay
-;; slot.
-(define_attr "dslot" "no,yes"
- (if_then_else (ior (eq_attr "type" "branch,jump,call,xfer,hilo,fcmp")
- (and (eq_attr "type" "load")
- (and (eq (symbol_ref "mips_isa") (const_int 1))
- (and (eq (symbol_ref "mips16") (const_int 0))
- (eq_attr "cpu" "!r3900")))))
- (const_string "yes")
- (const_string "no")))
+ "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson_2e,loongson_2f,m4k,octeon,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,r10000,sb1,sb1a,sr71000,xlr"
+ (const (symbol_ref "mips_tune")))
+
+;; The type of hardware hazard associated with this instruction.
+;; DELAY means that the next instruction cannot read the result
+;; of this one. HILO means that the next two instructions cannot
+;; write to HI or LO.
+(define_attr "hazard" "none,delay,hilo"
+ (cond [(and (eq_attr "type" "load,fpload,fpidxload")
+ (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
+ (const_string "delay")
+
+ (and (eq_attr "type" "mfc,mtc")
+ (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
+ (const_string "delay")
+
+ (and (eq_attr "type" "fcmp")
+ (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
+ (const_string "delay")
+
+ ;; The r4000 multiplication patterns include an mflo instruction.
+ (and (eq_attr "type" "imul")
+ (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
+ (const_string "hilo")
+
+ (and (eq_attr "type" "mfhilo")
+ (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
+ (const_string "hilo")]
+ (const_string "none")))
+
+;; Is it a single instruction?
+(define_attr "single_insn" "no,yes"
+ (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))
;; Can the instruction be put into a delay slot?
(define_attr "can_delay" "no,yes"
- (if_then_else (and (eq_attr "dslot" "no")
- ; ADJUST_INSN_LENGTH divides length by 2 on mips16,
- ; so cope with it here.
- (ior (and (eq (symbol_ref "mips16") (const_int 0))
- (eq_attr "length" "4"))
- (and (ne (symbol_ref "mips16") (const_int 0))
- (eq_attr "length" "2"))))
+ (if_then_else (and (eq_attr "type" "!branch,call,jump")
+ (and (eq_attr "hazard" "none")
+ (eq_attr "single_insn" "yes")))
(const_string "yes")
(const_string "no")))
-;; Attribute defining whether or not we can use the branch-likely instructions
-
+;; Attribute defining whether or not we can use the branch-likely
+;; instructions.
(define_attr "branch_likely" "no,yes"
- (const
- (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
- (const_string "yes")
- (const_string "no"))))
+ (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
+ (const_string "yes")
+ (const_string "no")))
+;; True if an instruction might assign to hi or lo when reloaded.
+;; This is used by the TUNE_MACC_CHAINS code.
+(define_attr "may_clobber_hilo" "no,yes"
+ (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
+ (const_string "yes")
+ (const_string "no")))
;; Describe a user's asm statement.
(define_asm_attributes
- [(set_attr "type" "multi")])
-
-;; whether or not generating calls to position independent functions
-(define_attr "abicalls" "no,yes"
- (const (symbol_ref "mips_abicalls_attr")))
-
+ [(set_attr "type" "multi")
+ (set_attr "can_delay" "no")])
+\f
+;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
+;; from the same template.
+(define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
+
+;; A copy of GPR that can be used when a pattern has two independent
+;; modes.
+(define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
+
+;; This mode iterator allows :HILO to be used as the mode of the
+;; concatenated HI and LO registers.
+(define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
+
+;; This mode iterator allows :P to be used for patterns that operate on
+;; pointer-sized quantities. Exactly one of the two alternatives will match.
+(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
+
+;; This mode iterator allows :MOVECC to be used anywhere that a
+;; conditional-move-type condition is needed.
+(define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
+ (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
+
+;; 32-bit integer moves for which we provide move patterns.
+(define_mode_iterator IMOVE32
+ [SI
+ (V2HI "TARGET_DSP")
+ (V4QI "TARGET_DSP")
+ (V2HQ "TARGET_DSP")
+ (V2UHQ "TARGET_DSP")
+ (V2HA "TARGET_DSP")
+ (V2UHA "TARGET_DSP")
+ (V4QQ "TARGET_DSP")
+ (V4UQQ "TARGET_DSP")])
+
+;; 64-bit modes for which we provide move patterns.
+(define_mode_iterator MOVE64
+ [DI DF
+ (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")
+ (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
+ (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
+ (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")])
+
+;; 128-bit modes for which we provide move patterns on 64-bit targets.
+(define_mode_iterator MOVE128 [TI TF])
+
+;; This mode iterator allows the QI and HI extension patterns to be
+;; defined from the same template.
+(define_mode_iterator SHORT [QI HI])
+
+;; Likewise the 64-bit truncate-and-shift patterns.
+(define_mode_iterator SUBDI [QI HI SI])
+
+;; This mode iterator allows :ANYF to be used wherever a scalar or vector
+;; floating-point mode is allowed.
+(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
+ (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
+ (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
+
+;; Like ANYF, but only applies to scalar modes.
+(define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
+ (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
+
+;; A floating-point mode for which moves involving FPRs may need to be split.
+(define_mode_iterator SPLITF
+ [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
+ (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
+ (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
+ (V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
+ (V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
+ (V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
+ (TF "TARGET_64BIT && TARGET_FLOAT64")])
+
+;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
+;; 32-bit version and "dsubu" in the 64-bit version.
+(define_mode_attr d [(SI "") (DI "d")
+ (QQ "") (HQ "") (SQ "") (DQ "d")
+ (UQQ "") (UHQ "") (USQ "") (UDQ "d")
+ (HA "") (SA "") (DA "d")
+ (UHA "") (USA "") (UDA "d")])
+
+;; Same as d but upper-case.
+(define_mode_attr D [(SI "") (DI "D")
+ (QQ "") (HQ "") (SQ "") (DQ "D")
+ (UQQ "") (UHQ "") (USQ "") (UDQ "D")
+ (HA "") (SA "") (DA "D")
+ (UHA "") (USA "") (UDA "D")])
+
+;; This attribute gives the length suffix for a sign- or zero-extension
+;; instruction.
+(define_mode_attr size [(QI "b") (HI "h")])
+
+;; This attributes gives the mode mask of a SHORT.
+(define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
+
+;; Mode attributes for GPR loads and stores.
+(define_mode_attr load [(SI "lw") (DI "ld")])
+(define_mode_attr store [(SI "sw") (DI "sd")])
+
+;; Similarly for MIPS IV indexed FPR loads and stores.
+(define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
+(define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
+
+;; The unextended ranges of the MIPS16 addiu and daddiu instructions
+;; are different. Some forms of unextended addiu have an 8-bit immediate
+;; field but the equivalent daddiu has only a 5-bit field.
+(define_mode_attr si8_di5 [(SI "8") (DI "5")])
+
+;; This attribute gives the best constraint to use for registers of
+;; a given mode.
+(define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
+
+;; This attribute gives the format suffix for floating-point operations.
+(define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
+
+;; This attribute gives the upper-case mode name for one unit of a
+;; floating-point mode.
+(define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
+
+;; This attribute gives the integer mode that has the same size as a
+;; fixed-point mode.
+(define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
+ (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
+ (HA "HI") (SA "SI") (DA "DI")
+ (UHA "HI") (USA "SI") (UDA "DI")
+ (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
+ (V2HQ "SI") (V2HA "SI")])
+
+;; This attribute gives the integer mode that has half the size of
+;; the controlling mode.
+(define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")
+ (V2SI "SI") (V4HI "SI") (V8QI "SI")
+ (TF "DI")])
+
+;; This attribute works around the early SB-1 rev2 core "F2" erratum:
+;;
+;; In certain cases, div.s and div.ps may have a rounding error
+;; and/or wrong inexact flag.
+;;
+;; Therefore, we only allow div.s if not working around SB-1 rev2
+;; errata or if a slight loss of precision is OK.
+(define_mode_attr divide_condition
+ [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
+ (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
+
+;; This attribute gives the conditions under which SQRT.fmt instructions
+;; can be used.
+(define_mode_attr sqrt_condition
+ [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
+
+;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt
+;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D
+;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs,
+;; so for safety's sake, we apply this restriction to all targets.
+(define_mode_attr recip_condition
+ [(SF "ISA_HAS_FP4")
+ (DF "ISA_HAS_FP4 && TARGET_FLOAT64")
+ (V2SF "TARGET_SB1")])
+
+;; This code iterator allows all branch instructions to be generated from
+;; a single define_expand template.
+(define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
+ eq ne gt ge lt le gtu geu ltu leu])
+
+;; This code iterator allows signed and unsigned widening multiplications
+;; to use the same template.
+(define_code_iterator any_extend [sign_extend zero_extend])
+
+;; This code iterator allows the two right shift instructions to be
+;; generated from the same template.
+(define_code_iterator any_shiftrt [ashiftrt lshiftrt])
+
+;; This code iterator allows the three shift instructions to be generated
+;; from the same template.
+(define_code_iterator any_shift [ashift ashiftrt lshiftrt])
+
+;; This code iterator allows unsigned and signed division to be generated
+;; from the same template.
+(define_code_iterator any_div [div udiv])
+
+;; This code iterator allows unsigned and signed modulus to be generated
+;; from the same template.
+(define_code_iterator any_mod [mod umod])
+
+;; This code iterator allows all native floating-point comparisons to be
+;; generated from the same template.
+(define_code_iterator fcond [unordered uneq unlt unle eq lt le])
+
+;; This code iterator is used for comparisons that can be implemented
+;; by swapping the operands.
+(define_code_iterator swapped_fcond [ge gt unge ungt])
+
+;; Equality operators.
+(define_code_iterator equality_op [eq ne])
+
+;; These code iterators allow the signed and unsigned scc operations to use
+;; the same template.
+(define_code_iterator any_gt [gt gtu])
+(define_code_iterator any_ge [ge geu])
+(define_code_iterator any_lt [lt ltu])
+(define_code_iterator any_le [le leu])
+
+;; <u> expands to an empty string when doing a signed operation and
+;; "u" when doing an unsigned operation.
+(define_code_attr u [(sign_extend "") (zero_extend "u")
+ (div "") (udiv "u")
+ (mod "") (umod "u")
+ (gt "") (gtu "u")
+ (ge "") (geu "u")
+ (lt "") (ltu "u")
+ (le "") (leu "u")])
+
+;; <su> is like <u>, but the signed form expands to "s" rather than "".
+(define_code_attr su [(sign_extend "s") (zero_extend "u")])
+
+;; <optab> expands to the name of the optab for a particular code.
+(define_code_attr optab [(ashift "ashl")
+ (ashiftrt "ashr")
+ (lshiftrt "lshr")
+ (ior "ior")
+ (xor "xor")
+ (and "and")
+ (plus "add")
+ (minus "sub")])
+
+;; <insn> expands to the name of the insn that implements a particular code.
+(define_code_attr insn [(ashift "sll")
+ (ashiftrt "sra")
+ (lshiftrt "srl")
+ (ior "or")
+ (xor "xor")
+ (and "and")
+ (plus "addu")
+ (minus "subu")])
+
+;; <immediate_insn> expands to the name of the insn that implements
+;; a particular code to operate on immediate values.
+(define_code_attr immediate_insn [(ior "ori")
+ (xor "xori")
+ (and "andi")])
+
+;; <fcond> is the c.cond.fmt condition associated with a particular code.
+(define_code_attr fcond [(unordered "un")
+ (uneq "ueq")
+ (unlt "ult")
+ (unle "ule")
+ (eq "eq")
+ (lt "lt")
+ (le "le")])
+
+;; Similar, but for swapped conditions.
+(define_code_attr swapped_fcond [(ge "le")
+ (gt "lt")
+ (unge "ule")
+ (ungt "ult")])
+
+;; The value of the bit when the branch is taken for branch_bit patterns.
+;; Comparison is always against zero so this depends on the operator.
+(define_code_attr bbv [(eq "0") (ne "1")])
+
+;; This is the inverse value of bbv.
+(define_code_attr bbinv [(eq "1") (ne "0")])
\f
-
;; .........................
;;
-;; Delay slots, can't describe load/fcmp/xfer delay slots here
+;; Branch, call and jump delay slots
;;
;; .........................
(define_delay (and (eq_attr "type" "branch")
- (eq (symbol_ref "mips16") (const_int 0)))
+ (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
+ (eq_attr "branch_likely" "yes"))
[(eq_attr "can_delay" "yes")
(nil)
- (and (eq_attr "branch_likely" "yes")
- (and (eq_attr "dslot" "no")
- (eq_attr "length" "4")))])
+ (eq_attr "can_delay" "yes")])
-(define_delay (eq_attr "type" "jump")
+;; Branches that don't have likely variants do not annul on false.
+(define_delay (and (eq_attr "type" "branch")
+ (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
+ (eq_attr "branch_likely" "no"))
[(eq_attr "can_delay" "yes")
(nil)
(nil)])
-(define_delay (and (eq_attr "type" "call") (eq_attr "abicalls" "no"))
+(define_delay (eq_attr "type" "jump")
[(eq_attr "can_delay" "yes")
(nil)
(nil)])
+(define_delay (and (eq_attr "type" "call")
+ (eq_attr "jal_macro" "no"))
+ [(eq_attr "can_delay" "yes")
+ (nil)
+ (nil)])
\f
-
-;; .........................
-;;
-;; Functional units
-;;
-;; .........................
-
-; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
-; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
-
-;; Make the default case (PROCESSOR_DEFAULT) handle the worst case
-
-(define_function_unit "memory" 1 0
- (and (eq_attr "type" "load")
- (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4300,r5000"))
- 3 0)
-
-(define_function_unit "memory" 1 0
- (and (eq_attr "type" "load")
- (eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4300,r5000"))
- 2 0)
-
-(define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
-
-(define_function_unit "memory" 1 0 (eq_attr "type" "xfer") 2 0)
-
-(define_function_unit "imuldiv" 1 0
- (eq_attr "type" "hilo")
- 1 3)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul")
- (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000"))
- 17 17)
-
-;; On them mips16, we want to stronly discourage a mult from appearing
-;; after an mflo, since that requires explicit nop instructions. We
-;; do this by pretending that mflo ties up the function unit for long
-;; enough that the scheduler will ignore load stalls and the like when
-;; selecting instructions to between the two instructions.
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "hilo") (ne (symbol_ref "mips16") (const_int 0)))
- 1 5)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul") (eq_attr "cpu" "r3000,r3900"))
- 12 12)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul") (eq_attr "cpu" "r4000,r4600"))
- 10 10)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul") (eq_attr "cpu" "r4650"))
- 4 4)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100")))
- 1 1)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100")))
- 4 4)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300,r5000")))
- 5 5)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
- 8 8)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
- 9 9)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000"))
- 38 38)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv") (eq_attr "cpu" "r3000,r3900"))
- 35 35)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4600"))
- 42 42)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4650"))
- 36 36)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4000"))
- 69 69)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100")))
- 35 35)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100")))
- 67 67)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300")))
- 37 37)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
- 69 69)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r5000")))
- 36 36)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
- 68 68)
-
-;; The R4300 does *NOT* have a separate Floating Point Unit, instead
-;; the FP hardware is part of the normal ALU circuitry. This means FP
-;; instructions affect the pipe-line, and no functional unit
-;; parallelism can occur on R4300 processors. To force GCC into coding
-;; for only a single functional unit, we force the R4300 FP
-;; instructions to be processed in the "imuldiv" unit.
-
-(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000"))
- 3 0)
-
-(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3000,r3900,r6000"))
- 2 0)
-
-(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r5000"))
- 1 0)
-
-(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r3900,r6000,r4300"))
- 4 0)
-
-(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3000,r3900"))
- 2 0)
-
-(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fadd") (eq_attr "cpu" "r6000"))
- 3 0)
-
-(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fabs,fneg")
- (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4300,r5000"))
- 2 0)
-
-(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fabs,fneg") (eq_attr "cpu" "r3000,r3900,r4600,r4650,r5000"))
- 1 0)
-
-(define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "SF")
- (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
- 7 0)
-
-(define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900,r5000")))
- 4 0)
-
-(define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
- 5 0)
-
-(define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
- 8 0)
-
-(define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000")))
- 8 0)
-
-(define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900,r5000")))
- 5 0)
-
-(define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
- 6 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "SF")
- (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
- 23 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900")))
- 12 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
- 15 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
- 32 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
- 21 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "DF")
- (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300")))
- 36 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900")))
- 19 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
- 16 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
- 61 0)
-
-;;; ??? Is this number right?
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
- 54 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
- 31 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
- 21 0)
-
-;;; ??? Is this number right?
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
- 112 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
- 60 0)
-
-(define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r5000")))
- 36 0)
-
-;; R4300 FP instruction classes treated as part of the "imuldiv"
-;; functional unit:
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "fadd") (eq_attr "cpu" "r4300"))
- 3 3)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "fcmp,fabs,fneg") (eq_attr "cpu" "r4300"))
- 1 1)
-
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
- 5 5)
-(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
- 8 8)
-
-(define_function_unit "imuldiv" 1 0
- (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt"))
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
- 29 29)
-(define_function_unit "imuldiv" 1 0
- (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt"))
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
- 58 58)
-\f
-;; The following functional units do not use the cpu type, and use
-;; much less memory in genattrtab.c.
-
-;; (define_function_unit "memory" 1 0 (eq_attr "type" "load") 3 0)
-;; (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
+;; Pipeline descriptions.
;;
-;; (define_function_unit "fp_comp" 1 0 (eq_attr "type" "fcmp") 2 0)
+;; generic.md provides a fallback for processors without a specific
+;; pipeline description. It is derived from the old define_function_unit
+;; version and uses the "alu" and "imuldiv" units declared below.
;;
-;; (define_function_unit "transfer" 1 0 (eq_attr "type" "xfer") 2 0)
-;; (define_function_unit "transfer" 1 0 (eq_attr "type" "hilo") 3 0)
-;;
-;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "imul") 17 0)
-;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "idiv") 38 0)
-;;
-;; (define_function_unit "adder" 1 1 (eq_attr "type" "fadd") 4 0)
-;; (define_function_unit "adder" 1 1 (eq_attr "type" "fabs,fneg") 2 0)
-;;
-;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "SF")) 7 0)
-;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "DF")) 8 0)
-;;
-;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "SF")) 23 0)
-;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "DF")) 36 0)
-;;
-;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "SF")) 54 0)
-;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "DF")) 112 0)
+;; Some of the processor-specific files are also derived from old
+;; define_function_unit descriptions and simply override the parts of
+;; generic.md that don't apply. The other processor-specific files
+;; are self-contained.
+(define_automaton "alu,imuldiv")
+
+(define_cpu_unit "alu" "alu")
+(define_cpu_unit "imuldiv" "imuldiv")
+
+;; Ghost instructions produce no real code and introduce no hazards.
+;; They exist purely to express an effect on dataflow.
+(define_insn_reservation "ghost" 0
+ (eq_attr "type" "ghost")
+ "nothing")
+
+(include "4k.md")
+(include "5k.md")
+(include "20kc.md")
+(include "24k.md")
+(include "74k.md")
+(include "3000.md")
+(include "4000.md")
+(include "4100.md")
+(include "4130.md")
+(include "4300.md")
+(include "4600.md")
+(include "5000.md")
+(include "5400.md")
+(include "5500.md")
+(include "6000.md")
+(include "7000.md")
+(include "9000.md")
+(include "10000.md")
+(include "loongson2ef.md")
+(include "octeon.md")
+(include "sb1.md")
+(include "sr71k.md")
+(include "xlr.md")
+(include "generic.md")
\f
;;
;; ....................
(define_insn "trap"
[(trap_if (const_int 1) (const_int 0))]
""
- "*
{
if (ISA_HAS_COND_TRAP)
- return \"teq\\t$0,$0\";
+ return "teq\t$0,$0";
+ else if (TARGET_MIPS16)
+ return "break 0";
else
- return \"break\";
-}")
+ return "break";
+}
+ [(set_attr "type" "trap")])
(define_expand "conditional_trap"
- [(trap_if (match_operator 0 "cmp_op"
+ [(trap_if (match_operator 0 "comparison_operator"
[(match_dup 2) (match_dup 3)])
- (match_operand 1 "const_int_operand" ""))]
+ (match_operand 1 "const_int_operand"))]
"ISA_HAS_COND_TRAP"
- "
{
- mips_gen_conditional_trap (operands);
- DONE;
-}")
-
-;; Match a TRAP_IF with 2nd arg of 0. The div_trap_* insns match a
-;; 2nd arg of any CONST_INT, so this insn must appear first.
-;; gen_div_trap always generates TRAP_IF with 2nd arg of 6 or 7.
+ if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
+ && operands[1] == const0_rtx)
+ {
+ mips_expand_conditional_trap (GET_CODE (operands[0]));
+ DONE;
+ }
+ FAIL;
+})
-(define_insn ""
- [(trap_if (match_operator 0 "trap_cmp_op"
- [(match_operand:SI 1 "reg_or_0_operand" "d")
- (match_operand:SI 2 "nonmemory_operand" "dI")])
+(define_insn "*conditional_trap<mode>"
+ [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
+ [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
+ (match_operand:GPR 2 "arith_operand" "dI")])
(const_int 0))]
"ISA_HAS_COND_TRAP"
- "t%C0\\t%z1,%z2")
+ "t%C0\t%z1,%2"
+ [(set_attr "type" "trap")])
\f
;;
;; ....................
;; ....................
;;
-(define_insn "adddf3"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (plus:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "add.d\\t%0,%1,%2"
- [(set_attr "type" "fadd")
- (set_attr "mode" "DF")])
-
-(define_insn "addsf3"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (plus:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "add.s\\t%0,%1,%2"
- [(set_attr "type" "fadd")
- (set_attr "mode" "SF")])
-
-(define_expand "addsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
- (match_operand:SI 2 "arith_operand" "dI")))]
+(define_insn "add<mode>3"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
+ (match_operand:ANYF 2 "register_operand" "f")))]
""
- "
-{
- /* The mips16 assembler handles -32768 correctly, and so does gas,
- but some other MIPS assemblers think that -32768 needs to be
- loaded into a register before it can be added in. */
- if (! TARGET_MIPS16
- && ! TARGET_GAS
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) == -32768)
- operands[2] = force_reg (SImode, operands[2]);
-}")
-
-(define_insn "addsi3_internal"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "! TARGET_MIPS16
- && (TARGET_GAS
- || GET_CODE (operands[2]) != CONST_INT
- || INTVAL (operands[2]) != -32768)"
- "addu\\t%0,%z1,%2"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-;; For the mips16, we need to recognize stack pointer additions
-;; explicitly, since we don't have a constraint for $sp. These insns
-;; will be generated by the save_restore_insns functions.
-
-(define_insn ""
- [(set (reg:SI 29)
- (plus:SI (reg:SI 29)
- (match_operand:SI 0 "small_int" "I")))]
- "TARGET_MIPS16"
- "addu\\t%$,%$,%0"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_simm8_8" "")
- (const_int 4)
- (const_int 8)))])
+ "add.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_expand "add<mode>3"
+ [(set (match_operand:GPR 0 "register_operand")
+ (plus:GPR (match_operand:GPR 1 "register_operand")
+ (match_operand:GPR 2 "arith_operand")))]
+ "")
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d")
- (plus:SI (reg:SI 29)
- (match_operand:SI 1 "small_int" "I")))]
+(define_insn "*add<mode>3"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
+ (match_operand:GPR 2 "arith_operand" "d,Q")))]
+ "!TARGET_MIPS16"
+ "@
+ <d>addu\t%0,%1,%2
+ <d>addiu\t%0,%1,%2"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "*add<mode>3_mips16"
+ [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
+ (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
+ (match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))]
"TARGET_MIPS16"
- "addu\\t%0,%$,%1"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set (attr "length") (if_then_else (match_operand:VOID 1 "m16_uimm8_4" "")
- (const_int 4)
- (const_int 8)))])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d,d")
- (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
- (match_operand:SI 2 "arith_operand" "IQ,O,d")))]
- "TARGET_MIPS16
- && (GET_CODE (operands[1]) != REG
- || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
- || M16_REG_P (REGNO (operands[1]))
- || REGNO (operands[1]) == ARG_POINTER_REGNUM
- || REGNO (operands[1]) == FRAME_POINTER_REGNUM
- || REGNO (operands[1]) == STACK_POINTER_REGNUM)
- && (GET_CODE (operands[2]) != REG
- || REGNO (operands[2]) >= FIRST_PSEUDO_REGISTER
- || M16_REG_P (REGNO (operands[2]))
- || REGNO (operands[2]) == ARG_POINTER_REGNUM
- || REGNO (operands[2]) == FRAME_POINTER_REGNUM
- || REGNO (operands[2]) == STACK_POINTER_REGNUM)"
- "*
-{
- if (REGNO (operands[0]) == REGNO (operands[1]))
- return \"addu\\t%0,%2\";
- return \"addu\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
+ "@
+ <d>addiu\t%0,%2
+ <d>addiu\t%0,%1,%2
+ <d>addiu\t%0,%2
+ <d>addiu\t%0,%1,%2
+ <d>addu\t%0,%1,%2"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "<MODE>")
(set_attr_alternative "length"
- [(if_then_else (match_operand:VOID 2 "m16_simm8_1" "")
+ [(if_then_else (match_operand 2 "m16_simm8_8")
+ (const_int 4)
+ (const_int 8))
+ (if_then_else (match_operand 2 "m16_uimm<si8_di5>_4")
(const_int 4)
(const_int 8))
- (if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
+ (if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
+ (const_int 4)
+ (const_int 8))
+ (if_then_else (match_operand 2 "m16_simm4_1")
(const_int 4)
(const_int 8))
(const_int 4)])])
-
;; On the mips16, we can sometimes split an add of a constant which is
;; a 4 byte instruction into two adds which are both 2 byte
;; instructions. There are two cases: one where we are adding a
;; simply adding a constant to a register.
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
+ [(set (match_operand:SI 0 "d_operand")
(plus:SI (match_dup 0)
- (match_operand:SI 1 "const_int_operand" "")))]
+ (match_operand:SI 1 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) > 0x7f
&& INTVAL (operands[1]) <= 0x7f + 0x7f)
|| (INTVAL (operands[1]) < - 0x80
&& INTVAL (operands[1]) >= - 0x80 - 0x80))"
[(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
- "
{
HOST_WIDE_INT val = INTVAL (operands[1]);
operands[1] = GEN_INT (- 0x80);
operands[2] = GEN_INT (val + 0x80);
}
-}")
+})
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (plus:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
+ [(set (match_operand:SI 0 "d_operand")
+ (plus:SI (match_operand:SI 1 "d_operand")
+ (match_operand:SI 2 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG
- && M16_REG_P (REGNO (operands[1]))
&& REGNO (operands[0]) != REGNO (operands[1])
- && GET_CODE (operands[2]) == CONST_INT
&& ((INTVAL (operands[2]) > 0x7
&& INTVAL (operands[2]) <= 0x7 + 0x7f)
|| (INTVAL (operands[2]) < - 0x8
&& INTVAL (operands[2]) >= - 0x8 - 0x80))"
[(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
- "
{
HOST_WIDE_INT val = INTVAL (operands[2]);
operands[2] = GEN_INT (- 0x8);
operands[3] = GEN_INT (val + 0x8);
}
-}")
-
-(define_expand "adddi3"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (plus:DI (match_operand:DI 1 "se_register_operand" "")
- (match_operand:DI 2 "se_arith_operand" "")))
- (clobber (match_dup 3))])]
- "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
- "
-{
- /* The mips16 assembler handles -32768 correctly, and so does gas,
- but some other MIPS assemblers think that -32768 needs to be
- loaded into a register before it can be added in. */
- if (! TARGET_MIPS16
- && ! TARGET_GAS
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) == -32768)
- operands[2] = force_reg (DImode, operands[2]);
-
- if (TARGET_64BIT)
- {
- emit_insn (gen_adddi3_internal_3 (operands[0], operands[1],
- operands[2]));
- DONE;
- }
-
- operands[3] = gen_reg_rtx (SImode);
-}")
-
-(define_insn "adddi3_internal_1"
- [(set (match_operand:DI 0 "register_operand" "=d,&d")
- (plus:DI (match_operand:DI 1 "register_operand" "0,d")
- (match_operand:DI 2 "register_operand" "d,d")))
- (clobber (match_operand:SI 3 "register_operand" "=d,d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "*
-{
- return (REGNO (operands[0]) == REGNO (operands[1])
- && REGNO (operands[0]) == REGNO (operands[2]))
- ? \"srl\\t%3,%L0,31\;sll\\t%M0,%M0,1\;sll\\t%L0,%L1,1\;addu\\t%M0,%M0,%3\"
- : \"addu\\t%L0,%L1,%L2\;sltu\\t%3,%L0,%L2\;addu\\t%M0,%M1,%M2\;addu\\t%M0,%M0,%3\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (plus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "register_operand" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
- && (REGNO (operands[0]) != REGNO (operands[1])
- || REGNO (operands[0]) != REGNO (operands[2]))"
-
- [(set (subreg:SI (match_dup 0) 0)
- (plus:SI (subreg:SI (match_dup 1) 0)
- (subreg:SI (match_dup 2) 0)))
-
- (set (match_dup 3)
- (ltu:SI (subreg:SI (match_dup 0) 0)
- (subreg:SI (match_dup 2) 0)))
-
- (set (subreg:SI (match_dup 0) 4)
- (plus:SI (subreg:SI (match_dup 1) 4)
- (subreg:SI (match_dup 2) 4)))
-
- (set (subreg:SI (match_dup 0) 4)
- (plus:SI (subreg:SI (match_dup 0) 4)
- (match_dup 3)))]
- "")
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (plus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "register_operand" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
- && (REGNO (operands[0]) != REGNO (operands[1])
- || REGNO (operands[0]) != REGNO (operands[2]))"
-
- [(set (subreg:SI (match_dup 0) 4)
- (plus:SI (subreg:SI (match_dup 1) 4)
- (subreg:SI (match_dup 2) 4)))
-
- (set (match_dup 3)
- (ltu:SI (subreg:SI (match_dup 0) 4)
- (subreg:SI (match_dup 2) 4)))
-
- (set (subreg:SI (match_dup 0) 0)
- (plus:SI (subreg:SI (match_dup 1) 0)
- (subreg:SI (match_dup 2) 0)))
-
- (set (subreg:SI (match_dup 0) 0)
- (plus:SI (subreg:SI (match_dup 0) 0)
- (match_dup 3)))]
- "")
-
-(define_insn "adddi3_internal_2"
- [(set (match_operand:DI 0 "register_operand" "=d,d,d")
- (plus:DI (match_operand:DI 1 "register_operand" "%d,%d,%d")
- (match_operand:DI 2 "small_int" "P,J,N")))
- (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && (TARGET_GAS
- || GET_CODE (operands[2]) != CONST_INT
- || INTVAL (operands[2]) != -32768)"
- "@
- addu\\t%L0,%L1,%2\;sltu\\t%3,%L0,%2\;addu\\t%M0,%M1,%3
- move\\t%L0,%L1\;move\\t%M0,%M1
- subu\\t%L0,%L1,%n2\;sltu\\t%3,%L0,%2\;subu\\t%M0,%M1,1\;addu\\t%M0,%M0,%3"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "12,8,16")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (plus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && INTVAL (operands[2]) > 0"
-
- [(set (subreg:SI (match_dup 0) 0)
- (plus:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ltu:SI (subreg:SI (match_dup 0) 0)
- (match_dup 2)))
-
- (set (subreg:SI (match_dup 0) 4)
- (plus:SI (subreg:SI (match_dup 1) 4)
- (match_dup 3)))]
- "")
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (plus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && INTVAL (operands[2]) > 0"
-
- [(set (subreg:SI (match_dup 0) 4)
- (plus:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ltu:SI (subreg:SI (match_dup 0) 4)
- (match_dup 2)))
-
- (set (subreg:SI (match_dup 0) 0)
- (plus:SI (subreg:SI (match_dup 1) 0)
- (match_dup 3)))]
- "")
-
-(define_insn "adddi3_internal_3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (plus:DI (match_operand:DI 1 "se_reg_or_0_operand" "dJ")
- (match_operand:DI 2 "se_arith_operand" "dI")))]
- "TARGET_64BIT
- && !TARGET_MIPS16
- && (TARGET_GAS
- || GET_CODE (operands[2]) != CONST_INT
- || INTVAL (operands[2]) != -32768)"
- "*
-{
- return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
- ? \"dsubu\\t%0,%z1,%n2\"
- : \"daddu\\t%0,%z1,%2\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")])
-
-;; For the mips16, we need to recognize stack pointer additions
-;; explicitly, since we don't have a constraint for $sp. These insns
-;; will be generated by the save_restore_insns functions.
-
-(define_insn ""
- [(set (reg:DI 29)
- (plus:DI (reg:DI 29)
- (match_operand:DI 0 "small_int" "I")))]
- "TARGET_MIPS16 && TARGET_64BIT"
- "daddu\\t%$,%$,%0"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_simm8_8" "")
- (const_int 4)
- (const_int 8)))])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d")
- (plus:DI (reg:DI 29)
- (match_operand:DI 1 "small_int" "I")))]
- "TARGET_MIPS16 && TARGET_64BIT"
- "daddu\\t%0,%$,%1"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_uimm5_4" "")
- (const_int 4)
- (const_int 8)))])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d,d")
- (plus:DI (match_operand:DI 1 "register_operand" "0,d,d")
- (match_operand:DI 2 "arith_operand" "IQ,O,d")))]
- "TARGET_MIPS16 && TARGET_64BIT
- && (GET_CODE (operands[1]) != REG
- || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
- || M16_REG_P (REGNO (operands[1]))
- || REGNO (operands[1]) == ARG_POINTER_REGNUM
- || REGNO (operands[1]) == FRAME_POINTER_REGNUM
- || REGNO (operands[1]) == STACK_POINTER_REGNUM)
- && (GET_CODE (operands[2]) != REG
- || REGNO (operands[2]) >= FIRST_PSEUDO_REGISTER
- || M16_REG_P (REGNO (operands[2]))
- || REGNO (operands[2]) == ARG_POINTER_REGNUM
- || REGNO (operands[2]) == FRAME_POINTER_REGNUM
- || REGNO (operands[2]) == STACK_POINTER_REGNUM)"
- "*
-{
- if (REGNO (operands[0]) == REGNO (operands[1]))
- return \"daddu\\t%0,%2\";
- return \"daddu\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr_alternative "length"
- [(if_then_else (match_operand:VOID 2 "m16_simm5_1" "")
- (const_int 4)
- (const_int 8))
- (if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
- (const_int 4)
- (const_int 8))
- (const_int 4)])])
-
-
-;; On the mips16, we can sometimes split an add of a constant which is
-;; a 4 byte instruction into two adds which are both 2 byte
-;; instructions. There are two cases: one where we are adding a
-;; constant plus a register to another register, and one where we are
-;; simply adding a constant to a register.
+})
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "d_operand")
(plus:DI (match_dup 0)
- (match_operand:DI 1 "const_int_operand" "")))]
+ (match_operand:DI 1 "const_int_operand")))]
"TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) > 0xf
&& INTVAL (operands[1]) <= 0xf + 0xf)
|| (INTVAL (operands[1]) < - 0x10
&& INTVAL (operands[1]) >= - 0x10 - 0x10))"
[(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
- "
{
HOST_WIDE_INT val = INTVAL (operands[1]);
operands[1] = GEN_INT (- 0x10);
operands[2] = GEN_INT (val + 0x10);
}
-}")
+})
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (plus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "const_int_operand" "")))]
+ [(set (match_operand:DI 0 "d_operand")
+ (plus:DI (match_operand:DI 1 "d_operand")
+ (match_operand:DI 2 "const_int_operand")))]
"TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG
- && M16_REG_P (REGNO (operands[1]))
&& REGNO (operands[0]) != REGNO (operands[1])
- && GET_CODE (operands[2]) == CONST_INT
&& ((INTVAL (operands[2]) > 0x7
&& INTVAL (operands[2]) <= 0x7 + 0xf)
|| (INTVAL (operands[2]) < - 0x8
&& INTVAL (operands[2]) >= - 0x8 - 0x10))"
[(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
- "
{
HOST_WIDE_INT val = INTVAL (operands[2]);
operands[2] = GEN_INT (- 0x8);
operands[3] = GEN_INT (val + 0x8);
}
-}")
+})
-(define_insn "addsi3_internal_2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (sign_extend:DI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
- (match_operand:SI 2 "arith_operand" "dI"))))]
- "TARGET_64BIT
- && !TARGET_MIPS16
- && (TARGET_GAS
- || GET_CODE (operands[2]) != CONST_INT
- || INTVAL (operands[2]) != -32768)"
- "*
-{
- return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
- ? \"subu\\t%0,%z1,%n2\"
- : \"addu\\t%0,%z1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
+(define_insn "*addsi3_extended"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (sign_extend:DI
+ (plus:SI (match_operand:SI 1 "register_operand" "d,d")
+ (match_operand:SI 2 "arith_operand" "d,Q"))))]
+ "TARGET_64BIT && !TARGET_MIPS16"
+ "@
+ addu\t%0,%1,%2
+ addiu\t%0,%1,%2"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")])
-(define_insn ""
+;; Split this insn so that the addiu splitters can have a crack at it.
+;; Use a conservative length estimate until the split.
+(define_insn_and_split "*addsi3_extended_mips16"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
- (sign_extend:DI (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
- (match_operand:SI 2 "arith_operand" "I,O,d"))))]
- "TARGET_MIPS16 && TARGET_64BIT"
- "*
-{
- if (REGNO (operands[0]) == REGNO (operands[1]))
- return \"addu\\t%0,%2\";
- return \"addu\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr_alternative "length"
- [(if_then_else (match_operand:VOID 2 "m16_simm8_1" "")
- (const_int 4)
- (const_int 8))
- (if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
- (const_int 4)
- (const_int 8))
- (const_int 4)])])
+ (sign_extend:DI
+ (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
+ (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
+ "TARGET_64BIT && TARGET_MIPS16"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
+ { operands[3] = gen_lowpart (SImode, operands[0]); }
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")
+ (set_attr "extended_mips16" "yes")])
+;; Combiner patterns for unsigned byte-add.
+
+(define_insn "*baddu_si_eb"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (zero_extend:SI
+ (subreg:QI
+ (plus:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d")) 3)))]
+ "ISA_HAS_BADDU && BYTES_BIG_ENDIAN"
+ "baddu\\t%0,%1,%2"
+ [(set_attr "type" "arith")])
+
+(define_insn "*baddu_si_el"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (zero_extend:SI
+ (subreg:QI
+ (plus:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d")) 0)))]
+ "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"
+ "baddu\\t%0,%1,%2"
+ [(set_attr "type" "arith")])
+
+(define_insn "*baddu_di<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (zero_extend:GPR
+ (truncate:QI
+ (plus:DI (match_operand:DI 1 "register_operand" "d")
+ (match_operand:DI 2 "register_operand" "d")))))]
+ "ISA_HAS_BADDU && TARGET_64BIT"
+ "baddu\\t%0,%1,%2"
+ [(set_attr "type" "arith")])
\f
;;
;; ....................
;; ....................
;;
-(define_insn "subdf3"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (minus:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "sub.d\\t%0,%1,%2"
- [(set_attr "type" "fadd")
- (set_attr "mode" "DF")])
+(define_insn "sub<mode>3"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
+ (match_operand:ANYF 2 "register_operand" "f")))]
+ ""
+ "sub.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "sub<mode>3"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (minus:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "register_operand" "d")))]
+ ""
+ "<d>subu\t%0,%1,%2"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "<MODE>")])
-(define_insn "subsf3"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (minus:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "sub.s\\t%0,%1,%2"
- [(set_attr "type" "fadd")
- (set_attr "mode" "SF")])
+(define_insn "*subsi3_extended"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (sign_extend:DI
+ (minus:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d"))))]
+ "TARGET_64BIT"
+ "subu\t%0,%1,%2"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "DI")])
+\f
+;;
+;; ....................
+;;
+;; MULTIPLICATION
+;;
+;; ....................
+;;
-(define_expand "subsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
- (match_operand:SI 2 "arith_operand" "dI")))]
+(define_expand "mul<mode>3"
+ [(set (match_operand:SCALARF 0 "register_operand")
+ (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
+ (match_operand:SCALARF 2 "register_operand")))]
""
- "
-{
- if (GET_CODE (operands[2]) == CONST_INT
- && (INTVAL (operands[2]) == -32768
- || (TARGET_MIPS16
- && INTVAL (operands[2]) == -0x4000)))
- operands[2] = force_reg (SImode, operands[2]);
-}")
+ "")
-(define_insn "subsi3_internal"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "!TARGET_MIPS16
- && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
- "subu\\t%0,%z1,%2"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
+(define_insn "*mul<mode>3"
+ [(set (match_operand:SCALARF 0 "register_operand" "=f")
+ (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
+ (match_operand:SCALARF 2 "register_operand" "f")))]
+ "!TARGET_4300_MUL_FIX"
+ "mul.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fmul")
+ (set_attr "mode" "<MODE>")])
-;; For the mips16, we need to recognize stack pointer subtractions
-;; explicitly, since we don't have a constraint for $sp. These insns
-;; will be generated by the save_restore_insns functions.
+;; Early VR4300 silicon has a CPU bug where multiplies with certain
+;; operands may corrupt immediately following multiplies. This is a
+;; simple fix to insert NOPs.
-(define_insn ""
- [(set (reg:SI 29)
- (minus:SI (reg:SI 29)
- (match_operand:SI 0 "small_int" "I")))]
- "TARGET_MIPS16
- && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
- "addu\\t%$,%$,%n0"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_nsimm8_8" "")
- (const_int 4)
- (const_int 8)))])
+(define_insn "*mul<mode>3_r4300"
+ [(set (match_operand:SCALARF 0 "register_operand" "=f")
+ (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
+ (match_operand:SCALARF 2 "register_operand" "f")))]
+ "TARGET_4300_MUL_FIX"
+ "mul.<fmt>\t%0,%1,%2\;nop"
+ [(set_attr "type" "fmul")
+ (set_attr "mode" "<MODE>")
+ (set_attr "length" "8")])
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d")
- (minus:SI (reg:SI 29)
- (match_operand:SI 1 "small_int" "I")))]
- "TARGET_MIPS16
- && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
- "addu\\t%0,%$,%n1"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set (attr "length") (if_then_else (match_operand:VOID 1 "m16_nuimm8_4" "")
- (const_int 4)
- (const_int 8)))])
+(define_insn "mulv2sf3"
+ [(set (match_operand:V2SF 0 "register_operand" "=f")
+ (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
+ (match_operand:V2SF 2 "register_operand" "f")))]
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
+ "mul.ps\t%0,%1,%2"
+ [(set_attr "type" "fmul")
+ (set_attr "mode" "SF")])
+;; The original R4000 has a cpu bug. If a double-word or a variable
+;; shift executes while an integer multiplication is in progress, the
+;; shift may give an incorrect result. Avoid this by keeping the mflo
+;; with the mult on the R4000.
+;;
+;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
+;; (also valid for MIPS R4000MC processors):
+;;
+;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
+;; this errata description.
+;; The following code sequence causes the R4000 to incorrectly
+;; execute the Double Shift Right Arithmetic 32 (dsra32)
+;; instruction. If the dsra32 instruction is executed during an
+;; integer multiply, the dsra32 will only shift by the amount in
+;; specified in the instruction rather than the amount plus 32
+;; bits.
+;; instruction 1: mult rs,rt integer multiply
+;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
+;; right arithmetic + 32
+;; Workaround: A dsra32 instruction placed after an integer
+;; multiply should not be one of the 11 instructions after the
+;; multiply instruction."
+;;
+;; and:
+;;
+;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
+;; the following description.
+;; All extended shifts (shift by n+32) and variable shifts (32 and
+;; 64-bit versions) may produce incorrect results under the
+;; following conditions:
+;; 1) An integer multiply is currently executing
+;; 2) These types of shift instructions are executed immediately
+;; following an integer divide instruction.
+;; Workaround:
+;; 1) Make sure no integer multiply is running wihen these
+;; instruction are executed. If this cannot be predicted at
+;; compile time, then insert a "mfhi" to R0 instruction
+;; immediately after the integer multiply instruction. This
+;; will cause the integer multiply to complete before the shift
+;; is executed.
+;; 2) Separate integer divide and these two classes of shift
+;; instructions by another instruction or a noop."
+;;
+;; These processors have PRId values of 0x00004220 and 0x00004300,
+;; respectively.
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d,d")
- (minus:SI (match_operand:SI 1 "register_operand" "0,d,d")
- (match_operand:SI 2 "arith_operand" "I,O,d")))]
- "TARGET_MIPS16
- && (GET_CODE (operands[2]) != CONST_INT
- || (INTVAL (operands[2]) != -32768 && INTVAL (operands[2]) != -0x4000))"
- "*
-{
- if (REGNO (operands[0]) == REGNO (operands[1]))
- return \"subu\\t%0,%2\";
- return \"subu\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
+(define_expand "mul<mode>3"
+ [(set (match_operand:GPR 0 "register_operand")
+ (mult:GPR (match_operand:GPR 1 "register_operand")
+ (match_operand:GPR 2 "register_operand")))]
+ ""
+{
+ if (TARGET_LOONGSON_2EF)
+ emit_insn (gen_mul<mode>3_mul3_ls2ef (operands[0], operands[1],
+ operands[2]));
+ else if (ISA_HAS_<D>MUL3)
+ emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2]));
+ else if (TARGET_FIX_R4000)
+ emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
+ else
+ emit_insn
+ (gen_mul<mode>3_internal (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_insn "mul<mode>3_mul3_ls2ef"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (mult:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "register_operand" "d")))]
+ "TARGET_LOONGSON_2EF"
+ "<d>multu.g\t%0,%1,%2"
+ [(set_attr "type" "imul3nc")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "mul<mode>3_mul3"
+ [(set (match_operand:GPR 0 "register_operand" "=d,l")
+ (mult:GPR (match_operand:GPR 1 "register_operand" "d,d")
+ (match_operand:GPR 2 "register_operand" "d,d")))
+ (clobber (match_scratch:GPR 3 "=l,X"))]
+ "ISA_HAS_<D>MUL3"
+{
+ if (which_alternative == 1)
+ return "<d>mult\t%1,%2";
+ if (<MODE>mode == SImode && TARGET_MIPS3900)
+ return "mult\t%0,%1,%2";
+ return "<d>mul\t%0,%1,%2";
+}
+ [(set_attr "type" "imul3,imul")
+ (set_attr "mode" "<MODE>")])
+
+;; If a register gets allocated to LO, and we spill to memory, the reload
+;; will include a move from LO to a GPR. Merge it into the multiplication
+;; if it can set the GPR directly.
+;;
+;; Operand 0: LO
+;; Operand 1: GPR (1st multiplication operand)
+;; Operand 2: GPR (2nd multiplication operand)
+;; Operand 3: GPR (destination)
+(define_peephole2
+ [(parallel
+ [(set (match_operand:SI 0 "lo_operand")
+ (mult:SI (match_operand:SI 1 "d_operand")
+ (match_operand:SI 2 "d_operand")))
+ (clobber (scratch:SI))])
+ (set (match_operand:SI 3 "d_operand")
+ (match_dup 0))]
+ "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
+ [(parallel
+ [(set (match_dup 3)
+ (mult:SI (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 0))])])
+
+(define_insn "mul<mode>3_internal"
+ [(set (match_operand:GPR 0 "register_operand" "=l")
+ (mult:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "register_operand" "d")))]
+ "!TARGET_FIX_R4000"
+ "<d>mult\t%1,%2"
+ [(set_attr "type" "imul")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "mul<mode>3_r4000"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (mult:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "register_operand" "d")))
+ (clobber (match_scratch:GPR 3 "=l"))]
+ "TARGET_FIX_R4000"
+ "<d>mult\t%1,%2\;mflo\t%0"
+ [(set_attr "type" "imul")
+ (set_attr "mode" "<MODE>")
+ (set_attr "length" "8")])
+
+;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
+;; of "mult; mflo". They have the same latency, but the first form gives
+;; us an extra cycle to compute the operands.
+
+;; Operand 0: LO
+;; Operand 1: GPR (1st multiplication operand)
+;; Operand 2: GPR (2nd multiplication operand)
+;; Operand 3: GPR (destination)
+(define_peephole2
+ [(set (match_operand:SI 0 "lo_operand")
+ (mult:SI (match_operand:SI 1 "d_operand")
+ (match_operand:SI 2 "d_operand")))
+ (set (match_operand:SI 3 "d_operand")
+ (match_dup 0))]
+ "ISA_HAS_MACC && !ISA_HAS_MUL3"
+ [(set (match_dup 0)
+ (const_int 0))
+ (parallel
+ [(set (match_dup 0)
+ (plus:SI (mult:SI (match_dup 1)
+ (match_dup 2))
+ (match_dup 0)))
+ (set (match_dup 3)
+ (plus:SI (mult:SI (match_dup 1)
+ (match_dup 2))
+ (match_dup 0)))])])
+
+;; Multiply-accumulate patterns
+
+;; This pattern is first matched by combine, which tries to use the
+;; pattern wherever it can. We don't know until later whether it
+;; is actually profitable to use MADD over a "MUL; ADDIU" sequence,
+;; so we need to keep both options open.
+;;
+;; The second alternative has a "?" marker because it is generally
+;; one instruction more costly than the first alternative. This "?"
+;; marker is enough to convey the relative costs to the register
+;; allocator.
+;;
+;; However, reload counts reloads of operands 4 and 5 in the same way as
+;; reloads of the other operands, even though operands 4 and 5 need no
+;; copy instructions. Reload therefore thinks that the second alternative
+;; is two reloads more costly than the first. We add "*?*?" to the first
+;; alternative as a counterweight.
+(define_insn "*mul_acc_si"
+ [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
+ (match_operand:SI 2 "register_operand" "d,d"))
+ (match_operand:SI 3 "register_operand" "0,d")))
+ (clobber (match_scratch:SI 4 "=X,l"))
+ (clobber (match_scratch:SI 5 "=X,&d"))]
+ "GENERATE_MADD_MSUB && !TARGET_MIPS16"
+ "@
+ madd\t%1,%2
+ #"
+ [(set_attr "type" "imadd")
(set_attr "mode" "SI")
- (set_attr_alternative "length"
- [(if_then_else (match_operand:VOID 2 "m16_nsimm8_1" "")
- (const_int 4)
- (const_int 8))
- (if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "")
- (const_int 4)
- (const_int 8))
- (const_int 4)])])
+ (set_attr "length" "4,8")])
-;; On the mips16, we can sometimes split an subtract of a constant
-;; which is a 4 byte instruction into two adds which are both 2 byte
-;; instructions. There are two cases: one where we are setting a
-;; register to a register minus a constant, and one where we are
-;; simply subtracting a constant from a register.
+;; The same idea applies here. The middle alternative needs one less
+;; clobber than the final alternative, so we add "*?" as a counterweight.
+(define_insn "*mul_acc_si_r3900"
+ [(set (match_operand:SI 0 "register_operand" "=l*?*?,d*?,d?")
+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
+ (match_operand:SI 2 "register_operand" "d,d,d"))
+ (match_operand:SI 3 "register_operand" "0,l,d")))
+ (clobber (match_scratch:SI 4 "=X,3,l"))
+ (clobber (match_scratch:SI 5 "=X,X,&d"))]
+ "TARGET_MIPS3900 && !TARGET_MIPS16"
+ "@
+ madd\t%1,%2
+ madd\t%0,%1,%2
+ #"
+ [(set_attr "type" "imadd")
+ (set_attr "mode" "SI")
+ (set_attr "length" "4,4,8")])
+;; Split *mul_acc_si if both the source and destination accumulator
+;; values are GPRs.
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (minus:SI (match_dup 0)
- (match_operand:SI 1 "const_int_operand" "")))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
- && ((INTVAL (operands[1]) > 0x80
- && INTVAL (operands[1]) <= 0x80 + 0x80)
- || (INTVAL (operands[1]) < - 0x7f
- && INTVAL (operands[1]) >= - 0x7f - 0x7f))"
- [(set (match_dup 0) (minus:SI (match_dup 0) (match_dup 1)))
- (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
- "
+ [(set (match_operand:SI 0 "d_operand")
+ (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
+ (match_operand:SI 2 "d_operand"))
+ (match_operand:SI 3 "d_operand")))
+ (clobber (match_operand:SI 4 "lo_operand"))
+ (clobber (match_operand:SI 5 "d_operand"))]
+ "reload_completed"
+ [(parallel [(set (match_dup 5)
+ (mult:SI (match_dup 1) (match_dup 2)))
+ (clobber (match_dup 4))])
+ (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))]
+ "")
+
+(define_insn "*macc"
+ [(set (match_operand:SI 0 "register_operand" "=l,d")
+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
+ (match_operand:SI 2 "register_operand" "d,d"))
+ (match_operand:SI 3 "register_operand" "0,l")))
+ (clobber (match_scratch:SI 4 "=X,3"))]
+ "ISA_HAS_MACC"
{
- HOST_WIDE_INT val = INTVAL (operands[1]);
+ if (which_alternative == 1)
+ return "macc\t%0,%1,%2";
+ else if (TARGET_MIPS5500)
+ return "madd\t%1,%2";
+ else
+ /* The VR4130 assumes that there is a two-cycle latency between a macc
+ that "writes" to $0 and an instruction that reads from it. We avoid
+ this by assigning to $1 instead. */
+ return "%[macc\t%@,%1,%2%]";
+}
+ [(set_attr "type" "imadd")
+ (set_attr "mode" "SI")])
- if (val >= 0)
- {
- operands[1] = GEN_INT (0x80);
- operands[2] = GEN_INT (val - 0x80);
- }
+(define_insn "*msac"
+ [(set (match_operand:SI 0 "register_operand" "=l,d")
+ (minus:SI (match_operand:SI 1 "register_operand" "0,l")
+ (mult:SI (match_operand:SI 2 "register_operand" "d,d")
+ (match_operand:SI 3 "register_operand" "d,d"))))
+ (clobber (match_scratch:SI 4 "=X,1"))]
+ "ISA_HAS_MSAC"
+{
+ if (which_alternative == 1)
+ return "msac\t%0,%2,%3";
+ else if (TARGET_MIPS5500)
+ return "msub\t%2,%3";
else
- {
- operands[1] = GEN_INT (- 0x7f);
- operands[2] = GEN_INT (val + 0x7f);
- }
-}")
+ return "msac\t$0,%2,%3";
+}
+ [(set_attr "type" "imadd")
+ (set_attr "mode" "SI")])
+
+;; An msac-like instruction implemented using negation and a macc.
+(define_insn_and_split "*msac_using_macc"
+ [(set (match_operand:SI 0 "register_operand" "=l,d")
+ (minus:SI (match_operand:SI 1 "register_operand" "0,l")
+ (mult:SI (match_operand:SI 2 "register_operand" "d,d")
+ (match_operand:SI 3 "register_operand" "d,d"))))
+ (clobber (match_scratch:SI 4 "=X,1"))
+ (clobber (match_scratch:SI 5 "=d,d"))]
+ "ISA_HAS_MACC && !ISA_HAS_MSAC"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 5)
+ (neg:SI (match_dup 3)))
+ (parallel
+ [(set (match_dup 0)
+ (plus:SI (mult:SI (match_dup 2)
+ (match_dup 5))
+ (match_dup 1)))
+ (clobber (match_dup 4))])]
+ ""
+ [(set_attr "type" "imadd")
+ (set_attr "length" "8")])
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (minus:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG
- && M16_REG_P (REGNO (operands[1]))
- && REGNO (operands[0]) != REGNO (operands[1])
- && GET_CODE (operands[2]) == CONST_INT
- && ((INTVAL (operands[2]) > 0x8
- && INTVAL (operands[2]) <= 0x8 + 0x80)
- || (INTVAL (operands[2]) < - 0x7
- && INTVAL (operands[2]) >= - 0x7 - 0x7f))"
- [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 3)))]
- "
+;; Patterns generated by the define_peephole2 below.
+
+(define_insn "*macc2"
+ [(set (match_operand:SI 0 "register_operand" "=l")
+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d"))
+ (match_dup 0)))
+ (set (match_operand:SI 3 "register_operand" "=d")
+ (plus:SI (mult:SI (match_dup 1)
+ (match_dup 2))
+ (match_dup 0)))]
+ "ISA_HAS_MACC && reload_completed"
+ "macc\t%3,%1,%2"
+ [(set_attr "type" "imadd")
+ (set_attr "mode" "SI")])
+
+(define_insn "*msac2"
+ [(set (match_operand:SI 0 "register_operand" "=l")
+ (minus:SI (match_dup 0)
+ (mult:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d"))))
+ (set (match_operand:SI 3 "register_operand" "=d")
+ (minus:SI (match_dup 0)
+ (mult:SI (match_dup 1)
+ (match_dup 2))))]
+ "ISA_HAS_MSAC && reload_completed"
+ "msac\t%3,%1,%2"
+ [(set_attr "type" "imadd")
+ (set_attr "mode" "SI")])
+
+;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
+;; Similarly msac.
+;;
+;; Operand 0: LO
+;; Operand 1: macc/msac
+;; Operand 2: GPR (destination)
+(define_peephole2
+ [(parallel
+ [(set (match_operand:SI 0 "lo_operand")
+ (match_operand:SI 1 "macc_msac_operand"))
+ (clobber (scratch:SI))])
+ (set (match_operand:SI 2 "d_operand")
+ (match_dup 0))]
+ ""
+ [(parallel [(set (match_dup 0)
+ (match_dup 1))
+ (set (match_dup 2)
+ (match_dup 1))])])
+
+;; When we have a three-address multiplication instruction, it should
+;; be faster to do a separate multiply and add, rather than moving
+;; something into LO in order to use a macc instruction.
+;;
+;; This peephole needs a scratch register to cater for the case when one
+;; of the multiplication operands is the same as the destination.
+;;
+;; Operand 0: GPR (scratch)
+;; Operand 1: LO
+;; Operand 2: GPR (addend)
+;; Operand 3: GPR (destination)
+;; Operand 4: macc/msac
+;; Operand 5: new multiplication
+;; Operand 6: new addition/subtraction
+(define_peephole2
+ [(match_scratch:SI 0 "d")
+ (set (match_operand:SI 1 "lo_operand")
+ (match_operand:SI 2 "d_operand"))
+ (match_dup 0)
+ (parallel
+ [(set (match_operand:SI 3 "d_operand")
+ (match_operand:SI 4 "macc_msac_operand"))
+ (clobber (match_dup 1))])]
+ "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])"
+ [(parallel [(set (match_dup 0)
+ (match_dup 5))
+ (clobber (match_dup 1))])
+ (set (match_dup 3)
+ (match_dup 6))]
{
- HOST_WIDE_INT val = INTVAL (operands[2]);
+ operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
+ operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
+ operands[2], operands[0]);
+})
- if (val >= 0)
- {
- operands[2] = GEN_INT (0x8);
- operands[3] = GEN_INT (val - 0x8);
- }
- else
- {
- operands[2] = GEN_INT (- 0x7);
- operands[3] = GEN_INT (val + 0x7);
- }
-}")
+;; Same as above, except LO is the initial target of the macc.
+;;
+;; Operand 0: GPR (scratch)
+;; Operand 1: LO
+;; Operand 2: GPR (addend)
+;; Operand 3: macc/msac
+;; Operand 4: GPR (destination)
+;; Operand 5: new multiplication
+;; Operand 6: new addition/subtraction
+(define_peephole2
+ [(match_scratch:SI 0 "d")
+ (set (match_operand:SI 1 "lo_operand")
+ (match_operand:SI 2 "d_operand"))
+ (match_dup 0)
+ (parallel
+ [(set (match_dup 1)
+ (match_operand:SI 3 "macc_msac_operand"))
+ (clobber (scratch:SI))])
+ (match_dup 0)
+ (set (match_operand:SI 4 "d_operand")
+ (match_dup 1))]
+ "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
+ [(parallel [(set (match_dup 0)
+ (match_dup 5))
+ (clobber (match_dup 1))])
+ (set (match_dup 4)
+ (match_dup 6))]
+{
+ operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1);
+ operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
+ operands[2], operands[0]);
+})
+
+;; See the comment above *mul_add_si for details.
+(define_insn "*mul_sub_si"
+ [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
+ (minus:SI (match_operand:SI 1 "register_operand" "0,d")
+ (mult:SI (match_operand:SI 2 "register_operand" "d,d")
+ (match_operand:SI 3 "register_operand" "d,d"))))
+ (clobber (match_scratch:SI 4 "=X,l"))
+ (clobber (match_scratch:SI 5 "=X,&d"))]
+ "GENERATE_MADD_MSUB"
+ "@
+ msub\t%2,%3
+ #"
+ [(set_attr "type" "imadd")
+ (set_attr "mode" "SI")
+ (set_attr "length" "4,8")])
-(define_expand "subdi3"
- [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
- (minus:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))
- (clobber (match_dup 3))])]
- "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
- "
+;; Split *mul_sub_si if both the source and destination accumulator
+;; values are GPRs.
+(define_split
+ [(set (match_operand:SI 0 "d_operand")
+ (minus:SI (match_operand:SI 1 "d_operand")
+ (mult:SI (match_operand:SI 2 "d_operand")
+ (match_operand:SI 3 "d_operand"))))
+ (clobber (match_operand:SI 4 "lo_operand"))
+ (clobber (match_operand:SI 5 "d_operand"))]
+ "reload_completed"
+ [(parallel [(set (match_dup 5)
+ (mult:SI (match_dup 2) (match_dup 3)))
+ (clobber (match_dup 4))])
+ (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))]
+ "")
+
+(define_insn "*muls"
+ [(set (match_operand:SI 0 "register_operand" "=l,d")
+ (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
+ (match_operand:SI 2 "register_operand" "d,d"))))
+ (clobber (match_scratch:SI 3 "=X,l"))]
+ "ISA_HAS_MULS"
+ "@
+ muls\t$0,%1,%2
+ muls\t%0,%1,%2"
+ [(set_attr "type" "imul,imul3")
+ (set_attr "mode" "SI")])
+
+(define_expand "<u>mulsidi3"
+ [(set (match_operand:DI 0 "register_operand")
+ (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
+ (any_extend:DI (match_operand:SI 2 "register_operand"))))]
+ "!TARGET_64BIT || !TARGET_FIX_R4000"
{
if (TARGET_64BIT)
- {
- emit_insn (gen_subdi3_internal_3 (operands[0], operands[1],
- operands[2]));
- DONE;
- }
+ emit_insn (gen_<u>mulsidi3_64bit (operands[0], operands[1], operands[2]));
+ else if (TARGET_FIX_R4000)
+ emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
+ operands[2]));
+ else
+ emit_insn (gen_<u>mulsidi3_32bit (operands[0], operands[1], operands[2]));
+ DONE;
+})
- operands[3] = gen_reg_rtx (SImode);
-}")
+(define_insn "<u>mulsidi3_32bit"
+ [(set (match_operand:DI 0 "register_operand" "=x")
+ (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
+ (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
+ "!TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DSPR2"
+ "mult<u>\t%1,%2"
+ [(set_attr "type" "imul")
+ (set_attr "mode" "SI")])
-(define_insn "subdi3_internal"
+(define_insn "<u>mulsidi3_32bit_r4000"
[(set (match_operand:DI 0 "register_operand" "=d")
- (minus:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:DI 2 "register_operand" "d")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "sltu\\t%3,%L1,%L2\;subu\\t%L0,%L1,%L2\;subu\\t%M0,%M1,%M2\;subu\\t%M0,%M0,%3"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (minus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "register_operand" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
+ (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
+ (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
+ (clobber (match_scratch:DI 3 "=x"))]
+ "!TARGET_64BIT && TARGET_FIX_R4000"
+ "mult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
+ [(set_attr "type" "imul")
+ (set_attr "mode" "SI")
+ (set_attr "length" "12")])
+(define_insn_and_split "<u>mulsidi3_64bit"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
+ (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
+ (clobber (match_scratch:TI 3 "=x"))
+ (clobber (match_scratch:DI 4 "=d"))]
+ "TARGET_64BIT && !TARGET_FIX_R4000"
+ "#"
+ "&& reload_completed"
[(set (match_dup 3)
- (ltu:SI (subreg:SI (match_dup 1) 0)
- (subreg:SI (match_dup 2) 0)))
-
- (set (subreg:SI (match_dup 0) 0)
- (minus:SI (subreg:SI (match_dup 1) 0)
- (subreg:SI (match_dup 2) 0)))
+ (unspec:TI [(mult:DI (any_extend:DI (match_dup 1))
+ (any_extend:DI (match_dup 2)))]
+ UNSPEC_SET_HILO))
+
+ ;; OP4 <- LO, OP0 <- HI
+ (set (match_dup 4) (match_dup 5))
+ (set (match_dup 0) (unspec:DI [(match_dup 3)] UNSPEC_MFHI))
+
+ ;; Zero-extend OP4.
+ (set (match_dup 4)
+ (ashift:DI (match_dup 4)
+ (const_int 32)))
+ (set (match_dup 4)
+ (lshiftrt:DI (match_dup 4)
+ (const_int 32)))
+
+ ;; Shift OP0 into place.
+ (set (match_dup 0)
+ (ashift:DI (match_dup 0)
+ (const_int 32)))
- (set (subreg:SI (match_dup 0) 4)
- (minus:SI (subreg:SI (match_dup 1) 4)
- (subreg:SI (match_dup 2) 4)))
+ ;; OR the two halves together
+ (set (match_dup 0)
+ (ior:DI (match_dup 0)
+ (match_dup 4)))]
+ { operands[5] = gen_rtx_REG (DImode, LO_REGNUM); }
+ [(set_attr "type" "imul")
+ (set_attr "mode" "SI")
+ (set_attr "length" "24")])
+
+(define_insn "<u>mulsidi3_64bit_hilo"
+ [(set (match_operand:TI 0 "register_operand" "=x")
+ (unspec:TI
+ [(mult:DI
+ (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
+ (any_extend:DI (match_operand:SI 2 "register_operand" "d")))]
+ UNSPEC_SET_HILO))]
+ "TARGET_64BIT && !TARGET_FIX_R4000"
+ "mult<u>\t%1,%2"
+ [(set_attr "type" "imul")
+ (set_attr "mode" "SI")])
- (set (subreg:SI (match_dup 0) 4)
- (minus:SI (subreg:SI (match_dup 0) 4)
- (match_dup 3)))]
- "")
+;; Widening multiply with negation.
+(define_insn "*muls<u>_di"
+ [(set (match_operand:DI 0 "register_operand" "=x")
+ (neg:DI
+ (mult:DI
+ (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
+ (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
+ "!TARGET_64BIT && ISA_HAS_MULS"
+ "muls<u>\t$0,%1,%2"
+ [(set_attr "type" "imul")
+ (set_attr "mode" "SI")])
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (minus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "register_operand" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
+(define_insn "<u>msubsidi4"
+ [(set (match_operand:DI 0 "register_operand" "=ka")
+ (minus:DI
+ (match_operand:DI 3 "register_operand" "0")
+ (mult:DI
+ (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
+ (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
+ "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)"
+{
+ if (ISA_HAS_DSPR2)
+ return "msub<u>\t%q0,%1,%2";
+ else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
+ return "msub<u>\t%1,%2";
+ else
+ return "msac<u>\t$0,%1,%2";
+}
+ [(set_attr "type" "imadd")
+ (set_attr "mode" "SI")])
- [(set (match_dup 3)
- (ltu:SI (subreg:SI (match_dup 1) 4)
- (subreg:SI (match_dup 2) 4)))
+;; _highpart patterns
- (set (subreg:SI (match_dup 0) 4)
- (minus:SI (subreg:SI (match_dup 1) 4)
- (subreg:SI (match_dup 2) 4)))
+(define_expand "<su>mulsi3_highpart"
+ [(set (match_operand:SI 0 "register_operand")
+ (truncate:SI
+ (lshiftrt:DI
+ (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
+ (any_extend:DI (match_operand:SI 2 "register_operand")))
+ (const_int 32))))]
+ ""
+{
+ if (ISA_HAS_MULHI)
+ emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
+ operands[1],
+ operands[2]));
+ else
+ emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
+ operands[2]));
+ DONE;
+})
- (set (subreg:SI (match_dup 0) 0)
- (minus:SI (subreg:SI (match_dup 1) 0)
- (subreg:SI (match_dup 2) 0)))
+(define_insn_and_split "<su>mulsi3_highpart_internal"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (truncate:SI
+ (lshiftrt:DI
+ (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
+ (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
+ (const_int 32))))
+ (clobber (match_scratch:SI 3 "=l"))]
+ "!ISA_HAS_MULHI"
+ { return TARGET_FIX_R4000 ? "mult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
+ "&& reload_completed && !TARGET_FIX_R4000"
+ [(const_int 0)]
+{
+ rtx hilo;
- (set (subreg:SI (match_dup 0) 0)
- (minus:SI (subreg:SI (match_dup 0) 0)
- (match_dup 3)))]
- "")
+ if (TARGET_64BIT)
+ {
+ hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
+ emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
+ emit_insn (gen_mfhisi_ti (operands[0], hilo));
+ }
+ else
+ {
+ hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
+ emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
+ emit_insn (gen_mfhisi_di (operands[0], hilo));
+ }
+ DONE;
+}
+ [(set_attr "type" "imul")
+ (set_attr "mode" "SI")
+ (set_attr "length" "8")])
-(define_insn "subdi3_internal_2"
- [(set (match_operand:DI 0 "register_operand" "=d,d,d")
- (minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
- (match_operand:DI 2 "small_int" "P,J,N")))
- (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && INTVAL (operands[2]) != -32768"
- "@
- sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,%3
- move\\t%L0,%L1\;move\\t%M0,%M1
- sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,1\;subu\\t%M0,%M0,%3"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "12,8,16")])
+(define_insn "<su>mulsi3_highpart_mulhi_internal"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (truncate:SI
+ (lshiftrt:DI
+ (mult:DI
+ (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
+ (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
+ (const_int 32))))
+ (clobber (match_scratch:SI 3 "=l"))]
+ "ISA_HAS_MULHI"
+ "mulhi<u>\t%0,%1,%2"
+ [(set_attr "type" "imul3")
+ (set_attr "mode" "SI")])
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (minus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && INTVAL (operands[2]) > 0"
+(define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (truncate:SI
+ (lshiftrt:DI
+ (neg:DI
+ (mult:DI
+ (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
+ (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
+ (const_int 32))))
+ (clobber (match_scratch:SI 3 "=l"))]
+ "ISA_HAS_MULHI"
+ "mulshi<u>\t%0,%1,%2"
+ [(set_attr "type" "imul3")
+ (set_attr "mode" "SI")])
- [(set (match_dup 3)
- (ltu:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))
+;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
+;; errata MD(0), which says that dmultu does not always produce the
+;; correct result.
+(define_insn_and_split "<su>muldi3_highpart"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (truncate:DI
+ (lshiftrt:TI
+ (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
+ (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
+ (const_int 64))))
+ (clobber (match_scratch:DI 3 "=l"))]
+ "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
+ { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
+ "&& reload_completed && !TARGET_FIX_R4000"
+ [(const_int 0)]
+{
+ rtx hilo;
- (set (subreg:SI (match_dup 0) 0)
- (minus:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))
+ hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
+ emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
+ emit_insn (gen_mfhidi_ti (operands[0], hilo));
+ DONE;
+}
+ [(set_attr "type" "imul")
+ (set_attr "mode" "DI")
+ (set_attr "length" "8")])
- (set (subreg:SI (match_dup 0) 4)
- (minus:SI (subreg:SI (match_dup 1) 4)
- (match_dup 3)))]
- "")
+(define_expand "<u>mulditi3"
+ [(set (match_operand:TI 0 "register_operand")
+ (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
+ (any_extend:TI (match_operand:DI 2 "register_operand"))))]
+ "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
+{
+ if (TARGET_FIX_R4000)
+ emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2]));
+ else
+ emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1],
+ operands[2]));
+ DONE;
+})
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (minus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && INTVAL (operands[2]) > 0"
+(define_insn "<u>mulditi3_internal"
+ [(set (match_operand:TI 0 "register_operand" "=x")
+ (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
+ (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
+ "TARGET_64BIT
+ && !TARGET_FIX_R4000
+ && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
+ "dmult<u>\t%1,%2"
+ [(set_attr "type" "imul")
+ (set_attr "mode" "DI")])
- [(set (match_dup 3)
- (ltu:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))
+(define_insn "<u>mulditi3_r4000"
+ [(set (match_operand:TI 0 "register_operand" "=d")
+ (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
+ (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))
+ (clobber (match_scratch:TI 3 "=x"))]
+ "TARGET_64BIT
+ && TARGET_FIX_R4000
+ && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
+ "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
+ [(set_attr "type" "imul")
+ (set_attr "mode" "DI")
+ (set_attr "length" "12")])
- (set (subreg:SI (match_dup 0) 4)
- (minus:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))
+;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
+;; instruction. The HI/LO registers are used as a 64-bit accumulator.
- (set (subreg:SI (match_dup 0) 0)
- (minus:SI (subreg:SI (match_dup 1) 0)
- (match_dup 3)))]
- "")
+(define_insn "madsi"
+ [(set (match_operand:SI 0 "register_operand" "+l")
+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d"))
+ (match_dup 0)))]
+ "TARGET_MAD"
+ "mad\t%1,%2"
+ [(set_attr "type" "imadd")
+ (set_attr "mode" "SI")])
-(define_insn "subdi3_internal_3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (minus:DI (match_operand:DI 1 "se_reg_or_0_operand" "dJ")
- (match_operand:DI 2 "se_arith_operand" "dI")))]
- "TARGET_64BIT && !TARGET_MIPS16
- && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
- "*
-{
- return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
- ? \"daddu\\t%0,%z1,%n2\"
- : \"dsubu\\t%0,%z1,%2\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")])
+(define_insn "<u>maddsidi4"
+ [(set (match_operand:DI 0 "register_operand" "=ka")
+ (plus:DI
+ (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
+ (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
+ (match_operand:DI 3 "register_operand" "0")))]
+ "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)
+ && !TARGET_64BIT"
+{
+ if (TARGET_MAD)
+ return "mad<u>\t%1,%2";
+ else if (ISA_HAS_DSPR2)
+ return "madd<u>\t%q0,%1,%2";
+ else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
+ return "madd<u>\t%1,%2";
+ else
+ /* See comment in *macc. */
+ return "%[macc<u>\t%@,%1,%2%]";
+}
+ [(set_attr "type" "imadd")
+ (set_attr "mode" "SI")])
-;; For the mips16, we need to recognize stack pointer subtractions
-;; explicitly, since we don't have a constraint for $sp. These insns
-;; will be generated by the save_restore_insns functions.
+;; Floating point multiply accumulate instructions.
-(define_insn ""
- [(set (reg:DI 29)
- (minus:DI (reg:DI 29)
- (match_operand:DI 0 "small_int" "I")))]
- "TARGET_MIPS16
- && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
- "daddu\\t%$,%$,%n0"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_nsimm8_8" "")
- (const_int 4)
- (const_int 8)))])
+(define_insn "*madd4<mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
+ (match_operand:ANYF 2 "register_operand" "f"))
+ (match_operand:ANYF 3 "register_operand" "f")))]
+ "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
+ "madd.<fmt>\t%0,%3,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*madd3<mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
+ (match_operand:ANYF 2 "register_operand" "f"))
+ (match_operand:ANYF 3 "register_operand" "0")))]
+ "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
+ "madd.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*msub4<mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
+ (match_operand:ANYF 2 "register_operand" "f"))
+ (match_operand:ANYF 3 "register_operand" "f")))]
+ "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
+ "msub.<fmt>\t%0,%3,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*msub3<mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
+ (match_operand:ANYF 2 "register_operand" "f"))
+ (match_operand:ANYF 3 "register_operand" "0")))]
+ "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
+ "msub.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*nmadd4<mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (neg:ANYF (plus:ANYF
+ (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
+ (match_operand:ANYF 2 "register_operand" "f"))
+ (match_operand:ANYF 3 "register_operand" "f"))))]
+ "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
+ && TARGET_FUSED_MADD
+ && HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
+ "nmadd.<fmt>\t%0,%3,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*nmadd3<mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (neg:ANYF (plus:ANYF
+ (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
+ (match_operand:ANYF 2 "register_operand" "f"))
+ (match_operand:ANYF 3 "register_operand" "0"))))]
+ "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
+ && TARGET_FUSED_MADD
+ && HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
+ "nmadd.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*nmadd4<mode>_fastmath"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (minus:ANYF
+ (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
+ (match_operand:ANYF 2 "register_operand" "f"))
+ (match_operand:ANYF 3 "register_operand" "f")))]
+ "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
+ && TARGET_FUSED_MADD
+ && !HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
+ "nmadd.<fmt>\t%0,%3,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*nmadd3<mode>_fastmath"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (minus:ANYF
+ (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
+ (match_operand:ANYF 2 "register_operand" "f"))
+ (match_operand:ANYF 3 "register_operand" "0")))]
+ "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
+ && TARGET_FUSED_MADD
+ && !HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
+ "nmadd.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*nmsub4<mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (neg:ANYF (minus:ANYF
+ (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
+ (match_operand:ANYF 3 "register_operand" "f"))
+ (match_operand:ANYF 1 "register_operand" "f"))))]
+ "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
+ && TARGET_FUSED_MADD
+ && HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
+ "nmsub.<fmt>\t%0,%1,%2,%3"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*nmsub3<mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (neg:ANYF (minus:ANYF
+ (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
+ (match_operand:ANYF 3 "register_operand" "f"))
+ (match_operand:ANYF 1 "register_operand" "0"))))]
+ "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
+ && TARGET_FUSED_MADD
+ && HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
+ "nmsub.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*nmsub4<mode>_fastmath"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (minus:ANYF
+ (match_operand:ANYF 1 "register_operand" "f")
+ (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
+ (match_operand:ANYF 3 "register_operand" "f"))))]
+ "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
+ && TARGET_FUSED_MADD
+ && !HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
+ "nmsub.<fmt>\t%0,%1,%2,%3"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*nmsub3<mode>_fastmath"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (minus:ANYF
+ (match_operand:ANYF 1 "register_operand" "f")
+ (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
+ (match_operand:ANYF 3 "register_operand" "0"))))]
+ "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
+ && TARGET_FUSED_MADD
+ && !HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
+ "nmsub.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d")
- (minus:DI (reg:DI 29)
- (match_operand:DI 1 "small_int" "I")))]
- "TARGET_MIPS16
- && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
- "daddu\\t%0,%$,%n1"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_nuimm5_4" "")
- (const_int 4)
- (const_int 8)))])
+;;
+;; ....................
+;;
+;; DIVISION and REMAINDER
+;;
+;; ....................
+;;
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d,d")
- (minus:DI (match_operand:DI 1 "register_operand" "0,d,d")
- (match_operand:DI 2 "arith_operand" "I,O,d")))]
- "TARGET_MIPS16
- && (GET_CODE (operands[2]) != CONST_INT
- || (INTVAL (operands[2]) != -32768 && INTVAL (operands[2]) != -0x4000))"
- "*
-{
- if (REGNO (operands[0]) == REGNO (operands[1]))
- return \"dsubu\\t%0,%2\";
- return \"dsubu\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr_alternative "length"
- [(if_then_else (match_operand:VOID 2 "m16_nsimm5_1" "")
- (const_int 4)
- (const_int 8))
- (if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "")
- (const_int 4)
- (const_int 8))
- (const_int 4)])])
+(define_expand "div<mode>3"
+ [(set (match_operand:ANYF 0 "register_operand")
+ (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
+ (match_operand:ANYF 2 "register_operand")))]
+ "<divide_condition>"
+{
+ if (const_1_operand (operands[1], <MODE>mode))
+ if (!(<recip_condition> && flag_unsafe_math_optimizations))
+ operands[1] = force_reg (<MODE>mode, operands[1]);
+})
-;; On the mips16, we can sometimes split an add of a constant which is
-;; a 4 byte instruction into two adds which are both 2 byte
-;; instructions. There are two cases: one where we are adding a
-;; constant plus a register to another register, and one where we are
-;; simply adding a constant to a register.
+;; These patterns work around the early SB-1 rev2 core "F1" erratum:
+;;
+;; If an mfc1 or dmfc1 happens to access the floating point register
+;; file at the same time a long latency operation (div, sqrt, recip,
+;; sqrt) iterates an intermediate result back through the floating
+;; point register file bypass, then instead returning the correct
+;; register value the mfc1 or dmfc1 operation returns the intermediate
+;; result of the long latency operation.
+;;
+;; The workaround is to insert an unconditional 'mov' from/to the
+;; long latency op destination register.
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (minus:DI (match_dup 0)
- (match_operand:DI 1 "const_int_operand" "")))]
- "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
- && ((INTVAL (operands[1]) > 0x10
- && INTVAL (operands[1]) <= 0x10 + 0x10)
- || (INTVAL (operands[1]) < - 0xf
- && INTVAL (operands[1]) >= - 0xf - 0xf))"
- [(set (match_dup 0) (minus:DI (match_dup 0) (match_dup 1)))
- (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
- "
+(define_insn "*div<mode>3"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
+ (match_operand:ANYF 2 "register_operand" "f")))]
+ "<divide_condition>"
{
- HOST_WIDE_INT val = INTVAL (operands[1]);
+ if (TARGET_FIX_SB1)
+ return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
+ else
+ return "div.<fmt>\t%0,%1,%2";
+}
+ [(set_attr "type" "fdiv")
+ (set_attr "mode" "<UNITMODE>")
+ (set (attr "length")
+ (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
+ (const_int 8)
+ (const_int 4)))])
+
+(define_insn "*recip<mode>3"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
+ (match_operand:ANYF 2 "register_operand" "f")))]
+ "<recip_condition> && flag_unsafe_math_optimizations"
+{
+ if (TARGET_FIX_SB1)
+ return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
+ else
+ return "recip.<fmt>\t%0,%2";
+}
+ [(set_attr "type" "frdiv")
+ (set_attr "mode" "<UNITMODE>")
+ (set (attr "length")
+ (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
+ (const_int 8)
+ (const_int 4)))])
+
+;; VR4120 errata MD(A1): signed division instructions do not work correctly
+;; with negative operands. We use special libgcc functions instead.
+(define_insn_and_split "divmod<mode>4"
+ [(set (match_operand:GPR 0 "register_operand" "=l")
+ (div:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "register_operand" "d")))
+ (set (match_operand:GPR 3 "register_operand" "=d")
+ (mod:GPR (match_dup 1)
+ (match_dup 2)))]
+ "!TARGET_FIX_VR4120"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ rtx hilo;
- if (val >= 0)
+ if (TARGET_64BIT)
{
- operands[1] = GEN_INT (0xf);
- operands[2] = GEN_INT (val - 0xf);
+ hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
+ emit_insn (gen_divmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
+ emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
}
else
{
- operands[1] = GEN_INT (- 0x10);
- operands[2] = GEN_INT (val + 0x10);
+ hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
+ emit_insn (gen_divmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
+ emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
}
-}")
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (minus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "const_int_operand" "")))]
- "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG
- && M16_REG_P (REGNO (operands[1]))
- && REGNO (operands[0]) != REGNO (operands[1])
- && GET_CODE (operands[2]) == CONST_INT
- && ((INTVAL (operands[2]) > 0x8
- && INTVAL (operands[2]) <= 0x8 + 0x10)
- || (INTVAL (operands[2]) < - 0x7
- && INTVAL (operands[2]) >= - 0x7 - 0xf))"
- [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))
- (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 3)))]
- "
+ DONE;
+}
+ [(set_attr "type" "idiv")
+ (set_attr "mode" "<MODE>")
+ (set_attr "length" "8")])
+
+(define_insn_and_split "udivmod<mode>4"
+ [(set (match_operand:GPR 0 "register_operand" "=l")
+ (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "register_operand" "d")))
+ (set (match_operand:GPR 3 "register_operand" "=d")
+ (umod:GPR (match_dup 1)
+ (match_dup 2)))]
+ ""
+ "#"
+ "reload_completed"
+ [(const_int 0)]
{
- HOST_WIDE_INT val = INTVAL (operands[2]);
+ rtx hilo;
- if (val >= 0)
+ if (TARGET_64BIT)
{
- operands[2] = GEN_INT (0x8);
- operands[3] = GEN_INT (val - 0x8);
+ hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
+ emit_insn (gen_udivmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
+ emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
}
else
{
- operands[2] = GEN_INT (- 0x7);
- operands[3] = GEN_INT (val + 0x7);
+ hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
+ emit_insn (gen_udivmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
+ emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
}
-}")
-
-(define_insn "subsi3_internal_2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
- (match_operand:SI 2 "arith_operand" "dI"))))]
- "TARGET_64BIT && !TARGET_MIPS16
- && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
- "*
-{
- return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
- ? \"addu\\t%0,%z1,%n2\"
- : \"subu\\t%0,%z1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d,d")
- (sign_extend:DI (minus:SI (match_operand:SI 1 "register_operand" "0,d,d")
- (match_operand:SI 2 "arith_operand" "I,O,d"))))]
- "TARGET_64BIT && TARGET_MIPS16
- && (GET_CODE (operands[2]) != CONST_INT
- || (INTVAL (operands[2]) != -32768 && INTVAL (operands[2]) != -0x4000))"
- "*
-{
- if (REGNO (operands[0]) == REGNO (operands[1]))
- return \"subu\\t%0,%2\";
- return \"subu\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr_alternative "length"
- [(if_then_else (match_operand:VOID 2 "m16_nsimm8_1" "")
- (const_int 4)
- (const_int 8))
- (if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "")
- (const_int 4)
- (const_int 8))
- (const_int 4)])])
-
-
+ DONE;
+}
+ [(set_attr "type" "idiv")
+ (set_attr "mode" "<MODE>")
+ (set_attr "length" "8")])
+
+(define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>"
+ [(set (match_operand:HILO 0 "register_operand" "=x")
+ (unspec:HILO
+ [(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "register_operand" "d"))]
+ UNSPEC_SET_HILO))]
+ ""
+ { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); }
+ [(set_attr "type" "idiv")
+ (set_attr "mode" "<GPR:MODE>")])
\f
;;
;; ....................
;;
-;; MULTIPLICATION
+;; SQUARE ROOT
;;
;; ....................
-;;
-;; Early Vr4300 silicon has a CPU bug where multiplies with certain
-;; operands may corrupt immediately following multiplies. This is a
-;; simple fix to insert NOPs.
+;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
+;; "*div[sd]f3" comment for details).
-(define_expand "muldf3"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (mult:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "
+(define_insn "sqrt<mode>2"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
+ "<sqrt_condition>"
{
- if (!TARGET_MIPS4300)
- emit_insn (gen_muldf3_internal (operands[0], operands[1], operands[2]));
+ if (TARGET_FIX_SB1)
+ return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
else
- emit_insn (gen_muldf3_r4300 (operands[0], operands[1], operands[2]));
- DONE;
-}")
+ return "sqrt.<fmt>\t%0,%1";
+}
+ [(set_attr "type" "fsqrt")
+ (set_attr "mode" "<UNITMODE>")
+ (set (attr "length")
+ (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
+ (const_int 8)
+ (const_int 4)))])
+
+(define_insn "*rsqrt<mode>a"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
+ (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
+ "<recip_condition> && flag_unsafe_math_optimizations"
+{
+ if (TARGET_FIX_SB1)
+ return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
+ else
+ return "rsqrt.<fmt>\t%0,%2";
+}
+ [(set_attr "type" "frsqrt")
+ (set_attr "mode" "<UNITMODE>")
+ (set (attr "length")
+ (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
+ (const_int 8)
+ (const_int 4)))])
+
+(define_insn "*rsqrt<mode>b"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
+ (match_operand:ANYF 2 "register_operand" "f"))))]
+ "<recip_condition> && flag_unsafe_math_optimizations"
+{
+ if (TARGET_FIX_SB1)
+ return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
+ else
+ return "rsqrt.<fmt>\t%0,%2";
+}
+ [(set_attr "type" "frsqrt")
+ (set_attr "mode" "<UNITMODE>")
+ (set (attr "length")
+ (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
+ (const_int 8)
+ (const_int 4)))])
+\f
+;;
+;; ....................
+;;
+;; ABSOLUTE VALUE
+;;
+;; ....................
-(define_insn "muldf3_internal"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (mult:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_MIPS4300"
- "mul.d\\t%0,%1,%2"
- [(set_attr "type" "fmul")
- (set_attr "mode" "DF")])
+;; Do not use the integer abs macro instruction, since that signals an
+;; exception on -2147483648 (sigh).
-(define_insn "muldf3_r4300"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (mult:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_MIPS4300"
- "*
-{
- output_asm_insn (\"mul.d\\t%0,%1,%2\", operands);
- if (TARGET_4300_MUL_FIX)
- output_asm_insn (\"nop\", operands);
- return \"\";
-}"
- [(set_attr "type" "fmul")
- (set_attr "mode" "DF")
- (set_attr "length" "8")]) ;; mul.d + nop
+;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
+;; invalid; it does not clear their sign bits. We therefore can't use
+;; abs.fmt if the signs of NaNs matter.
+
+(define_insn "abs<mode>2"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
+ "!HONOR_NANS (<MODE>mode)"
+ "abs.<fmt>\t%0,%1"
+ [(set_attr "type" "fabs")
+ (set_attr "mode" "<UNITMODE>")])
+\f
+;;
+;; ...................
+;;
+;; Count leading zeroes.
+;;
+;; ...................
+;;
-(define_expand "mulsf3"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (mult:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "
-{
- if (!TARGET_MIPS4300)
- emit_insn( gen_mulsf3_internal (operands[0], operands[1], operands[2]));
- else
- emit_insn( gen_mulsf3_r4300 (operands[0], operands[1], operands[2]));
- DONE;
-}")
+(define_insn "clz<mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
+ "ISA_HAS_CLZ_CLO"
+ "<d>clz\t%0,%1"
+ [(set_attr "type" "clz")
+ (set_attr "mode" "<MODE>")])
-(define_insn "mulsf3_internal"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (mult:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && !TARGET_MIPS4300"
- "mul.s\\t%0,%1,%2"
- [(set_attr "type" "fmul")
- (set_attr "mode" "SF")])
+;;
+;; ...................
+;;
+;; Count number of set bits.
+;;
+;; ...................
+;;
-(define_insn "mulsf3_r4300"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (mult:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_MIPS4300"
- "*
-{
- output_asm_insn (\"mul.s\\t%0,%1,%2\", operands);
- if (TARGET_4300_MUL_FIX)
- output_asm_insn (\"nop\", operands);
- return \"\";
-}"
- [(set_attr "type" "fmul")
- (set_attr "mode" "SF")
- (set_attr "length" "8")]) ;; mul.s + nop
+(define_insn "popcount<mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (popcount:GPR (match_operand:GPR 1 "register_operand" "d")))]
+ "ISA_HAS_POP"
+ "<d>pop\t%0,%1"
+ [(set_attr "type" "pop")
+ (set_attr "mode" "<MODE>")])
+\f
+;;
+;; ....................
+;;
+;; NEGATION and ONE'S COMPLEMENT
+;;
+;; ....................
+(define_insn "negsi2"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (neg:SI (match_operand:SI 1 "register_operand" "d")))]
+ ""
+{
+ if (TARGET_MIPS16)
+ return "neg\t%0,%1";
+ else
+ return "subu\t%0,%.,%1";
+}
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")])
-;; ??? The R4000 (only) has a cpu bug. If a double-word shift executes while
-;; a multiply is in progress, it may give an incorrect result. Avoid
-;; this by keeping the mflo with the mult on the R4000.
+(define_insn "negdi2"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (neg:DI (match_operand:DI 1 "register_operand" "d")))]
+ "TARGET_64BIT && !TARGET_MIPS16"
+ "dsubu\t%0,%.,%1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "DI")])
-(define_expand "mulsi3"
- [(set (match_operand:SI 0 "register_operand" "=l")
- (mult:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (clobber (match_scratch:SI 3 "=h"))
- (clobber (match_scratch:SI 4 "=a"))]
+;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
+;; invalid; it does not flip their sign bit. We therefore can't use
+;; neg.fmt if the signs of NaNs matter.
+
+(define_insn "neg<mode>2"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
+ "!HONOR_NANS (<MODE>mode)"
+ "neg.<fmt>\t%0,%1"
+ [(set_attr "type" "fneg")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "one_cmpl<mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
""
- "
{
- if (GENERATE_MULT3_SI || TARGET_MAD)
- emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
- else if (!TARGET_MIPS4000 || TARGET_MIPS16)
- emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
+ if (TARGET_MIPS16)
+ return "not\t%0,%1";
else
- emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
- DONE;
-}")
+ return "nor\t%0,%.,%1";
+}
+ [(set_attr "type" "logical")
+ (set_attr "mode" "<MODE>")])
+\f
+;;
+;; ....................
+;;
+;; LOGICAL
+;;
+;; ....................
+;;
+
+;; Many of these instructions use trivial define_expands, because we
+;; want to use a different set of constraints when TARGET_MIPS16.
-(define_insn "mulsi3_mult3"
- [(set (match_operand:SI 0 "register_operand" "=d,l")
- (mult:SI (match_operand:SI 1 "register_operand" "d,d")
- (match_operand:SI 2 "register_operand" "d,d")))
- (clobber (match_scratch:SI 3 "=h,h"))
- (clobber (match_scratch:SI 4 "=l,X"))
- (clobber (match_scratch:SI 5 "=a,a"))]
- "GENERATE_MULT3_SI
- || TARGET_MAD"
- "*
+(define_expand "and<mode>3"
+ [(set (match_operand:GPR 0 "register_operand")
+ (and:GPR (match_operand:GPR 1 "register_operand")
+ (match_operand:GPR 2 "uns_arith_operand")))]
+ ""
{
- if (which_alternative == 1)
- return \"mult\\t%1,%2\";
- if (TARGET_MAD
- || mips_isa == 32
- || mips_isa == 64)
- return \"mul\\t%0,%1,%2\";
- return \"mult\\t%0,%1,%2\";
-}"
- [(set_attr "type" "imul")
- (set_attr "mode" "SI")])
+ if (TARGET_MIPS16)
+ operands[2] = force_reg (<MODE>mode, operands[2]);
+})
-(define_insn "mulsi3_internal"
- [(set (match_operand:SI 0 "register_operand" "=l")
- (mult:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (clobber (match_scratch:SI 3 "=h"))
- (clobber (match_scratch:SI 4 "=a"))]
- "!TARGET_MIPS4000 || TARGET_MIPS16"
- "mult\\t%1,%2"
- [(set_attr "type" "imul")
- (set_attr "mode" "SI")])
+(define_insn "*and<mode>3"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (and:GPR (match_operand:GPR 1 "register_operand" "%d,d")
+ (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
+ "!TARGET_MIPS16"
+ "@
+ and\t%0,%1,%2
+ andi\t%0,%1,%x2"
+ [(set_attr "type" "logical")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "*and<mode>3_mips16"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (and:GPR (match_operand:GPR 1 "register_operand" "%0")
+ (match_operand:GPR 2 "register_operand" "d")))]
+ "TARGET_MIPS16"
+ "and\t%0,%2"
+ [(set_attr "type" "logical")
+ (set_attr "mode" "<MODE>")])
+
+(define_expand "ior<mode>3"
+ [(set (match_operand:GPR 0 "register_operand")
+ (ior:GPR (match_operand:GPR 1 "register_operand")
+ (match_operand:GPR 2 "uns_arith_operand")))]
+ ""
+{
+ if (TARGET_MIPS16)
+ operands[2] = force_reg (<MODE>mode, operands[2]);
+})
-(define_insn "mulsi3_r4000"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (mult:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (clobber (match_scratch:SI 3 "=h"))
- (clobber (match_scratch:SI 4 "=l"))
- (clobber (match_scratch:SI 5 "=a"))]
- "TARGET_MIPS4000 && !TARGET_MIPS16"
- "*
-{
- rtx xoperands[10];
-
- xoperands[0] = operands[0];
- xoperands[1] = gen_rtx_REG (SImode, LO_REGNUM);
-
- output_asm_insn (\"mult\\t%1,%2\", operands);
- output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
- return \"\";
-}"
- [(set_attr "type" "imul")
- (set_attr "mode" "SI")
- (set_attr "length" "12")]) ;; mult + mflo + delay
+(define_insn "*ior<mode>3"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
+ (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
+ "!TARGET_MIPS16"
+ "@
+ or\t%0,%1,%2
+ ori\t%0,%1,%x2"
+ [(set_attr "type" "logical")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "*ior<mode>3_mips16"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
+ (match_operand:GPR 2 "register_operand" "d")))]
+ "TARGET_MIPS16"
+ "or\t%0,%2"
+ [(set_attr "type" "logical")
+ (set_attr "mode" "<MODE>")])
+
+(define_expand "xor<mode>3"
+ [(set (match_operand:GPR 0 "register_operand")
+ (xor:GPR (match_operand:GPR 1 "register_operand")
+ (match_operand:GPR 2 "uns_arith_operand")))]
+ ""
+ "")
-;; Multiply-accumulate patterns
+(define_insn ""
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
+ (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
+ "!TARGET_MIPS16"
+ "@
+ xor\t%0,%1,%2
+ xori\t%0,%1,%x2"
+ [(set_attr "type" "logical")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn ""
+ [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
+ (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
+ (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
+ "TARGET_MIPS16"
+ "@
+ xor\t%0,%2
+ cmpi\t%1,%2
+ cmp\t%1,%2"
+ [(set_attr "type" "logical,arith,arith")
+ (set_attr "mode" "<MODE>")
+ (set_attr_alternative "length"
+ [(const_int 4)
+ (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
+ (const_int 4)
+ (const_int 8))
+ (const_int 4)])])
-;; For processors that can copy the output to a general register:
+(define_insn "*nor<mode>3"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
+ (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
+ "!TARGET_MIPS16"
+ "nor\t%0,%1,%2"
+ [(set_attr "type" "logical")
+ (set_attr "mode" "<MODE>")])
+\f
;;
-;; The all-d alternative is needed because the combiner will find this
-;; pattern and then register alloc/reload will move registers around to
-;; make them fit, and we don't want to trigger unnecessary loads to LO.
+;; ....................
;;
-;; The last alternative should be made slightly less desirable, but adding
-;; "?" to the constraint is too strong, and causes values to be loaded into
-;; LO even when that's more costly. For now, using "*d" mostly does the
-;; trick.
-(define_insn "*mul_acc_si"
- [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
- (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
- (match_operand:SI 2 "register_operand" "d,d,d"))
- (match_operand:SI 3 "register_operand" "0,l,*d")))
- (clobber (match_scratch:SI 4 "=h,h,h"))
- (clobber (match_scratch:SI 5 "=X,3,l"))
- (clobber (match_scratch:SI 6 "=a,a,a"))
- (clobber (match_scratch:SI 7 "=X,X,d"))]
- "(TARGET_MIPS3900
- || ISA_HAS_MADD_MSUB)
- && !TARGET_MIPS16"
- "*
-{
- static const char *const madd[] = { \"madd\\t%1,%2\", \"madd\\t%0,%1,%2\" };
- if (which_alternative == 2)
- return \"#\";
- if (ISA_HAS_MADD_MSUB && which_alternative != 0)
- return \"#\";
- return madd[which_alternative];
-}"
- [(set_attr "type" "imul,imul,multi")
- (set_attr "mode" "SI")
- (set_attr "length" "4,4,8")])
-
-;; Split the above insn if we failed to get LO allocated.
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "register_operand" ""))
- (match_operand:SI 3 "register_operand" "")))
- (clobber (match_scratch:SI 4 ""))
- (clobber (match_scratch:SI 5 ""))
- (clobber (match_scratch:SI 6 ""))
- (clobber (match_scratch:SI 7 ""))]
- "reload_completed && !TARGET_DEBUG_D_MODE
- && GP_REG_P (true_regnum (operands[0]))
- && GP_REG_P (true_regnum (operands[3]))"
- [(parallel [(set (match_dup 7)
- (mult:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 4))
- (clobber (match_dup 5))
- (clobber (match_dup 6))])
- (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 3)))]
- "")
-
-;; Splitter to copy result of MADD to a general register
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "register_operand" ""))
- (match_operand:SI 3 "register_operand" "")))
- (clobber (match_scratch:SI 4 ""))
- (clobber (match_scratch:SI 5 ""))
- (clobber (match_scratch:SI 6 ""))
- (clobber (match_scratch:SI 7 ""))]
- "reload_completed && !TARGET_DEBUG_D_MODE
- && GP_REG_P (true_regnum (operands[0]))
- && true_regnum (operands[3]) == LO_REGNUM"
- [(parallel [(set (match_dup 3)
- (plus:SI (mult:SI (match_dup 1) (match_dup 2))
- (match_dup 3)))
- (clobber (match_dup 4))
- (clobber (match_dup 5))
- (clobber (match_dup 6))
- (clobber (match_dup 7))])
- (set (match_dup 0) (match_dup 3))]
- "")
+;; TRUNCATION
+;;
+;; ....................
-(define_insn "*mul_sub_si"
- [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
- (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
- (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
- (match_operand:SI 3 "register_operand" "d,d,d"))))
- (clobber (match_scratch:SI 4 "=h,h,h"))
- (clobber (match_scratch:SI 5 "=X,3,l"))
- (clobber (match_scratch:SI 6 "=a,a,a"))
- (clobber (match_scratch:SI 7 "=X,X,d"))]
- "ISA_HAS_MADD_MSUB"
- "*
-{
- if (which_alternative != 0)
- return \"#\";
- return \"msub\\t%2,%3\";
-}"
- [(set_attr "type" "imul,imul,multi")
- (set_attr "mode" "SI")
- (set_attr "length" "4,8,8")])
-;; Split the above insn if we failed to get LO allocated.
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (minus:SI (match_operand:SI 1 "register_operand" "")
- (mult:SI (match_operand:SI 2 "register_operand" "")
- (match_operand:SI 3 "register_operand" ""))))
- (clobber (match_scratch:SI 4 ""))
- (clobber (match_scratch:SI 5 ""))
- (clobber (match_scratch:SI 6 ""))
- (clobber (match_scratch:SI 7 ""))]
- "reload_completed && !TARGET_DEBUG_D_MODE
- && GP_REG_P (true_regnum (operands[0]))
- && GP_REG_P (true_regnum (operands[1]))"
- [(parallel [(set (match_dup 7)
- (mult:SI (match_dup 2) (match_dup 3)))
- (clobber (match_dup 4))
- (clobber (match_dup 5))
- (clobber (match_dup 6))])
- (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 7)))]
- "")
-;; Splitter to copy result of MSUB to a general register
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (minus:SI (match_operand:SI 1 "register_operand" "")
- (mult:SI (match_operand:SI 2 "register_operand" "")
- (match_operand:SI 3 "register_operand" ""))))
- (clobber (match_scratch:SI 4 ""))
- (clobber (match_scratch:SI 5 ""))
- (clobber (match_scratch:SI 6 ""))
- (clobber (match_scratch:SI 7 ""))]
- "reload_completed && !TARGET_DEBUG_D_MODE
- && GP_REG_P (true_regnum (operands[0]))
- && true_regnum (operands[1]) == LO_REGNUM"
- [(parallel [(set (match_dup 1)
- (minus:SI (match_dup 1)
- (mult:SI (match_dup 2) (match_dup 3))))
- (clobber (match_dup 4))
- (clobber (match_dup 5))
- (clobber (match_dup 6))
- (clobber (match_dup 7))])
- (set (match_dup 0) (match_dup 1))]
- "")
+(define_insn "truncdfsf2"
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "cvt.s.d\t%0,%1"
+ [(set_attr "type" "fcvt")
+ (set_attr "cnv_mode" "D2S")
+ (set_attr "mode" "SF")])
+;; Integer truncation patterns. Truncating SImode values to smaller
+;; modes is a no-op, as it is for most other GCC ports. Truncating
+;; DImode values to SImode is not a no-op for TARGET_64BIT since we
+;; need to make sure that the lower 32 bits are properly sign-extended
+;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
+;; smaller than SImode is equivalent to two separate truncations:
+;;
+;; A B
+;; DI ---> HI == DI ---> SI ---> HI
+;; DI ---> QI == DI ---> SI ---> QI
+;;
+;; Step A needs a real instruction but step B does not.
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (minus:SI (match_operand:SI 1 "register_operand" "")
- (mult:SI (match_operand:SI 2 "register_operand" "")
- (match_operand:SI 3 "register_operand" ""))))
- (clobber (match_scratch:SI 4 ""))
- (clobber (match_scratch:SI 5 ""))
- (clobber (match_scratch:SI 6 ""))
- (clobber (match_scratch:SI 7 ""))]
- "reload_completed && !TARGET_DEBUG_D_MODE
- && GP_REG_P (true_regnum (operands[0]))
- && GP_REG_P (true_regnum (operands[1]))"
- [(parallel [(set (match_dup 7)
- (mult:SI (match_dup 2) (match_dup 3)))
- (clobber (match_dup 4))
- (clobber (match_dup 5))
- (clobber (match_dup 6))])
- (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 7)))]
- "")
+(define_insn "truncdisi2"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
+ (truncate:SI (match_operand:DI 1 "register_operand" "d,d")))]
+ "TARGET_64BIT"
+ "@
+ sll\t%0,%1,0
+ sw\t%1,%0"
+ [(set_attr "move_type" "sll0,store")
+ (set_attr "mode" "SI")])
-(define_expand "muldi3"
- [(set (match_operand:DI 0 "register_operand" "=l")
- (mult:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "register_operand" "d")))
- (clobber (match_scratch:DI 3 "=h"))
- (clobber (match_scratch:DI 4 "=a"))]
+(define_insn "truncdihi2"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
+ (truncate:HI (match_operand:DI 1 "register_operand" "d,d")))]
"TARGET_64BIT"
+ "@
+ sll\t%0,%1,0
+ sh\t%1,%0"
+ [(set_attr "move_type" "sll0,store")
+ (set_attr "mode" "SI")])
- "
-{
- if (GENERATE_MULT3_DI || TARGET_MIPS4000 || TARGET_MIPS16)
- emit_insn (gen_muldi3_internal2 (operands[0], operands[1], operands[2]));
- else
- emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
- DONE;
-}")
+(define_insn "truncdiqi2"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
+ (truncate:QI (match_operand:DI 1 "register_operand" "d,d")))]
+ "TARGET_64BIT"
+ "@
+ sll\t%0,%1,0
+ sb\t%1,%0"
+ [(set_attr "move_type" "sll0,store")
+ (set_attr "mode" "SI")])
-;; Don't accept both operands using se_register_operand, because if
-;; both operands are sign extended we would prefer to use mult in the
-;; mulsidi3 pattern. Commutativity should permit either operand to be
-;; sign extended.
-
-(define_insn "muldi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=l")
- (mult:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "register_operand" "d")))
- (clobber (match_scratch:DI 3 "=h"))
- (clobber (match_scratch:DI 4 "=a"))]
- "TARGET_64BIT && !TARGET_MIPS4000 && !TARGET_MIPS16"
- "dmult\\t%1,%2"
- [(set_attr "type" "imul")
- (set_attr "mode" "DI")])
+;; Combiner patterns to optimize shift/truncate combinations.
-(define_insn "muldi3_internal2"
+(define_insn "*ashr_trunc<mode>"
+ [(set (match_operand:SUBDI 0 "register_operand" "=d")
+ (truncate:SUBDI
+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
+ (match_operand:DI 2 "const_arith_operand" ""))))]
+ "TARGET_64BIT && !TARGET_MIPS16 && IN_RANGE (INTVAL (operands[2]), 32, 63)"
+ "dsra\t%0,%1,%2"
+ [(set_attr "type" "shift")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "*lshr32_trunc<mode>"
+ [(set (match_operand:SUBDI 0 "register_operand" "=d")
+ (truncate:SUBDI
+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
+ (const_int 32))))]
+ "TARGET_64BIT && !TARGET_MIPS16"
+ "dsra\t%0,%1,32"
+ [(set_attr "type" "shift")
+ (set_attr "mode" "<MODE>")])
+
+;; Logical shift by 32 or more results in proper SI values so
+;; truncation is removed by the middle end.
+(define_insn "*<optab>_trunc<mode>_exts"
+ [(set (match_operand:SUBDI 0 "register_operand" "=d")
+ (truncate:SUBDI
+ (any_shiftrt:DI (match_operand:DI 1 "register_operand" "d")
+ (match_operand:DI 2 "const_arith_operand" ""))))]
+ "ISA_HAS_EXTS && TARGET_64BIT && UINTVAL (operands[2]) < 32"
+ "exts\t%0,%1,%2,31"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "<MODE>")])
+
+;; Combiner patterns for truncate/sign_extend combinations. The SI versions
+;; use the shift/truncate patterns above.
+
+(define_insn_and_split "*extenddi_truncate<mode>"
[(set (match_operand:DI 0 "register_operand" "=d")
- (mult:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "register_operand" "d")))
- (clobber (match_scratch:DI 3 "=h"))
- (clobber (match_scratch:DI 4 "=l"))
- (clobber (match_scratch:DI 5 "=a"))]
- "TARGET_64BIT && (GENERATE_MULT3_DI || TARGET_MIPS4000 || TARGET_MIPS16)"
- "*
-{
- if (GENERATE_MULT3_DI)
- output_asm_insn (\"dmult\\t%0,%1,%2\", operands);
- else
- {
- rtx xoperands[10];
+ (sign_extend:DI
+ (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
+ "TARGET_64BIT && !TARGET_MIPS16"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 2)
+ (ashift:DI (match_dup 1)
+ (match_dup 3)))
+ (set (match_dup 0)
+ (ashiftrt:DI (match_dup 2)
+ (match_dup 3)))]
+{
+ operands[2] = gen_lowpart (DImode, operands[0]);
+ operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
+})
- xoperands[0] = operands[0];
- xoperands[1] = gen_rtx_REG (DImode, LO_REGNUM);
+(define_insn_and_split "*extendsi_truncate<mode>"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (sign_extend:SI
+ (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
+ "TARGET_64BIT && !TARGET_MIPS16"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 2)
+ (ashift:DI (match_dup 1)
+ (match_dup 3)))
+ (set (match_dup 0)
+ (truncate:SI (ashiftrt:DI (match_dup 2)
+ (match_dup 3))))]
+{
+ operands[2] = gen_lowpart (DImode, operands[0]);
+ operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
+})
- output_asm_insn (\"dmult\\t%1,%2\", operands);
- output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
- }
- return \"\";
-}"
- [(set_attr "type" "imul")
- (set_attr "mode" "DI")
- (set (attr "length")
- (if_then_else (ne (symbol_ref "GENERATE_MULT3_DI") (const_int 0))
- (const_int 4)
- (const_int 12)))]) ;; mult + mflo + delay
+;; Combiner patterns to optimize truncate/zero_extend combinations.
-;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
+(define_insn "*zero_extend<mode>_trunchi"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (zero_extend:GPR
+ (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
+ "TARGET_64BIT && !TARGET_MIPS16"
+ "andi\t%0,%1,0xffff"
+ [(set_attr "type" "logical")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "*zero_extend<mode>_truncqi"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (zero_extend:GPR
+ (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
+ "TARGET_64BIT && !TARGET_MIPS16"
+ "andi\t%0,%1,0xff"
+ [(set_attr "type" "logical")
+ (set_attr "mode" "<MODE>")])
-(define_expand "mulsidi3"
- [(set (match_operand:DI 0 "register_operand" "=x")
- (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
- (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
- ""
- "
-{
- rtx dummy = gen_rtx (SIGN_EXTEND, DImode, const0_rtx);
- if (TARGET_64BIT)
- emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2],
- dummy, dummy));
- else
- emit_insn (gen_mulsidi3_internal (operands[0], operands[1], operands[2],
- dummy, dummy));
- DONE;
-}")
+(define_insn ""
+ [(set (match_operand:HI 0 "register_operand" "=d")
+ (zero_extend:HI
+ (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
+ "TARGET_64BIT && !TARGET_MIPS16"
+ "andi\t%0,%1,0xff"
+ [(set_attr "type" "logical")
+ (set_attr "mode" "HI")])
+\f
+;;
+;; ....................
+;;
+;; ZERO EXTENSION
+;;
+;; ....................
-(define_expand "umulsidi3"
- [(set (match_operand:DI 0 "register_operand" "=x")
- (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
- (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
- ""
- "
-{
- rtx dummy = gen_rtx (ZERO_EXTEND, DImode, const0_rtx);
- if (TARGET_64BIT)
- emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2],
- dummy, dummy));
- else
- emit_insn (gen_mulsidi3_internal (operands[0], operands[1], operands[2],
- dummy, dummy));
- DONE;
-}")
+;; Extension insns.
-(define_insn "mulsidi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=x")
- (mult:DI (match_operator:DI 3 "extend_operator"
- [(match_operand:SI 1 "register_operand" "d")])
- (match_operator:DI 4 "extend_operator"
- [(match_operand:SI 2 "register_operand" "d")])))
- (clobber (match_scratch:SI 5 "=a"))]
- "!TARGET_64BIT && GET_CODE (operands[3]) == GET_CODE (operands[4])"
- "*
-{
- if (GET_CODE (operands[3]) == SIGN_EXTEND)
- return \"mult\\t%1,%2\";
- return \"multu\\t%1,%2\";
-}"
- [(set_attr "type" "imul")
- (set_attr "mode" "SI")])
+(define_insn_and_split "zero_extendsidi2"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
+ "TARGET_64BIT"
+ "@
+ #
+ lwu\t%0,%1"
+ "&& reload_completed && REG_P (operands[1])"
+ [(set (match_dup 0)
+ (ashift:DI (match_dup 1) (const_int 32)))
+ (set (match_dup 0)
+ (lshiftrt:DI (match_dup 0) (const_int 32)))]
+ { operands[1] = gen_lowpart (DImode, operands[1]); }
+ [(set_attr "move_type" "shift_shift,load")
+ (set_attr "mode" "DI")])
-(define_insn "mulsidi3_64bit"
- [(set (match_operand:DI 0 "register_operand" "=a")
- (mult:DI (match_operator:DI 3 "extend_operator"
- [(match_operand:SI 1 "register_operand" "d")])
- (match_operator:DI 4 "extend_operator"
- [(match_operand:SI 2 "register_operand" "d")])))
- (clobber (match_scratch:DI 5 "=l"))
- (clobber (match_scratch:DI 6 "=h"))]
- "TARGET_64BIT && GET_CODE (operands[3]) == GET_CODE (operands[4])"
- "*
-{
- if (GET_CODE (operands[3]) == SIGN_EXTEND)
- return \"mult\\t%1,%2\";
- return \"multu\\t%1,%2\";
-}"
- [(set_attr "type" "imul")
- (set_attr "mode" "SI")])
+;; Combine is not allowed to convert this insn into a zero_extendsidi2
+;; because of TRULY_NOOP_TRUNCATION.
-;; _highpart patterns
-(define_expand "smulsi3_highpart"
- [(set (match_operand:SI 0 "register_operand" "=h")
- (truncate:SI
- (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
- (sign_extend:DI (match_operand:SI 2 "register_operand" "d")))
- (const_int 32))))]
- ""
- "
+(define_insn_and_split "*clear_upper32"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,W")
+ (const_int 4294967295)))]
+ "TARGET_64BIT"
{
- rtx dummy = gen_rtx (SIGN_EXTEND, DImode, const0_rtx);
- rtx dummy2 = gen_rtx_LSHIFTRT (DImode, const0_rtx, const0_rtx);
-#ifndef NO_MD_PROTOTYPES
- rtx (*genfn) PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
-#else
- rtx (*genfn) ();
-#endif
- genfn = gen_xmulsi3_highpart_internal;
- emit_insn ((*genfn) (operands[0], operands[1], operands[2], dummy,
- dummy, dummy2));
- DONE;
-}")
+ if (which_alternative == 0)
+ return "#";
-(define_expand "umulsi3_highpart"
- [(set (match_operand:SI 0 "register_operand" "=h")
- (truncate:SI
- (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
- (zero_extend:DI (match_operand:SI 2 "register_operand" "d")))
- (const_int 32))))]
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ return "lwu\t%0,%1";
+}
+ "&& reload_completed && REG_P (operands[1])"
+ [(set (match_dup 0)
+ (ashift:DI (match_dup 1) (const_int 32)))
+ (set (match_dup 0)
+ (lshiftrt:DI (match_dup 0) (const_int 32)))]
""
- "
-{
- rtx dummy = gen_rtx (ZERO_EXTEND, DImode, const0_rtx);
- rtx dummy2 = gen_rtx_LSHIFTRT (DImode, const0_rtx, const0_rtx);
-#ifndef NO_MD_PROTOTYPES
- rtx (*genfn) PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
-#else
- rtx (*genfn) ();
-#endif
- genfn = gen_xmulsi3_highpart_internal;
- emit_insn ((*genfn) (operands[0], operands[1], operands[2], dummy,
- dummy, dummy2));
- DONE;
-}")
-
-(define_insn "xmulsi3_highpart_internal"
- [(set (match_operand:SI 0 "register_operand" "=h")
- (truncate:SI
- (match_operator:DI 5 "highpart_shift_operator"
- [(mult:DI (match_operator:DI 3 "extend_operator"
- [(match_operand:SI 1 "register_operand" "d")])
- (match_operator:DI 4 "extend_operator"
- [(match_operand:SI 2 "register_operand" "d")]))
- (const_int 32)])))
- (clobber (match_scratch:SI 6 "=l"))
- (clobber (match_scratch:SI 7 "=a"))]
- "GET_CODE (operands[3]) == GET_CODE (operands[4])"
- "*
-{
- if (GET_CODE (operands[3]) == SIGN_EXTEND)
- return \"mult\\t%1,%2\";
- else
- return \"multu\\t%1,%2\";
-}"
- [(set_attr "type" "imul")
- (set_attr "mode" "SI")])
-
-(define_insn "smuldi3_highpart"
- [(set (match_operand:DI 0 "register_operand" "=h")
- (truncate:DI
- (lshiftrt:TI (mult:TI (sign_extend:TI (match_operand:DI 1 "se_register_operand" "d"))
- (sign_extend:TI (match_operand:DI 2 "se_register_operand" "d")))
- (const_int 64))))
- (clobber (match_scratch:DI 3 "=l"))
- (clobber (match_scratch:DI 4 "=a"))]
- "TARGET_64BIT"
- "dmult\\t%1,%2"
- [(set_attr "type" "imul")
- (set_attr "mode" "DI")])
+ [(set_attr "move_type" "shift_shift,load")
+ (set_attr "mode" "DI")])
-(define_insn "umuldi3_highpart"
- [(set (match_operand:DI 0 "register_operand" "=h")
- (truncate:DI
- (lshiftrt:TI (mult:TI (zero_extend:TI (match_operand:DI 1 "se_register_operand" "d"))
- (zero_extend:TI (match_operand:DI 2 "se_register_operand" "d")))
- (const_int 64))))
- (clobber (match_scratch:DI 3 "=l"))
- (clobber (match_scratch:DI 4 "=a"))]
- "TARGET_64BIT"
- "dmultu\\t%1,%2"
- [(set_attr "type" "imul")
- (set_attr "mode" "DI")])
+(define_expand "zero_extend<SHORT:mode><GPR:mode>2"
+ [(set (match_operand:GPR 0 "register_operand")
+ (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
+ ""
+{
+ if (TARGET_MIPS16 && !GENERATE_MIPS16E
+ && !memory_operand (operands[1], <SHORT:MODE>mode))
+ {
+ emit_insn (gen_and<GPR:mode>3 (operands[0],
+ gen_lowpart (<GPR:MODE>mode, operands[1]),
+ force_reg (<GPR:MODE>mode,
+ GEN_INT (<SHORT:mask>))));
+ DONE;
+ }
+})
-;; The R4650 supports a 32 bit multiply/ 64 bit accumulate
-;; instruction. The HI/LO registers are used as a 64 bit accumulator.
+(define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (zero_extend:GPR
+ (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
+ "!TARGET_MIPS16"
+ "@
+ andi\t%0,%1,<SHORT:mask>
+ l<SHORT:size>u\t%0,%1"
+ [(set_attr "move_type" "andi,load")
+ (set_attr "mode" "<GPR:MODE>")])
+
+(define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
+ "GENERATE_MIPS16E"
+ "ze<SHORT:size>\t%0"
+ ;; This instruction is effectively a special encoding of ANDI.
+ [(set_attr "move_type" "andi")
+ (set_attr "mode" "<GPR:MODE>")])
+
+(define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
+ "TARGET_MIPS16"
+ "l<SHORT:size>u\t%0,%1"
+ [(set_attr "move_type" "load")
+ (set_attr "mode" "<GPR:MODE>")])
-(define_insn "madsi"
- [(set (match_operand:SI 0 "register_operand" "+l")
- (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d"))
- (match_dup 0)))
- (clobber (match_scratch:SI 3 "=h"))
- (clobber (match_scratch:SI 4 "=a"))]
- "TARGET_MAD"
- "mad\\t%1,%2"
- [(set_attr "type" "imul")
- (set_attr "mode" "SI")])
+(define_expand "zero_extendqihi2"
+ [(set (match_operand:HI 0 "register_operand")
+ (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
+ ""
+{
+ if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
+ {
+ emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
+ operands[1]));
+ DONE;
+ }
+})
-(define_insn "*mul_acc_di"
- [(set (match_operand:DI 0 "register_operand" "+x")
- (plus:DI (mult:DI (match_operator:DI 3 "extend_operator"
- [(match_operand:SI 1 "register_operand" "d")])
- (match_operator:DI 4 "extend_operator"
- [(match_operand:SI 2 "register_operand" "d")]))
- (match_dup 0)))
- (clobber (match_scratch:SI 5 "=a"))]
- "TARGET_MAD
- && ! TARGET_64BIT
- && GET_CODE (operands[3]) == GET_CODE (operands[4])"
- "*
-{
- if (GET_CODE (operands[3]) == SIGN_EXTEND)
- return \"mad\\t%1,%2\";
- else
- return \"madu\\t%1,%2\";
-}"
- [(set_attr "type" "imul")
- (set_attr "mode" "SI")])
+(define_insn "*zero_extendqihi2"
+ [(set (match_operand:HI 0 "register_operand" "=d,d")
+ (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
+ "!TARGET_MIPS16"
+ "@
+ andi\t%0,%1,0x00ff
+ lbu\t%0,%1"
+ [(set_attr "move_type" "andi,load")
+ (set_attr "mode" "HI")])
-(define_insn "*mul_acc_64bit_di"
- [(set (match_operand:DI 0 "register_operand" "+a")
- (plus:DI (mult:DI (match_operator:DI 3 "extend_operator"
- [(match_operand:SI 1 "register_operand" "d")])
- (match_operator:DI 4 "extend_operator"
- [(match_operand:SI 2 "register_operand" "d")]))
- (match_dup 0)))
- (clobber (match_scratch:SI 5 "=h"))
- (clobber (match_scratch:SI 6 "=l"))]
- "TARGET_MAD
- && TARGET_64BIT
- && GET_CODE (operands[3]) == GET_CODE (operands[4])"
- "*
-{
- if (GET_CODE (operands[3]) == SIGN_EXTEND)
- return \"mad\\t%1,%2\";
- else
- return \"madu\\t%1,%2\";
-}"
- [(set_attr "type" "imul")
- (set_attr "mode" "SI")])
+(define_insn "*zero_extendqihi2_mips16"
+ [(set (match_operand:HI 0 "register_operand" "=d")
+ (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
+ "TARGET_MIPS16"
+ "lbu\t%0,%1"
+ [(set_attr "move_type" "load")
+ (set_attr "mode" "HI")])
+\f
+;;
+;; ....................
+;;
+;; SIGN EXTENSION
+;;
+;; ....................
-;; Floating point multiply accumulate instructions.
+;; Extension insns.
+;; Those for integer source operand are ordered widest source type first.
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f")
- (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f"))
- (match_operand:DF 3 "register_operand" "f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
- "madd.d\\t%0,%3,%1,%2"
- [(set_attr "type" "fmadd")
- (set_attr "mode" "DF")])
+;; When TARGET_64BIT, all SImode integer registers should already be in
+;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
+;; therefore get rid of register->register instructions if we constrain
+;; the source to be in the same register as the destination.
+;;
+;; The register alternative has type "arith" so that the pre-reload
+;; scheduler will treat it as a move. This reflects what happens if
+;; the register alternative needs a reload.
+(define_insn_and_split "extendsidi2"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
+ "TARGET_64BIT"
+ "@
+ #
+ lw\t%0,%1"
+ "&& reload_completed && register_operand (operands[1], VOIDmode)"
+ [(const_int 0)]
+{
+ emit_note (NOTE_INSN_DELETED);
+ DONE;
+}
+ [(set_attr "move_type" "move,load")
+ (set_attr "mode" "DI")])
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f"))
- (match_operand:SF 3 "register_operand" "f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
- "madd.s\\t%0,%3,%1,%2"
- [(set_attr "type" "fmadd")
- (set_attr "mode" "SF")])
+(define_expand "extend<SHORT:mode><GPR:mode>2"
+ [(set (match_operand:GPR 0 "register_operand")
+ (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
+ "")
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f")
- (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f"))
- (match_operand:DF 3 "register_operand" "f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
- "msub.d\\t%0,%3,%1,%2"
- [(set_attr "type" "fmadd")
- (set_attr "mode" "DF")])
+(define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
+ "GENERATE_MIPS16E"
+ "@
+ se<SHORT:size>\t%0
+ l<SHORT:size>\t%0,%1"
+ [(set_attr "move_type" "signext,load")
+ (set_attr "mode" "<GPR:MODE>")])
+
+(define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (sign_extend:GPR
+ (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
+ "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
+ "@
+ #
+ l<SHORT:size>\t%0,%1"
+ "&& reload_completed && REG_P (operands[1])"
+ [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
+ (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
+{
+ operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
+ operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
+ - GET_MODE_BITSIZE (<SHORT:MODE>mode));
+}
+ [(set_attr "move_type" "shift_shift,load")
+ (set_attr "mode" "<GPR:MODE>")])
+
+(define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (sign_extend:GPR
+ (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
+ "ISA_HAS_SEB_SEH"
+ "@
+ se<SHORT:size>\t%0,%1
+ l<SHORT:size>\t%0,%1"
+ [(set_attr "move_type" "signext,load")
+ (set_attr "mode" "<GPR:MODE>")])
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f"))
- (match_operand:SF 3 "register_operand" "f")))]
+(define_expand "extendqihi2"
+ [(set (match_operand:HI 0 "register_operand")
+ (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
+ "")
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
- "msub.s\\t%0,%3,%1,%2"
- [(set_attr "type" "fmadd")
- (set_attr "mode" "SF")])
+(define_insn "*extendqihi2_mips16e"
+ [(set (match_operand:HI 0 "register_operand" "=d,d")
+ (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
+ "GENERATE_MIPS16E"
+ "@
+ seb\t%0
+ lb\t%0,%1"
+ [(set_attr "move_type" "signext,load")
+ (set_attr "mode" "SI")])
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f")
- (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f"))
- (match_operand:DF 3 "register_operand" "f"))))]
- "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
- "nmadd.d\\t%0,%3,%1,%2"
- [(set_attr "type" "fmadd")
- (set_attr "mode" "DF")])
+(define_insn_and_split "*extendqihi2"
+ [(set (match_operand:HI 0 "register_operand" "=d,d")
+ (sign_extend:HI
+ (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
+ "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
+ "@
+ #
+ lb\t%0,%1"
+ "&& reload_completed && REG_P (operands[1])"
+ [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
+ (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
+{
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
+ - GET_MODE_BITSIZE (QImode));
+}
+ [(set_attr "move_type" "shift_shift,load")
+ (set_attr "mode" "SI")])
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f"))
- (match_operand:SF 3 "register_operand" "f"))))]
- "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
- "nmadd.s\\t%0,%3,%1,%2"
- [(set_attr "type" "fmadd")
- (set_attr "mode" "SF")])
+(define_insn "*extendqihi2_seb"
+ [(set (match_operand:HI 0 "register_operand" "=d,d")
+ (sign_extend:HI
+ (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
+ "ISA_HAS_SEB_SEH"
+ "@
+ seb\t%0,%1
+ lb\t%0,%1"
+ [(set_attr "move_type" "signext,load")
+ (set_attr "mode" "SI")])
-(define_insn ""
+(define_insn "extendsfdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
- (minus:DF (match_operand:DF 1 "register_operand" "f")
- (mult:DF (match_operand:DF 2 "register_operand" "f")
- (match_operand:DF 3 "register_operand" "f"))))]
- "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
- "nmsub.d\\t%0,%1,%2,%3"
- [(set_attr "type" "fmadd")
+ (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "cvt.d.s\t%0,%1"
+ [(set_attr "type" "fcvt")
+ (set_attr "cnv_mode" "S2D")
(set_attr "mode" "DF")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (minus:SF (match_operand:SF 1 "register_operand" "f")
- (mult:SF (match_operand:SF 2 "register_operand" "f")
- (match_operand:SF 3 "register_operand" "f"))))]
- "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
- "nmsub.s\\t%0,%1,%2,%3"
- [(set_attr "type" "fmadd")
- (set_attr "mode" "SF")])
\f
;;
;; ....................
;;
-;; DIVISION and REMAINDER
+;; CONVERSIONS
;;
;; ....................
-;;
-(define_insn "divdf3"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (div:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
+(define_expand "fix_truncdfsi2"
+ [(set (match_operand:SI 0 "register_operand")
+ (fix:SI (match_operand:DF 1 "register_operand")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "div.d\\t%0,%1,%2"
- [(set_attr "type" "fdiv")
- (set_attr "mode" "DF")])
-
-(define_insn "divsf3"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (div:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "div.s\\t%0,%1,%2"
- [(set_attr "type" "fdiv")
- (set_attr "mode" "SF")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f")
- (div:DF (match_operand:DF 1 "const_float_1_operand" "")
- (match_operand:DF 2 "register_operand" "f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
- "recip.d\\t%0,%2"
- [(set_attr "type" "fdiv")
- (set_attr "mode" "DF")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (div:SF (match_operand:SF 1 "const_float_1_operand" "")
- (match_operand:SF 2 "register_operand" "f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
- "recip.s\\t%0,%2"
- [(set_attr "type" "fdiv")
- (set_attr "mode" "SF")])
-
-;; If optimizing, prefer the divmod functions over separate div and
-;; mod functions, since this will allow using one instruction for both
-;; the quotient and remainder. At present, the divmod is not moved out
-;; of loops if it is constant within the loop, so allow -mdebugc to
-;; use the old method of doing things.
-
-;; 64 is the multiply/divide hi register
-;; 65 is the multiply/divide lo register
-
-;; ??? We can't accept constants here, because the MIPS assembler will replace
-;; a divide by power of 2 with a shift, and then the remainder is no longer
-;; available.
-
-(define_expand "divmodsi4"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (div:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (set (match_operand:SI 3 "register_operand" "=d")
- (mod:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_scratch:SI 4 "=l"))
- (clobber (match_scratch:SI 5 "=h"))
- (clobber (match_scratch:SI 6 "=a"))]
- "optimize"
- "
{
- emit_insn (gen_divmodsi4_internal (operands[0], operands[1], operands[2],
- operands[3]));
- if (!TARGET_NO_CHECK_ZERO_DIV)
- {
- emit_insn (gen_div_trap (operands[2],
- GEN_INT (0),
- GEN_INT (0x7)));
- }
- if (TARGET_CHECK_RANGE_DIV)
+ if (!ISA_HAS_TRUNC_W)
{
- emit_insn (gen_div_trap (operands[2],
- copy_to_mode_reg (SImode, GEN_INT (-1)),
- GEN_INT (0x6)));
- emit_insn (gen_div_trap (operands[2],
- copy_to_mode_reg (SImode,
- GEN_INT
- (trunc_int_for_mode
- (BITMASK_HIGH, SImode))),
- GEN_INT (0x6)));
+ emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
+ DONE;
}
+})
- DONE;
-}")
+(define_insn "fix_truncdfsi2_insn"
+ [(set (match_operand:SI 0 "register_operand" "=f")
+ (fix:SI (match_operand:DF 1 "register_operand" "f")))]
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
+ "trunc.w.d %0,%1"
+ [(set_attr "type" "fcvt")
+ (set_attr "mode" "DF")
+ (set_attr "cnv_mode" "D2I")])
-(define_insn "divmodsi4_internal"
- [(set (match_operand:SI 0 "register_operand" "=l")
- (div:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (set (match_operand:SI 3 "register_operand" "=h")
- (mod:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_scratch:SI 4 "=a"))]
- "optimize"
- "div\\t$0,%1,%2"
- [(set_attr "type" "idiv")
- (set_attr "mode" "SI")])
+(define_insn "fix_truncdfsi2_macro"
+ [(set (match_operand:SI 0 "register_operand" "=f")
+ (fix:SI (match_operand:DF 1 "register_operand" "f")))
+ (clobber (match_scratch:DF 2 "=d"))]
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
+{
+ if (set_nomacro)
+ return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
+ else
+ return "trunc.w.d %0,%1,%2";
+}
+ [(set_attr "type" "fcvt")
+ (set_attr "mode" "DF")
+ (set_attr "cnv_mode" "D2I")
+ (set_attr "length" "36")])
-(define_expand "divmoddi4"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (div:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))
- (set (match_operand:DI 3 "register_operand" "=d")
- (mod:DI (match_dup 1)
- (match_dup 2)))
- (clobber (match_scratch:DI 4 "=l"))
- (clobber (match_scratch:DI 5 "=h"))
- (clobber (match_scratch:DI 6 "=a"))]
- "TARGET_64BIT && optimize"
- "
+(define_expand "fix_truncsfsi2"
+ [(set (match_operand:SI 0 "register_operand")
+ (fix:SI (match_operand:SF 1 "register_operand")))]
+ "TARGET_HARD_FLOAT"
{
- emit_insn (gen_divmoddi4_internal (operands[0], operands[1], operands[2],
- operands[3]));
- if (!TARGET_NO_CHECK_ZERO_DIV)
- {
- emit_insn (gen_div_trap (operands[2],
- GEN_INT (0),
- GEN_INT (0x7)));
- }
- if (TARGET_CHECK_RANGE_DIV)
+ if (!ISA_HAS_TRUNC_W)
{
- emit_insn (gen_div_trap (operands[2],
- copy_to_mode_reg (DImode, GEN_INT (-1)),
- GEN_INT (0x6)));
- emit_insn (gen_div_trap (operands[2],
- copy_to_mode_reg (DImode,
- GEN_INT (BITMASK_HIGH)),
- GEN_INT (0x6)));
+ emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
+ DONE;
}
+})
- DONE;
-}")
-
-(define_insn "divmoddi4_internal"
- [(set (match_operand:DI 0 "register_operand" "=l")
- (div:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))
- (set (match_operand:DI 3 "register_operand" "=h")
- (mod:DI (match_dup 1)
- (match_dup 2)))
- (clobber (match_scratch:DI 4 "=a"))]
- "TARGET_64BIT && optimize"
- "ddiv\\t$0,%1,%2"
- [(set_attr "type" "idiv")
- (set_attr "mode" "SI")])
+(define_insn "fix_truncsfsi2_insn"
+ [(set (match_operand:SI 0 "register_operand" "=f")
+ (fix:SI (match_operand:SF 1 "register_operand" "f")))]
+ "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
+ "trunc.w.s %0,%1"
+ [(set_attr "type" "fcvt")
+ (set_attr "mode" "SF")
+ (set_attr "cnv_mode" "S2I")])
-(define_expand "udivmodsi4"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (udiv:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (set (match_operand:SI 3 "register_operand" "=d")
- (umod:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_scratch:SI 4 "=l"))
- (clobber (match_scratch:SI 5 "=h"))
- (clobber (match_scratch:SI 6 "=a"))]
- "optimize"
- "
+(define_insn "fix_truncsfsi2_macro"
+ [(set (match_operand:SI 0 "register_operand" "=f")
+ (fix:SI (match_operand:SF 1 "register_operand" "f")))
+ (clobber (match_scratch:SF 2 "=d"))]
+ "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
{
- emit_insn (gen_udivmodsi4_internal (operands[0], operands[1], operands[2],
- operands[3]));
- if (!TARGET_NO_CHECK_ZERO_DIV)
- {
- emit_insn (gen_div_trap (operands[2],
- GEN_INT (0),
- GEN_INT (0x7)));
- }
+ if (set_nomacro)
+ return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
+ else
+ return "trunc.w.s %0,%1,%2";
+}
+ [(set_attr "type" "fcvt")
+ (set_attr "mode" "SF")
+ (set_attr "cnv_mode" "S2I")
+ (set_attr "length" "36")])
- DONE;
-}")
-(define_insn "udivmodsi4_internal"
- [(set (match_operand:SI 0 "register_operand" "=l")
- (udiv:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (set (match_operand:SI 3 "register_operand" "=h")
- (umod:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_scratch:SI 4 "=a"))]
- "optimize"
- "divu\\t$0,%1,%2"
- [(set_attr "type" "idiv")
- (set_attr "mode" "SI")])
+(define_insn "fix_truncdfdi2"
+ [(set (match_operand:DI 0 "register_operand" "=f")
+ (fix:DI (match_operand:DF 1 "register_operand" "f")))]
+ "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
+ "trunc.l.d %0,%1"
+ [(set_attr "type" "fcvt")
+ (set_attr "mode" "DF")
+ (set_attr "cnv_mode" "D2I")])
-(define_expand "udivmoddi4"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (udiv:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))
- (set (match_operand:DI 3 "register_operand" "=d")
- (umod:DI (match_dup 1)
- (match_dup 2)))
- (clobber (match_scratch:DI 4 "=l"))
- (clobber (match_scratch:DI 5 "=h"))
- (clobber (match_scratch:DI 6 "=a"))]
- "TARGET_64BIT && optimize"
- "
-{
- emit_insn (gen_udivmoddi4_internal (operands[0], operands[1], operands[2],
- operands[3]));
- if (!TARGET_NO_CHECK_ZERO_DIV)
- {
- emit_insn (gen_div_trap (operands[2],
- GEN_INT (0),
- GEN_INT (0x7)));
- }
- DONE;
-}")
+(define_insn "fix_truncsfdi2"
+ [(set (match_operand:DI 0 "register_operand" "=f")
+ (fix:DI (match_operand:SF 1 "register_operand" "f")))]
+ "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
+ "trunc.l.s %0,%1"
+ [(set_attr "type" "fcvt")
+ (set_attr "mode" "SF")
+ (set_attr "cnv_mode" "S2I")])
-(define_insn "udivmoddi4_internal"
- [(set (match_operand:DI 0 "register_operand" "=l")
- (udiv:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))
- (set (match_operand:DI 3 "register_operand" "=h")
- (umod:DI (match_dup 1)
- (match_dup 2)))
- (clobber (match_scratch:DI 4 "=a"))]
- "TARGET_64BIT && optimize"
- "ddivu\\t$0,%1,%2"
- [(set_attr "type" "idiv")
- (set_attr "mode" "SI")])
-;; Division trap
+(define_insn "floatsidf2"
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (float:DF (match_operand:SI 1 "register_operand" "f")))]
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "cvt.d.w\t%0,%1"
+ [(set_attr "type" "fcvt")
+ (set_attr "mode" "DF")
+ (set_attr "cnv_mode" "I2D")])
-(define_expand "div_trap"
- [(trap_if (eq (match_operand 0 "register_operand" "d")
- (match_operand 1 "true_reg_or_0_operand" "dJ"))
- (match_operand 2 "immediate_operand" ""))]
- ""
- "
-{
- if (TARGET_MIPS16)
- emit_insn (gen_div_trap_mips16 (operands[0],operands[1],operands[2]));
- else
- emit_insn (gen_div_trap_normal (operands[0],operands[1],operands[2]));
- DONE;
-}")
-(define_insn "div_trap_normal"
- [(trap_if (eq (match_operand 0 "register_operand" "d,d")
- (match_operand 1 "true_reg_or_0_operand" "d,J"))
- (match_operand 2 "immediate_operand" ""))]
- "!TARGET_MIPS16"
- "*
-{
- rtx link;
- int have_dep_anti = 0;
+(define_insn "floatdidf2"
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (float:DF (match_operand:DI 1 "register_operand" "f")))]
+ "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
+ "cvt.d.l\t%0,%1"
+ [(set_attr "type" "fcvt")
+ (set_attr "mode" "DF")
+ (set_attr "cnv_mode" "I2D")])
- /* For divmod if one division is not needed then we don't need an extra
- divide by zero trap, which is anti dependent on previous trap */
- for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
- if ((int) REG_DEP_ANTI == (int) REG_NOTE_KIND (link)
- && GET_CODE (XEXP (link, 0)) == INSN
- && GET_CODE (PATTERN (XEXP (link, 0))) == TRAP_IF
- && which_alternative == 1)
- have_dep_anti = 1;
- if (! have_dep_anti)
- {
- if (GENERATE_BRANCHLIKELY)
- {
- if (which_alternative == 1)
- return \"%(beql\\t%0,$0,1f\\n\\tbreak\\t%2\\n%~1:%)\";
- else
- return \"%(beql\\t%0,%1,1f\\n\\tbreak\\t%2\\n%~1:%)\";
- }
- else
- {
- if (which_alternative == 1)
- return \"%(bne\\t%0,$0,1f\\n\\tnop\\n\\tbreak\\t%2\\n%~1:%)\";
- else
- return \"%(bne\\t%0,%1,1f\\n\\tnop\\n\\tbreak\\t%2\\n%~1:%)\";
- }
- }
- return \"\";
-}"
- [(set_attr "type" "unknown")
- (set_attr "length" "12")])
+(define_insn "floatsisf2"
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (float:SF (match_operand:SI 1 "register_operand" "f")))]
+ "TARGET_HARD_FLOAT"
+ "cvt.s.w\t%0,%1"
+ [(set_attr "type" "fcvt")
+ (set_attr "mode" "SF")
+ (set_attr "cnv_mode" "I2S")])
-;; The mips16 bne insns is a macro which uses reg 24 as an intermediate.
+(define_insn "floatdisf2"
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (float:SF (match_operand:DI 1 "register_operand" "f")))]
+ "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
+ "cvt.s.l\t%0,%1"
+ [(set_attr "type" "fcvt")
+ (set_attr "mode" "SF")
+ (set_attr "cnv_mode" "I2S")])
+
-(define_insn "div_trap_mips16"
- [(trap_if (eq (match_operand 0 "register_operand" "d,d")
- (match_operand 1 "true_reg_or_0_operand" "d,J"))
- (match_operand 2 "immediate_operand" ""))
- (clobber (reg:SI 24))]
- "TARGET_MIPS16"
- "*
+(define_expand "fixuns_truncdfsi2"
+ [(set (match_operand:SI 0 "register_operand")
+ (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
{
- rtx link;
- int have_dep_anti = 0;
+ rtx reg1 = gen_reg_rtx (DFmode);
+ rtx reg2 = gen_reg_rtx (DFmode);
+ rtx reg3 = gen_reg_rtx (SImode);
+ rtx label1 = gen_label_rtx ();
+ rtx label2 = gen_label_rtx ();
+ REAL_VALUE_TYPE offset;
- /* For divmod if one division is not needed then we don't need an extra
- divide by zero trap, which is anti dependent on previous trap */
- for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
+ real_2expN (&offset, 31, DFmode);
- if ((int) REG_DEP_ANTI == (int) REG_NOTE_KIND (link)
- && GET_CODE (XEXP (link, 0)) == INSN
- && GET_CODE (PATTERN (XEXP (link, 0))) == TRAP_IF
- && which_alternative == 1)
- have_dep_anti = 1;
- if (! have_dep_anti)
+ if (reg1) /* Turn off complaints about unreached code. */
{
- /* No branch delay slots on mips16. */
- if (which_alternative == 1)
- return \"%(bnez\\t%0,1f\\n\\tbreak\\t%2\\n%~1:%)\";
- else
- return \"%(bne\\t%0,%1,1f\\n\\tbreak\\t%2\\n%~1:%)\";
- }
- return \"\";
-}"
- [(set_attr "type" "unknown")
- (set_attr "length" "12")])
+ mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
+ do_pending_stack_adjust ();
-(define_expand "divsi3"
- [(set (match_operand:SI 0 "register_operand" "=l")
- (div:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (clobber (match_scratch:SI 3 "=h"))
- (clobber (match_scratch:SI 4 "=a"))]
- "!optimize"
- "
-{
- emit_insn (gen_divsi3_internal (operands[0], operands[1], operands[2]));
- if (!TARGET_NO_CHECK_ZERO_DIV)
- {
- emit_insn (gen_div_trap (operands[2],
- GEN_INT (0),
- GEN_INT (0x7)));
- }
- if (TARGET_CHECK_RANGE_DIV)
- {
- emit_insn (gen_div_trap (operands[2],
- copy_to_mode_reg (SImode, GEN_INT (-1)),
- GEN_INT (0x6)));
- emit_insn (gen_div_trap (operands[2],
- copy_to_mode_reg (SImode,
- GEN_INT
- (trunc_int_for_mode
- (BITMASK_HIGH, SImode))),
- GEN_INT (0x6)));
- }
+ emit_insn (gen_cmpdf (operands[1], reg1));
+ emit_jump_insn (gen_bge (label1));
- DONE;
-}")
+ emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
+ emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
+ gen_rtx_LABEL_REF (VOIDmode, label2)));
+ emit_barrier ();
-(define_insn "divsi3_internal"
- [(set (match_operand:SI 0 "register_operand" "=l")
- (div:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "nonmemory_operand" "di")))
- (clobber (match_scratch:SI 3 "=h"))
- (clobber (match_scratch:SI 4 "=a"))]
- "!optimize"
- "div\\t$0,%1,%2"
- [(set_attr "type" "idiv")
- (set_attr "mode" "SI")])
+ emit_label (label1);
+ mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
+ mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
+ (BITMASK_HIGH, SImode)));
-(define_expand "divdi3"
- [(set (match_operand:DI 0 "register_operand" "=l")
- (div:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))
- (clobber (match_scratch:DI 3 "=h"))
- (clobber (match_scratch:DI 4 "=a"))]
- "TARGET_64BIT && !optimize"
- "
-{
- emit_insn (gen_divdi3_internal (operands[0], operands[1], operands[2]));
- if (!TARGET_NO_CHECK_ZERO_DIV)
- {
- emit_insn (gen_div_trap (operands[2],
- GEN_INT (0),
- GEN_INT (0x7)));
- }
- if (TARGET_CHECK_RANGE_DIV)
- {
- emit_insn (gen_div_trap (operands[2],
- copy_to_mode_reg (DImode, GEN_INT (-1)),
- GEN_INT (0x6)));
- emit_insn (gen_div_trap (operands[2],
- copy_to_mode_reg (DImode,
- GEN_INT (BITMASK_HIGH)),
- GEN_INT (0x6)));
- }
+ emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
+ emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
- DONE;
-}")
+ emit_label (label2);
-(define_insn "divdi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=l")
- (div:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_nonmemory_operand" "di")))
- (clobber (match_scratch:SI 3 "=h"))
- (clobber (match_scratch:SI 4 "=a"))]
- "TARGET_64BIT && !optimize"
- "ddiv\\t$0,%1,%2"
- [(set_attr "type" "idiv")
- (set_attr "mode" "DI")])
+ /* Allow REG_NOTES to be set on last insn (labels don't have enough
+ fields, and can't be used for REG_NOTES anyway). */
+ emit_use (stack_pointer_rtx);
+ DONE;
+ }
+})
-(define_expand "modsi3"
- [(set (match_operand:SI 0 "register_operand" "=h")
- (mod:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (clobber (match_scratch:SI 3 "=l"))
- (clobber (match_scratch:SI 4 "=a"))]
- "!optimize"
- "
+
+(define_expand "fixuns_truncdfdi2"
+ [(set (match_operand:DI 0 "register_operand")
+ (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
+ "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
{
- emit_insn (gen_modsi3_internal (operands[0], operands[1], operands[2]));
- if (!TARGET_NO_CHECK_ZERO_DIV)
- {
- emit_insn (gen_div_trap (operands[2],
- GEN_INT (0),
- GEN_INT (0x7)));
- }
- if (TARGET_CHECK_RANGE_DIV)
- {
- emit_insn (gen_div_trap (operands[2],
- copy_to_mode_reg (SImode, GEN_INT (-1)),
- GEN_INT (0x6)));
- emit_insn (gen_div_trap (operands[2],
- copy_to_mode_reg (SImode,
- GEN_INT
- (trunc_int_for_mode
- (BITMASK_HIGH, SImode))),
- GEN_INT (0x6)));
- }
+ rtx reg1 = gen_reg_rtx (DFmode);
+ rtx reg2 = gen_reg_rtx (DFmode);
+ rtx reg3 = gen_reg_rtx (DImode);
+ rtx label1 = gen_label_rtx ();
+ rtx label2 = gen_label_rtx ();
+ REAL_VALUE_TYPE offset;
- DONE;
-}")
+ real_2expN (&offset, 63, DFmode);
-(define_insn "modsi3_internal"
- [(set (match_operand:SI 0 "register_operand" "=h")
- (mod:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "nonmemory_operand" "di")))
- (clobber (match_scratch:SI 3 "=l"))
- (clobber (match_scratch:SI 4 "=a"))]
- "!optimize"
- "div\\t$0,%1,%2"
- [(set_attr "type" "idiv")
- (set_attr "mode" "SI")])
+ mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
+ do_pending_stack_adjust ();
-(define_expand "moddi3"
- [(set (match_operand:DI 0 "register_operand" "=h")
- (mod:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))
- (clobber (match_scratch:DI 3 "=l"))
- (clobber (match_scratch:DI 4 "=a"))]
- "TARGET_64BIT && !optimize"
- "
-{
- emit_insn (gen_moddi3_internal (operands[0], operands[1], operands[2]));
- if (!TARGET_NO_CHECK_ZERO_DIV)
- {
- emit_insn (gen_div_trap (operands[2],
- GEN_INT (0),
- GEN_INT (0x7)));
- }
- if (TARGET_CHECK_RANGE_DIV)
- {
- emit_insn (gen_div_trap (operands[2],
- copy_to_mode_reg (DImode, GEN_INT (-1)),
- GEN_INT (0x6)));
- emit_insn (gen_div_trap (operands[2],
- copy_to_mode_reg (DImode,
- GEN_INT (BITMASK_HIGH)),
- GEN_INT (0x6)));
- }
+ emit_insn (gen_cmpdf (operands[1], reg1));
+ emit_jump_insn (gen_bge (label1));
- DONE;
-}")
+ emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
+ emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
+ gen_rtx_LABEL_REF (VOIDmode, label2)));
+ emit_barrier ();
-(define_insn "moddi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=h")
- (mod:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_nonmemory_operand" "di")))
- (clobber (match_scratch:SI 3 "=l"))
- (clobber (match_scratch:SI 4 "=a"))]
- "TARGET_64BIT && !optimize"
- "ddiv\\t$0,%1,%2"
- [(set_attr "type" "idiv")
- (set_attr "mode" "DI")])
+ emit_label (label1);
+ mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
+ mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
+ emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
-(define_expand "udivsi3"
- [(set (match_operand:SI 0 "register_operand" "=l")
- (udiv:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (clobber (match_scratch:SI 3 "=h"))
- (clobber (match_scratch:SI 4 "=a"))]
- "!optimize"
- "
-{
- emit_insn (gen_udivsi3_internal (operands[0], operands[1], operands[2]));
- if (!TARGET_NO_CHECK_ZERO_DIV)
- {
- emit_insn (gen_div_trap (operands[2],
- GEN_INT (0),
- GEN_INT (0x7)));
- }
+ emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
+ emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
+ emit_label (label2);
+
+ /* Allow REG_NOTES to be set on last insn (labels don't have enough
+ fields, and can't be used for REG_NOTES anyway). */
+ emit_use (stack_pointer_rtx);
DONE;
-}")
+})
-(define_insn "udivsi3_internal"
- [(set (match_operand:SI 0 "register_operand" "=l")
- (udiv:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "nonmemory_operand" "di")))
- (clobber (match_scratch:SI 3 "=h"))
- (clobber (match_scratch:SI 4 "=a"))]
- "!optimize"
- "divu\\t$0,%1,%2"
- [(set_attr "type" "idiv")
- (set_attr "mode" "SI")])
-(define_expand "udivdi3"
- [(set (match_operand:DI 0 "register_operand" "=l")
- (udiv:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "di")))
- (clobber (match_scratch:DI 3 "=h"))
- (clobber (match_scratch:DI 4 "=a"))]
- "TARGET_64BIT && !optimize"
- "
+(define_expand "fixuns_truncsfsi2"
+ [(set (match_operand:SI 0 "register_operand")
+ (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
+ "TARGET_HARD_FLOAT"
{
- emit_insn (gen_udivdi3_internal (operands[0], operands[1], operands[2]));
- if (!TARGET_NO_CHECK_ZERO_DIV)
- {
- emit_insn (gen_div_trap (operands[2],
- GEN_INT (0),
- GEN_INT (0x7)));
- }
+ rtx reg1 = gen_reg_rtx (SFmode);
+ rtx reg2 = gen_reg_rtx (SFmode);
+ rtx reg3 = gen_reg_rtx (SImode);
+ rtx label1 = gen_label_rtx ();
+ rtx label2 = gen_label_rtx ();
+ REAL_VALUE_TYPE offset;
- DONE;
-}")
+ real_2expN (&offset, 31, SFmode);
-(define_insn "udivdi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=l")
- (udiv:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_nonmemory_operand" "di")))
- (clobber (match_scratch:SI 3 "=h"))
- (clobber (match_scratch:SI 4 "=a"))]
- "TARGET_64BIT && !optimize"
- "ddivu\\t$0,%1,%2"
- [(set_attr "type" "idiv")
- (set_attr "mode" "DI")])
+ mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
+ do_pending_stack_adjust ();
-(define_expand "umodsi3"
- [(set (match_operand:SI 0 "register_operand" "=h")
- (umod:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (clobber (match_scratch:SI 3 "=l"))
- (clobber (match_scratch:SI 4 "=a"))]
- "!optimize"
- "
-{
- emit_insn (gen_umodsi3_internal (operands[0], operands[1], operands[2]));
- if (!TARGET_NO_CHECK_ZERO_DIV)
- {
- emit_insn (gen_div_trap (operands[2],
- GEN_INT (0),
- GEN_INT (0x7)));
- }
+ emit_insn (gen_cmpsf (operands[1], reg1));
+ emit_jump_insn (gen_bge (label1));
+
+ emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
+ emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
+ gen_rtx_LABEL_REF (VOIDmode, label2)));
+ emit_barrier ();
+
+ emit_label (label1);
+ mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
+ mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
+ (BITMASK_HIGH, SImode)));
+
+ emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
+ emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
+ emit_label (label2);
+
+ /* Allow REG_NOTES to be set on last insn (labels don't have enough
+ fields, and can't be used for REG_NOTES anyway). */
+ emit_use (stack_pointer_rtx);
DONE;
-}")
+})
-(define_insn "umodsi3_internal"
- [(set (match_operand:SI 0 "register_operand" "=h")
- (umod:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "nonmemory_operand" "di")))
- (clobber (match_scratch:SI 3 "=l"))
- (clobber (match_scratch:SI 4 "=a"))]
- "!optimize"
- "divu\\t$0,%1,%2"
- [(set_attr "type" "idiv")
- (set_attr "mode" "SI")])
-(define_expand "umoddi3"
- [(set (match_operand:DI 0 "register_operand" "=h")
- (umod:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "di")))
- (clobber (match_scratch:DI 3 "=l"))
- (clobber (match_scratch:DI 4 "=a"))]
- "TARGET_64BIT && !optimize"
- "
+(define_expand "fixuns_truncsfdi2"
+ [(set (match_operand:DI 0 "register_operand")
+ (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
+ "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
{
- emit_insn (gen_umoddi3_internal (operands[0], operands[1], operands[2]));
- if (!TARGET_NO_CHECK_ZERO_DIV)
- {
- emit_insn (gen_div_trap (operands[2],
- GEN_INT (0),
- GEN_INT (0x7)));
- }
+ rtx reg1 = gen_reg_rtx (SFmode);
+ rtx reg2 = gen_reg_rtx (SFmode);
+ rtx reg3 = gen_reg_rtx (DImode);
+ rtx label1 = gen_label_rtx ();
+ rtx label2 = gen_label_rtx ();
+ REAL_VALUE_TYPE offset;
- DONE;
-}")
+ real_2expN (&offset, 63, SFmode);
-(define_insn "umoddi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=h")
- (umod:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_nonmemory_operand" "di")))
- (clobber (match_scratch:SI 3 "=l"))
- (clobber (match_scratch:SI 4 "=a"))]
- "TARGET_64BIT && !optimize"
- "ddivu\\t$0,%1,%2"
- [(set_attr "type" "idiv")
- (set_attr "mode" "DI")])
-\f
-;;
-;; ....................
-;;
-;; SQUARE ROOT
-;;
-;; ....................
+ mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
+ do_pending_stack_adjust ();
-(define_insn "sqrtdf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && HAVE_SQRT_P() && TARGET_DOUBLE_FLOAT"
- "sqrt.d\\t%0,%1"
- [(set_attr "type" "fsqrt")
- (set_attr "mode" "DF")])
+ emit_insn (gen_cmpsf (operands[1], reg1));
+ emit_jump_insn (gen_bge (label1));
-(define_insn "sqrtsf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && HAVE_SQRT_P()"
- "sqrt.s\\t%0,%1"
- [(set_attr "type" "fsqrt")
- (set_attr "mode" "SF")])
+ emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
+ emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
+ gen_rtx_LABEL_REF (VOIDmode, label2)));
+ emit_barrier ();
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f")
- (div:DF (match_operand:DF 1 "const_float_1_operand" "")
- (sqrt:DF (match_operand:DF 2 "register_operand" "f"))))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
- "rsqrt.d\\t%0,%2"
- [(set_attr "type" "fsqrt")
- (set_attr "mode" "DF")])
+ emit_label (label1);
+ mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
+ mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
+ emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (div:SF (match_operand:SF 1 "const_float_1_operand" "")
- (sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
- "rsqrt.s\\t%0,%2"
- [(set_attr "type" "fsqrt")
- (set_attr "mode" "SF")])
+ emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
+ emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
+
+ emit_label (label2);
+ /* Allow REG_NOTES to be set on last insn (labels don't have enough
+ fields, and can't be used for REG_NOTES anyway). */
+ emit_use (stack_pointer_rtx);
+ DONE;
+})
\f
;;
;; ....................
;;
-;; ABSOLUTE VALUE
+;; DATA MOVEMENT
;;
;; ....................
-;; Do not use the integer abs macro instruction, since that signals an
-;; exception on -2147483648 (sigh).
+;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
-(define_insn "abssi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (abs:SI (match_operand:SI 1 "register_operand" "d")))]
+(define_expand "extv"
+ [(set (match_operand 0 "register_operand")
+ (sign_extract (match_operand 1 "nonimmediate_operand")
+ (match_operand 2 "const_int_operand")
+ (match_operand 3 "const_int_operand")))]
"!TARGET_MIPS16"
- "*
{
- dslots_jump_total++;
- dslots_jump_filled++;
- operands[2] = const0_rtx;
-
- if (REGNO (operands[0]) == REGNO (operands[1]))
+ if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
+ INTVAL (operands[2]),
+ INTVAL (operands[3])))
+ DONE;
+ else if (register_operand (operands[1], GET_MODE (operands[0]))
+ && ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32)
{
- if (GENERATE_BRANCHLIKELY)
- return \"%(bltzl\\t%1,1f\\n\\tsubu\\t%0,%z2,%0\\n%~1:%)\";
+ if (GET_MODE (operands[0]) == DImode)
+ emit_insn (gen_extvdi (operands[0], operands[1], operands[2],
+ operands[3]));
else
- return \"bgez\\t%1,1f%#\\n\\tsubu\\t%0,%z2,%0\\n%~1:\";
+ emit_insn (gen_extvsi (operands[0], operands[1], operands[2],
+ operands[3]));
+ DONE;
}
else
- return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tsubu\\t%0,%z2,%0\\n%~1:%)\";
-}"
- [(set_attr "type" "multi")
- (set_attr "mode" "SI")
- (set_attr "length" "12")])
+ FAIL;
+})
-(define_insn "absdi2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (abs:DI (match_operand:DI 1 "se_register_operand" "d")))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "*
-{
- unsigned int regno1;
- dslots_jump_total++;
- dslots_jump_filled++;
- operands[2] = const0_rtx;
+(define_insn "extv<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (sign_extract:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand 2 "const_int_operand" "")
+ (match_operand 3 "const_int_operand" "")))]
+ "ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32"
+ "exts\t%0,%1,%3,%m2"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "<MODE>")])
- if (GET_CODE (operands[1]) == REG)
- regno1 = REGNO (operands[1]);
- else
- regno1 = REGNO (XEXP (operands[1], 0));
- if (REGNO (operands[0]) == regno1)
- return \"%(bltzl\\t%1,1f\\n\\tdsubu\\t%0,%z2,%0\\n%~1:%)\";
+(define_expand "extzv"
+ [(set (match_operand 0 "register_operand")
+ (zero_extract (match_operand 1 "nonimmediate_operand")
+ (match_operand 2 "const_int_operand")
+ (match_operand 3 "const_int_operand")))]
+ "!TARGET_MIPS16"
+{
+ if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
+ INTVAL (operands[2]),
+ INTVAL (operands[3])))
+ DONE;
+ else if (mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
+ INTVAL (operands[3])))
+ {
+ if (GET_MODE (operands[0]) == DImode)
+ emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
+ operands[3]));
+ else
+ emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
+ operands[3]));
+ DONE;
+ }
else
- return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tdsubu\\t%0,%z2,%0\\n%~1:%)\";
-}"
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "12")])
+ FAIL;
+})
+
+(define_insn "extzv<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand 2 "const_int_operand" "")
+ (match_operand 3 "const_int_operand" "")))]
+ "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
+ INTVAL (operands[3]))"
+ "<d>ext\t%0,%1,%3,%2"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "<MODE>")])
-(define_insn "absdf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (abs:DF (match_operand:DF 1 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "abs.d\\t%0,%1"
- [(set_attr "type" "fabs")
- (set_attr "mode" "DF")])
+(define_insn "*extzv_trunc<mode>_exts"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (truncate:GPR
+ (zero_extract:DI (match_operand:DI 1 "register_operand" "d")
+ (match_operand 2 "const_int_operand" "")
+ (match_operand 3 "const_int_operand" ""))))]
+ "ISA_HAS_EXTS && TARGET_64BIT && IN_RANGE (INTVAL (operands[2]), 32, 63)"
+ "exts\t%0,%1,%3,31"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "<MODE>")])
-(define_insn "abssf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (abs:SF (match_operand:SF 1 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "abs.s\\t%0,%1"
- [(set_attr "type" "fabs")
- (set_attr "mode" "SF")])
-\f
-;;
-;; ....................
+(define_expand "insv"
+ [(set (zero_extract (match_operand 0 "nonimmediate_operand")
+ (match_operand 1 "immediate_operand")
+ (match_operand 2 "immediate_operand"))
+ (match_operand 3 "reg_or_0_operand"))]
+ "!TARGET_MIPS16"
+{
+ if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
+ INTVAL (operands[1]),
+ INTVAL (operands[2])))
+ DONE;
+ else if (mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
+ INTVAL (operands[2])))
+ {
+ if (GET_MODE (operands[0]) == DImode)
+ emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
+ operands[3]));
+ else
+ emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
+ operands[3]));
+ DONE;
+ }
+ else
+ FAIL;
+})
+
+(define_insn "insv<mode>"
+ [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
+ (match_operand:SI 1 "immediate_operand" "I")
+ (match_operand:SI 2 "immediate_operand" "I"))
+ (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
+ "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
+ INTVAL (operands[2]))"
+ "<d>ins\t%0,%z3,%2,%1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "<MODE>")])
+
+;; Combiner pattern for cins (clear and insert bit field). We can
+;; implement mask-and-shift-left operation with this. Note that if
+;; the upper bit of the mask is set in an SImode operation, the mask
+;; itself will be sign-extended. mask_low_and_shift_len will
+;; therefore be greater than our threshold of 32.
+
+(define_insn "*cins<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (and:GPR
+ (ashift:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "const_int_operand" ""))
+ (match_operand:GPR 3 "const_int_operand" "")))]
+ "ISA_HAS_CINS
+ && mask_low_and_shift_p (<MODE>mode, operands[3], operands[2], 32)"
+{
+ operands[3] =
+ GEN_INT (mask_low_and_shift_len (<MODE>mode, operands[3], operands[2]));
+ return "cins\t%0,%1,%2,%m3";
+}
+ [(set_attr "type" "shift")
+ (set_attr "mode" "<MODE>")])
+
+;; Unaligned word moves generated by the bit field patterns.
;;
-;; FIND FIRST BIT INSTRUCTION
+;; As far as the rtl is concerned, both the left-part and right-part
+;; instructions can access the whole field. However, the real operand
+;; refers to just the first or the last byte (depending on endianness).
+;; We therefore use two memory operands to each instruction, one to
+;; describe the rtl effect and one to use in the assembly output.
;;
-;; ....................
+;; Operands 0 and 1 are the rtl-level target and source respectively.
+;; This allows us to use the standard length calculations for the "load"
+;; and "store" type attributes.
+
+(define_insn "mov_<load>l"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
+ (match_operand:QI 2 "memory_operand" "m")]
+ UNSPEC_LOAD_LEFT))]
+ "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
+ "<load>l\t%0,%2"
+ [(set_attr "move_type" "load")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "mov_<load>r"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
+ (match_operand:QI 2 "memory_operand" "m")
+ (match_operand:GPR 3 "register_operand" "0")]
+ UNSPEC_LOAD_RIGHT))]
+ "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
+ "<load>r\t%0,%2"
+ [(set_attr "move_type" "load")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "mov_<store>l"
+ [(set (match_operand:BLK 0 "memory_operand" "=m")
+ (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
+ (match_operand:QI 2 "memory_operand" "m")]
+ UNSPEC_STORE_LEFT))]
+ "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
+ "<store>l\t%z1,%2"
+ [(set_attr "move_type" "store")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "mov_<store>r"
+ [(set (match_operand:BLK 0 "memory_operand" "+m")
+ (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
+ (match_operand:QI 2 "memory_operand" "m")
+ (match_dup 0)]
+ UNSPEC_STORE_RIGHT))]
+ "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
+ "<store>r\t%z1,%2"
+ [(set_attr "move_type" "store")
+ (set_attr "mode" "<MODE>")])
+
+;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
+;; The required value is:
;;
-
-(define_insn "ffssi2"
- [(set (match_operand:SI 0 "register_operand" "=&d")
- (ffs:SI (match_operand:SI 1 "register_operand" "d")))
- (clobber (match_scratch:SI 2 "=&d"))
- (clobber (match_scratch:SI 3 "=&d"))]
- "!TARGET_MIPS16"
- "*
-{
- dslots_jump_total += 2;
- dslots_jump_filled += 2;
- operands[4] = const0_rtx;
-
- if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
- return \"%(\\
-move\\t%0,%z4\\n\\
-\\tbeq\\t%1,%z4,2f\\n\\
-%~1:\\tand\\t%2,%1,0x0001\\n\\
-\\taddu\\t%0,%0,1\\n\\
-\\tbeq\\t%2,%z4,1b\\n\\
-\\tsrl\\t%1,%1,1\\n\\
-%~2:%)\";
-
- return \"%(\\
-move\\t%0,%z4\\n\\
-\\tmove\\t%3,%1\\n\\
-\\tbeq\\t%3,%z4,2f\\n\\
-%~1:\\tand\\t%2,%3,0x0001\\n\\
-\\taddu\\t%0,%0,1\\n\\
-\\tbeq\\t%2,%z4,1b\\n\\
-\\tsrl\\t%3,%3,1\\n\\
-%~2:%)\";
-}"
- [(set_attr "type" "multi")
- (set_attr "mode" "SI")
- (set_attr "length" "12")])
-
-(define_insn "ffsdi2"
- [(set (match_operand:DI 0 "register_operand" "=&d")
- (ffs:DI (match_operand:DI 1 "se_register_operand" "d")))
- (clobber (match_scratch:DI 2 "=&d"))
- (clobber (match_scratch:DI 3 "=&d"))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "*
-{
- dslots_jump_total += 2;
- dslots_jump_filled += 2;
- operands[4] = const0_rtx;
-
- if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
- return \"%(\\
-move\\t%0,%z4\\n\\
-\\tbeq\\t%1,%z4,2f\\n\\
-%~1:\\tand\\t%2,%1,0x0001\\n\\
-\\tdaddu\\t%0,%0,1\\n\\
-\\tbeq\\t%2,%z4,1b\\n\\
-\\tdsrl\\t%1,%1,1\\n\\
-%~2:%)\";
-
- return \"%(\\
-move\\t%0,%z4\\n\\
-\\tmove\\t%3,%1\\n\\
-\\tbeq\\t%3,%z4,2f\\n\\
-%~1:\\tand\\t%2,%3,0x0001\\n\\
-\\tdaddu\\t%0,%0,1\\n\\
-\\tbeq\\t%2,%z4,1b\\n\\
-\\tdsrl\\t%3,%3,1\\n\\
-%~2:%)\";
-}"
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "24")])
-
-\f
+;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
;;
-;; ....................
+;; which translates to:
;;
-;; NEGATION and ONE'S COMPLEMENT
+;; lui op0,%highest(op1)
+;; daddiu op0,op0,%higher(op1)
+;; dsll op0,op0,16
+;; daddiu op0,op0,%hi(op1)
+;; dsll op0,op0,16
;;
-;; ....................
-
-(define_insn "negsi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (neg:SI (match_operand:SI 1 "register_operand" "d")))]
- ""
- "*
-{
- if (TARGET_MIPS16)
- return \"neg\\t%0,%1\";
- operands[2] = const0_rtx;
- return \"subu\\t%0,%z2,%1\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-(define_expand "negdi2"
- [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
- (neg:DI (match_operand:DI 1 "se_register_operand" "d")))
- (clobber (match_dup 2))])]
- "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
- "
-{
- if (TARGET_64BIT)
- {
- emit_insn (gen_negdi2_internal_2 (operands[0], operands[1]));
- DONE;
- }
-
- operands[2] = gen_reg_rtx (SImode);
-}")
-
-(define_insn "negdi2_internal"
+;; The split is deferred until after flow2 to allow the peephole2 below
+;; to take effect.
+(define_insn_and_split "*lea_high64"
[(set (match_operand:DI 0 "register_operand" "=d")
- (neg:DI (match_operand:DI 1 "register_operand" "d")))
- (clobber (match_operand:SI 2 "register_operand" "=d"))]
- "! TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "*
-{
- operands[3] = const0_rtx;
- return \"subu\\t%L0,%z3,%L1\;subu\\t%M0,%z3,%M1\;sltu\\t%2,%z3,%L0\;subu\\t%M0,%M0,%2\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-(define_insn "negdi2_internal_2"
+ (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
+ "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
+ "#"
+ "&& epilogue_completed"
+ [(set (match_dup 0) (high:DI (match_dup 2)))
+ (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
+ (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
+ (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
+ (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
+{
+ operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
+ operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
+}
+ [(set_attr "length" "20")])
+
+;; Use a scratch register to reduce the latency of the above pattern
+;; on superscalar machines. The optimized sequence is:
+;;
+;; lui op1,%highest(op2)
+;; lui op0,%hi(op2)
+;; daddiu op1,op1,%higher(op2)
+;; dsll32 op1,op1,0
+;; daddu op1,op1,op0
+(define_peephole2
+ [(set (match_operand:DI 1 "d_operand")
+ (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
+ (match_scratch:DI 0 "d")]
+ "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
+ [(set (match_dup 1) (high:DI (match_dup 3)))
+ (set (match_dup 0) (high:DI (match_dup 4)))
+ (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
+ (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
+ (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
+{
+ operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
+ operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
+})
+
+;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
+;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
+;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
+;; used once. We can then use the sequence:
+;;
+;; lui op0,%highest(op1)
+;; lui op2,%hi(op1)
+;; daddiu op0,op0,%higher(op1)
+;; daddiu op2,op2,%lo(op1)
+;; dsll32 op0,op0,0
+;; daddu op0,op0,op2
+;;
+;; which takes 4 cycles on most superscalar targets.
+(define_insn_and_split "*lea64"
[(set (match_operand:DI 0 "register_operand" "=d")
- (neg:DI (match_operand:DI 1 "se_register_operand" "d")))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "*
+ (match_operand:DI 1 "absolute_symbolic_operand" ""))
+ (clobber (match_scratch:DI 2 "=&d"))]
+ "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (high:DI (match_dup 3)))
+ (set (match_dup 2) (high:DI (match_dup 4)))
+ (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
+ (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
+ (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
+ (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
{
- operands[2] = const0_rtx;
- return \"dsubu\\t%0,%z2,%1\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
-
-(define_insn "negdf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (neg:DF (match_operand:DF 1 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "neg.d\\t%0,%1"
- [(set_attr "type" "fneg")
- (set_attr "mode" "DF")])
-
-(define_insn "negsf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (neg:SF (match_operand:SF 1 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "neg.s\\t%0,%1"
- [(set_attr "type" "fneg")
- (set_attr "mode" "SF")])
+ operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
+ operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
+}
+ [(set_attr "length" "24")])
-(define_insn "one_cmplsi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (not:SI (match_operand:SI 1 "register_operand" "d")))]
+;; Split HIGHs into:
+;;
+;; li op0,%hi(sym)
+;; sll op0,16
+;;
+;; on MIPS16 targets.
+(define_split
+ [(set (match_operand:SI 0 "d_operand")
+ (high:SI (match_operand:SI 1 "absolute_symbolic_operand")))]
+ "TARGET_MIPS16 && reload_completed"
+ [(set (match_dup 0) (match_dup 2))
+ (set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))]
+{
+ operands[2] = mips_unspec_address (operands[1], SYMBOL_32_HIGH);
+})
+
+;; Insns to fetch a symbol from a big GOT.
+
+(define_insn_and_split "*xgot_hi<mode>"
+ [(set (match_operand:P 0 "register_operand" "=d")
+ (high:P (match_operand:P 1 "got_disp_operand" "")))]
+ "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (high:P (match_dup 2)))
+ (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
+{
+ operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
+ operands[3] = pic_offset_table_rtx;
+}
+ [(set_attr "got" "xgot_high")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn_and_split "*xgot_lo<mode>"
+ [(set (match_operand:P 0 "register_operand" "=d")
+ (lo_sum:P (match_operand:P 1 "register_operand" "d")
+ (match_operand:P 2 "got_disp_operand" "")))]
+ "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
+ { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
+ [(set_attr "got" "load")
+ (set_attr "mode" "<MODE>")])
+
+;; Insns to fetch a symbol from a normal GOT.
+
+(define_insn_and_split "*got_disp<mode>"
+ [(set (match_operand:P 0 "register_operand" "=d")
+ (match_operand:P 1 "got_disp_operand" ""))]
+ "TARGET_EXPLICIT_RELOCS && !mips_split_p[SYMBOL_GOT_DISP]"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (match_dup 2))]
+ { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_DISP); }
+ [(set_attr "got" "load")
+ (set_attr "mode" "<MODE>")])
+
+;; Insns for loading the "page" part of a page/ofst address from the GOT.
+
+(define_insn_and_split "*got_page<mode>"
+ [(set (match_operand:P 0 "register_operand" "=d")
+ (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
+ "TARGET_EXPLICIT_RELOCS && !mips_split_hi_p[SYMBOL_GOT_PAGE_OFST]"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (match_dup 2))]
+ { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_PAGE); }
+ [(set_attr "got" "load")
+ (set_attr "mode" "<MODE>")])
+
+;; Convenience expander that generates the rhs of a load_got<mode> insn.
+(define_expand "unspec_got<mode>"
+ [(unspec:P [(match_operand:P 0)
+ (match_operand:P 1)] UNSPEC_LOAD_GOT)])
+
+;; Lower-level instructions for loading an address from the GOT.
+;; We could use MEMs, but an unspec gives more optimization
+;; opportunities.
+
+(define_insn "load_got<mode>"
+ [(set (match_operand:P 0 "register_operand" "=d")
+ (unspec:P [(match_operand:P 1 "register_operand" "d")
+ (match_operand:P 2 "immediate_operand" "")]
+ UNSPEC_LOAD_GOT))]
""
- "*
-{
- if (TARGET_MIPS16)
- return \"not\\t%0,%1\";
- operands[2] = const0_rtx;
- return \"nor\\t%0,%z2,%1\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
+ "<load>\t%0,%R2(%1)"
+ [(set_attr "got" "load")
+ (set_attr "mode" "<MODE>")])
+
+;; Instructions for adding the low 16 bits of an address to a register.
+;; Operand 2 is the address: mips_print_operand works out which relocation
+;; should be applied.
+
+(define_insn "*low<mode>"
+ [(set (match_operand:P 0 "register_operand" "=d")
+ (lo_sum:P (match_operand:P 1 "register_operand" "d")
+ (match_operand:P 2 "immediate_operand" "")))]
+ "!TARGET_MIPS16"
+ "<d>addiu\t%0,%1,%R2"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "*low<mode>_mips16"
+ [(set (match_operand:P 0 "register_operand" "=d")
+ (lo_sum:P (match_operand:P 1 "register_operand" "0")
+ (match_operand:P 2 "immediate_operand" "")))]
+ "TARGET_MIPS16"
+ "<d>addiu\t%0,%R2"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "<MODE>")
+ (set_attr "extended_mips16" "yes")])
-(define_insn "one_cmpldi2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (not:DI (match_operand:DI 1 "se_register_operand" "d")))]
+;; Expose MIPS16 uses of the global pointer after reload if the function
+;; is responsible for setting up the register itself.
+(define_split
+ [(set (match_operand:GPR 0 "d_operand")
+ (const:GPR (unspec:GPR [(const_int 0)] UNSPEC_GP)))]
+ "TARGET_MIPS16 && TARGET_USE_GOT && reload_completed"
+ [(set (match_dup 0) (match_dup 1))]
+ { operands[1] = pic_offset_table_rtx; })
+
+;; Allow combine to split complex const_int load sequences, using operand 2
+;; to store the intermediate results. See move_operand for details.
+(define_split
+ [(set (match_operand:GPR 0 "register_operand")
+ (match_operand:GPR 1 "splittable_const_int_operand"))
+ (clobber (match_operand:GPR 2 "register_operand"))]
""
- "*
+ [(const_int 0)]
{
- if (TARGET_MIPS16)
- {
- if (TARGET_64BIT)
- return \"not\\t%0,%1\";
- return \"not\\t%M0,%M1\;not\\t%L0,%L1\";
- }
- operands[2] = const0_rtx;
- if (TARGET_64BIT)
- return \"nor\\t%0,%z2,%1\";
- return \"nor\\t%M0,%z2,%M1\;nor\\t%L0,%z2,%L1\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set (attr "length")
- (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
- (const_int 4)
- (const_int 8)))])
+ mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
+ DONE;
+})
+;; Likewise, for symbolic operands.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (not:DI (match_operand:DI 1 "register_operand" "")))]
- "reload_completed && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
-
- [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0)))
- (set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))]
- "")
+ [(set (match_operand:P 0 "register_operand")
+ (match_operand:P 1))
+ (clobber (match_operand:P 2 "register_operand"))]
+ "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
+ [(set (match_dup 0) (match_dup 3))]
+{
+ mips_split_symbol (operands[2], operands[1],
+ MAX_MACHINE_MODE, &operands[3]);
+})
-\f
-;;
-;; ....................
-;;
-;; LOGICAL
-;;
-;; ....................
-;;
+;; 64-bit integer moves
-;; Many of these instructions uses trivial define_expands, because we
-;; want to use a different set of constraints when TARGET_MIPS16.
+;; Unlike most other insns, the move insns can't be split with
+;; different predicates, because register spilling and other parts of
+;; the compiler, have memoized the insn number already.
-(define_expand "andsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
- (match_operand:SI 2 "uns_arith_operand" "d,K")))]
+(define_expand "movdi"
+ [(set (match_operand:DI 0 "")
+ (match_operand:DI 1 ""))]
""
- "
{
- if (TARGET_MIPS16)
- operands[2] = force_reg (SImode, operands[2]);
-}")
+ if (mips_legitimize_move (DImode, operands[0], operands[1]))
+ DONE;
+})
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
- (match_operand:SI 2 "uns_arith_operand" "d,K")))]
- "!TARGET_MIPS16"
- "@
- and\\t%0,%1,%2
- andi\\t%0,%1,%x2"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
+;; For mips16, we need a special case to handle storing $31 into
+;; memory, since we don't have a constraint to match $31. This
+;; instruction can be generated by save_restore_insns.
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d")
- (and:SI (match_operand:SI 1 "register_operand" "%0")
- (match_operand:SI 2 "register_operand" "d")))]
+(define_insn "*mov<mode>_ra"
+ [(set (match_operand:GPR 0 "stack_operand" "=m")
+ (reg:GPR 31))]
"TARGET_MIPS16"
- "and\\t%0,%2"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-(define_expand "anddi3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (and:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))]
- "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
- "
-{
- if (TARGET_MIPS16)
- operands[2] = force_reg (DImode, operands[2]);
-}")
+ "<store>\t$31,%0"
+ [(set_attr "move_type" "store")
+ (set_attr "mode" "<MODE>")])
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d")
- (and:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))]
- "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
- "*
-{
- if (TARGET_64BIT)
- return \"and\\t%0,%1,%2\";
- return \"and\\t%M0,%M1,%M2\;and\\t%L0,%L1,%L2\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set (attr "length")
- (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
- (const_int 4)
- (const_int 8)))])
+(define_insn "*movdi_32bit"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*d,*m,*B*C*D,*B*C*D,*d,*m")
+ (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*J*d,*m,*f,*f,*d,*m,*B*C*D,*B*C*D"))]
+ "!TARGET_64BIT && !TARGET_MIPS16
+ && (register_operand (operands[0], DImode)
+ || reg_or_0_operand (operands[1], DImode))"
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore")
+ (set_attr "mode" "DI")])
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d")
- (and:DI (match_operand:DI 1 "se_register_operand" "0")
- (match_operand:DI 2 "se_register_operand" "d")))]
- "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && TARGET_MIPS16"
- "*
-{
- if (TARGET_64BIT)
- return \"and\\t%0,%2\";
- return \"and\\t%M0,%M2\;and\\t%L0,%L2\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set (attr "length")
- (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
- (const_int 4)
- (const_int 8)))])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (and:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "register_operand" "")))]
- "reload_completed && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
-
- [(set (subreg:SI (match_dup 0) 0) (and:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
- (set (subreg:SI (match_dup 0) 4) (and:SI (subreg:SI (match_dup 1) 4) (subreg:SI (match_dup 2) 4)))]
- "")
-
-(define_insn "anddi3_internal1"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (and:DI (match_operand:DI 1 "se_register_operand" "%d,d")
- (match_operand:DI 2 "se_uns_arith_operand" "d,K")))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "@
- and\\t%0,%1,%2
- andi\\t%0,%1,%x2"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
-
-(define_expand "iorsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
- (match_operand:SI 2 "uns_arith_operand" "d,K")))]
- ""
- "
-{
- if (TARGET_MIPS16)
- operands[2] = force_reg (SImode, operands[2]);
-}")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
- (match_operand:SI 2 "uns_arith_operand" "d,K")))]
- "!TARGET_MIPS16"
- "@
- or\\t%0,%1,%2
- ori\\t%0,%1,%x2"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ior:SI (match_operand:SI 1 "register_operand" "%0")
- (match_operand:SI 2 "register_operand" "d")))]
- "TARGET_MIPS16"
- "or\\t%0,%2"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-;;; ??? There is no iordi3 pattern which accepts 'K' constants when
-;;; TARGET_64BIT
-
-(define_expand "iordi3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ior:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))]
- "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
- "")
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ior:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))]
- "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
- "*
-{
- if (TARGET_64BIT)
- return \"or\\t%0,%1,%2\";
- return \"or\\t%M0,%M1,%M2\;or\\t%L0,%L1,%L2\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set (attr "length")
- (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
- (const_int 4)
- (const_int 8)))])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ior:DI (match_operand:DI 1 "se_register_operand" "0")
- (match_operand:DI 2 "se_register_operand" "d")))]
- "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && TARGET_MIPS16"
- "*
-{
- if (TARGET_64BIT)
- return \"or\\t%0,%2\";
- return \"or\\t%M0,%M2\;or\\t%L0,%L2\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set (attr "length")
- (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
- (const_int 4)
- (const_int 8)))])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ior:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "register_operand" "")))]
- "reload_completed && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
-
- [(set (subreg:SI (match_dup 0) 0) (ior:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
- (set (subreg:SI (match_dup 0) 4) (ior:SI (subreg:SI (match_dup 1) 4) (subreg:SI (match_dup 2) 4)))]
- "")
-
-(define_expand "xorsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
- (match_operand:SI 2 "uns_arith_operand" "d,K")))]
- ""
- "")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
- (match_operand:SI 2 "uns_arith_operand" "d,K")))]
- "!TARGET_MIPS16"
- "@
- xor\\t%0,%1,%2
- xori\\t%0,%1,%x2"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,t,t")
- (xor:SI (match_operand:SI 1 "uns_arith_operand" "%0,d,d")
- (match_operand:SI 2 "uns_arith_operand" "d,K,d")))]
- "TARGET_MIPS16"
- "@
- xor\\t%0,%2
- cmpi\\t%1,%2
- cmp\\t%1,%2"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr_alternative "length"
- [(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
- (const_int 4)
- (const_int 8))
- (const_int 4)])])
-
-;; ??? If delete the 32-bit long long patterns, then could merge this with
-;; the following xordi3_internal pattern.
-(define_expand "xordi3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (xor:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))]
- "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
- "")
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d")
- (xor:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))]
- "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
- "*
-{
- if (TARGET_64BIT)
- return \"xor\\t%0,%1,%2\";
- return \"xor\\t%M0,%M1,%M2\;xor\\t%L0,%L1,%L2\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set (attr "length")
- (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
- (const_int 4)
- (const_int 8)))])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d")
- (xor:DI (match_operand:DI 1 "se_register_operand" "0")
- (match_operand:DI 2 "se_register_operand" "d")))]
- "!TARGET_64BIT && TARGET_MIPS16"
- "xor\\t%M0,%M2\;xor\\t%L0,%L2"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,t,t")
- (xor:DI (match_operand:DI 1 "se_register_operand" "%0,d,d")
- (match_operand:DI 2 "se_uns_arith_operand" "d,K,d")))]
- "TARGET_64BIT && TARGET_MIPS16"
- "@
- xor\\t%0,%2
- cmpi\\t%1,%2
- cmp\\t%1,%2"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr_alternative "length"
- [(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
- (const_int 4)
- (const_int 8))
- (const_int 4)])])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (xor:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "register_operand" "")))]
- "reload_completed && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
-
- [(set (subreg:SI (match_dup 0) 0) (xor:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
- (set (subreg:SI (match_dup 0) 4) (xor:SI (subreg:SI (match_dup 1) 4) (subreg:SI (match_dup 2) 4)))]
- "")
+(define_insn "*movdi_32bit_mips16"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
+ (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
+ "!TARGET_64BIT && TARGET_MIPS16
+ && (register_operand (operands[0], DImode)
+ || register_operand (operands[1], DImode))"
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
+ (set_attr "mode" "DI")])
-(define_insn "xordi3_immed"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (xor:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_uns_arith_operand" "K")))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "xori\\t%0,%1,%x2"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
+(define_insn "*movdi_64bit"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m")
+ (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
+ "TARGET_64BIT && !TARGET_MIPS16
+ && (register_operand (operands[0], DImode)
+ || reg_or_0_operand (operands[1], DImode))"
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
+ (set_attr "mode" "DI")])
-(define_insn "*norsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (and:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
- (not:SI (match_operand:SI 2 "register_operand" "d"))))]
- "!TARGET_MIPS16"
- "nor\\t%0,%z1,%z2"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
+(define_insn "*movdi_64bit_mips16"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
+ (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
+ "TARGET_64BIT && TARGET_MIPS16
+ && (register_operand (operands[0], DImode)
+ || register_operand (operands[1], DImode))"
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
+ (set_attr "mode" "DI")])
-(define_insn "*nordi3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (and:DI (not:DI (match_operand:DI 1 "se_register_operand" "d"))
- (not:DI (match_operand:DI 2 "se_register_operand" "d"))))]
- "!TARGET_MIPS16"
- "*
-{
- if (TARGET_64BIT)
- return \"nor\\t%0,%z1,%z2\";
- return \"nor\\t%M0,%M1,%M2\;nor\\t%L0,%L1,%L2\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set (attr "length")
- (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
- (const_int 4)
- (const_int 8)))])
+;; On the mips16, we can split ld $r,N($r) into an add and a load,
+;; when the original load is a 4 byte instruction but the add and the
+;; load are 2 2 byte instructions.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (and:DI (not:DI (match_operand:DI 1 "register_operand" ""))
- (not:DI (match_operand:DI 2 "register_operand" ""))))]
- "reload_completed && !TARGET_MIPS16 && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
-
- [(set (subreg:SI (match_dup 0) 0) (and:SI (not:SI (subreg:SI (match_dup 1) 0)) (not:SI (subreg:SI (match_dup 2) 0))))
- (set (subreg:SI (match_dup 0) 4) (and:SI (not:SI (subreg:SI (match_dup 1) 4)) (not:SI (subreg:SI (match_dup 2) 4))))]
- "")
-\f
-;;
-;; ....................
-;;
-;; TRUNCATION
-;;
-;; ....................
-
-(define_insn "truncdfsf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "cvt.s.d\\t%0,%1"
- [(set_attr "type" "fcvt")
- (set_attr "mode" "SF")])
-
-(define_insn "truncdisi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (truncate:SI (match_operand:DI 1 "se_register_operand" "d")))]
- "TARGET_64BIT"
- "*
-{
- if (TARGET_MIPS16)
- return \"dsll\\t%0,%1,32\;dsra\\t%0,32\";
- return \"dsll\\t%0,%1,32\;dsra\\t%0,%0,32\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "SI")
- (set (attr "length") (if_then_else (eq (symbol_ref "mips16") (const_int 0))
- (const_int 8)
- (const_int 16)))])
-
-(define_insn "truncdihi2"
- [(set (match_operand:HI 0 "register_operand" "=d")
- (truncate:HI (match_operand:DI 1 "se_register_operand" "d")))]
- "TARGET_64BIT"
- "*
-{
- if (TARGET_MIPS16)
- return \"dsll\\t%0,%1,48\;dsra\\t%0,48\";
- return \"andi\\t%0,%1,0xffff\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "HI")
- (set (attr "length") (if_then_else (eq (symbol_ref "mips16") (const_int 0))
- (const_int 4)
- (const_int 16)))])
-(define_insn "truncdiqi2"
- [(set (match_operand:QI 0 "register_operand" "=d")
- (truncate:QI (match_operand:DI 1 "se_register_operand" "d")))]
- "TARGET_64BIT"
- "*
-{
- if (TARGET_MIPS16)
- return \"dsll\\t%0,%1,56\;dsra\\t%0,56\";
- return \"andi\\t%0,%1,0x00ff\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "QI")
- (set (attr "length") (if_then_else (eq (symbol_ref "mips16") (const_int 0))
- (const_int 4)
- (const_int 16)))])
-
-;; Combiner patterns to optimize shift/truncate combinations.
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d")
- (truncate:SI (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "small_int" "I"))))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "*
+ [(set (match_operand:DI 0 "d_operand")
+ (mem:DI (plus:DI (match_dup 0)
+ (match_operand:DI 1 "const_int_operand"))))]
+ "TARGET_64BIT && TARGET_MIPS16 && reload_completed
+ && !TARGET_DEBUG_D_MODE
+ && ((INTVAL (operands[1]) < 0
+ && INTVAL (operands[1]) >= -0x10)
+ || (INTVAL (operands[1]) >= 32 * 8
+ && INTVAL (operands[1]) <= 31 * 8 + 0x8)
+ || (INTVAL (operands[1]) >= 0
+ && INTVAL (operands[1]) < 32 * 8
+ && (INTVAL (operands[1]) & 7) != 0))"
+ [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
+ (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
{
- int shift_amt = INTVAL (operands[2]) & 0x3f;
+ HOST_WIDE_INT val = INTVAL (operands[1]);
- if (shift_amt < 32)
- {
- operands[2] = GEN_INT (32 - shift_amt);
- return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\";
- }
- else
+ if (val < 0)
+ operands[2] = const0_rtx;
+ else if (val >= 32 * 8)
{
- operands[2] = GEN_INT (shift_amt);
- return \"dsra\\t%0,%1,%2\";
- }
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "SI")
- (set_attr "length" "8")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d")
- (truncate:SI (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "small_int" "I"))))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "*
-{
- int shift_amt = INTVAL (operands[2]) & 0x3f;
+ int off = val & 7;
- if (shift_amt < 32)
- {
- operands[2] = GEN_INT (32 - shift_amt);
- return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\";
+ operands[1] = GEN_INT (0x8 + off);
+ operands[2] = GEN_INT (val - off - 0x8);
}
- else if (shift_amt == 32)
- return \"dsra\\t%0,%1,32\";
else
{
- operands[2] = GEN_INT (shift_amt);
- return \"dsrl\\t%0,%1,%2\";
- }
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "SI")
- (set_attr "length" "8")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d")
- (truncate:SI (ashift:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "small_int" "I"))))]
- "TARGET_64BIT"
- "*
-{
- int shift_amt = INTVAL (operands[2]) & 0x3f;
+ int off = val & 7;
- if (shift_amt < 32)
- {
- operands[2] = GEN_INT (32 + shift_amt);
- if (TARGET_MIPS16)
- return \"dsll\\t%0,%1,%2\;dsra\\t%0,32\";
- return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\";
+ operands[1] = GEN_INT (off);
+ operands[2] = GEN_INT (val - off);
}
- else
- return \"move\\t%0,%.\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "SI")
- (set_attr "length" "8")])
-
-;; Combiner patterns to optimize truncate/zero_extend combinations.
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d")
- (zero_extend:SI (truncate:HI
- (match_operand:DI 1 "se_register_operand" "d"))))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "andi\\t%0,%1,0xffff"
- [(set_attr "type" "darith")
- (set_attr "mode" "SI")])
+})
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d")
- (zero_extend:SI (truncate:QI
- (match_operand:DI 1 "se_register_operand" "d"))))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "andi\\t%0,%1,0xff"
- [(set_attr "type" "darith")
- (set_attr "mode" "SI")])
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=d")
- (zero_extend:HI (truncate:QI
- (match_operand:DI 1 "se_register_operand" "d"))))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "andi\\t%0,%1,0xff"
- [(set_attr "type" "darith")
- (set_attr "mode" "HI")])
-\f
-;;
-;; ....................
-;;
-;; ZERO EXTENSION
-;;
-;; ....................
-
-;; Extension insns.
-;; Those for integer source operand are ordered widest source type first.
-
-(define_expand "zero_extendsidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
- "TARGET_64BIT"
- "
-{
- if ((optimize || TARGET_MIPS16) && GET_CODE (operands[1]) == MEM)
- operands[1] = force_not_mem (operands[1]);
-
- if (GET_CODE (operands[1]) != MEM)
- {
- rtx op1 = gen_lowpart (DImode, operands[1]);
- rtx temp = gen_reg_rtx (DImode);
- rtx shift = GEN_INT (32);
-
- emit_insn (gen_ashldi3 (temp, op1, shift));
- emit_insn (gen_lshrdi3 (operands[0], temp, shift));
- DONE;
- }
-}")
+;; 32-bit Integer moves
-(define_insn "zero_extendsidi2_internal"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (zero_extend:DI (match_operand:SI 1 "memory_operand" "R,m")))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "load")
- (set_attr "mode" "DI")
- (set_attr "length" "4,8")])
-
-(define_expand "zero_extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
- ""
- "
-{
- if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
- {
- rtx op = gen_lowpart (SImode, operands[1]);
- rtx temp = force_reg (SImode, GEN_INT (0xffff));
-
- emit_insn (gen_andsi3 (operands[0], op, temp));
- DONE;
- }
-}")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d,d")
- (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
- "!TARGET_MIPS16"
- "*
-{
- if (which_alternative == 0)
- return \"andi\\t%0,%1,0xffff\";
- else
- return mips_move_1word (operands, insn, TRUE);
-}"
- [(set_attr "type" "arith,load,load")
- (set_attr "mode" "SI")
- (set_attr "length" "4,4,8")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (zero_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
- "TARGET_MIPS16"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "load,load")
- (set_attr "mode" "SI")
- (set_attr "length" "4,8")])
-
-(define_expand "zero_extendhidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
- "TARGET_64BIT"
- "
-{
- if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
- {
- rtx op = gen_lowpart (DImode, operands[1]);
- rtx temp = force_reg (DImode, GEN_INT (0xffff));
-
- emit_insn (gen_anddi3 (operands[0], op, temp));
- DONE;
- }
-}")
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d,d")
- (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "*
-{
- if (which_alternative == 0)
- return \"andi\\t%0,%1,0xffff\";
- else
- return mips_move_1word (operands, insn, TRUE);
-}"
- [(set_attr "type" "arith,load,load")
- (set_attr "mode" "DI")
- (set_attr "length" "4,4,8")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (zero_extend:DI (match_operand:HI 1 "memory_operand" "R,m")))]
- "TARGET_64BIT && TARGET_MIPS16"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "load,load")
- (set_attr "mode" "DI")
- (set_attr "length" "4,8")])
-
-(define_expand "zero_extendqihi2"
- [(set (match_operand:HI 0 "register_operand" "")
- (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
- ""
- "
-{
- if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
- {
- rtx op0 = gen_lowpart (SImode, operands[0]);
- rtx op1 = gen_lowpart (SImode, operands[1]);
- rtx temp = force_reg (SImode, GEN_INT (0xff));
-
- emit_insn (gen_andsi3 (op0, op1, temp));
- DONE;
- }
-}")
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=d,d,d")
- (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
- "!TARGET_MIPS16"
- "*
-{
- if (which_alternative == 0)
- return \"andi\\t%0,%1,0x00ff\";
- else
- return mips_move_1word (operands, insn, TRUE);
-}"
- [(set_attr "type" "arith,load,load")
- (set_attr "mode" "HI")
- (set_attr "length" "4,4,8")])
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=d,d")
- (zero_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
- "TARGET_MIPS16"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "load,load")
- (set_attr "mode" "HI")
- (set_attr "length" "4,8")])
-
-(define_expand "zero_extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
- ""
- "
-{
- if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
- {
- rtx op = gen_lowpart (SImode, operands[1]);
- rtx temp = force_reg (SImode, GEN_INT (0xff));
-
- emit_insn (gen_andsi3 (operands[0], op, temp));
- DONE;
- }
-}")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d,d")
- (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
- "!TARGET_MIPS16"
- "*
-{
- if (which_alternative == 0)
- return \"andi\\t%0,%1,0x00ff\";
- else
- return mips_move_1word (operands, insn, TRUE);
-}"
- [(set_attr "type" "arith,load,load")
- (set_attr "mode" "SI")
- (set_attr "length" "4,4,8")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (zero_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
- "TARGET_MIPS16"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "load,load")
- (set_attr "mode" "SI")
- (set_attr "length" "4,8")])
-
-(define_expand "zero_extendqidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
- "TARGET_64BIT"
- "
-{
- if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
- {
- rtx op = gen_lowpart (DImode, operands[1]);
- rtx temp = force_reg (DImode, GEN_INT (0xff));
-
- emit_insn (gen_anddi3 (operands[0], op, temp));
- DONE;
- }
-}")
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d,d")
- (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "*
-{
- if (which_alternative == 0)
- return \"andi\\t%0,%1,0x00ff\";
- else
- return mips_move_1word (operands, insn, TRUE);
-}"
- [(set_attr "type" "arith,load,load")
- (set_attr "mode" "DI")
- (set_attr "length" "4,4,8")])
-
-;; These can be created when a paradoxical subreg operand with an implicit
-;; sign_extend operator is reloaded. Because of the subreg, this is really
-;; a zero extend.
-;; ??? It might be possible to eliminate the need for these patterns by adding
-;; more support to reload for implicit sign_extend operators.
-(define_insn "*paradoxical_extendhidi2"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (sign_extend:DI
- (subreg:SI (match_operand:HI 1 "memory_operand" "R,m") 0)))]
- "TARGET_64BIT"
- "*
-{
- return mips_move_1word (operands, insn, TRUE);
-}"
- [(set_attr "type" "load,load")
- (set_attr "mode" "DI")
- (set_attr "length" "4,8")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (zero_extend:DI (match_operand:QI 1 "memory_operand" "R,m")))]
- "TARGET_64BIT && TARGET_MIPS16"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "load,load")
- (set_attr "mode" "DI")
- (set_attr "length" "4,8")])
-\f
-;;
-;; ....................
-;;
-;; SIGN EXTENSION
-;;
-;; ....................
-
-;; Extension insns.
-;; Those for integer source operand are ordered widest source type first.
-
-;; In 64 bit mode, 32 bit values in general registers are always
-;; correctly sign extended. That means that if the target is a
-;; general register, we can sign extend from SImode to DImode just by
-;; doing a move.
-
-(define_insn "extendsidi2"
- [(set (match_operand:DI 0 "register_operand" "=d,y,d,*d,d,d")
- (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,d,y,*x,R,m")))]
- "TARGET_64BIT"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "move,move,move,hilo,load,load")
- (set_attr "mode" "DI")
- (set_attr "length" "4,4,4,4,4,8")])
-
-;; These patterns originally accepted general_operands, however, slightly
-;; better code is generated by only accepting register_operands, and then
-;; letting combine generate the lh and lb insns.
-
-(define_expand "extendhidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
- "TARGET_64BIT"
- "
-{
- if (optimize && GET_CODE (operands[1]) == MEM)
- operands[1] = force_not_mem (operands[1]);
-
- if (GET_CODE (operands[1]) != MEM)
- {
- rtx op1 = gen_lowpart (DImode, operands[1]);
- rtx temp = gen_reg_rtx (DImode);
- rtx shift = GEN_INT (48);
-
- emit_insn (gen_ashldi3 (temp, op1, shift));
- emit_insn (gen_ashrdi3 (operands[0], temp, shift));
- DONE;
- }
-}")
-
-(define_insn "extendhidi2_internal"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (sign_extend:DI (match_operand:HI 1 "memory_operand" "R,m")))]
- "TARGET_64BIT"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "load")
- (set_attr "mode" "DI")
- (set_attr "length" "4,8")])
-
-(define_expand "extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
- ""
- "
-{
- if (optimize && GET_CODE (operands[1]) == MEM)
- operands[1] = force_not_mem (operands[1]);
-
- if (GET_CODE (operands[1]) != MEM)
- {
- rtx op1 = gen_lowpart (SImode, operands[1]);
- rtx temp = gen_reg_rtx (SImode);
- rtx shift = GEN_INT (16);
-
- emit_insn (gen_ashlsi3 (temp, op1, shift));
- emit_insn (gen_ashrsi3 (operands[0], temp, shift));
- DONE;
- }
-}")
-
-(define_insn "extendhisi2_internal"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
- ""
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "load")
- (set_attr "mode" "SI")
- (set_attr "length" "4,8")])
-
-(define_expand "extendqihi2"
- [(set (match_operand:HI 0 "register_operand" "")
- (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
- ""
- "
-{
- if (optimize && GET_CODE (operands[1]) == MEM)
- operands[1] = force_not_mem (operands[1]);
-
- if (GET_CODE (operands[1]) != MEM)
- {
- rtx op0 = gen_lowpart (SImode, operands[0]);
- rtx op1 = gen_lowpart (SImode, operands[1]);
- rtx temp = gen_reg_rtx (SImode);
- rtx shift = GEN_INT (24);
-
- emit_insn (gen_ashlsi3 (temp, op1, shift));
- emit_insn (gen_ashrsi3 (op0, temp, shift));
- DONE;
- }
-}")
-
-(define_insn "extendqihi2_internal"
- [(set (match_operand:HI 0 "register_operand" "=d,d")
- (sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
- ""
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "load")
- (set_attr "mode" "SI")
- (set_attr "length" "4,8")])
-
-
-(define_expand "extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
- ""
- "
-{
- if (optimize && GET_CODE (operands[1]) == MEM)
- operands[1] = force_not_mem (operands[1]);
-
- if (GET_CODE (operands[1]) != MEM)
- {
- rtx op1 = gen_lowpart (SImode, operands[1]);
- rtx temp = gen_reg_rtx (SImode);
- rtx shift = GEN_INT (24);
-
- emit_insn (gen_ashlsi3 (temp, op1, shift));
- emit_insn (gen_ashrsi3 (operands[0], temp, shift));
- DONE;
- }
-}")
-
-(define_insn "extendqisi2_insn"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
- ""
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "load")
- (set_attr "mode" "SI")
- (set_attr "length" "4,8")])
-
-(define_expand "extendqidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
- "TARGET_64BIT"
- "
-{
- if (optimize && GET_CODE (operands[1]) == MEM)
- operands[1] = force_not_mem (operands[1]);
-
- if (GET_CODE (operands[1]) != MEM)
- {
- rtx op1 = gen_lowpart (DImode, operands[1]);
- rtx temp = gen_reg_rtx (DImode);
- rtx shift = GEN_INT (56);
-
- emit_insn (gen_ashldi3 (temp, op1, shift));
- emit_insn (gen_ashrdi3 (operands[0], temp, shift));
- DONE;
- }
-}")
-
-(define_insn "extendqidi2_insn"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (sign_extend:DI (match_operand:QI 1 "memory_operand" "R,m")))]
- "TARGET_64BIT"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "load")
- (set_attr "mode" "DI")
- (set_attr "length" "4,8")])
-
-
-(define_insn "extendsfdf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "cvt.d.s\\t%0,%1"
- [(set_attr "type" "fcvt")
- (set_attr "mode" "DF")])
-
-\f
-
-;;
-;; ....................
-;;
-;; CONVERSIONS
-;;
-;; ....................
-
-;; The SImode scratch register can not be shared with address regs used for
-;; operand zero, because then the address in the move instruction will be
-;; clobbered. We mark the scratch register as early clobbered to prevent this.
-
-;; We need the ?X in alternative 1 so that it will be chosen only if the
-;; destination is a floating point register. Otherwise, alternative 1 can
-;; have lower cost than alternative 0 (because there is one less loser), and
-;; can be chosen when it won't work (because integral reloads into FP
-;; registers are not supported).
-
-(define_insn "fix_truncdfsi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,*f,R,To")
- (fix:SI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
- (clobber (match_scratch:SI 2 "=d,*d,&d,&d"))
- (clobber (match_scratch:DF 3 "=f,?*X,f,f"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "*
-{
- rtx xoperands[10];
-
- if (which_alternative == 1)
- return \"trunc.w.d %0,%1,%2\";
-
- output_asm_insn (\"trunc.w.d %3,%1,%2\", operands);
-
- xoperands[0] = operands[0];
- xoperands[1] = operands[3];
- output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
- return \"\";
-}"
- [(set_attr "type" "fcvt")
- (set_attr "mode" "DF")
- (set_attr "length" "44,36,40,44")])
-
-
-(define_insn "fix_truncsfsi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,*f,R,To")
- (fix:SI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
- (clobber (match_scratch:SI 2 "=d,*d,&d,&d"))
- (clobber (match_scratch:SF 3 "=f,?*X,f,f"))]
- "TARGET_HARD_FLOAT"
- "*
-{
- rtx xoperands[10];
-
- if (which_alternative == 1)
- return \"trunc.w.s %0,%1,%2\";
-
- output_asm_insn (\"trunc.w.s %3,%1,%2\", operands);
-
- xoperands[0] = operands[0];
- xoperands[1] = operands[3];
- output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
- return \"\";
-}"
- [(set_attr "type" "fcvt")
- (set_attr "mode" "SF")
- (set_attr "length" "44,36,40,44")])
-
-
-;;; ??? trunc.l.d is mentioned in the appendix of the 1993 r4000/r4600 manuals
-;;; but not in the chapter that describes the FPU. It is not mentioned at all
-;;; in the 1991 manuals. The r4000 at Cygnus does not have this instruction.
-
-;;; Deleting this means that we now need two libgcc2.a libraries. One for
-;;; the 32 bit calling convention and one for the 64 bit calling convention.
-
-;;; If this is disabled, then fixuns_truncdfdi2 must be disabled also.
-
-(define_insn "fix_truncdfdi2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,*f,R,To")
- (fix:DI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
- (clobber (match_scratch:DF 2 "=f,?*X,f,f"))]
- "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
- "*
-{
- rtx xoperands[10];
-
- if (which_alternative == 1)
- return \"trunc.l.d %0,%1\";
-
- output_asm_insn (\"trunc.l.d %2,%1\", operands);
-
- xoperands[0] = operands[0];
- xoperands[1] = operands[2];
- output_asm_insn (mips_move_2words (xoperands, insn), xoperands);
- return \"\";
-}"
- [(set_attr "type" "fcvt")
- (set_attr "mode" "DF")
- (set_attr "length" "8,4,8,12")])
-
-
-;;; ??? trunc.l.s is mentioned in the appendix of the 1993 r4000/r4600 manuals
-;;; but not in the chapter that describes the FPU. It is not mentioned at all
-;;; in the 1991 manuals. The r4000 at Cygnus does not have this instruction.
-(define_insn "fix_truncsfdi2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,*f,R,To")
- (fix:DI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
- (clobber (match_scratch:DF 2 "=f,?*X,f,f"))]
- "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
- "*
-{
- rtx xoperands[10];
-
- if (which_alternative == 1)
- return \"trunc.l.s %0,%1\";
-
- output_asm_insn (\"trunc.l.s %2,%1\", operands);
-
- xoperands[0] = operands[0];
- xoperands[1] = operands[2];
- output_asm_insn (mips_move_2words (xoperands, insn), xoperands);
- return \"\";
-}"
- [(set_attr "type" "fcvt")
- (set_attr "mode" "SF")
- (set_attr "length" "8,4,8,12")])
-
-
-(define_insn "floatsidf2"
- [(set (match_operand:DF 0 "register_operand" "=f,f,f")
- (float:DF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "*
-{
- dslots_load_total++;
- if (GET_CODE (operands[1]) == MEM)
- return \"l.s\\t%0,%1%#\;cvt.d.w\\t%0,%0\";
-
- return \"mtc1\\t%1,%0%#\;cvt.d.w\\t%0,%0\";
-}"
- [(set_attr "type" "fcvt")
- (set_attr "mode" "DF")
- (set_attr "length" "12,16,12")])
-
-
-(define_insn "floatdidf2"
- [(set (match_operand:DF 0 "register_operand" "=f,f,f")
- (float:DF (match_operand:DI 1 "se_nonimmediate_operand" "d,R,m")))]
- "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
- "*
-{
- dslots_load_total++;
- if (GET_CODE (operands[1]) == MEM)
- return \"l.d\\t%0,%1%#\;cvt.d.l\\t%0,%0\";
-
- return \"dmtc1\\t%1,%0%#\;cvt.d.l\\t%0,%0\";
-}"
- [(set_attr "type" "fcvt")
- (set_attr "mode" "DF")
- (set_attr "length" "12,16,12")])
-
-
-(define_insn "floatsisf2"
- [(set (match_operand:SF 0 "register_operand" "=f,f,f")
- (float:SF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
- "TARGET_HARD_FLOAT"
- "*
-{
- dslots_load_total++;
- if (GET_CODE (operands[1]) == MEM)
- return \"l.s\\t%0,%1%#\;cvt.s.w\\t%0,%0\";
-
- return \"mtc1\\t%1,%0%#\;cvt.s.w\\t%0,%0\";
-}"
- [(set_attr "type" "fcvt")
- (set_attr "mode" "SF")
- (set_attr "length" "12,16,12")])
-
-
-(define_insn "floatdisf2"
- [(set (match_operand:SF 0 "register_operand" "=f,f,f")
- (float:SF (match_operand:DI 1 "se_nonimmediate_operand" "d,R,m")))]
- "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
- "*
-{
- dslots_load_total++;
- if (GET_CODE (operands[1]) == MEM)
- return \"l.d\\t%0,%1%#\;cvt.s.l\\t%0,%0\";
-
- return \"dmtc1\\t%1,%0%#\;cvt.s.l\\t%0,%0\";
-}"
- [(set_attr "type" "fcvt")
- (set_attr "mode" "SF")
- (set_attr "length" "12,16,12")])
-
-
-(define_expand "fixuns_truncdfsi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "
-{
- rtx reg1 = gen_reg_rtx (DFmode);
- rtx reg2 = gen_reg_rtx (DFmode);
- rtx reg3 = gen_reg_rtx (SImode);
- rtx label1 = gen_label_rtx ();
- rtx label2 = gen_label_rtx ();
- REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31);
-
- if (reg1) /* turn off complaints about unreached code */
- {
- emit_move_insn (reg1, immed_real_const_1 (offset, DFmode));
- do_pending_stack_adjust ();
-
- emit_insn (gen_cmpdf (operands[1], reg1));
- emit_jump_insn (gen_bge (label1));
-
- emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
- emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
- gen_rtx_LABEL_REF (VOIDmode, label2)));
- emit_barrier ();
-
- emit_label (label1);
- emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
- emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
- (BITMASK_HIGH, SImode)));
-
- emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
- emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
-
- emit_label (label2);
-
- /* allow REG_NOTES to be set on last insn (labels don't have enough
- fields, and can't be used for REG_NOTES anyway). */
- emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
- DONE;
- }
-}")
-
-
-(define_expand "fixuns_truncdfdi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
- "
-{
- rtx reg1 = gen_reg_rtx (DFmode);
- rtx reg2 = gen_reg_rtx (DFmode);
- rtx reg3 = gen_reg_rtx (DImode);
- rtx label1 = gen_label_rtx ();
- rtx label2 = gen_label_rtx ();
- REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 63);
-
- if (reg1) /* turn off complaints about unreached code */
- {
- emit_move_insn (reg1, immed_real_const_1 (offset, DFmode));
- do_pending_stack_adjust ();
-
- emit_insn (gen_cmpdf (operands[1], reg1));
- emit_jump_insn (gen_bge (label1));
-
- emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
- emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
- gen_rtx_LABEL_REF (VOIDmode, label2)));
- emit_barrier ();
-
- emit_label (label1);
- emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
- emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
- emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
-
- emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
- emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
-
- emit_label (label2);
-
- /* allow REG_NOTES to be set on last insn (labels don't have enough
- fields, and can't be used for REG_NOTES anyway). */
- emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
- DONE;
- }
-}")
-
-
-(define_expand "fixuns_truncsfsi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT"
- "
-{
- rtx reg1 = gen_reg_rtx (SFmode);
- rtx reg2 = gen_reg_rtx (SFmode);
- rtx reg3 = gen_reg_rtx (SImode);
- rtx label1 = gen_label_rtx ();
- rtx label2 = gen_label_rtx ();
- REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31);
-
- if (reg1) /* turn off complaints about unreached code */
- {
- emit_move_insn (reg1, immed_real_const_1 (offset, SFmode));
- do_pending_stack_adjust ();
-
- emit_insn (gen_cmpsf (operands[1], reg1));
- emit_jump_insn (gen_bge (label1));
-
- emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
- emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
- gen_rtx_LABEL_REF (VOIDmode, label2)));
- emit_barrier ();
-
- emit_label (label1);
- emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
- emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
- (BITMASK_HIGH, SImode)));
-
- emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
- emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
-
- emit_label (label2);
-
- /* allow REG_NOTES to be set on last insn (labels don't have enough
- fields, and can't be used for REG_NOTES anyway). */
- emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
- DONE;
- }
-}")
-
-
-(define_expand "fixuns_truncsfdi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
- "
-{
- rtx reg1 = gen_reg_rtx (SFmode);
- rtx reg2 = gen_reg_rtx (SFmode);
- rtx reg3 = gen_reg_rtx (DImode);
- rtx label1 = gen_label_rtx ();
- rtx label2 = gen_label_rtx ();
- REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 63);
-
- if (reg1) /* turn off complaints about unreached code */
- {
- emit_move_insn (reg1, immed_real_const_1 (offset, SFmode));
- do_pending_stack_adjust ();
-
- emit_insn (gen_cmpsf (operands[1], reg1));
- emit_jump_insn (gen_bge (label1));
-
- emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
- emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
- gen_rtx_LABEL_REF (VOIDmode, label2)));
- emit_barrier ();
-
- emit_label (label1);
- emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
- emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
- emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
-
- emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
- emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
-
- emit_label (label2);
-
- /* allow REG_NOTES to be set on last insn (labels don't have enough
- fields, and can't be used for REG_NOTES anyway). */
- emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
- DONE;
- }
-}")
-
-\f
-;;
-;; ....................
-;;
-;; DATA MOVEMENT
-;;
-;; ....................
-
-;; Bit field extract patterns which use lwl/lwr.
-
-;; ??? There could be HImode variants for the ulh/ulhu/ush macros.
-;; It isn't clear whether this will give better code.
-
-;; Only specify the mode operand 1, the rest are assumed to be word_mode.
-(define_expand "extv"
- [(set (match_operand 0 "register_operand" "")
- (sign_extract (match_operand:QI 1 "memory_operand" "")
- (match_operand 2 "immediate_operand" "")
- (match_operand 3 "immediate_operand" "")))]
- "!TARGET_MIPS16"
- "
-{
- /* If the field does not start on a byte boundary, then fail. */
- if (INTVAL (operands[3]) % 8 != 0)
- FAIL;
-
- /* MIPS I and MIPS II can only handle a 32bit field. */
- if (!TARGET_64BIT && INTVAL (operands[2]) != 32)
- FAIL;
-
- /* MIPS III and MIPS IV can handle both 32bit and 64bit fields. */
- if (TARGET_64BIT
- && INTVAL (operands[2]) != 64
- && INTVAL (operands[2]) != 32)
- FAIL;
-
- /* This can happen for a 64 bit target, when extracting a value from
- a 64 bit union member. extract_bit_field doesn't verify that our
- source matches the predicate, so we force it to be a MEM here. */
- if (GET_CODE (operands[1]) != MEM)
- FAIL;
-
- /* Change the mode to BLKmode for aliasing purposes. */
- operands[1] = adjust_address (operands[1], BLKmode, 0);
-
- /* Otherwise, emit a l[wd]l/l[wd]r pair to load the value. */
- if (INTVAL (operands[2]) == 64)
- emit_insn (gen_movdi_uld (operands[0], operands[1]));
- else
- {
- if (TARGET_64BIT)
- {
- operands[0] = gen_lowpart (SImode, operands[0]);
- if (operands[0] == NULL_RTX)
- FAIL;
- }
- emit_insn (gen_movsi_ulw (operands[0], operands[1]));
- }
- DONE;
-}")
-
-;; Only specify the mode operand 1, the rest are assumed to be word_mode.
-(define_expand "extzv"
- [(set (match_operand 0 "register_operand" "")
- (zero_extract (match_operand:QI 1 "memory_operand" "")
- (match_operand 2 "immediate_operand" "")
- (match_operand 3 "immediate_operand" "")))]
- "!TARGET_MIPS16"
- "
-{
- /* If the field does not start on a byte boundary, then fail. */
- if (INTVAL (operands[3]) % 8 != 0)
- FAIL;
-
- /* MIPS I and MIPS II can only handle a 32bit field. */
- if (!TARGET_64BIT && INTVAL (operands[2]) != 32)
- FAIL;
-
- /* MIPS III and MIPS IV can handle both 32bit and 64bit fields. */
- if (TARGET_64BIT
- && INTVAL (operands[2]) != 64
- && INTVAL (operands[2]) != 32)
- FAIL;
-
- /* This can happen for a 64 bit target, when extracting a value from
- a 64 bit union member. extract_bit_field doesn't verify that our
- source matches the predicate, so we force it to be a MEM here. */
- if (GET_CODE (operands[1]) != MEM)
- FAIL;
-
- /* Change the mode to BLKmode for aliasing purposes. */
- operands[1] = adjust_address (operands[1], BLKmode, 0);
-
- /* Otherwise, emit a lwl/lwr pair to load the value. */
- if (INTVAL (operands[2]) == 64)
- emit_insn (gen_movdi_uld (operands[0], operands[1]));
- else
- {
- if (TARGET_64BIT)
- {
- operands[0] = gen_lowpart (SImode, operands[0]);
- if (operands[0] == NULL_RTX)
- FAIL;
- }
- emit_insn (gen_movsi_ulw (operands[0], operands[1]));
- }
- DONE;
-}")
-
-;; Only specify the mode operands 0, the rest are assumed to be word_mode.
-(define_expand "insv"
- [(set (zero_extract (match_operand:QI 0 "memory_operand" "")
- (match_operand 1 "immediate_operand" "")
- (match_operand 2 "immediate_operand" ""))
- (match_operand 3 "register_operand" ""))]
- "!TARGET_MIPS16"
- "
-{
- /* If the field does not start on a byte boundary, then fail. */
- if (INTVAL (operands[2]) % 8 != 0)
- FAIL;
-
- /* MIPS I and MIPS II can only handle a 32bit field. */
- if (!TARGET_64BIT && INTVAL (operands[1]) != 32)
- FAIL;
-
- /* MIPS III and MIPS IV can handle both 32bit and 64bit fields. */
- if (TARGET_64BIT
- && INTVAL (operands[1]) != 64
- && INTVAL (operands[1]) != 32)
- FAIL;
-
- /* This can happen for a 64 bit target, when storing into a 32 bit union
- member. store_bit_field doesn't verify that our target matches the
- predicate, so we force it to be a MEM here. */
- if (GET_CODE (operands[0]) != MEM)
- FAIL;
-
- /* Change the mode to BLKmode for aliasing purposes. */
- operands[0] = adjust_address (operands[0], BLKmode, 0);
-
- /* Otherwise, emit a s[wd]l/s[wd]r pair to load the value. */
- if (INTVAL (operands[1]) == 64)
- emit_insn (gen_movdi_usd (operands[0], operands[3]));
- else
- {
- if (TARGET_64BIT)
- {
- operands[3] = gen_lowpart (SImode, operands[3]);
- if (operands[3] == NULL_RTX)
- FAIL;
- }
- emit_insn (gen_movsi_usw (operands[0], operands[3]));
- }
- DONE;
-}")
-
-;; unaligned word moves generated by the bit field patterns
-
-(define_insn "movsi_ulw"
- [(set (match_operand:SI 0 "register_operand" "=&d,&d")
- (unspec:SI [(match_operand:BLK 1 "general_operand" "R,o")] 0))]
- "!TARGET_MIPS16"
- "*
-{
- rtx offset = const0_rtx;
- rtx addr = XEXP (operands[1], 0);
- rtx mem_addr = eliminate_constant_term (addr, &offset);
- const char *ret;
-
- if (TARGET_STATS)
- mips_count_memory_refs (operands[1], 2);
-
- /* The stack/frame pointers are always aligned, so we can convert
- to the faster lw if we are referencing an aligned stack location. */
-
- if ((INTVAL (offset) & 3) == 0
- && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
- ret = \"lw\\t%0,%1\";
- else
- ret = \"ulw\\t%0,%1\";
-
- return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn);
-}"
- [(set_attr "type" "load,load")
- (set_attr "mode" "SI")
- (set_attr "length" "8,16")])
-
-(define_insn "movsi_usw"
- [(set (match_operand:BLK 0 "memory_operand" "=R,o")
- (unspec:BLK [(match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")] 1))]
- "!TARGET_MIPS16"
- "*
-{
- rtx offset = const0_rtx;
- rtx addr = XEXP (operands[0], 0);
- rtx mem_addr = eliminate_constant_term (addr, &offset);
-
- if (TARGET_STATS)
- mips_count_memory_refs (operands[0], 2);
-
- /* The stack/frame pointers are always aligned, so we can convert
- to the faster sw if we are referencing an aligned stack location. */
-
- if ((INTVAL (offset) & 3) == 0
- && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
- return \"sw\\t%z1,%0\";
-
- return \"usw\\t%z1,%0\";
-}"
- [(set_attr "type" "store")
- (set_attr "mode" "SI")
- (set_attr "length" "8,16")])
-
-;; Bit field extract patterns which use ldl/ldr.
-
-;; unaligned double word moves generated by the bit field patterns
-
-(define_insn "movdi_uld"
- [(set (match_operand:DI 0 "register_operand" "=&d,&d")
- (unspec:DI [(match_operand:BLK 1 "general_operand" "R,o")] 0))]
- ""
- "*
-{
- rtx offset = const0_rtx;
- rtx addr = XEXP (operands[1], 0);
- rtx mem_addr = eliminate_constant_term (addr, &offset);
- const char *ret;
-
- if (TARGET_STATS)
- mips_count_memory_refs (operands[1], 2);
-
- /* The stack/frame pointers are always aligned, so we can convert
- to the faster lw if we are referencing an aligned stack location. */
-
- if ((INTVAL (offset) & 7) == 0
- && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
- ret = \"ld\\t%0,%1\";
- else
- ret = \"uld\\t%0,%1\";
-
- return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn);
-}"
- [(set_attr "type" "load,load")
- (set_attr "mode" "SI")
- (set_attr "length" "8,16")])
-
-(define_insn "movdi_usd"
- [(set (match_operand:BLK 0 "memory_operand" "=R,o")
- (unspec:BLK [(match_operand:DI 1 "reg_or_0_operand" "dJ,dJ")] 111))]
- ""
- "*
-{
- rtx offset = const0_rtx;
- rtx addr = XEXP (operands[0], 0);
- rtx mem_addr = eliminate_constant_term (addr, &offset);
-
- if (TARGET_STATS)
- mips_count_memory_refs (operands[0], 2);
-
- /* The stack/frame pointers are always aligned, so we can convert
- to the faster sw if we are referencing an aligned stack location. */
-
- if ((INTVAL (offset) & 7) == 0
- && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
- return \"sd\\t%z1,%0\";
-
- return \"usd\\t%z1,%0\";
-}"
- [(set_attr "type" "store")
- (set_attr "mode" "SI")
- (set_attr "length" "8,16")])
-
-;; These two patterns support loading addresses with two instructions instead
-;; of using the macro instruction la.
-
-;; ??? mips_move_1word has support for HIGH, so this pattern may be
-;; unnecessary.
-
-(define_insn "high"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (high:SI (match_operand:SI 1 "immediate_operand" "")))]
- "mips_split_addresses && !TARGET_MIPS16"
- "lui\\t%0,%%hi(%1) # high"
- [(set_attr "type" "move")])
-
-(define_insn "low"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "immediate_operand" "")))]
- "mips_split_addresses && !TARGET_MIPS16"
- "addiu\\t%0,%1,%%lo(%2) # low"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-;; 64-bit integer moves
-
-;; Unlike most other insns, the move insns can't be split with
-;; different predicates, because register spilling and other parts of
-;; the compiler, have memoized the insn number already.
-
-(define_expand "movdi"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (match_operand:DI 1 "general_operand" ""))]
- ""
- "
-{
- if (mips_split_addresses && mips_check_split (operands[1], DImode))
- {
- enum machine_mode mode = GET_MODE (operands[0]);
- rtx tem = ((reload_in_progress | reload_completed)
- ? operands[0] : gen_reg_rtx (mode));
-
- emit_insn (gen_rtx_SET (VOIDmode, tem,
- gen_rtx_HIGH (mode, operands[1])));
-
- operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]);
- }
-
- /* If we are generating embedded PIC code, and we are referring to a
- symbol in the .text section, we must use an offset from the start
- of the function. */
- if (TARGET_EMBEDDED_PIC
- && (GET_CODE (operands[1]) == LABEL_REF
- || (GET_CODE (operands[1]) == SYMBOL_REF
- && ! SYMBOL_REF_FLAG (operands[1]))))
- {
- rtx temp;
-
- temp = embedded_pic_offset (operands[1]);
- temp = gen_rtx_PLUS (Pmode, embedded_pic_fnaddr_rtx,
- force_reg (DImode, temp));
- emit_move_insn (operands[0], force_reg (DImode, temp));
- DONE;
- }
-
- /* If operands[1] is a constant address illegal for pic, then we need to
- handle it just like LEGITIMIZE_ADDRESS does. */
- if (flag_pic && pic_address_needs_scratch (operands[1]))
- {
- rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0));
- rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
-
- if (! SMALL_INT (temp2))
- temp2 = force_reg (DImode, temp2);
-
- emit_move_insn (operands[0], gen_rtx_PLUS (DImode, temp, temp2));
- DONE;
- }
-
- /* On the mips16, we can handle a GP relative reference by adding in
- $gp. We need to check the name to see whether this is a string
- constant. */
- if (TARGET_MIPS16
- && register_operand (operands[0], DImode)
- && GET_CODE (operands[1]) == SYMBOL_REF
- && SYMBOL_REF_FLAG (operands[1]))
- {
- const char *name = XSTR (operands[1], 0);
-
- if (name[0] != '*'
- || strncmp (name + 1, LOCAL_LABEL_PREFIX,
- sizeof LOCAL_LABEL_PREFIX - 1) != 0)
- {
- rtx base_reg;
-
- if (reload_in_progress || reload_completed)
- {
- /* In movsi we use the constant table here. However, in
- this case, we're better off copying $28 into a
- register and adding, because the constant table entry
- would be 8 bytes. */
- base_reg = operands[0];
- emit_move_insn (base_reg,
- gen_rtx (CONST, DImode,
- gen_rtx (REG, DImode,
- GP_REG_FIRST + 28)));
- }
- else
- {
- base_reg = gen_reg_rtx (Pmode);
- emit_move_insn (base_reg, mips16_gp_pseudo_reg ());
- }
-
- emit_move_insn (operands[0],
- gen_rtx (PLUS, Pmode, base_reg,
- mips16_gp_offset (operands[1])));
- DONE;
- }
- }
-
- if ((reload_in_progress | reload_completed) == 0
- && !register_operand (operands[0], DImode)
- && !register_operand (operands[1], DImode)
- && (TARGET_MIPS16
- || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
- && operands[1] != CONST0_RTX (DImode))))
- {
- rtx temp = force_reg (DImode, operands[1]);
- emit_move_insn (operands[0], temp);
- DONE;
- }
-}")
-
-;; For mips16, we need a special case to handle storing $31 into
-;; memory, since we don't have a constraint to match $31. This
-;; instruction can be generated by save_restore_insns.
-
-(define_insn ""
- [(set (match_operand:DI 0 "memory_operand" "=R,m")
- (reg:DI 31))]
- "TARGET_MIPS16 && TARGET_64BIT"
- "*
-{
- operands[1] = gen_rtx (REG, DImode, 31);
- return mips_move_2words (operands, insn);
-}"
- [(set_attr "type" "store")
- (set_attr "mode" "DI")
- (set_attr "length" "4,8")])
-
-(define_insn "movdi_internal"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,R,o,*x,*d,*x")
- (match_operand:DI 1 "general_operand" "d,iF,R,o,d,d,J,*x,*d"))]
- "!TARGET_64BIT && !TARGET_MIPS16
- && (register_operand (operands[0], DImode)
- || register_operand (operands[1], DImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
- || operands[1] == CONST0_RTX (DImode))"
- "* return mips_move_2words (operands, insn); "
- [(set_attr "type" "move,arith,load,load,store,store,hilo,hilo,hilo")
- (set_attr "mode" "DI")
- (set_attr "length" "8,16,8,16,8,16,8,8,8")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,To,*d")
- (match_operand:DI 1 "general_operand" "d,d,y,K,N,R,To,d,d,*x"))]
- "!TARGET_64BIT && TARGET_MIPS16
- && (register_operand (operands[0], DImode)
- || register_operand (operands[1], DImode))"
- "* return mips_move_2words (operands, insn);"
- [(set_attr "type" "move,move,move,arith,arith,load,load,store,store,hilo")
- (set_attr "mode" "DI")
- (set_attr "length" "8,8,8,8,12,8,16,8,16,8")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "register_operand" ""))]
- "reload_completed && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
-
- [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
- (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
- "")
-
-(define_insn "movdi_internal2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*x,*d,*x,*a")
- (match_operand:DI 1 "movdi_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,J,*x,*d,*J"))]
- "TARGET_64BIT && !TARGET_MIPS16
- && (register_operand (operands[0], DImode)
- || se_register_operand (operands[1], DImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
- || operands[1] == CONST0_RTX (DImode))"
- "* return mips_move_2words (operands, insn); "
- [(set_attr "type" "move,load,arith,arith,load,load,store,store,hilo,hilo,hilo,hilo")
- (set_attr "mode" "DI")
- (set_attr "length" "4,8,4,8,4,8,4,8,4,4,4,8")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,R,m,*d")
- (match_operand:DI 1 "movdi_operand" "d,d,y,K,N,s,R,m,d,d,*x"))]
- "TARGET_64BIT && TARGET_MIPS16
- && (register_operand (operands[0], DImode)
- || se_register_operand (operands[1], DImode))"
- "* return mips_move_2words (operands, insn);"
- [(set_attr "type" "move,move,move,arith,arith,arith,load,load,store,store,hilo")
- (set_attr "mode" "DI")
- (set_attr_alternative "length"
- [(const_int 4)
- (const_int 4)
- (const_int 4)
- (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
- (const_int 4)
- (const_int 8))
- (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
- (const_int 8)
- (const_int 12))
- (if_then_else (match_operand:VOID 1 "m16_usym5_4" "")
- (const_int 4)
- (const_int 8))
- (const_int 4)
- (const_int 8)
- (const_int 4)
- (const_int 8)
- (const_int 4)])])
-
-;; On the mips16, we can split ld $r,N($r) into an add and a load,
-;; when the original load is a 4 byte instruction but the add and the
-;; load are 2 2 byte instructions.
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (mem:DI (plus:DI (match_dup 0)
- (match_operand:DI 1 "const_int_operand" ""))))]
- "TARGET_64BIT && TARGET_MIPS16 && reload_completed
- && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
- && ((INTVAL (operands[1]) < 0
- && INTVAL (operands[1]) >= -0x10)
- || (INTVAL (operands[1]) >= 32 * 8
- && INTVAL (operands[1]) <= 31 * 8 + 0x8)
- || (INTVAL (operands[1]) >= 0
- && INTVAL (operands[1]) < 32 * 8
- && (INTVAL (operands[1]) & 7) != 0))"
- [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
- (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
- "
-{
- HOST_WIDE_INT val = INTVAL (operands[1]);
-
- if (val < 0)
- operands[2] = GEN_INT (0);
- else if (val >= 32 * 8)
- {
- int off = val & 7;
-
- operands[1] = GEN_INT (0x8 + off);
- operands[2] = GEN_INT (val - off - 0x8);
- }
- else
- {
- int off = val & 7;
-
- operands[1] = GEN_INT (off);
- operands[2] = GEN_INT (val - off);
- }
-}")
-
-;; Handle input reloads in DImode.
-;; This is mainly to handle reloading HILO_REGNUM. Note that we may
-;; see it as the source or the destination, depending upon which way
-;; reload handles the instruction.
-;; Making the second operand TImode is a trick. The compiler may
-;; reuse the same register for operand 0 and operand 2. Using TImode
-;; gives us two registers, so we can always use the one which is not
-;; used.
-
-(define_expand "reload_indi"
- [(set (match_operand:DI 0 "register_operand" "=b")
- (match_operand:DI 1 "" "b"))
- (clobber (match_operand:TI 2 "register_operand" "=&d"))]
- "TARGET_64BIT"
- "
-{
- rtx scratch = gen_rtx_REG (DImode,
- (REGNO (operands[0]) == REGNO (operands[2])
- ? REGNO (operands[2]) + 1
- : REGNO (operands[2])));
-
- if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
- {
- if (GET_CODE (operands[1]) == MEM)
- {
- rtx memword, offword, hi_word, lo_word;
- rtx addr = find_replacement (&XEXP (operands[1], 0));
- rtx op1 = replace_equiv_address (operands[1], addr);
-
- scratch = gen_rtx_REG (SImode, REGNO (scratch));
- memword = adjust_address (op1, SImode, 0);
- offword = adjust_address (op1, SImode, 4);
-
- if (BYTES_BIG_ENDIAN)
- {
- hi_word = memword;
- lo_word = offword;
- }
- else
- {
- hi_word = offword;
- lo_word = memword;
- }
- emit_move_insn (scratch, hi_word);
- emit_move_insn (gen_rtx_REG (SImode, 64), scratch);
- emit_move_insn (scratch, lo_word);
- emit_move_insn (gen_rtx (REG, SImode, 65), scratch);
- emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[0]), 2));
- }
- else
- {
- emit_insn (gen_ashrdi3 (scratch, operands[1], GEN_INT (32)));
- emit_insn (gen_movdi (gen_rtx_REG (DImode, 64), scratch));
- emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32)));
- emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32)));
- emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch));
- emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[0]), 2));
- }
- DONE;
- }
- if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM)
- {
- emit_insn (gen_movdi (scratch, gen_rtx_REG (DImode, 65)));
- emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
- emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
- emit_insn (gen_movdi (operands[0], gen_rtx_REG (DImode, 64)));
- emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
- emit_insn (gen_iordi3 (operands[0], operands[0], scratch));
- emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[1]), 2));
- DONE;
- }
- /* This handles moves between a float register and HI/LO. */
- emit_move_insn (scratch, operands[1]);
- emit_move_insn (operands[0], scratch);
- DONE;
-}")
-
-;; Handle output reloads in DImode.
-
-;; Reloading HILO_REG in MIPS16 mode requires two scratch registers, so we
-;; use a TImode scratch reg.
-
-(define_expand "reload_outdi"
- [(set (match_operand:DI 0 "general_operand" "=b")
- (match_operand:DI 1 "se_register_operand" "b"))
- (clobber (match_operand:TI 2 "register_operand" "=&d"))]
- "TARGET_64BIT"
- "
-{
- rtx scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
-
- if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
- {
- emit_insn (gen_ashrdi3 (scratch, operands[1], GEN_INT (32)));
- emit_insn (gen_movdi (gen_rtx (REG, DImode, 64), scratch));
- emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32)));
- emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32)));
- emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch));
- emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[0]), 2));
- DONE;
- }
- if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM)
- {
- if (GET_CODE (operands[0]) == MEM)
- {
- rtx scratch, memword, offword, hi_word, lo_word;
- rtx addr = find_replacement (&XEXP (operands[0], 0));
- rtx op0 = replace_equiv_address (operands[0], addr);
-
- scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
- memword = adjust_address (op0, SImode, 0);
- offword = adjust_address (op0, SImode, 4);
-
- if (BYTES_BIG_ENDIAN)
- {
- hi_word = memword;
- lo_word = offword;
- }
- else
- {
- hi_word = offword;
- lo_word = memword;
- }
- emit_move_insn (scratch, gen_rtx_REG (SImode, 64));
- emit_move_insn (hi_word, scratch);
- emit_move_insn (scratch, gen_rtx_REG (SImode, 65));
- emit_move_insn (lo_word, scratch);
- emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[1]), 2));
- }
- else if (TARGET_MIPS16 && ! M16_REG_P (REGNO (operands[0])))
- {
- /* Handle the case where operand[0] is not a 'd' register,
- and hence we can not directly move from the HILO register
- into it. */
- rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
- emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65)));
- emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
- emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
- emit_insn (gen_movdi (scratch2, gen_rtx (REG, DImode, 64)));
- emit_insn (gen_ashldi3 (scratch2, scratch2, GEN_INT (32)));
- emit_insn (gen_iordi3 (scratch, scratch, scratch2));
- emit_insn (gen_movdi (operands[0], scratch));
- emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[1]), 2));
- }
- else
- {
- emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65)));
- emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
- emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
- emit_insn (gen_movdi (operands[0], gen_rtx (REG, DImode, 64)));
- emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
- emit_insn (gen_iordi3 (operands[0], operands[0], scratch));
- emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[1]), 2));
- }
- DONE;
- }
- /* This handles moves between a float register and HI/LO. */
- emit_move_insn (scratch, operands[1]);
- emit_move_insn (operands[0], scratch);
- DONE;
-}")
-
-;; 32-bit Integer moves
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "large_int" ""))]
- "!TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
- [(set (match_dup 0)
- (match_dup 2))
- (set (match_dup 0)
- (ior:SI (match_dup 0)
- (match_dup 3)))]
- "
-{
- operands[2] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1])
- & BITMASK_UPPER16,
- SImode));
- operands[3] = GEN_INT (INTVAL (operands[1]) & BITMASK_LOWER16);
-}")
-
-;; Unlike most other insns, the move insns can't be split with
-;; different predicates, because register spilling and other parts of
-;; the compiler, have memoized the insn number already.
-
-(define_expand "movsi"
- [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (match_operand:SI 1 "general_operand" ""))]
- ""
- "
-{
- if (mips_split_addresses && mips_check_split (operands[1], SImode))
- {
- enum machine_mode mode = GET_MODE (operands[0]);
- rtx tem = ((reload_in_progress | reload_completed)
- ? operands[0] : gen_reg_rtx (mode));
-
- emit_insn (gen_rtx_SET (VOIDmode, tem,
- gen_rtx_HIGH (mode, operands[1])));
-
- operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]);
- }
-
- /* If we are generating embedded PIC code, and we are referring to a
- symbol in the .text section, we must use an offset from the start
- of the function. */
- if (TARGET_EMBEDDED_PIC
- && (GET_CODE (operands[1]) == LABEL_REF
- || (GET_CODE (operands[1]) == SYMBOL_REF
- && ! SYMBOL_REF_FLAG (operands[1]))))
- {
- rtx temp;
-
- temp = embedded_pic_offset (operands[1]);
- temp = gen_rtx_PLUS (Pmode, embedded_pic_fnaddr_rtx,
- force_reg (SImode, temp));
- emit_move_insn (operands[0], force_reg (SImode, temp));
- DONE;
- }
-
- /* If operands[1] is a constant address invalid for pic, then we need to
- handle it just like LEGITIMIZE_ADDRESS does. */
- if (flag_pic && pic_address_needs_scratch (operands[1]))
- {
- rtx temp = force_reg (SImode, XEXP (XEXP (operands[1], 0), 0));
- rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
-
- if (! SMALL_INT (temp2))
- temp2 = force_reg (SImode, temp2);
-
- emit_move_insn (operands[0], gen_rtx_PLUS (SImode, temp, temp2));
- DONE;
- }
-
- /* On the mips16, we can handle a GP relative reference by adding in
- $gp. We need to check the name to see whether this is a string
- constant. */
- if (TARGET_MIPS16
- && register_operand (operands[0], SImode)
- && GET_CODE (operands[1]) == SYMBOL_REF
- && SYMBOL_REF_FLAG (operands[1]))
- {
- const char *name = XSTR (operands[1], 0);
-
- if (name[0] != '*'
- || strncmp (name + 1, LOCAL_LABEL_PREFIX,
- sizeof LOCAL_LABEL_PREFIX - 1) != 0)
- {
- rtx base_reg;
-
- if (reload_in_progress || reload_completed)
- {
- /* We need to reload this address. In this case we
- aren't going to have a chance to combine loading the
- address with the load or store. That means that we
- can either generate a 2 byte move followed by a 4
- byte addition, or a 2 byte load with a 4 byte entry
- in the constant table. Since the entry in the
- constant table might be shared, we're better off, on
- average, loading the address from the constant table. */
- emit_move_insn (operands[0],
- force_const_mem (SImode, operands[1]));
- DONE;
- }
-
- base_reg = gen_reg_rtx (Pmode);
- emit_move_insn (base_reg, mips16_gp_pseudo_reg ());
-
- emit_move_insn (operands[0],
- gen_rtx (PLUS, Pmode, base_reg,
- mips16_gp_offset (operands[1])));
- DONE;
- }
- }
-
- if ((reload_in_progress | reload_completed) == 0
- && !register_operand (operands[0], SImode)
- && !register_operand (operands[1], SImode)
- && (TARGET_MIPS16
- || GET_CODE (operands[1]) != CONST_INT
- || INTVAL (operands[1]) != 0))
- {
- rtx temp = force_reg (SImode, operands[1]);
- emit_move_insn (operands[0], temp);
- DONE;
- }
-}")
-
-;; For mips16, we need a special case to handle storing $31 into
-;; memory, since we don't have a constraint to match $31. This
-;; instruction can be generated by save_restore_insns.
-
-(define_insn ""
- [(set (match_operand:SI 0 "memory_operand" "=R,m")
- (reg:SI 31))]
- "TARGET_MIPS16"
- "*
-{
- operands[1] = gen_rtx (REG, SImode, 31);
- return mips_move_1word (operands, insn, FALSE);
-}"
- [(set_attr "type" "store")
- (set_attr "mode" "SI")
- (set_attr "length" "4,8")])
-
-;; The difference between these two is whether or not ints are allowed
-;; in FP registers (off by default, use -mdebugh to enable).
-
-(define_insn "movsi_internal1"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*f*z,*f,*f,*f,*R,*m,*x,*x,*d,*d")
- (match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*f*z,*d,*f,*R,*m,*f,*f,J,*d,*x,*a"))]
- "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
- && (register_operand (operands[0], SImode)
- || register_operand (operands[1], SImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,move,load,load,store,store,hilo,hilo,hilo,hilo")
- (set_attr "mode" "SI")
- (set_attr "length" "4,8,4,8,4,8,4,8,4,4,4,4,8,4,8,4,4,4,4")])
-
-(define_insn "movsi_internal2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*z,*x,*d,*x,*d")
- (match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*z,*d,J,*x,*d,*a"))]
- "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
- && (register_operand (operands[0], SImode)
- || register_operand (operands[1], SImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,hilo,hilo,hilo,hilo")
- (set_attr "mode" "SI")
- (set_attr "length" "4,8,4,8,4,8,4,8,4,4,4,4,4,4")])
-
-;; This is the mips16 movsi instruction. We accept a small integer as
-;; the source if the destination is a GP memory reference. This is
-;; because we want the combine pass to turn adding a GP reference to a
-;; register into a direct GP reference, but the combine pass will pass
-;; in the source as a constant if it finds an equivalent one. If the
-;; instruction is recognized, reload will force the constant back out
-;; into a register.
-
-(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,d,R,m,*d,*d")
- (match_operand:SI 1 "move_operand" "d,d,y,S,K,N,s,R,m,d,d,*x,*a"))]
- "TARGET_MIPS16
- && (register_operand (operands[0], SImode)
- || register_operand (operands[1], SImode)
- || (GET_CODE (operands[0]) == MEM
- && GET_CODE (XEXP (operands[0], 0)) == PLUS
- && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST
- && mips16_gp_offset_p (XEXP (XEXP (operands[0], 0), 1))
- && GET_CODE (operands[1]) == CONST_INT
- && (SMALL_INT (operands[1])
- || SMALL_INT_UNSIGNED (operands[1]))))"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "move,move,move,load,arith,arith,arith,load,load,store,store,hilo,hilo")
- (set_attr "mode" "SI")
- (set_attr_alternative "length"
- [(const_int 4)
- (const_int 4)
- (const_int 4)
- (const_int 8)
- (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
- (const_int 4)
- (const_int 8))
- (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
- (const_int 8)
- (const_int 12))
- (if_then_else (match_operand:VOID 1 "m16_usym8_4" "")
- (const_int 4)
- (const_int 8))
- (const_int 4)
- (const_int 8)
- (const_int 4)
- (const_int 8)
- (const_int 4)
- (const_int 4)])])
-
-;; On the mips16, we can split lw $r,N($r) into an add and a load,
-;; when the original load is a 4 byte instruction but the add and the
-;; load are 2 2 byte instructions.
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (mem:SI (plus:SI (match_dup 0)
- (match_operand:SI 1 "const_int_operand" ""))))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
- && ((INTVAL (operands[1]) < 0
- && INTVAL (operands[1]) >= -0x80)
- || (INTVAL (operands[1]) >= 32 * 4
- && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
- || (INTVAL (operands[1]) >= 0
- && INTVAL (operands[1]) < 32 * 4
- && (INTVAL (operands[1]) & 3) != 0))"
- [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
- (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
- "
-{
- HOST_WIDE_INT val = INTVAL (operands[1]);
-
- if (val < 0)
- operands[2] = GEN_INT (0);
- else if (val >= 32 * 4)
- {
- int off = val & 3;
-
- operands[1] = GEN_INT (0x7c + off);
- operands[2] = GEN_INT (val - off - 0x7c);
- }
- else
- {
- int off = val & 3;
-
- operands[1] = GEN_INT (off);
- operands[2] = GEN_INT (val - off);
- }
-}")
-
-;; On the mips16, we can split a load of certain constants into a load
-;; and an add. This turns a 4 byte instruction into 2 2 byte
-;; instructions.
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "const_int_operand" ""))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
- && INTVAL (operands[1]) >= 0x100
- && INTVAL (operands[1]) <= 0xff + 0x7f"
- [(set (match_dup 0) (match_dup 1))
- (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
- "
-{
- int val = INTVAL (operands[1]);
-
- operands[1] = GEN_INT (0xff);
- operands[2] = GEN_INT (val - 0xff);
-}")
-
-;; On the mips16, we can split a load of a negative constant into a
-;; load and a neg. That's what mips_move_1word will generate anyhow.
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "const_int_operand" ""))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
- && INTVAL (operands[1]) < 0
- && INTVAL (operands[1]) > - 0x8000"
- [(set (match_dup 0) (match_dup 1))
- (set (match_dup 0) (neg:SI (match_dup 0)))]
- "
-{
- operands[1] = GEN_INT (- INTVAL (operands[1]));
-}")
-
-;; Reload HILO_REGNUM in SI mode. This needs a scratch register in
-;; order to set the sign bit correctly in the HI register.
-
-(define_expand "reload_outsi"
- [(set (match_operand:SI 0 "general_operand" "=b")
- (match_operand:SI 1 "register_operand" "b"))
- (clobber (match_operand:SI 2 "register_operand" "=&d"))]
- "TARGET_64BIT || TARGET_MIPS16"
- "
-{
- if (TARGET_64BIT
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
- {
- emit_insn (gen_movsi (gen_rtx_REG (SImode, 65), operands[1]));
- emit_insn (gen_ashrsi3 (operands[2], operands[1], GEN_INT (31)));
- emit_insn (gen_movsi (gen_rtx (REG, SImode, 64), operands[2]));
- emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[0]), 2));
- DONE;
- }
- /* Use a mult to reload LO on mips16. ??? This is hideous. */
- if (TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == LO_REGNUM)
- {
- emit_insn (gen_movsi (operands[2], GEN_INT (1)));
- /* This is gen_mulsi3_internal, but we need to fill in the
- scratch registers. */
- emit_insn (gen_rtx (PARALLEL, VOIDmode,
- gen_rtvec (3,
- gen_rtx (SET, VOIDmode,
- operands[0],
- gen_rtx (MULT, SImode,
- operands[1],
- operands[2])),
- gen_rtx (CLOBBER, VOIDmode,
- gen_rtx (REG, SImode, 64)),
- gen_rtx (CLOBBER, VOIDmode,
- gen_rtx (REG, SImode, 66)))));
- DONE;
- }
- /* FIXME: I don't know how to get a value into the HI register. */
- if (GET_CODE (operands[0]) == REG
- && (TARGET_MIPS16 ? M16_REG_P (REGNO (operands[0]))
- : GP_REG_P (REGNO (operands[0]))))
- {
- emit_move_insn (operands[0], operands[1]);
- DONE;
- }
- /* This handles moves between a float register and HI/LO. */
- emit_move_insn (operands[2], operands[1]);
- emit_move_insn (operands[0], operands[2]);
- DONE;
-}")
-
-;; Reload a value into HI or LO. There is no mthi or mtlo on mips16,
-;; so we use a mult. ??? This is hideous, and we ought to figure out
-;; something better.
-
-;; We use no predicate for operand1, because it may be a PLUS, and there
-;; is no convenient predicate for that.
-
-(define_expand "reload_insi"
- [(set (match_operand:SI 0 "register_operand" "=b")
- (match_operand:SI 1 "" "b"))
- (clobber (match_operand:SI 2 "register_operand" "=&d"))]
- "TARGET_MIPS16"
- "
-{
- if (TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == LO_REGNUM)
- {
- emit_insn (gen_movsi (operands[2], GEN_INT (1)));
- /* This is gen_mulsi3_internal, but we need to fill in the
- scratch registers. */
- emit_insn (gen_rtx (PARALLEL, VOIDmode,
- gen_rtvec (3,
- gen_rtx (SET, VOIDmode,
- operands[0],
- gen_rtx (MULT, SImode,
- operands[1],
- operands[2])),
- gen_rtx (CLOBBER, VOIDmode,
- gen_rtx (REG, SImode, 64)),
- gen_rtx (CLOBBER, VOIDmode,
- gen_rtx (REG, SImode, 66)))));
- DONE;
- }
-
- /* If this is a plus, then this must be an add of the stack pointer against
- either a hard register or a pseudo. */
- if (TARGET_MIPS16 && GET_CODE (operands[1]) == PLUS)
- {
- rtx plus_op;
-
- if (XEXP (operands[1], 0) == stack_pointer_rtx)
- plus_op = XEXP (operands[1], 1);
- else if (XEXP (operands[1], 1) == stack_pointer_rtx)
- plus_op = XEXP (operands[1], 0);
- else
- abort ();
-
- /* We should have a register now. */
- if (GET_CODE (plus_op) != REG)
- abort ();
-
- if (REGNO (plus_op) < FIRST_PSEUDO_REGISTER)
- {
- /* We have to have at least one temporary register which is not
- overlapping plus_op. */
- if (! rtx_equal_p (plus_op, operands[0]))
- {
- emit_move_insn (operands[0], stack_pointer_rtx);
- emit_insn (gen_addsi3 (operands[0], operands[0], plus_op));
- }
- else if (! rtx_equal_p (plus_op, operands[2]))
- {
- emit_move_insn (operands[2], stack_pointer_rtx);
- emit_insn (gen_addsi3 (operands[0], plus_op, operands[2]));
- }
- else
- abort ();
- }
- else
- {
- /* We need two registers in this case. */
- if (! rtx_equal_p (operands[0], operands[2]))
- {
- emit_move_insn (operands[0], stack_pointer_rtx);
- emit_move_insn (operands[2], plus_op);
- emit_insn (gen_addsi3 (operands[0], operands[0], operands[2]));
- }
- else
- abort ();
- }
- DONE;
- }
-
- /* FIXME: I don't know how to get a value into the HI register. */
- emit_move_insn (operands[0], operands[1]);
- DONE;
-}")
-
-;; This insn is for the unspec delay for HILO.
-
-(define_insn "*HILO_delay"
- [(unspec [(match_operand 0 "register_operand" "=b")] 2 )]
- ""
- ""
- [(set_attr "type" "nop")
- (set_attr "mode" "none")
- (set_attr "can_delay" "no")])
-
-;; This insn handles moving CCmode values. It's really just a
-;; slightly simplified copy of movsi_internal2, with additional cases
-;; to move a condition register to a general register and to move
-;; between the general registers and the floating point registers.
-
-(define_insn "movcc"
- [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*d,*R,*m,*d,*f,*f,*f,*f,*R,*m")
- (match_operand:CC 1 "general_operand" "z,*d,*R,*m,*d,*d,*f,*d,*f,*R,*m,*f,*f"))]
- "ISA_HAS_8CC && TARGET_HARD_FLOAT"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "move,move,load,load,store,store,xfer,xfer,move,load,load,store,store")
- (set_attr "mode" "SI")
- (set_attr "length" "8,4,4,8,4,8,4,4,4,4,8,4,8")])
-
-;; Reload condition code registers. reload_incc and reload_outcc
-;; both handle moves from arbitrary operands into condition code
-;; registers. reload_incc handles the more common case in which
-;; a source operand is constrained to be in a condition-code
-;; register, but has not been allocated to one.
-;;
-;; Sometimes, such as in movcc, we have a CCmode destination whose
-;; constraints do not include 'z'. reload_outcc handles the case
-;; when such an operand is allocated to a condition-code register.
-;;
-;; Note that reloads from a condition code register to some
-;; other location can be done using ordinary moves. Moving
-;; into a GPR takes a single movcc, moving elsewhere takes
-;; two. We can leave these cases to the generic reload code.
-(define_expand "reload_incc"
- [(set (match_operand:CC 0 "fcc_register_operand" "=z")
- (match_operand:CC 1 "general_operand" ""))
- (clobber (match_operand:TF 2 "register_operand" "=&f"))]
- "ISA_HAS_8CC && TARGET_HARD_FLOAT"
- "
-{
- mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
- DONE;
-}")
-
-(define_expand "reload_outcc"
- [(set (match_operand:CC 0 "fcc_register_operand" "=z")
- (match_operand:CC 1 "register_operand" ""))
- (clobber (match_operand:TF 2 "register_operand" "=&f"))]
- "ISA_HAS_8CC && TARGET_HARD_FLOAT"
- "
-{
- mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
- DONE;
-}")
-
-;; MIPS4 supports loading and storing a floating point register from
-;; the sum of two general registers. We use two versions for each of
-;; these four instructions: one where the two general registers are
-;; SImode, and one where they are DImode. This is because general
-;; registers will be in SImode when they hold 32 bit values, but,
-;; since the 32 bit values are always sign extended, the [ls][wd]xc1
-;; instructions will still work correctly.
-
-;; ??? Perhaps it would be better to support these instructions by
-;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
-;; these instructions can only be used to load and store floating
-;; point registers, that would probably cause trouble in reload.
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d"))))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
- "lwxc1\\t%0,%1(%2)"
- [(set_attr "type" "load")
- (set_attr "mode" "SF")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d"))))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
- "lwxc1\\t%0,%1(%2)"
- [(set_attr "type" "load")
- (set_attr "mode" "SF")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f")
- (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d"))))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "ldxc1\\t%0,%1(%2)"
- [(set_attr "type" "load")
- (set_attr "mode" "DF")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f")
- (mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d"))))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "ldxc1\\t%0,%1(%2)"
- [(set_attr "type" "load")
- (set_attr "mode" "DF")])
-
-(define_insn ""
- [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (match_operand:SF 0 "register_operand" "f"))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
- "swxc1\\t%0,%1(%2)"
- [(set_attr "type" "store")
- (set_attr "mode" "SF")])
-
-(define_insn ""
- [(set (mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))
- (match_operand:SF 0 "register_operand" "f"))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
- "swxc1\\t%0,%1(%2)"
- [(set_attr "type" "store")
- (set_attr "mode" "SF")])
-
-(define_insn ""
- [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (match_operand:DF 0 "register_operand" "f"))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "sdxc1\\t%0,%1(%2)"
- [(set_attr "type" "store")
- (set_attr "mode" "DF")])
-
-(define_insn ""
- [(set (mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))
- (match_operand:DF 0 "register_operand" "f"))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "sdxc1\\t%0,%1(%2)"
- [(set_attr "type" "store")
- (set_attr "mode" "DF")])
-
-;; 16-bit Integer moves
-
-;; Unlike most other insns, the move insns can't be split with
-;; different predicates, because register spilling and other parts of
-;; the compiler, have memoized the insn number already.
-;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
-
-(define_expand "movhi"
- [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (match_operand:HI 1 "general_operand" ""))]
- ""
- "
-{
- if ((reload_in_progress | reload_completed) == 0
- && !register_operand (operands[0], HImode)
- && !register_operand (operands[1], HImode)
- && (TARGET_MIPS16
- || (GET_CODE (operands[1]) != CONST_INT
- || INTVAL (operands[1]) != 0)))
- {
- rtx temp = force_reg (HImode, operands[1]);
- emit_move_insn (operands[0], temp);
- DONE;
- }
-}")
-
-;; The difference between these two is whether or not ints are allowed
-;; in FP registers (off by default, use -mdebugh to enable).
-
-(define_insn "movhi_internal1"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f,*f*z,*x,*d")
- (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
- "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
- && (register_operand (operands[0], HImode)
- || register_operand (operands[1], HImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
- (set_attr "mode" "HI")
- (set_attr "length" "4,4,4,8,4,8,4,4,4,4,4")])
-
-(define_insn "movhi_internal2"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
- (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
- "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
- && (register_operand (operands[0], HImode)
- || register_operand (operands[1], HImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
- (set_attr "mode" "HI")
- (set_attr "length" "4,4,4,8,4,8,4,4,4,4")])
-
-(define_insn ""
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,m,*d")
- (match_operand:HI 1 "general_operand" "d,d,y,K,N,R,m,d,d,*x"))]
- "TARGET_MIPS16
- && (register_operand (operands[0], HImode)
- || register_operand (operands[1], HImode))"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "move,move,move,arith,arith,load,load,store,store,hilo")
- (set_attr "mode" "HI")
- (set_attr_alternative "length"
- [(const_int 4)
- (const_int 4)
- (const_int 4)
- (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
- (const_int 4)
- (const_int 8))
- (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
- (const_int 8)
- (const_int 12))
- (const_int 4)
- (const_int 8)
- (const_int 4)
- (const_int 8)
- (const_int 4)])])
-
-
-;; On the mips16, we can split lh $r,N($r) into an add and a load,
-;; when the original load is a 4 byte instruction but the add and the
-;; load are 2 2 byte instructions.
-
-(define_split
- [(set (match_operand:HI 0 "register_operand" "")
- (mem:HI (plus:SI (match_dup 0)
- (match_operand:SI 1 "const_int_operand" ""))))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
- && ((INTVAL (operands[1]) < 0
- && INTVAL (operands[1]) >= -0x80)
- || (INTVAL (operands[1]) >= 32 * 2
- && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
- || (INTVAL (operands[1]) >= 0
- && INTVAL (operands[1]) < 32 * 2
- && (INTVAL (operands[1]) & 1) != 0))"
- [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
- (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
- "
-{
- HOST_WIDE_INT val = INTVAL (operands[1]);
-
- if (val < 0)
- operands[2] = GEN_INT (0);
- else if (val >= 32 * 2)
- {
- int off = val & 1;
-
- operands[1] = GEN_INT (0x7e + off);
- operands[2] = GEN_INT (val - off - 0x7e);
- }
- else
- {
- int off = val & 1;
-
- operands[1] = GEN_INT (off);
- operands[2] = GEN_INT (val - off);
- }
-}")
-
-;; 8-bit Integer moves
-
-;; Unlike most other insns, the move insns can't be split with
-;; different predicates, because register spilling and other parts of
-;; the compiler, have memoized the insn number already.
-;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
-
-(define_expand "movqi"
- [(set (match_operand:QI 0 "nonimmediate_operand" "")
- (match_operand:QI 1 "general_operand" ""))]
- ""
- "
-{
- if ((reload_in_progress | reload_completed) == 0
- && !register_operand (operands[0], QImode)
- && !register_operand (operands[1], QImode)
- && (TARGET_MIPS16
- || (GET_CODE (operands[1]) != CONST_INT
- || INTVAL (operands[1]) != 0)))
- {
- rtx temp = force_reg (QImode, operands[1]);
- emit_move_insn (operands[0], temp);
- DONE;
- }
-}")
-
-;; The difference between these two is whether or not ints are allowed
-;; in FP registers (off by default, use -mdebugh to enable).
-
-(define_insn "movqi_internal1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f*z,*f,*x,*d")
- (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
- "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
- && (register_operand (operands[0], QImode)
- || register_operand (operands[1], QImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
- (set_attr "mode" "QI")
- (set_attr "length" "4,4,4,8,4,8,4,4,4,4,4")])
-
-(define_insn "movqi_internal2"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
- (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
- "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
- && (register_operand (operands[0], QImode)
- || register_operand (operands[1], QImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
- (set_attr "mode" "QI")
- (set_attr "length" "4,4,4,8,4,8,4,4,4,4")])
-
-(define_insn ""
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,m,*d")
- (match_operand:QI 1 "general_operand" "d,d,y,K,N,R,m,d,d,*x"))]
- "TARGET_MIPS16
- && (register_operand (operands[0], QImode)
- || register_operand (operands[1], QImode))"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "move,move,move,arith,arith,load,load,store,store,hilo")
- (set_attr "mode" "QI")
- (set_attr_alternative "length"
- [(const_int 4)
- (const_int 4)
- (const_int 4)
- (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
- (const_int 4)
- (const_int 8))
- (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
- (const_int 8)
- (const_int 12))
- (const_int 4)
- (const_int 8)
- (const_int 4)
- (const_int 8)
- (const_int 4)])])
-
-
-;; On the mips16, we can split lb $r,N($r) into an add and a load,
-;; when the original load is a 4 byte instruction but the add and the
-;; load are 2 2 byte instructions.
-
-(define_split
- [(set (match_operand:QI 0 "register_operand" "")
- (mem:QI (plus:SI (match_dup 0)
- (match_operand:SI 1 "const_int_operand" ""))))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
- && ((INTVAL (operands[1]) < 0
- && INTVAL (operands[1]) >= -0x80)
- || (INTVAL (operands[1]) >= 32
- && INTVAL (operands[1]) <= 31 + 0x7f))"
- [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
- (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
- "
-{
- HOST_WIDE_INT val = INTVAL (operands[1]);
-
- if (val < 0)
- operands[2] = GEN_INT (0);
- else
- {
- operands[1] = GEN_INT (0x7f);
- operands[2] = GEN_INT (val - 0x7f);
- }
-}")
-
-;; 32-bit floating point moves
-
-(define_expand "movsf"
- [(set (match_operand:SF 0 "nonimmediate_operand" "")
- (match_operand:SF 1 "general_operand" ""))]
- ""
- "
-{
- if ((reload_in_progress | reload_completed) == 0
- && !register_operand (operands[0], SFmode)
- && !register_operand (operands[1], SFmode)
- && (TARGET_MIPS16
- || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
- && operands[1] != CONST0_RTX (SFmode))))
- {
- rtx temp = force_reg (SFmode, operands[1]);
- emit_move_insn (operands[0], temp);
- DONE;
- }
-}")
-
-(define_insn "movsf_internal1"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,m,*f,*d,*d,*d,*d,*R,*m")
- (match_operand:SF 1 "general_operand" "f,G,R,Fm,fG,fG,*d,*f,*G*d,*R,*F*m,*d,*d"))]
- "TARGET_HARD_FLOAT
- && (register_operand (operands[0], SFmode)
- || register_operand (operands[1], SFmode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
- || operands[1] == CONST0_RTX (SFmode))"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "move,xfer,load,load,store,store,xfer,xfer,move,load,load,store,store")
- (set_attr "mode" "SF")
- (set_attr "length" "4,4,4,8,4,8,4,4,4,4,8,4,8")])
-
-
-(define_insn "movsf_internal2"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,R,m")
- (match_operand:SF 1 "general_operand" " Gd,R,Fm,d,d"))]
- "TARGET_SOFT_FLOAT && !TARGET_MIPS16
- && (register_operand (operands[0], SFmode)
- || register_operand (operands[1], SFmode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
- || operands[1] == CONST0_RTX (SFmode))"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "move,load,load,store,store")
- (set_attr "mode" "SF")
- (set_attr "length" "4,4,8,4,8")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,d,R,m")
- (match_operand:SF 1 "general_operand" "d,d,y,R,Fm,d,d"))]
- "TARGET_MIPS16
- && (register_operand (operands[0], SFmode)
- || register_operand (operands[1], SFmode))"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "move,move,move,load,load,store,store")
- (set_attr "mode" "SF")
- (set_attr "length" "4,4,4,4,8,4,8")])
-
-
-;; 64-bit floating point moves
-
-(define_expand "movdf"
- [(set (match_operand:DF 0 "nonimmediate_operand" "")
- (match_operand:DF 1 "general_operand" ""))]
- ""
- "
-{
- if ((reload_in_progress | reload_completed) == 0
- && !register_operand (operands[0], DFmode)
- && !register_operand (operands[1], DFmode)
- && (TARGET_MIPS16
- || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
- && operands[1] != CONST0_RTX (DFmode))))
- {
- rtx temp = force_reg (DFmode, operands[1]);
- emit_move_insn (operands[0], temp);
- DONE;
- }
-}")
-
-(define_insn "movdf_internal1"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,To,f,*f,*d,*d,*d,*d,*R,*T")
- (match_operand:DF 1 "general_operand" "f,R,To,fG,fG,F,*d,*f,*d*G,*R,*T*F,*d,*d"))]
- "TARGET_HARD_FLOAT && !(TARGET_FLOAT64 && !TARGET_64BIT)
- && TARGET_DOUBLE_FLOAT
- && (register_operand (operands[0], DFmode)
- || register_operand (operands[1], DFmode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
- || operands[1] == CONST0_RTX (DFmode))"
- "* return mips_move_2words (operands, insn); "
- [(set_attr "type" "move,load,load,store,store,load,xfer,xfer,move,load,load,store,store")
- (set_attr "mode" "DF")
- (set_attr "length" "4,8,16,8,16,16,8,8,8,8,16,8,16")])
-
-(define_insn "movdf_internal1a"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,R,R,To,To,*d,*d,*d,*To,*R,*d")
- (match_operand:DF 1 "general_operand" " f,To,f,G,f,G,*F,*To,*R,*d,*d,*d"))]
- "TARGET_HARD_FLOAT && (TARGET_FLOAT64 && !TARGET_64BIT)
- && TARGET_DOUBLE_FLOAT
- && (register_operand (operands[0], DFmode)
- || register_operand (operands[1], DFmode)
- || (GET_CODE (operands [0]) == MEM
- && ((GET_CODE (operands[1]) == CONST_INT
- && INTVAL (operands[1]) == 0)
- || operands[1] == CONST0_RTX (DFmode))))"
- "* return mips_move_2words (operands, insn); "
- [(set_attr "type" "move,load,store,store,store,store,load,load,load,store,store,move")
- (set_attr "mode" "DF")
- (set_attr "length" "4,8,4,4,8,8,8,8,4,8,4,4")])
-
-(define_insn "movdf_internal2"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,R,To,*d")
- (match_operand:DF 1 "general_operand" "dG,R,ToF,d,d,*f"))]
- "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
- && (register_operand (operands[0], DFmode)
- || register_operand (operands[1], DFmode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
- || operands[1] == CONST0_RTX (DFmode))"
- "* return mips_move_2words (operands, insn); "
- [(set_attr "type" "move,load,load,store,store,xfer")
- (set_attr "mode" "DF")
- (set_attr "length" "8,8,16,8,16,8")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,d,R,To")
- (match_operand:DF 1 "general_operand" "d,d,y,R,ToF,d,d"))]
- "TARGET_MIPS16
- && (register_operand (operands[0], DFmode)
- || register_operand (operands[1], DFmode))"
- "* return mips_move_2words (operands, insn);"
- [(set_attr "type" "move,move,move,load,load,store,store")
- (set_attr "mode" "DF")
- (set_attr "length" "8,8,8,8,16,8,16")])
-
-(define_split
- [(set (match_operand:DF 0 "register_operand" "")
- (match_operand:DF 1 "register_operand" ""))]
- "reload_completed && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
- [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
- (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
- "")
-
-;; Instructions to load the global pointer register.
-;; This is volatile to make sure that the scheduler won't move any symbol_ref
-;; uses in front of it. All symbol_refs implicitly use the gp reg.
-
-(define_insn "loadgp"
- [(set (reg:DI 28)
- (unspec_volatile:DI [(match_operand:DI 0 "address_operand" "")
- (match_operand:DI 1 "register_operand" "")] 2))
- (clobber (reg:DI 1))]
- ""
- "%[lui\\t$1,%%hi(%%neg(%%gp_rel(%a0)))\\n\\taddiu\\t$1,$1,%%lo(%%neg(%%gp_rel(%a0)))\\n\\tdaddu\\t$gp,$1,%1%]"
- [(set_attr "type" "move")
- (set_attr "mode" "DI")
- (set_attr "length" "12")])
-\f
-;; Block moves, see mips.c for more details.
-;; Argument 0 is the destination
-;; Argument 1 is the source
-;; Argument 2 is the length
-;; Argument 3 is the alignment
-
-(define_expand "movstrsi"
- [(parallel [(set (match_operand:BLK 0 "general_operand" "")
- (match_operand:BLK 1 "general_operand" ""))
- (use (match_operand:SI 2 "arith32_operand" ""))
- (use (match_operand:SI 3 "immediate_operand" ""))])]
- "!TARGET_MIPS16"
- "
-{
- if (operands[0]) /* avoid unused code messages */
- {
- expand_block_move (operands);
- DONE;
- }
-}")
-
-;; Insn generated by block moves
-
-(define_insn "movstrsi_internal"
- [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination
- (match_operand:BLK 1 "memory_operand" "o")) ;; source
- (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
- (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
- (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
- (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
- (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
- (use (match_operand:SI 3 "small_int" "I")) ;; alignment
- (use (const_int 0))] ;; normal block move
- ""
- "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
- [(set_attr "type" "store")
- (set_attr "mode" "none")
- (set_attr "length" "80")])
-
-;; We need mips16 versions, because an offset from the stack pointer
-;; is not offsettable, since the stack pointer can only handle 4 and 8
-;; byte loads.
-
-(define_insn ""
- [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination
- (match_operand:BLK 1 "memory_operand" "o")) ;; source
- (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
- (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
- (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
- (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
- (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
- (use (match_operand:SI 3 "small_int" "I")) ;; alignment
- (use (const_int 0))] ;; normal block move
- "TARGET_MIPS16"
- "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
- [(set_attr "type" "multi")
- (set_attr "mode" "none")
- (set_attr "length" "80")])
-
-;; Split a block move into 2 parts, the first part is everything
-;; except for the last move, and the second part is just the last
-;; store, which is exactly 1 instruction (ie, not a usw), so it can
-;; fill a delay slot. This also prevents a bug in delayed branches
-;; from showing up, which reuses one of the registers in our clobbers.
-
-(define_split
- [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
- (mem:BLK (match_operand:SI 1 "register_operand" "")))
- (clobber (match_operand:SI 4 "register_operand" ""))
- (clobber (match_operand:SI 5 "register_operand" ""))
- (clobber (match_operand:SI 6 "register_operand" ""))
- (clobber (match_operand:SI 7 "register_operand" ""))
- (use (match_operand:SI 2 "small_int" ""))
- (use (match_operand:SI 3 "small_int" ""))
- (use (const_int 0))]
-
- "reload_completed && !TARGET_DEBUG_D_MODE && INTVAL (operands[2]) > 0"
-
- ;; All but the last move
- [(parallel [(set (mem:BLK (match_dup 0))
- (mem:BLK (match_dup 1)))
- (clobber (match_dup 4))
- (clobber (match_dup 5))
- (clobber (match_dup 6))
- (clobber (match_dup 7))
- (use (match_dup 2))
- (use (match_dup 3))
- (use (const_int 1))])
-
- ;; The last store, so it can fill a delay slot
- (parallel [(set (mem:BLK (match_dup 0))
- (mem:BLK (match_dup 1)))
- (clobber (match_dup 4))
- (clobber (match_dup 5))
- (clobber (match_dup 6))
- (clobber (match_dup 7))
- (use (match_dup 2))
- (use (match_dup 3))
- (use (const_int 2))])]
-
- "")
-
-(define_insn "movstrsi_internal2"
- [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination
- (match_operand:BLK 1 "memory_operand" "o")) ;; source
- (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
- (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
- (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
- (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
- (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
- (use (match_operand:SI 3 "small_int" "I")) ;; alignment
- (use (const_int 1))] ;; all but last store
- ""
- "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);"
- [(set_attr "type" "store")
- (set_attr "mode" "none")
- (set_attr "length" "80")])
-
-(define_insn ""
- [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination
- (match_operand:BLK 1 "memory_operand" "o")) ;; source
- (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
- (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
- (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
- (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
- (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
- (use (match_operand:SI 3 "small_int" "I")) ;; alignment
- (use (const_int 1))] ;; all but last store
- "TARGET_MIPS16"
- "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);"
- [(set_attr "type" "multi")
- (set_attr "mode" "none")
- (set_attr "length" "80")])
-
-(define_insn "movstrsi_internal3"
- [(set (match_operand:BLK 0 "memory_operand" "=Ro") ;; destination
- (match_operand:BLK 1 "memory_operand" "Ro")) ;; source
- (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
- (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
- (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
- (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
- (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
- (use (match_operand:SI 3 "small_int" "I")) ;; alignment
- (use (const_int 2))] ;; just last store of block move
- ""
- "* return output_block_move (insn, operands, 4, BLOCK_MOVE_LAST);"
- [(set_attr "type" "store")
- (set_attr "mode" "none")])
-\f
-;;
-;; ....................
-;;
-;; SHIFTS
-;;
-;; ....................
-
-;; Many of these instructions uses trivial define_expands, because we
-;; want to use a different set of constraints when TARGET_MIPS16.
-
-(define_expand "ashlsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ashift:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- ""
- "
-{
- /* On the mips16, a shift of more than 8 is a four byte instruction,
- so, for a shift between 8 and 16, it is just as fast to do two
- shifts of 8 or less. If there is a lot of shifting going on, we
- may win in CSE. Otherwise combine will put the shifts back
- together again. This can be called by function_arg, so we must
- be careful not to allocate a new register if we've reached the
- reload pass. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16
- && ! reload_in_progress
- && ! reload_completed)
- {
- rtx temp = gen_reg_rtx (SImode);
-
- emit_insn (gen_ashlsi3_internal2 (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_ashlsi3_internal2 (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
-}")
-
-(define_insn "ashlsi3_internal1"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ashift:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "!TARGET_MIPS16"
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
- return \"sll\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-(define_insn "ashlsi3_internal2"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (ashift:SI (match_operand:SI 1 "register_operand" "0,d")
- (match_operand:SI 2 "arith_operand" "d,I")))]
- "TARGET_MIPS16"
- "*
-{
- if (which_alternative == 0)
- return \"sll\\t%0,%2\";
-
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
- return \"sll\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr_alternative "length"
- [(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 4)
- (const_int 8))])])
-
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (ashift:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16"
- [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 8)))
- (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))]
-"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
-
-(define_expand "ashldi3"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "se_register_operand" "")
- (match_operand:SI 2 "arith_operand" "")))
- (clobber (match_dup 3))])]
- "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
- "
-{
- if (TARGET_64BIT)
- {
- /* On the mips16, a shift of more than 8 is a four byte
- instruction, so, for a shift between 8 and 16, it is just as
- fast to do two shifts of 8 or less. If there is a lot of
- shifting going on, we may win in CSE. Otherwise combine will
- put the shifts back together again. This can be called by
- function_arg, so we must be careful not to allocate a new
- register if we've reached the reload pass. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16
- && ! reload_in_progress
- && ! reload_completed)
- {
- rtx temp = gen_reg_rtx (DImode);
-
- emit_insn (gen_ashldi3_internal4 (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_ashldi3_internal4 (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
-
- emit_insn (gen_ashldi3_internal4 (operands[0], operands[1],
- operands[2]));
- DONE;
- }
-
- operands[3] = gen_reg_rtx (SImode);
-}")
-
-
-(define_insn "ashldi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=&d")
- (ashift:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "*
-{
- operands[4] = const0_rtx;
- dslots_jump_total += 3;
- dslots_jump_filled += 2;
-
- return \"sll\\t%3,%2,26\\n\\
-\\tbgez\\t%3,1f\\n\\
-\\tsll\\t%M0,%L1,%2\\n\\
-\\t%(b\\t3f\\n\\
-\\tmove\\t%L0,%z4%)\\n\\
-\\n\\
-%~1:\\n\\
-\\t%(beq\\t%3,%z4,2f\\n\\
-\\tsll\\t%M0,%M1,%2%)\\n\\
-\\n\\
-\\tsubu\\t%3,%z4,%2\\n\\
-\\tsrl\\t%3,%L1,%3\\n\\
-\\tor\\t%M0,%M0,%3\\n\\
-%~2:\\n\\
-\\tsll\\t%L0,%L1,%2\\n\\
-%~3:\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "SI")
- (set_attr "length" "48")])
-
-
-(define_insn "ashldi3_internal2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashift:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && (INTVAL (operands[2]) & 32) != 0"
- "*
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
- operands[4] = const0_rtx;
- return \"sll\\t%M0,%L1,%2\;move\\t%L0,%z4\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 4) (ashift:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 0) (const_int 0))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 0) (ashift:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 4) (const_int 0))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_insn "ashldi3_internal3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashift:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
- "*
-{
- int amount = INTVAL (operands[2]);
-
- operands[2] = GEN_INT (amount & 31);
- operands[4] = const0_rtx;
- operands[5] = GEN_INT ((-amount) & 31);
-
- return \"sll\\t%M0,%M1,%2\;srl\\t%3,%L1,%5\;or\\t%M0,%M0,%3\;sll\\t%L0,%L1,%2\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 4)
- (ashift:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))
-
- (set (match_dup 3)
- (lshiftrt:SI (subreg:SI (match_dup 1) 0)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 4)
- (ior:SI (subreg:SI (match_dup 0) 4)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 0)
- (ashift:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))]
- "
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-}")
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 0)
- (ashift:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))
-
- (set (match_dup 3)
- (lshiftrt:SI (subreg:SI (match_dup 1) 4)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 0)
- (ior:SI (subreg:SI (match_dup 0) 0)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 4)
- (ashift:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))]
- "
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-}")
-
-
-(define_insn "ashldi3_internal4"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashift:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
- return \"dsll\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (ashift:DI (match_operand:DI 1 "se_register_operand" "0,d")
- (match_operand:SI 2 "arith_operand" "d,I")))]
- "TARGET_64BIT && TARGET_MIPS16"
- "*
-{
- if (which_alternative == 0)
- return \"dsll\\t%0,%2\";
-
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
- return \"dsll\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr_alternative "length"
- [(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 4)
- (const_int 8))])])
-
-
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
- "TARGET_MIPS16 && TARGET_64BIT && !TARGET_DEBUG_D_MODE
- && reload_completed
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16"
- [(set (match_dup 0) (ashift:DI (match_dup 1) (const_int 8)))
- (set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))]
-"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
-
-(define_expand "ashrsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- ""
- "
-{
- /* On the mips16, a shift of more than 8 is a four byte instruction,
- so, for a shift between 8 and 16, it is just as fast to do two
- shifts of 8 or less. If there is a lot of shifting going on, we
- may win in CSE. Otherwise combine will put the shifts back
- together again. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16)
- {
- rtx temp = gen_reg_rtx (SImode);
-
- emit_insn (gen_ashrsi3_internal2 (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_ashrsi3_internal2 (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
-}")
-
-(define_insn "ashrsi3_internal1"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "!TARGET_MIPS16"
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
- return \"sra\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-(define_insn "ashrsi3_internal2"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
- (match_operand:SI 2 "arith_operand" "d,I")))]
- "TARGET_MIPS16"
- "*
-{
- if (which_alternative == 0)
- return \"sra\\t%0,%2\";
-
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
- return \"sra\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr_alternative "length"
- [(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 4)
- (const_int 8))])])
-
-
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16"
- [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 8)))
- (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
-"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
-
-(define_expand "ashrdi3"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "")
- (match_operand:SI 2 "arith_operand" "")))
- (clobber (match_dup 3))])]
- "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
- "
-{
- if (TARGET_64BIT)
- {
- /* On the mips16, a shift of more than 8 is a four byte
- instruction, so, for a shift between 8 and 16, it is just as
- fast to do two shifts of 8 or less. If there is a lot of
- shifting going on, we may win in CSE. Otherwise combine will
- put the shifts back together again. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16)
- {
- rtx temp = gen_reg_rtx (DImode);
-
- emit_insn (gen_ashrdi3_internal4 (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_ashrdi3_internal4 (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
-
- emit_insn (gen_ashrdi3_internal4 (operands[0], operands[1],
- operands[2]));
- DONE;
- }
-
- operands[3] = gen_reg_rtx (SImode);
-}")
-
-
-(define_insn "ashrdi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=&d")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "*
-{
- operands[4] = const0_rtx;
- dslots_jump_total += 3;
- dslots_jump_filled += 2;
-
- return \"sll\\t%3,%2,26\\n\\
-\\tbgez\\t%3,1f\\n\\
-\\tsra\\t%L0,%M1,%2\\n\\
-\\t%(b\\t3f\\n\\
-\\tsra\\t%M0,%M1,31%)\\n\\
-\\n\\
-%~1:\\n\\
-\\t%(beq\\t%3,%z4,2f\\n\\
-\\tsrl\\t%L0,%L1,%2%)\\n\\
-\\n\\
-\\tsubu\\t%3,%z4,%2\\n\\
-\\tsll\\t%3,%M1,%3\\n\\
-\\tor\\t%L0,%L0,%3\\n\\
-%~2:\\n\\
-\\tsra\\t%M0,%M1,%2\\n\\
-%~3:\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "48")])
-
-
-(define_insn "ashrdi3_internal2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
- "*
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
- return \"sra\\t%L0,%M1,%2\;sra\\t%M0,%M1,31\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 4) (ashiftrt:SI (subreg:SI (match_dup 1) 4) (const_int 31)))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 4) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (const_int 31)))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_insn "ashrdi3_internal3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
- "*
-{
- int amount = INTVAL (operands[2]);
-
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-
- return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;sra\\t%M0,%M1,%2\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 0)
- (lshiftrt:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ashift:SI (subreg:SI (match_dup 1) 4)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 0)
- (ior:SI (subreg:SI (match_dup 0) 0)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 4)
- (ashiftrt:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))]
- "
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-}")
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 4)
- (lshiftrt:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ashift:SI (subreg:SI (match_dup 1) 0)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 4)
- (ior:SI (subreg:SI (match_dup 0) 4)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 0)
- (ashiftrt:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))]
- "
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-}")
-
-
-(define_insn "ashrdi3_internal4"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
- return \"dsra\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "0,0")
- (match_operand:SI 2 "arith_operand" "d,I")))]
- "TARGET_64BIT && TARGET_MIPS16"
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
- return \"dsra\\t%0,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr_alternative "length"
- [(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 4)
- (const_int 8))])])
-
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
- "TARGET_MIPS16 && TARGET_64BIT && !TARGET_DEBUG_D_MODE
- && reload_completed
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16"
- [(set (match_dup 0) (ashiftrt:DI (match_dup 1) (const_int 8)))
- (set (match_dup 0) (ashiftrt:DI (match_dup 0) (match_dup 2)))]
-"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
-
-(define_expand "lshrsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- ""
- "
-{
- /* On the mips16, a shift of more than 8 is a four byte instruction,
- so, for a shift between 8 and 16, it is just as fast to do two
- shifts of 8 or less. If there is a lot of shifting going on, we
- may win in CSE. Otherwise combine will put the shifts back
- together again. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16)
- {
- rtx temp = gen_reg_rtx (SImode);
-
- emit_insn (gen_lshrsi3_internal2 (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_lshrsi3_internal2 (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
-}")
-
-(define_insn "lshrsi3_internal1"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "!TARGET_MIPS16"
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
- return \"srl\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-(define_insn "lshrsi3_internal2"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
- (match_operand:SI 2 "arith_operand" "d,I")))]
- "TARGET_MIPS16"
- "*
-{
- if (which_alternative == 0)
- return \"srl\\t%0,%2\";
-
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
- return \"srl\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr_alternative "length"
- [(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 4)
- (const_int 8))])])
-
-
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16"
- [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (const_int 8)))
- (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
-"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
-
-;; If we load a byte on the mips16 as a bitfield, the resulting
-;; sequence of instructions is too complicated for combine, because it
-;; involves four instructions: a load, a shift, a constant load into a
-;; register, and an and (the key problem here is that the mips16 does
-;; not have and immediate). We recognize a shift of a load in order
-;; to make it simple enough for combine to understand.
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (lshiftrt:SI (match_operand:SI 1 "memory_operand" "R,m")
- (match_operand:SI 2 "immediate_operand" "I,I")))]
- "TARGET_MIPS16"
- "lw\\t%0,%1\;srl\\t%0,%2"
- [(set_attr "type" "load")
- (set_attr "mode" "SI")
- (set_attr_alternative "length"
- [(if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 8)
- (const_int 12))
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 12)
- (const_int 16))])])
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (lshiftrt:SI (match_operand:SI 1 "memory_operand" "")
- (match_operand:SI 2 "immediate_operand" "")))]
- "TARGET_MIPS16 && !TARGET_DEBUG_D_MODE"
- [(set (match_dup 0) (match_dup 1))
- (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
- "")
-
-(define_expand "lshrdi3"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "")
- (match_operand:SI 2 "arith_operand" "")))
- (clobber (match_dup 3))])]
- "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
- "
-{
- if (TARGET_64BIT)
- {
- /* On the mips16, a shift of more than 8 is a four byte
- instruction, so, for a shift between 8 and 16, it is just as
- fast to do two shifts of 8 or less. If there is a lot of
- shifting going on, we may win in CSE. Otherwise combine will
- put the shifts back together again. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16)
- {
- rtx temp = gen_reg_rtx (DImode);
-
- emit_insn (gen_lshrdi3_internal4 (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_lshrdi3_internal4 (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
-
- emit_insn (gen_lshrdi3_internal4 (operands[0], operands[1],
- operands[2]));
- DONE;
- }
-
- operands[3] = gen_reg_rtx (SImode);
-}")
-
-
-(define_insn "lshrdi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=&d")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "*
-{
- operands[4] = const0_rtx;
- dslots_jump_total += 3;
- dslots_jump_filled += 2;
-
- return \"sll\\t%3,%2,26\\n\\
-\\tbgez\\t%3,1f\\n\\
-\\tsrl\\t%L0,%M1,%2\\n\\
-\\t%(b\\t3f\\n\\
-\\tmove\\t%M0,%z4%)\\n\\
-\\n\\
-%~1:\\n\\
-\\t%(beq\\t%3,%z4,2f\\n\\
-\\tsrl\\t%L0,%L1,%2%)\\n\\
-\\n\\
-\\tsubu\\t%3,%z4,%2\\n\\
-\\tsll\\t%3,%M1,%3\\n\\
-\\tor\\t%L0,%L0,%3\\n\\
-%~2:\\n\\
-\\tsrl\\t%M0,%M1,%2\\n\\
-%~3:\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "48")])
-
-
-(define_insn "lshrdi3_internal2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && (INTVAL (operands[2]) & 32) != 0"
- "*
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
- operands[4] = const0_rtx;
- return \"srl\\t%L0,%M1,%2\;move\\t%M0,%z4\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 0) (lshiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 4) (const_int 0))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 4) (lshiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 0) (const_int 0))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_insn "lshrdi3_internal3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
- "*
-{
- int amount = INTVAL (operands[2]);
-
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-
- return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;srl\\t%M0,%M1,%2\";
-}"
- [(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 0)
- (lshiftrt:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ashift:SI (subreg:SI (match_dup 1) 4)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 0)
- (ior:SI (subreg:SI (match_dup 0) 0)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 4)
- (lshiftrt:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))]
- "
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-}")
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 4)
- (lshiftrt:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ashift:SI (subreg:SI (match_dup 1) 0)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 4)
- (ior:SI (subreg:SI (match_dup 0) 4)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 0)
- (lshiftrt:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))]
- "
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-}")
-
-
-(define_insn "lshrdi3_internal4"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
- return \"dsrl\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "0,0")
- (match_operand:SI 2 "arith_operand" "d,I")))]
- "TARGET_64BIT && TARGET_MIPS16"
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
- return \"dsrl\\t%0,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr_alternative "length"
- [(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 4)
- (const_int 8))])])
-
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16"
- [(set (match_dup 0) (lshiftrt:DI (match_dup 1) (const_int 8)))
- (set (match_dup 0) (lshiftrt:DI (match_dup 0) (match_dup 2)))]
-"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
-
-\f
-;;
-;; ....................
-;;
-;; COMPARISONS
-;;
-;; ....................
-
-;; Flow here is rather complex:
-;;
-;; 1) The cmp{si,di,sf,df} routine is called. It deposits the
-;; arguments into the branch_cmp array, and the type into
-;; branch_type. No RTL is generated.
-;;
-;; 2) The appropriate branch define_expand is called, which then
-;; creates the appropriate RTL for the comparison and branch.
-;; Different CC modes are used, based on what type of branch is
-;; done, so that we can constrain things appropriately. There
-;; are assumptions in the rest of GCC that break if we fold the
-;; operands into the branchs for integer operations, and use cc0
-;; for floating point, so we use the fp status register instead.
-;; If needed, an appropriate temporary is created to hold the
-;; of the integer compare.
-
-(define_expand "cmpsi"
- [(set (cc0)
- (compare:CC (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "arith_operand" "")))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code message */
- {
- branch_cmp[0] = operands[0];
- branch_cmp[1] = operands[1];
- branch_type = CMP_SI;
- DONE;
- }
-}")
-
-(define_expand "tstsi"
- [(set (cc0)
- (match_operand:SI 0 "register_operand" ""))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code message */
- {
- branch_cmp[0] = operands[0];
- branch_cmp[1] = const0_rtx;
- branch_type = CMP_SI;
- DONE;
- }
-}")
-
-(define_expand "cmpdi"
- [(set (cc0)
- (compare:CC (match_operand:DI 0 "se_register_operand" "")
- (match_operand:DI 1 "se_arith_operand" "")))]
- "TARGET_64BIT"
- "
-{
- if (operands[0]) /* avoid unused code message */
- {
- branch_cmp[0] = operands[0];
- branch_cmp[1] = operands[1];
- branch_type = CMP_DI;
- DONE;
- }
-}")
-
-(define_expand "tstdi"
- [(set (cc0)
- (match_operand:DI 0 "se_register_operand" ""))]
- "TARGET_64BIT"
- "
-{
- if (operands[0]) /* avoid unused code message */
- {
- branch_cmp[0] = operands[0];
- branch_cmp[1] = const0_rtx;
- branch_type = CMP_DI;
- DONE;
- }
-}")
-
-(define_expand "cmpdf"
- [(set (cc0)
- (compare:CC (match_operand:DF 0 "register_operand" "")
- (match_operand:DF 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "
-{
- if (operands[0]) /* avoid unused code message */
- {
- branch_cmp[0] = operands[0];
- branch_cmp[1] = operands[1];
- branch_type = CMP_DF;
- DONE;
- }
-}")
-
-(define_expand "cmpsf"
- [(set (cc0)
- (compare:CC (match_operand:SF 0 "register_operand" "")
- (match_operand:SF 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT"
- "
-{
- if (operands[0]) /* avoid unused code message */
- {
- branch_cmp[0] = operands[0];
- branch_cmp[1] = operands[1];
- branch_type = CMP_SF;
- DONE;
- }
-}")
-
-\f
-;;
-;; ....................
-;;
-;; CONDITIONAL BRANCHES
-;;
-;; ....................
-
-;; Conditional branches on floating-point equality tests.
-
-(define_insn "branch_fp"
- [(set (pc)
- (if_then_else
- (match_operator:CC 0 "cmp_op"
- [(match_operand:CC 2 "register_operand" "z")
- (const_int 0)])
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- "TARGET_HARD_FLOAT"
- "*
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/0,
- /*float_p=*/1,
- /*inverted_p=*/0,
- get_attr_length (insn));
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-(define_insn "branch_fp_inverted"
- [(set (pc)
- (if_then_else
- (match_operator:CC 0 "cmp_op"
- [(match_operand:CC 2 "register_operand" "z")
- (const_int 0)])
- (pc)
- (label_ref (match_operand 1 "" ""))))]
- "TARGET_HARD_FLOAT"
- "*
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/0,
- /*float_p=*/1,
- /*inverted_p=*/1,
- get_attr_length (insn));
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-;; Conditional branches on comparisons with zero.
-
-(define_insn "branch_zero"
- [(set (pc)
- (if_then_else
- (match_operator:SI 0 "cmp_op"
- [(match_operand:SI 2 "register_operand" "d")
- (const_int 0)])
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- "!TARGET_MIPS16"
- "*
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/0,
- /*float_p=*/0,
- /*inverted_p=*/0,
- get_attr_length (insn));
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-(define_insn "branch_zero_inverted"
- [(set (pc)
- (if_then_else
- (match_operator:SI 0 "cmp_op"
- [(match_operand:SI 2 "register_operand" "d")
- (const_int 0)])
- (pc)
- (label_ref (match_operand 1 "" ""))))]
- "!TARGET_MIPS16"
- "*
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/0,
- /*float_p=*/0,
- /*inverted_p=*/1,
- get_attr_length (insn));
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-(define_insn "branch_zero_di"
- [(set (pc)
- (if_then_else
- (match_operator:DI 0 "cmp_op"
- [(match_operand:DI 2 "se_register_operand" "d")
- (const_int 0)])
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- "!TARGET_MIPS16"
- "*
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/0,
- /*float_p=*/0,
- /*inverted_p=*/0,
- get_attr_length (insn));
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-(define_insn "branch_zero_di_inverted"
- [(set (pc)
- (if_then_else
- (match_operator:DI 0 "cmp_op"
- [(match_operand:DI 2 "se_register_operand" "d")
- (const_int 0)])
- (pc)
- (label_ref (match_operand 1 "" ""))))]
- "!TARGET_MIPS16"
- "*
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/0,
- /*float_p=*/0,
- /*inverted_p=*/1,
- get_attr_length (insn));
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-;; Conditional branch on equality comparision.
-
-(define_insn "branch_equality"
- [(set (pc)
- (if_then_else
- (match_operator:SI 0 "equality_op"
- [(match_operand:SI 2 "register_operand" "d")
- (match_operand:SI 3 "register_operand" "d")])
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- "!TARGET_MIPS16"
- "*
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/1,
- /*float_p=*/0,
- /*inverted_p=*/0,
- get_attr_length (insn));
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-(define_insn "branch_equality_di"
- [(set (pc)
- (if_then_else
- (match_operator:DI 0 "equality_op"
- [(match_operand:DI 2 "se_register_operand" "d")
- (match_operand:DI 3 "se_register_operand" "d")])
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- "!TARGET_MIPS16"
- "*
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/1,
- /*float_p=*/0,
- /*inverted_p=*/0,
- get_attr_length (insn));
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-(define_insn "branch_equality_inverted"
- [(set (pc)
- (if_then_else
- (match_operator:SI 0 "equality_op"
- [(match_operand:SI 2 "register_operand" "d")
- (match_operand:SI 3 "register_operand" "d")])
- (pc)
- (label_ref (match_operand 1 "" ""))))]
- "!TARGET_MIPS16"
- "*
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/1,
- /*float_p=*/0,
- /*inverted_p=*/1,
- get_attr_length (insn));
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-(define_insn "branch_equality_di_inverted"
- [(set (pc)
- (if_then_else
- (match_operator:DI 0 "equality_op"
- [(match_operand:DI 2 "se_register_operand" "d")
- (match_operand:DI 3 "se_register_operand" "d")])
- (pc)
- (label_ref (match_operand 1 "" ""))))]
- "!TARGET_MIPS16"
- "*
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/1,
- /*float_p=*/0,
- /*inverted_p=*/1,
- get_attr_length (insn));
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
-
-;; MIPS16 branches
-
-(define_insn ""
- [(set (pc)
- (if_then_else (match_operator:SI 0 "equality_op"
- [(match_operand:SI 1 "register_operand" "d,t")
- (const_int 0)])
- (match_operand 2 "pc_or_label_operand" "")
- (match_operand 3 "pc_or_label_operand" "")))]
- "TARGET_MIPS16"
- "*
-{
- if (operands[2] != pc_rtx)
- {
- if (which_alternative == 0)
- return \"%*b%C0z\\t%1,%2\";
- else
- return \"%*bt%C0z\\t%2\";
- }
- else
- {
- if (which_alternative == 0)
- return \"%*b%N0z\\t%1,%3\";
- else
- return \"%*bt%N0z\\t%3\";
- }
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")
- (set_attr "length" "8")])
-
-(define_insn ""
- [(set (pc)
- (if_then_else (match_operator:DI 0 "equality_op"
- [(match_operand:DI 1 "se_register_operand" "d,t")
- (const_int 0)])
- (match_operand 2 "pc_or_label_operand" "")
- (match_operand 3 "pc_or_label_operand" "")))]
- "TARGET_MIPS16"
- "*
-{
- if (operands[2] != pc_rtx)
- {
- if (which_alternative == 0)
- return \"%*b%C0z\\t%1,%2\";
- else
- return \"%*bt%C0z\\t%2\";
- }
- else
- {
- if (which_alternative == 0)
- return \"%*b%N0z\\t%1,%3\";
- else
- return \"%*bt%N0z\\t%3\";
- }
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")
- (set_attr "length" "8")])
-
-(define_expand "beq"
- [(set (pc)
- (if_then_else (eq:CC (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code warning */
- {
- gen_conditional_branch (operands, EQ);
- DONE;
- }
-}")
-
-(define_expand "bne"
- [(set (pc)
- (if_then_else (ne:CC (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code warning */
- {
- gen_conditional_branch (operands, NE);
- DONE;
- }
-}")
-
-(define_expand "bgt"
- [(set (pc)
- (if_then_else (gt:CC (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code warning */
- {
- gen_conditional_branch (operands, GT);
- DONE;
- }
-}")
-
-(define_expand "bge"
- [(set (pc)
- (if_then_else (ge:CC (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code warning */
- {
- gen_conditional_branch (operands, GE);
- DONE;
- }
-}")
-
-(define_expand "blt"
- [(set (pc)
- (if_then_else (lt:CC (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code warning */
- {
- gen_conditional_branch (operands, LT);
- DONE;
- }
-}")
-
-(define_expand "ble"
- [(set (pc)
- (if_then_else (le:CC (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code warning */
- {
- gen_conditional_branch (operands, LE);
- DONE;
- }
-}")
-
-(define_expand "bgtu"
- [(set (pc)
- (if_then_else (gtu:CC (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code warning */
- {
- gen_conditional_branch (operands, GTU);
- DONE;
- }
-}")
-
-(define_expand "bgeu"
- [(set (pc)
- (if_then_else (geu:CC (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code warning */
- {
- gen_conditional_branch (operands, GEU);
- DONE;
- }
-}")
-
-
-(define_expand "bltu"
- [(set (pc)
- (if_then_else (ltu:CC (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code warning */
- {
- gen_conditional_branch (operands, LTU);
- DONE;
- }
-}")
-
-(define_expand "bleu"
- [(set (pc)
- (if_then_else (leu:CC (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (operands[0]) /* avoid unused code warning */
- {
- gen_conditional_branch (operands, LEU);
- DONE;
- }
-}")
-
-\f
-;;
-;; ....................
-;;
-;; SETTING A REGISTER FROM A COMPARISON
-;;
-;; ....................
-
-(define_expand "seq"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (eq:SI (match_dup 1)
- (match_dup 2)))]
- ""
- "
-{
- if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
- FAIL;
-
- /* set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
-
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
- {
- gen_int_relational (EQ, operands[0], operands[1], operands[2], (int *)0);
- DONE;
- }
-
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
- operands[2] = force_reg (SImode, operands[2]);
-
- /* fall through and generate default code */
-}")
-
-
-(define_insn "seq_si_zero"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (eq:SI (match_operand:SI 1 "register_operand" "d")
- (const_int 0)))]
- "!TARGET_MIPS16"
- "sltu\\t%0,%1,1"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=t")
- (eq:SI (match_operand:SI 1 "register_operand" "d")
- (const_int 0)))]
- "TARGET_MIPS16"
- "sltu\\t%1,1"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-(define_insn "seq_di_zero"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (eq:DI (match_operand:DI 1 "se_register_operand" "d")
- (const_int 0)))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "sltu\\t%0,%1,1"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=t")
- (eq:DI (match_operand:DI 1 "se_register_operand" "d")
- (const_int 0)))]
- "TARGET_64BIT && TARGET_MIPS16"
- "sltu\\t%1,1"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
-
-(define_insn "seq_si"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (eq:SI (match_operand:SI 1 "register_operand" "%d,d")
- (match_operand:SI 2 "uns_arith_operand" "d,K")))]
- "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "@
- xor\\t%0,%1,%2\;sltu\\t%0,%0,1
- xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "8")])
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (eq:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "uns_arith_operand" "")))]
- "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
- && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
- [(set (match_dup 0)
- (xor:SI (match_dup 1)
- (match_dup 2)))
- (set (match_dup 0)
- (ltu:SI (match_dup 0)
- (const_int 1)))]
- "")
-
-(define_insn "seq_di"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (eq:DI (match_operand:DI 1 "se_register_operand" "%d,d")
- (match_operand:DI 2 "se_uns_arith_operand" "d,K")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "@
- xor\\t%0,%1,%2\;sltu\\t%0,%0,1
- xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (eq:DI (match_operand:DI 1 "se_register_operand" "")
- (match_operand:DI 2 "se_uns_arith_operand" "")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
- && !TARGET_MIPS16
- && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
- [(set (match_dup 0)
- (xor:DI (match_dup 1)
- (match_dup 2)))
- (set (match_dup 0)
- (ltu:DI (match_dup 0)
- (const_int 1)))]
- "")
-
-;; On the mips16 the default code is better than using sltu.
-
-(define_expand "sne"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ne:SI (match_dup 1)
- (match_dup 2)))]
- "!TARGET_MIPS16"
- "
-{
- if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
- FAIL;
-
- /* set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
-
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
- {
- gen_int_relational (NE, operands[0], operands[1], operands[2], (int *)0);
- DONE;
- }
-
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
- operands[2] = force_reg (SImode, operands[2]);
-
- /* fall through and generate default code */
-}")
+;; Unlike most other insns, the move insns can't be split with
+;; different predicates, because register spilling and other parts of
+;; the compiler, have memoized the insn number already.
-(define_insn "sne_si_zero"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ne:SI (match_operand:SI 1 "register_operand" "d")
- (const_int 0)))]
- "!TARGET_MIPS16"
- "sltu\\t%0,%.,%1"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
+(define_expand "mov<mode>"
+ [(set (match_operand:IMOVE32 0 "")
+ (match_operand:IMOVE32 1 ""))]
+ ""
+{
+ if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
+ DONE;
+})
-(define_insn "sne_di_zero"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ne:DI (match_operand:DI 1 "se_register_operand" "d")
- (const_int 0)))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "sltu\\t%0,%.,%1"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
+;; The difference between these two is whether or not ints are allowed
+;; in FP registers (off by default, use -mdebugh to enable).
-(define_insn "sne_si"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (ne:SI (match_operand:SI 1 "register_operand" "%d,d")
- (match_operand:SI 2 "uns_arith_operand" "d,K")))]
- "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "@
- xor\\t%0,%1,%2\;sltu\\t%0,%.,%0
- xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "8")])
+(define_insn "*mov<mode>_internal"
+ [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
+ (match_operand:IMOVE32 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
+ "!TARGET_MIPS16
+ && (register_operand (operands[0], <MODE>mode)
+ || reg_or_0_operand (operands[1], <MODE>mode))"
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
+ (set_attr "mode" "SI")])
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (ne:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "uns_arith_operand" "")))]
- "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
- && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
- [(set (match_dup 0)
- (xor:SI (match_dup 1)
- (match_dup 2)))
- (set (match_dup 0)
- (gtu:SI (match_dup 0)
- (const_int 0)))]
- "")
+(define_insn "*mov<mode>_mips16"
+ [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
+ (match_operand:IMOVE32 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
+ "TARGET_MIPS16
+ && (register_operand (operands[0], <MODE>mode)
+ || register_operand (operands[1], <MODE>mode))"
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
+ (set_attr "mode" "SI")])
-(define_insn "sne_di"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (ne:DI (match_operand:DI 1 "se_register_operand" "%d,d")
- (match_operand:DI 2 "se_uns_arith_operand" "d,K")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "@
- xor\\t%0,%1,%2\;sltu\\t%0,%.,%0
- xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
+;; On the mips16, we can split lw $r,N($r) into an add and a load,
+;; when the original load is a 4 byte instruction but the add and the
+;; load are 2 2 byte instructions.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ne:DI (match_operand:DI 1 "se_register_operand" "")
- (match_operand:DI 2 "se_uns_arith_operand" "")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
- && !TARGET_MIPS16
- && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
- [(set (match_dup 0)
- (xor:DI (match_dup 1)
- (match_dup 2)))
- (set (match_dup 0)
- (gtu:DI (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_expand "sgt"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (gt:SI (match_dup 1)
- (match_dup 2)))]
- ""
- "
+ [(set (match_operand:SI 0 "d_operand")
+ (mem:SI (plus:SI (match_dup 0)
+ (match_operand:SI 1 "const_int_operand"))))]
+ "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
+ && ((INTVAL (operands[1]) < 0
+ && INTVAL (operands[1]) >= -0x80)
+ || (INTVAL (operands[1]) >= 32 * 4
+ && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
+ || (INTVAL (operands[1]) >= 0
+ && INTVAL (operands[1]) < 32 * 4
+ && (INTVAL (operands[1]) & 3) != 0))"
+ [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
+ (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
{
- if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
- FAIL;
+ HOST_WIDE_INT val = INTVAL (operands[1]);
- /* set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
+ if (val < 0)
+ operands[2] = const0_rtx;
+ else if (val >= 32 * 4)
+ {
+ int off = val & 3;
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
+ operands[1] = GEN_INT (0x7c + off);
+ operands[2] = GEN_INT (val - off - 0x7c);
+ }
+ else
{
- gen_int_relational (GT, operands[0], operands[1], operands[2], (int *)0);
- DONE;
+ int off = val & 3;
+
+ operands[1] = GEN_INT (off);
+ operands[2] = GEN_INT (val - off);
}
+})
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
- operands[2] = force_reg (SImode, operands[2]);
+;; On the mips16, we can split a load of certain constants into a load
+;; and an add. This turns a 4 byte instruction into 2 2 byte
+;; instructions.
- /* fall through and generate default code */
-}")
+(define_split
+ [(set (match_operand:SI 0 "d_operand")
+ (match_operand:SI 1 "const_int_operand"))]
+ "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
+ && INTVAL (operands[1]) >= 0x100
+ && INTVAL (operands[1]) <= 0xff + 0x7f"
+ [(set (match_dup 0) (match_dup 1))
+ (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
+{
+ int val = INTVAL (operands[1]);
-(define_insn "sgt_si"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (gt:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
- "!TARGET_MIPS16"
- "slt\\t%0,%z2,%1"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
+ operands[1] = GEN_INT (0xff);
+ operands[2] = GEN_INT (val - 0xff);
+})
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=t")
- (gt:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))]
- "TARGET_MIPS16"
- "slt\\t%2,%1"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
+;; This insn handles moving CCmode values. It's really just a
+;; slightly simplified copy of movsi_internal2, with additional cases
+;; to move a condition register to a general register and to move
+;; between the general registers and the floating point registers.
-(define_insn "sgt_di"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (gt:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_reg_or_0_operand" "dJ")))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "slt\\t%0,%z2,%1"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
+(define_insn "movcc"
+ [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
+ (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
+ "ISA_HAS_8CC && TARGET_HARD_FLOAT"
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "lui_movf,move,load,store,mfc,mtc,fmove,fpload,fpstore")
+ (set_attr "mode" "SI")])
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d")
- (gt:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))]
- "TARGET_64BIT && TARGET_MIPS16"
- "slt\\t%2,%1"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
+;; Reload condition code registers. reload_incc and reload_outcc
+;; both handle moves from arbitrary operands into condition code
+;; registers. reload_incc handles the more common case in which
+;; a source operand is constrained to be in a condition-code
+;; register, but has not been allocated to one.
+;;
+;; Sometimes, such as in movcc, we have a CCmode destination whose
+;; constraints do not include 'z'. reload_outcc handles the case
+;; when such an operand is allocated to a condition-code register.
+;;
+;; Note that reloads from a condition code register to some
+;; other location can be done using ordinary moves. Moving
+;; into a GPR takes a single movcc, moving elsewhere takes
+;; two. We can leave these cases to the generic reload code.
+(define_expand "reload_incc"
+ [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
+ (match_operand:CC 1 "general_operand" ""))
+ (clobber (match_operand:TF 2 "register_operand" "=&f"))]
+ "ISA_HAS_8CC && TARGET_HARD_FLOAT"
+{
+ mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
+ DONE;
+})
-(define_expand "sge"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ge:SI (match_dup 1)
- (match_dup 2)))]
- ""
- "
+(define_expand "reload_outcc"
+ [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
+ (match_operand:CC 1 "register_operand" ""))
+ (clobber (match_operand:TF 2 "register_operand" "=&f"))]
+ "ISA_HAS_8CC && TARGET_HARD_FLOAT"
{
- if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
- FAIL;
+ mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
+ DONE;
+})
- /* set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
+;; MIPS4 supports loading and storing a floating point register from
+;; the sum of two general registers. We use two versions for each of
+;; these four instructions: one where the two general registers are
+;; SImode, and one where they are DImode. This is because general
+;; registers will be in SImode when they hold 32-bit values, but,
+;; since the 32-bit values are always sign extended, the [ls][wd]xc1
+;; instructions will still work correctly.
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
- {
- gen_int_relational (GE, operands[0], operands[1], operands[2], (int *)0);
- DONE;
- }
+;; ??? Perhaps it would be better to support these instructions by
+;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
+;; these instructions can only be used to load and store floating
+;; point registers, that would probably cause trouble in reload.
- /* fall through and generate default code */
-}")
+(define_insn "*<ANYF:loadx>_<P:mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
+ (match_operand:P 2 "register_operand" "d"))))]
+ "ISA_HAS_FP4"
+ "<ANYF:loadx>\t%0,%1(%2)"
+ [(set_attr "type" "fpidxload")
+ (set_attr "mode" "<ANYF:UNITMODE>")])
+
+(define_insn "*<ANYF:storex>_<P:mode>"
+ [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
+ (match_operand:P 2 "register_operand" "d")))
+ (match_operand:ANYF 0 "register_operand" "f"))]
+ "ISA_HAS_FP4"
+ "<ANYF:storex>\t%0,%1(%2)"
+ [(set_attr "type" "fpidxstore")
+ (set_attr "mode" "<ANYF:UNITMODE>")])
+
+;; Scaled indexed address load.
+;; Per md.texi, we only need to look for a pattern with multiply in the
+;; address expression, not shift.
+
+(define_insn "*lwxs"
+ [(set (match_operand:IMOVE32 0 "register_operand" "=d")
+ (mem:IMOVE32
+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
+ (const_int 4))
+ (match_operand:SI 2 "register_operand" "d"))))]
+ "ISA_HAS_LWXS"
+ "lwxs\t%0,%1(%2)"
+ [(set_attr "type" "load")
+ (set_attr "mode" "SI")])
-(define_insn "sge_si"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ge:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "8")])
+;; 16-bit Integer moves
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (ge:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "arith_operand" "")))]
- "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
- [(set (match_dup 0)
- (lt:SI (match_dup 1)
- (match_dup 2)))
- (set (match_dup 0)
- (xor:SI (match_dup 0)
- (const_int 1)))]
- "")
+;; Unlike most other insns, the move insns can't be split with
+;; different predicates, because register spilling and other parts of
+;; the compiler, have memoized the insn number already.
+;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
-(define_insn "sge_di"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ge:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_arith_operand" "dI")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
+(define_expand "movhi"
+ [(set (match_operand:HI 0 "")
+ (match_operand:HI 1 ""))]
+ ""
+{
+ if (mips_legitimize_move (HImode, operands[0], operands[1]))
+ DONE;
+})
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ge:DI (match_operand:DI 1 "se_register_operand" "")
- (match_operand:DI 2 "se_arith_operand" "")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
- && !TARGET_MIPS16"
- [(set (match_dup 0)
- (lt:DI (match_dup 1)
- (match_dup 2)))
- (set (match_dup 0)
- (xor:DI (match_dup 0)
- (const_int 1)))]
- "")
+(define_insn "*movhi_internal"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
+ (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
+ "!TARGET_MIPS16
+ && (register_operand (operands[0], HImode)
+ || reg_or_0_operand (operands[1], HImode))"
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
+ (set_attr "mode" "HI")])
+
+(define_insn "*movhi_mips16"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
+ (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
+ "TARGET_MIPS16
+ && (register_operand (operands[0], HImode)
+ || register_operand (operands[1], HImode))"
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
+ (set_attr "mode" "HI")])
-(define_expand "slt"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (lt:SI (match_dup 1)
- (match_dup 2)))]
- ""
- "
+;; On the mips16, we can split lh $r,N($r) into an add and a load,
+;; when the original load is a 4 byte instruction but the add and the
+;; load are 2 2 byte instructions.
+
+(define_split
+ [(set (match_operand:HI 0 "d_operand")
+ (mem:HI (plus:SI (match_dup 0)
+ (match_operand:SI 1 "const_int_operand"))))]
+ "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
+ && ((INTVAL (operands[1]) < 0
+ && INTVAL (operands[1]) >= -0x80)
+ || (INTVAL (operands[1]) >= 32 * 2
+ && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
+ || (INTVAL (operands[1]) >= 0
+ && INTVAL (operands[1]) < 32 * 2
+ && (INTVAL (operands[1]) & 1) != 0))"
+ [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
+ (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
{
- if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
- FAIL;
+ HOST_WIDE_INT val = INTVAL (operands[1]);
- /* set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
+ if (val < 0)
+ operands[2] = const0_rtx;
+ else if (val >= 32 * 2)
+ {
+ int off = val & 1;
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
+ operands[1] = GEN_INT (0x7e + off);
+ operands[2] = GEN_INT (val - off - 0x7e);
+ }
+ else
{
- gen_int_relational (LT, operands[0], operands[1], operands[2], (int *)0);
- DONE;
+ int off = val & 1;
+
+ operands[1] = GEN_INT (off);
+ operands[2] = GEN_INT (val - off);
}
+})
- /* fall through and generate default code */
-}")
+;; 8-bit Integer moves
-(define_insn "slt_si"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (lt:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "!TARGET_MIPS16"
- "slt\\t%0,%1,%2"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
+;; Unlike most other insns, the move insns can't be split with
+;; different predicates, because register spilling and other parts of
+;; the compiler, have memoized the insn number already.
+;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=t,t")
- (lt:SI (match_operand:SI 1 "register_operand" "d,d")
- (match_operand:SI 2 "arith_operand" "d,I")))]
- "TARGET_MIPS16"
- "slt\\t%1,%2"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr_alternative "length"
- [(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
- (const_int 4)
- (const_int 8))])])
+(define_expand "movqi"
+ [(set (match_operand:QI 0 "")
+ (match_operand:QI 1 ""))]
+ ""
+{
+ if (mips_legitimize_move (QImode, operands[0], operands[1]))
+ DONE;
+})
-(define_insn "slt_di"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (lt:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_arith_operand" "dI")))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "slt\\t%0,%1,%2"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
+(define_insn "*movqi_internal"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
+ (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
+ "!TARGET_MIPS16
+ && (register_operand (operands[0], QImode)
+ || reg_or_0_operand (operands[1], QImode))"
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
+ (set_attr "mode" "QI")])
+
+(define_insn "*movqi_mips16"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
+ (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
+ "TARGET_MIPS16
+ && (register_operand (operands[0], QImode)
+ || register_operand (operands[1], QImode))"
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
+ (set_attr "mode" "QI")])
+
+;; On the mips16, we can split lb $r,N($r) into an add and a load,
+;; when the original load is a 4 byte instruction but the add and the
+;; load are 2 2 byte instructions.
+
+(define_split
+ [(set (match_operand:QI 0 "d_operand")
+ (mem:QI (plus:SI (match_dup 0)
+ (match_operand:SI 1 "const_int_operand"))))]
+ "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
+ && ((INTVAL (operands[1]) < 0
+ && INTVAL (operands[1]) >= -0x80)
+ || (INTVAL (operands[1]) >= 32
+ && INTVAL (operands[1]) <= 31 + 0x7f))"
+ [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
+ (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
+{
+ HOST_WIDE_INT val = INTVAL (operands[1]);
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=t,t")
- (lt:DI (match_operand:DI 1 "se_register_operand" "d,d")
- (match_operand:DI 2 "se_arith_operand" "d,I")))]
- "TARGET_64BIT && TARGET_MIPS16"
- "slt\\t%1,%2"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr_alternative "length"
- [(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
- (const_int 4)
- (const_int 8))])])
+ if (val < 0)
+ operands[2] = const0_rtx;
+ else
+ {
+ operands[1] = GEN_INT (0x7f);
+ operands[2] = GEN_INT (val - 0x7f);
+ }
+})
-(define_expand "sle"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (le:SI (match_dup 1)
- (match_dup 2)))]
+;; 32-bit floating point moves
+
+(define_expand "movsf"
+ [(set (match_operand:SF 0 "")
+ (match_operand:SF 1 ""))]
""
- "
{
- if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
- FAIL;
+ if (mips_legitimize_move (SFmode, operands[0], operands[1]))
+ DONE;
+})
- /* set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
+(define_insn "*movsf_hardfloat"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
+ (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
+ "TARGET_HARD_FLOAT
+ && (register_operand (operands[0], SFmode)
+ || reg_or_0_operand (operands[1], SFmode))"
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
+ (set_attr "mode" "SF")])
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
- {
- gen_int_relational (LE, operands[0], operands[1], operands[2], (int *)0);
- DONE;
- }
+(define_insn "*movsf_softfloat"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
+ (match_operand:SF 1 "move_operand" "Gd,m,d"))]
+ "TARGET_SOFT_FLOAT && !TARGET_MIPS16
+ && (register_operand (operands[0], SFmode)
+ || reg_or_0_operand (operands[1], SFmode))"
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "move,load,store")
+ (set_attr "mode" "SF")])
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
- operands[2] = force_reg (SImode, operands[2]);
+(define_insn "*movsf_mips16"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
+ (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
+ "TARGET_MIPS16
+ && (register_operand (operands[0], SFmode)
+ || register_operand (operands[1], SFmode))"
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "move,move,move,load,store")
+ (set_attr "mode" "SF")])
- /* fall through and generate default code */
-}")
+;; 64-bit floating point moves
-(define_insn "sle_si_const"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (le:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "I")))]
- "!TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
- "*
-{
- operands[2] = GEN_INT (INTVAL (operands[2])+1);
- return \"slt\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
+(define_expand "movdf"
+ [(set (match_operand:DF 0 "")
+ (match_operand:DF 1 ""))]
+ ""
+{
+ if (mips_legitimize_move (DFmode, operands[0], operands[1]))
+ DONE;
+})
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=t")
- (le:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "I")))]
- "TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
- "*
-{
- operands[2] = GEN_INT (INTVAL (operands[2])+1);
- return \"slt\\t%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
- (const_int 4)
- (const_int 8)))])
+(define_insn "*movdf_hardfloat"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
+ (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
+ && (register_operand (operands[0], DFmode)
+ || reg_or_0_operand (operands[1], DFmode))"
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
+ (set_attr "mode" "DF")])
-(define_insn "sle_di_const"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (le:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "small_int" "I")))]
- "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
- "*
-{
- operands[2] = GEN_INT (INTVAL (operands[2])+1);
- return \"slt\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
+(define_insn "*movdf_softfloat"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m")
+ (match_operand:DF 1 "move_operand" "dG,m,dG"))]
+ "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
+ && (register_operand (operands[0], DFmode)
+ || reg_or_0_operand (operands[1], DFmode))"
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "move,load,store")
+ (set_attr "mode" "DF")])
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=t")
- (le:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "small_int" "I")))]
- "TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
- "*
-{
- operands[2] = GEN_INT (INTVAL (operands[2])+1);
- return \"slt\\t%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
- (const_int 4)
- (const_int 8)))])
+(define_insn "*movdf_mips16"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
+ (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
+ "TARGET_MIPS16
+ && (register_operand (operands[0], DFmode)
+ || register_operand (operands[1], DFmode))"
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "move,move,move,load,store")
+ (set_attr "mode" "DF")])
-(define_insn "sle_si_reg"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (le:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))]
- "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "8")])
+;; 128-bit integer moves
+
+(define_expand "movti"
+ [(set (match_operand:TI 0)
+ (match_operand:TI 1))]
+ "TARGET_64BIT"
+{
+ if (mips_legitimize_move (TImode, operands[0], operands[1]))
+ DONE;
+})
+
+(define_insn "*movti"
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
+ (match_operand:TI 1 "move_operand" "d,i,m,dJ,*d*J,*a"))]
+ "TARGET_64BIT
+ && !TARGET_MIPS16
+ && (register_operand (operands[0], TImode)
+ || reg_or_0_operand (operands[1], TImode))"
+ "#"
+ [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
+ (set_attr "mode" "TI")])
+
+(define_insn "*movti_mips16"
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
+ (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
+ "TARGET_64BIT
+ && TARGET_MIPS16
+ && (register_operand (operands[0], TImode)
+ || register_operand (operands[1], TImode))"
+ "#"
+ [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
+ (set_attr "mode" "TI")])
+
+;; 128-bit floating point moves
+
+(define_expand "movtf"
+ [(set (match_operand:TF 0)
+ (match_operand:TF 1))]
+ "TARGET_64BIT"
+{
+ if (mips_legitimize_move (TFmode, operands[0], operands[1]))
+ DONE;
+})
+
+;; This pattern handles both hard- and soft-float cases.
+(define_insn "*movtf"
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m")
+ (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))]
+ "TARGET_64BIT
+ && !TARGET_MIPS16
+ && (register_operand (operands[0], TFmode)
+ || reg_or_0_operand (operands[1], TFmode))"
+ "#"
+ [(set_attr "move_type" "move,load,store,mtc,mfc,fpload,fpstore")
+ (set_attr "mode" "TF")])
+
+(define_insn "*movtf_mips16"
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m")
+ (match_operand:TF 1 "move_operand" "d,d,y,m,d"))]
+ "TARGET_64BIT
+ && TARGET_MIPS16
+ && (register_operand (operands[0], TFmode)
+ || register_operand (operands[1], TFmode))"
+ "#"
+ [(set_attr "move_type" "move,move,move,load,store")
+ (set_attr "mode" "TF")])
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (le:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "register_operand" "")))]
- "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
- [(set (match_dup 0)
- (lt:SI (match_dup 2)
- (match_dup 1)))
- (set (match_dup 0)
- (xor:SI (match_dup 0)
- (const_int 1)))]
- "")
+ [(set (match_operand:MOVE64 0 "nonimmediate_operand")
+ (match_operand:MOVE64 1 "move_operand"))]
+ "reload_completed && !TARGET_64BIT
+ && mips_split_64bit_move_p (operands[0], operands[1])"
+ [(const_int 0)]
+{
+ mips_split_doubleword_move (operands[0], operands[1]);
+ DONE;
+})
-(define_insn "sle_di_reg"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (le:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
+(define_split
+ [(set (match_operand:MOVE128 0 "nonimmediate_operand")
+ (match_operand:MOVE128 1 "move_operand"))]
+ "TARGET_64BIT && reload_completed"
+ [(const_int 0)]
+{
+ mips_split_doubleword_move (operands[0], operands[1]);
+ DONE;
+})
+;; When generating mips16 code, split moves of negative constants into
+;; a positive "li" followed by a negation.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (le:DI (match_operand:DI 1 "se_register_operand" "")
- (match_operand:DI 2 "se_register_operand" "")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
- && !TARGET_MIPS16"
- [(set (match_dup 0)
- (lt:DI (match_dup 2)
- (match_dup 1)))
- (set (match_dup 0)
- (xor:DI (match_dup 0)
- (const_int 1)))]
- "")
+ [(set (match_operand 0 "d_operand")
+ (match_operand 1 "const_int_operand"))]
+ "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
+ [(set (match_dup 2)
+ (match_dup 3))
+ (set (match_dup 2)
+ (neg:SI (match_dup 2)))]
+{
+ operands[2] = gen_lowpart (SImode, operands[0]);
+ operands[3] = GEN_INT (-INTVAL (operands[1]));
+})
+
+;; 64-bit paired-single floating point moves
+
+(define_expand "movv2sf"
+ [(set (match_operand:V2SF 0)
+ (match_operand:V2SF 1))]
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
+{
+ if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
+ DONE;
+})
+
+(define_insn "*movv2sf"
+ [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
+ (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
+ "TARGET_HARD_FLOAT
+ && TARGET_PAIRED_SINGLE_FLOAT
+ && (register_operand (operands[0], V2SFmode)
+ || reg_or_0_operand (operands[1], V2SFmode))"
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
+ (set_attr "mode" "DF")])
-(define_expand "sgtu"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (gtu:SI (match_dup 1)
- (match_dup 2)))]
+;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p
+;; for the reason why we can't just use (reg:GPR HI_REGNUM).
+;;
+;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI
+;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards
+;; and the errata related to -mfix-vr4130.
+(define_insn "mfhi<GPR:mode>_<HILO:mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (unspec:GPR [(match_operand:HILO 1 "register_operand" "x")]
+ UNSPEC_MFHI))]
""
- "
-{
- if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
- FAIL;
+ { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; }
+ [(set_attr "move_type" "mfhilo")
+ (set_attr "mode" "<GPR:MODE>")])
+
+;; Set the high part of a HI/LO value, given that the low part has
+;; already been set. See mips_hard_regno_mode_ok_p for the reason
+;; why we can't just use (reg:GPR HI_REGNUM).
+(define_insn "mthi<GPR:mode>_<HILO:mode>"
+ [(set (match_operand:HILO 0 "register_operand" "=x")
+ (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
+ (match_operand:GPR 2 "register_operand" "l")]
+ UNSPEC_MTHI))]
+ ""
+ "mthi\t%z1"
+ [(set_attr "move_type" "mthilo")
+ (set_attr "mode" "SI")])
- /* set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
+;; Emit a doubleword move in which exactly one of the operands is
+;; a floating-point register. We can't just emit two normal moves
+;; because of the constraints imposed by the FPU register model;
+;; see mips_cannot_change_mode_class for details. Instead, we keep
+;; the FPR whole and use special patterns to refer to each word of
+;; the other operand.
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
+(define_expand "move_doubleword_fpr<mode>"
+ [(set (match_operand:SPLITF 0)
+ (match_operand:SPLITF 1))]
+ ""
+{
+ if (FP_REG_RTX_P (operands[0]))
{
- gen_int_relational (GTU, operands[0], operands[1], operands[2], (int *)0);
- DONE;
+ rtx low = mips_subword (operands[1], 0);
+ rtx high = mips_subword (operands[1], 1);
+ emit_insn (gen_load_low<mode> (operands[0], low));
+ if (TARGET_FLOAT64 && !TARGET_64BIT)
+ emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
+ else
+ emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
}
+ else
+ {
+ rtx low = mips_subword (operands[0], 0);
+ rtx high = mips_subword (operands[0], 1);
+ emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
+ if (TARGET_FLOAT64 && !TARGET_64BIT)
+ emit_insn (gen_mfhc1<mode> (high, operands[1]));
+ else
+ emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
+ }
+ DONE;
+})
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
- operands[2] = force_reg (SImode, operands[2]);
-
- /* fall through and generate default code */
-}")
-
-(define_insn "sgtu_si"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (gtu:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
+;; Load the low word of operand 0 with operand 1.
+(define_insn "load_low<mode>"
+ [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
+ (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")]
+ UNSPEC_LOAD_LOW))]
+ "TARGET_HARD_FLOAT"
+{
+ operands[0] = mips_subword (operands[0], 0);
+ return mips_output_move (operands[0], operands[1]);
+}
+ [(set_attr "move_type" "mtc,fpload")
+ (set_attr "mode" "<HALFMODE>")])
+
+;; Load the high word of operand 0 from operand 1, preserving the value
+;; in the low word.
+(define_insn "load_high<mode>"
+ [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
+ (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")
+ (match_operand:SPLITF 2 "register_operand" "0,0")]
+ UNSPEC_LOAD_HIGH))]
+ "TARGET_HARD_FLOAT"
+{
+ operands[0] = mips_subword (operands[0], 1);
+ return mips_output_move (operands[0], operands[1]);
+}
+ [(set_attr "move_type" "mtc,fpload")
+ (set_attr "mode" "<HALFMODE>")])
+
+;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
+;; high word and 0 to store the low word.
+(define_insn "store_word<mode>"
+ [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m")
+ (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
+ (match_operand 2 "const_int_operand")]
+ UNSPEC_STORE_WORD))]
+ "TARGET_HARD_FLOAT"
+{
+ operands[1] = mips_subword (operands[1], INTVAL (operands[2]));
+ return mips_output_move (operands[0], operands[1]);
+}
+ [(set_attr "move_type" "mfc,fpstore")
+ (set_attr "mode" "<HALFMODE>")])
+
+;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
+;; value in the low word.
+(define_insn "mthc1<mode>"
+ [(set (match_operand:SPLITF 0 "register_operand" "=f")
+ (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ")
+ (match_operand:SPLITF 2 "register_operand" "0")]
+ UNSPEC_MTHC1))]
+ "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
+ "mthc1\t%z1,%0"
+ [(set_attr "move_type" "mtc")
+ (set_attr "mode" "<HALFMODE>")])
+
+;; Move high word of operand 1 to operand 0 using mfhc1.
+(define_insn "mfhc1<mode>"
+ [(set (match_operand:<HALFMODE> 0 "register_operand" "=d")
+ (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
+ UNSPEC_MFHC1))]
+ "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
+ "mfhc1\t%0,%1"
+ [(set_attr "move_type" "mfc")
+ (set_attr "mode" "<HALFMODE>")])
+
+;; Move a constant that satisfies CONST_GP_P into operand 0.
+(define_expand "load_const_gp_<mode>"
+ [(set (match_operand:P 0 "register_operand" "=d")
+ (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))])
+
+;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
+;; of _gp from the start of this function. Operand 1 is the incoming
+;; function address.
+(define_insn_and_split "loadgp_newabi_<mode>"
+ [(set (match_operand:P 0 "register_operand" "=d")
+ (unspec_volatile:P [(match_operand:P 1)
+ (match_operand:P 2 "register_operand" "d")]
+ UNSPEC_LOADGP))]
+ "mips_current_loadgp_style () == LOADGP_NEWABI"
+ "#"
""
- "sltu\\t%0,%z2,%1"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=t")
- (gtu:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))]
+ [(set (match_dup 0) (match_dup 3))
+ (set (match_dup 0) (match_dup 4))
+ (set (match_dup 0) (match_dup 5))]
+{
+ operands[3] = gen_rtx_HIGH (Pmode, operands[1]);
+ operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
+ operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]);
+}
+ [(set_attr "length" "12")])
+
+;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
+(define_insn_and_split "loadgp_absolute_<mode>"
+ [(set (match_operand:P 0 "register_operand" "=d")
+ (unspec_volatile:P [(match_operand:P 1)] UNSPEC_LOADGP))]
+ "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
+ "#"
""
- "sltu\\t%2,%1"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-(define_insn "sgtu_di"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (gtu:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_reg_or_0_operand" "dJ")))]
- "TARGET_64BIT"
- "sltu\\t%0,%z2,%1"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=t")
- (gtu:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))]
- "TARGET_64BIT"
- "sltu\\t%2,%1"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
-
-(define_expand "sgeu"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (geu:SI (match_dup 1)
- (match_dup 2)))]
+ [(const_int 0)]
+{
+ mips_emit_move (operands[0], operands[1]);
+ DONE;
+}
+ [(set_attr "length" "8")])
+
+;; This blockage instruction prevents the gp load from being
+;; scheduled after an implicit use of gp. It also prevents
+;; the load from being deleted as dead.
+(define_insn "loadgp_blockage"
+ [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)]
+ ""
+ ""
+ [(set_attr "type" "ghost")
+ (set_attr "mode" "none")])
+
+;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
+;; and operand 1 is the __GOTT_INDEX__ symbol.
+(define_insn_and_split "loadgp_rtp_<mode>"
+ [(set (match_operand:P 0 "register_operand" "=d")
+ (unspec_volatile:P [(match_operand:P 1 "symbol_ref_operand")
+ (match_operand:P 2 "symbol_ref_operand")]
+ UNSPEC_LOADGP))]
+ "mips_current_loadgp_style () == LOADGP_RTP"
+ "#"
+ ""
+ [(set (match_dup 0) (high:P (match_dup 3)))
+ (set (match_dup 0) (unspec:P [(match_dup 0)
+ (match_dup 3)] UNSPEC_LOAD_GOT))
+ (set (match_dup 0) (unspec:P [(match_dup 0)
+ (match_dup 4)] UNSPEC_LOAD_GOT))]
+{
+ operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE);
+ operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF);
+}
+ [(set_attr "length" "12")])
+
+;; Initialize the global pointer for MIPS16 code. Operand 0 is the
+;; global pointer and operand 1 is the MIPS16 register that holds
+;; the required value.
+(define_insn_and_split "copygp_mips16"
+ [(set (match_operand:SI 0 "register_operand" "=y")
+ (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d")]
+ UNSPEC_COPYGP))]
+ "TARGET_MIPS16"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (match_dup 1))])
+
+;; Emit a .cprestore directive, which normally expands to a single store
+;; instruction. Note that we continue to use .cprestore for explicit reloc
+;; code so that jals inside inline asms will work correctly.
+(define_insn "cprestore"
+ [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")
+ (use (reg:SI 28))]
+ UNSPEC_CPRESTORE)]
+ ""
+{
+ if (set_nomacro && which_alternative == 1)
+ return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
+ else
+ return ".cprestore\t%0";
+}
+ [(set_attr "type" "store")
+ (set_attr "length" "4,12")])
+
+;; Expand in-line code to clear the instruction cache between operand[0] and
+;; operand[1].
+(define_expand "clear_cache"
+ [(match_operand 0 "pmode_register_operand")
+ (match_operand 1 "pmode_register_operand")]
""
"
{
- if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
- FAIL;
+ if (ISA_HAS_SYNCI)
+ {
+ mips_expand_synci_loop (operands[0], operands[1]);
+ emit_insn (gen_sync ());
+ emit_insn (Pmode == SImode
+ ? gen_clear_hazard_si ()
+ : gen_clear_hazard_di ());
+ }
+ else if (mips_cache_flush_func && mips_cache_flush_func[0])
+ {
+ rtx len = gen_reg_rtx (Pmode);
+ emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
+ MIPS_ICACHE_SYNC (operands[0], len);
+ }
+ DONE;
+}")
+
+(define_insn "sync"
+ [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
+ "GENERATE_SYNC"
+ "%|sync%-")
+
+(define_insn "synci"
+ [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
+ UNSPEC_SYNCI)]
+ "ISA_HAS_SYNCI"
+ "synci\t0(%0)")
+
+(define_insn "rdhwr_synci_step_<mode>"
+ [(set (match_operand:P 0 "register_operand" "=d")
+ (unspec_volatile [(const_int 1)]
+ UNSPEC_RDHWR))]
+ "ISA_HAS_SYNCI"
+ "rdhwr\t%0,$1")
+
+(define_insn "clear_hazard_<mode>"
+ [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
+ (clobber (reg:P 31))]
+ "ISA_HAS_SYNCI"
+{
+ return "%(%<bal\t1f\n"
+ "\tnop\n"
+ "1:\t<d>addiu\t$31,$31,12\n"
+ "\tjr.hb\t$31\n"
+ "\tnop%>%)";
+}
+ [(set_attr "length" "20")])
+
+;; Cache operations for R4000-style caches.
+(define_insn "mips_cache"
+ [(set (mem:BLK (scratch))
+ (unspec:BLK [(match_operand:SI 0 "const_int_operand")
+ (match_operand:QI 1 "address_operand" "p")]
+ UNSPEC_MIPS_CACHE))]
+ "ISA_HAS_CACHE"
+ "cache\t%X0,%a1")
+
+;; Similar, but with the operands hard-coded to an R10K cache barrier
+;; operation. We keep the pattern distinct so that we can identify
+;; cache operations inserted by -mr10k-cache-barrier=, and so that
+;; the operation is never inserted into a delay slot.
+(define_insn "r10k_cache_barrier"
+ [(set (mem:BLK (scratch))
+ (unspec:BLK [(const_int 0)] UNSPEC_R10K_CACHE_BARRIER))]
+ "ISA_HAS_CACHE"
+ "cache\t0x14,0(%$)"
+ [(set_attr "can_delay" "no")])
+\f
+;; Block moves, see mips.c for more details.
+;; Argument 0 is the destination
+;; Argument 1 is the source
+;; Argument 2 is the length
+;; Argument 3 is the alignment
- /* set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
+(define_expand "movmemsi"
+ [(parallel [(set (match_operand:BLK 0 "general_operand")
+ (match_operand:BLK 1 "general_operand"))
+ (use (match_operand:SI 2 ""))
+ (use (match_operand:SI 3 "const_int_operand"))])]
+ "!TARGET_MIPS16 && !TARGET_MEMCPY"
+{
+ if (mips_expand_block_move (operands[0], operands[1], operands[2]))
+ DONE;
+ else
+ FAIL;
+})
+\f
+;;
+;; ....................
+;;
+;; SHIFTS
+;;
+;; ....................
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
+(define_expand "<optab><mode>3"
+ [(set (match_operand:GPR 0 "register_operand")
+ (any_shift:GPR (match_operand:GPR 1 "register_operand")
+ (match_operand:SI 2 "arith_operand")))]
+ ""
+{
+ /* On the mips16, a shift of more than 8 is a four byte instruction,
+ so, for a shift between 8 and 16, it is just as fast to do two
+ shifts of 8 or less. If there is a lot of shifting going on, we
+ may win in CSE. Otherwise combine will put the shifts back
+ together again. This can be called by mips_function_arg, so we must
+ be careful not to allocate a new register if we've reached the
+ reload pass. */
+ if (TARGET_MIPS16
+ && optimize
+ && GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) > 8
+ && INTVAL (operands[2]) <= 16
+ && !reload_in_progress
+ && !reload_completed)
{
- gen_int_relational (GEU, operands[0], operands[1], operands[2], (int *)0);
+ rtx temp = gen_reg_rtx (<MODE>mode);
+
+ emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
+ emit_insn (gen_<optab><mode>3 (operands[0], temp,
+ GEN_INT (INTVAL (operands[2]) - 8)));
DONE;
}
+})
- /* fall through and generate default code */
-}")
-
-(define_insn "sgeu_si"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (geu:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "8")])
+(define_insn "*<optab><mode>3"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:SI 2 "arith_operand" "dI")))]
+ "!TARGET_MIPS16"
+{
+ if (GET_CODE (operands[2]) == CONST_INT)
+ operands[2] = GEN_INT (INTVAL (operands[2])
+ & (GET_MODE_BITSIZE (<MODE>mode) - 1));
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (geu:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "arith_operand" "")))]
- "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
- [(set (match_dup 0)
- (ltu:SI (match_dup 1)
- (match_dup 2)))
- (set (match_dup 0)
- (xor:SI (match_dup 0)
- (const_int 1)))]
- "")
+ return "<d><insn>\t%0,%1,%2";
+}
+ [(set_attr "type" "shift")
+ (set_attr "mode" "<MODE>")])
-(define_insn "sgeu_di"
+(define_insn "*<optab>si3_extend"
[(set (match_operand:DI 0 "register_operand" "=d")
- (geu:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_arith_operand" "dI")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
+ (sign_extend:DI
+ (any_shift:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "arith_operand" "dI"))))]
+ "TARGET_64BIT && !TARGET_MIPS16"
+{
+ if (GET_CODE (operands[2]) == CONST_INT)
+ operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (geu:DI (match_operand:DI 1 "se_register_operand" "")
- (match_operand:DI 2 "se_arith_operand" "")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
- && !TARGET_MIPS16"
- [(set (match_dup 0)
- (ltu:DI (match_dup 1)
- (match_dup 2)))
- (set (match_dup 0)
- (xor:DI (match_dup 0)
- (const_int 1)))]
- "")
+ return "<insn>\t%0,%1,%2";
+}
+ [(set_attr "type" "shift")
+ (set_attr "mode" "SI")])
-(define_expand "sltu"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ltu:SI (match_dup 1)
- (match_dup 2)))]
- ""
- "
+(define_insn "*<optab>si3_mips16"
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
+ (match_operand:SI 2 "arith_operand" "d,I")))]
+ "TARGET_MIPS16"
{
- if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
- FAIL;
+ if (which_alternative == 0)
+ return "<insn>\t%0,%2";
- /* set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
+ operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+ return "<insn>\t%0,%1,%2";
+}
+ [(set_attr "type" "shift")
+ (set_attr "mode" "SI")
+ (set_attr_alternative "length"
+ [(const_int 4)
+ (if_then_else (match_operand 2 "m16_uimm3_b")
+ (const_int 4)
+ (const_int 8))])])
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
- {
- gen_int_relational (LTU, operands[0], operands[1], operands[2], (int *)0);
- DONE;
- }
+;; We need separate DImode MIPS16 patterns because of the irregularity
+;; of right shifts.
+(define_insn "*ashldi3_mips16"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
+ (match_operand:SI 2 "arith_operand" "d,I")))]
+ "TARGET_64BIT && TARGET_MIPS16"
+{
+ if (which_alternative == 0)
+ return "dsll\t%0,%2";
- /* fall through and generate default code */
-}")
+ operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
+ return "dsll\t%0,%1,%2";
+}
+ [(set_attr "type" "shift")
+ (set_attr "mode" "DI")
+ (set_attr_alternative "length"
+ [(const_int 4)
+ (if_then_else (match_operand 2 "m16_uimm3_b")
+ (const_int 4)
+ (const_int 8))])])
-(define_insn "sltu_si"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ltu:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "!TARGET_MIPS16"
- "sltu\\t%0,%1,%2"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
+(define_insn "*ashrdi3_mips16"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
+ (match_operand:SI 2 "arith_operand" "d,I")))]
+ "TARGET_64BIT && TARGET_MIPS16"
+{
+ if (GET_CODE (operands[2]) == CONST_INT)
+ operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=t,t")
- (ltu:SI (match_operand:SI 1 "register_operand" "d,d")
- (match_operand:SI 2 "arith_operand" "d,I")))]
- "TARGET_MIPS16"
- "sltu\\t%1,%2"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
+ return "dsra\t%0,%2";
+}
+ [(set_attr "type" "shift")
+ (set_attr "mode" "DI")
(set_attr_alternative "length"
[(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
+ (if_then_else (match_operand 2 "m16_uimm3_b")
(const_int 4)
(const_int 8))])])
-(define_insn "sltu_di"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ltu:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_arith_operand" "dI")))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "sltu\\t%0,%1,%2"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=t,t")
- (ltu:DI (match_operand:DI 1 "se_register_operand" "d,d")
- (match_operand:DI 2 "se_arith_operand" "d,I")))]
+(define_insn "*lshrdi3_mips16"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
+ (match_operand:SI 2 "arith_operand" "d,I")))]
"TARGET_64BIT && TARGET_MIPS16"
- "sltu\\t%1,%2"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
+{
+ if (GET_CODE (operands[2]) == CONST_INT)
+ operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
+
+ return "dsrl\t%0,%2";
+}
+ [(set_attr "type" "shift")
+ (set_attr "mode" "DI")
(set_attr_alternative "length"
[(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
+ (if_then_else (match_operand 2 "m16_uimm3_b")
(const_int 4)
(const_int 8))])])
-(define_expand "sleu"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (leu:SI (match_dup 1)
- (match_dup 2)))]
- ""
- "
-{
- if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
- FAIL;
-
- /* set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
-
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
- {
- gen_int_relational (LEU, operands[0], operands[1], operands[2], (int *)0);
- DONE;
- }
-
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
- operands[2] = force_reg (SImode, operands[2]);
+;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
- /* fall through and generate default code */
-}")
+(define_split
+ [(set (match_operand:GPR 0 "d_operand")
+ (any_shift:GPR (match_operand:GPR 1 "d_operand")
+ (match_operand:GPR 2 "const_int_operand")))]
+ "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
+ && INTVAL (operands[2]) > 8
+ && INTVAL (operands[2]) <= 16"
+ [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
+ (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
+ { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
-(define_insn "sleu_si_const"
+;; If we load a byte on the mips16 as a bitfield, the resulting
+;; sequence of instructions is too complicated for combine, because it
+;; involves four instructions: a load, a shift, a constant load into a
+;; register, and an and (the key problem here is that the mips16 does
+;; not have and immediate). We recognize a shift of a load in order
+;; to make it simple enough for combine to understand.
+;;
+;; The length here is the worst case: the length of the split version
+;; will be more accurate.
+(define_insn_and_split ""
[(set (match_operand:SI 0 "register_operand" "=d")
- (leu:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "I")))]
- "!TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
- "*
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
- return \"sltu\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=t")
- (leu:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "I")))]
- "TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
- "*
-{
- operands[2] = GEN_INT (INTVAL (operands[2])+1);
- return \"sltu\\t%1,%2\";
-}"
- [(set_attr "type" "arith")
+ (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
+ (match_operand:SI 2 "immediate_operand" "I")))]
+ "TARGET_MIPS16"
+ "#"
+ ""
+ [(set (match_dup 0) (match_dup 1))
+ (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
+ ""
+ [(set_attr "type" "load")
(set_attr "mode" "SI")
- (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
- (const_int 4)
- (const_int 8)))])
+ (set_attr "length" "16")])
-(define_insn "sleu_di_const"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (leu:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "small_int" "I")))]
- "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
- "*
+(define_insn "rotr<mode>3"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:SI 2 "arith_operand" "dI")))]
+ "ISA_HAS_ROR"
{
- operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
- return \"sltu\\t%0,%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=t")
- (leu:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "small_int" "I")))]
- "TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
- "*
-{
- operands[2] = GEN_INT (INTVAL (operands[2])+1);
- return \"sltu\\t%1,%2\";
-}"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
- (const_int 4)
- (const_int 8)))])
-
-(define_insn "sleu_si_reg"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (leu:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))]
- "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "8")])
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (leu:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "register_operand" "")))]
- "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
- [(set (match_dup 0)
- (ltu:SI (match_dup 2)
- (match_dup 1)))
- (set (match_dup 0)
- (xor:SI (match_dup 0)
- (const_int 1)))]
- "")
-
-(define_insn "sleu_di_reg"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (leu:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (leu:DI (match_operand:DI 1 "se_register_operand" "")
- (match_operand:DI 2 "se_register_operand" "")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
- && !TARGET_MIPS16"
- [(set (match_dup 0)
- (ltu:DI (match_dup 2)
- (match_dup 1)))
- (set (match_dup 0)
- (xor:DI (match_dup 0)
- (const_int 1)))]
- "")
+ if (GET_CODE (operands[2]) == CONST_INT)
+ gcc_assert (INTVAL (operands[2]) >= 0
+ && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
+ return "<d>ror\t%0,%1,%2";
+}
+ [(set_attr "type" "shift")
+ (set_attr "mode" "<MODE>")])
\f
;;
;; ....................
;;
-;; FLOATING POINT COMPARISONS
+;; COMPARISONS
;;
;; ....................
-(define_insn "seq_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (eq:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.eq.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "slt_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (lt:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.lt.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+;; Flow here is rather complex:
+;;
+;; 1) The cmp{si,di,sf,df} routine is called. It deposits the arguments
+;; into cmp_operands[] but generates no RTL.
+;;
+;; 2) The appropriate branch define_expand is called, which then
+;; creates the appropriate RTL for the comparison and branch.
+;; Different CC modes are used, based on what type of branch is
+;; done, so that we can constrain things appropriately. There
+;; are assumptions in the rest of GCC that break if we fold the
+;; operands into the branches for integer operations, and use cc0
+;; for floating point, so we use the fp status register instead.
+;; If needed, an appropriate temporary is created to hold the
+;; of the integer compare.
-(define_insn "sle_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (le:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "*
+(define_expand "cmp<mode>"
+ [(set (cc0)
+ (compare:CC (match_operand:GPR 0 "register_operand")
+ (match_operand:GPR 1 "nonmemory_operand")))]
+ ""
{
- return mips_fill_delay_slot (\"c.le.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ cmp_operands[0] = operands[0];
+ cmp_operands[1] = operands[1];
+ DONE;
+})
-(define_insn "sgt_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (gt:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "*
+(define_expand "cmp<mode>"
+ [(set (cc0)
+ (compare:CC (match_operand:SCALARF 0 "register_operand")
+ (match_operand:SCALARF 1 "register_operand")))]
+ ""
{
- return mips_fill_delay_slot (\"c.lt.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ cmp_operands[0] = operands[0];
+ cmp_operands[1] = operands[1];
+ DONE;
+})
+\f
+;;
+;; ....................
+;;
+;; CONDITIONAL BRANCHES
+;;
+;; ....................
-(define_insn "sge_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (ge:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.le.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+;; Conditional branches on floating-point equality tests.
-(define_insn "seq_sf"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (eq:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
+(define_insn "*branch_fp"
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "equality_operator"
+ [(match_operand:CC 2 "register_operand" "z")
+ (const_int 0)])
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
"TARGET_HARD_FLOAT"
- "*
{
- return mips_fill_delay_slot (\"c.eq.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ return mips_output_conditional_branch (insn, operands,
+ MIPS_BRANCH ("b%F0", "%Z2%1"),
+ MIPS_BRANCH ("b%W0", "%Z2%1"));
+}
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
-(define_insn "slt_sf"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (lt:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
+(define_insn "*branch_fp_inverted"
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "equality_operator"
+ [(match_operand:CC 2 "register_operand" "z")
+ (const_int 0)])
+ (pc)
+ (label_ref (match_operand 1 "" ""))))]
"TARGET_HARD_FLOAT"
- "*
{
- return mips_fill_delay_slot (\"c.lt.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+ return mips_output_conditional_branch (insn, operands,
+ MIPS_BRANCH ("b%W0", "%Z2%1"),
+ MIPS_BRANCH ("b%F0", "%Z2%1"));
+}
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
-(define_insn "sle_sf"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (le:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.le.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+;; Conditional branches on ordered comparisons with zero.
-(define_insn "sgt_sf"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (gt:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.lt.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+(define_insn "*branch_order<mode>"
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "order_operator"
+ [(match_operand:GPR 2 "register_operand" "d")
+ (const_int 0)])
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
+ "!TARGET_MIPS16"
+ { return mips_output_order_conditional_branch (insn, operands, false); }
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
-(define_insn "sge_sf"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (ge:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "*
-{
- return mips_fill_delay_slot (\"c.le.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
+(define_insn "*branch_order<mode>_inverted"
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "order_operator"
+ [(match_operand:GPR 2 "register_operand" "d")
+ (const_int 0)])
+ (pc)
+ (label_ref (match_operand 1 "" ""))))]
+ "!TARGET_MIPS16"
+ { return mips_output_order_conditional_branch (insn, operands, true); }
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
-\f
-;;
-;; ....................
-;;
-;; UNCONDITIONAL BRANCHES
-;;
-;; ....................
+;; Conditional branch on equality comparison.
-;; Unconditional branches.
+(define_insn "*branch_equality<mode>"
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "equality_operator"
+ [(match_operand:GPR 2 "register_operand" "d")
+ (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
+ "!TARGET_MIPS16"
+{
+ return mips_output_conditional_branch (insn, operands,
+ MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
+ MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
+}
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
-(define_insn "jump"
+(define_insn "*branch_equality<mode>_inverted"
[(set (pc)
- (label_ref (match_operand 0 "" "")))]
+ (if_then_else
+ (match_operator 0 "equality_operator"
+ [(match_operand:GPR 2 "register_operand" "d")
+ (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
+ (pc)
+ (label_ref (match_operand 1 "" ""))))]
"!TARGET_MIPS16"
- "*
-{
- if (GET_CODE (operands[0]) == REG)
- return \"%*j\\t%0\";
- /* ??? I don't know why this is necessary. This works around an
- assembler problem that appears when a label is defined, then referenced
- in a switch table, then used in a `j' instruction. */
- else if (mips_abi != ABI_32 && mips_abi != ABI_O64)
- return \"%*b\\t%l0\";
- else
- return \"%*j\\t%l0\";
-}"
- [(set_attr "type" "jump")
- (set_attr "mode" "none")])
+{
+ return mips_output_conditional_branch (insn, operands,
+ MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
+ MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
+}
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
-;; We need a different insn for the mips16, because a mips16 branch
-;; does not have a delay slot.
+;; MIPS16 branches
-(define_insn ""
+(define_insn "*branch_equality<mode>_mips16"
[(set (pc)
- (label_ref (match_operand 0 "" "")))]
- "TARGET_MIPS16 && GET_CODE (operands[0]) != REG"
- "b\\t%l0"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")
- (set_attr "length" "8")])
+ (if_then_else
+ (match_operator 0 "equality_operator"
+ [(match_operand:GPR 1 "register_operand" "d,t")
+ (const_int 0)])
+ (match_operand 2 "pc_or_label_operand" "")
+ (match_operand 3 "pc_or_label_operand" "")))]
+ "TARGET_MIPS16"
+{
+ if (operands[2] != pc_rtx)
+ {
+ if (which_alternative == 0)
+ return "b%C0z\t%1,%2";
+ else
+ return "bt%C0z\t%2";
+ }
+ else
+ {
+ if (which_alternative == 0)
+ return "b%N0z\t%1,%3";
+ else
+ return "bt%N0z\t%3";
+ }
+}
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
-(define_expand "indirect_jump"
- [(set (pc) (match_operand 0 "register_operand" "d"))]
+(define_expand "b<code>"
+ [(set (pc)
+ (if_then_else (any_cond:CC (cc0)
+ (const_int 0))
+ (label_ref (match_operand 0 ""))
+ (pc)))]
""
- "
{
- rtx dest;
+ mips_expand_conditional_branch (operands, <CODE>);
+ DONE;
+})
- if (operands[0]) /* eliminate unused code warnings */
- {
- dest = operands[0];
- if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
- operands[0] = copy_to_mode_reg (Pmode, dest);
+;; Used to implement built-in functions.
+(define_expand "condjump"
+ [(set (pc)
+ (if_then_else (match_operand 0)
+ (label_ref (match_operand 1))
+ (pc)))])
- if (!(Pmode == DImode))
- emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
- else
- emit_jump_insn (gen_indirect_jump_internal2 (operands[0]));
+;; Branch if bit is set/clear.
- DONE;
- }
-}")
+(define_insn "*branch_bit<bbv><mode>"
+ [(set (pc)
+ (if_then_else
+ (equality_op (zero_extract:GPR
+ (match_operand:GPR 0 "register_operand" "d")
+ (const_int 1)
+ (match_operand 2 "const_int_operand" ""))
+ (const_int 0))
+ (label_ref (match_operand 1 ""))
+ (pc)))]
+ "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
+{
+ return
+ mips_output_conditional_branch (insn, operands,
+ MIPS_BRANCH ("bbit<bbv>", "%0,%2,%1"),
+ MIPS_BRANCH ("bbit<bbinv>", "%0,%2,%1"));
+}
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")
+ (set_attr "branch_likely" "no")])
+
+(define_insn "*branch_bit<bbv><mode>_inverted"
+ [(set (pc)
+ (if_then_else
+ (equality_op (zero_extract:GPR
+ (match_operand:GPR 0 "register_operand" "d")
+ (const_int 1)
+ (match_operand 2 "const_int_operand" ""))
+ (const_int 0))
+ (pc)
+ (label_ref (match_operand 1 ""))))]
+ "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
+{
+ return
+ mips_output_conditional_branch (insn, operands,
+ MIPS_BRANCH ("bbit<bbinv>", "%0,%2,%1"),
+ MIPS_BRANCH ("bbit<bbv>", "%0,%2,%1"));
+}
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")
+ (set_attr "branch_likely" "no")])
+\f
+;;
+;; ....................
+;;
+;; SETTING A REGISTER FROM A COMPARISON
+;;
+;; ....................
-(define_insn "indirect_jump_internal1"
- [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
- "!(Pmode == DImode)"
- "%*j\\t%0"
- [(set_attr "type" "jump")
- (set_attr "mode" "none")])
+;; Destination is always set in SI mode.
-(define_insn "indirect_jump_internal2"
- [(set (pc) (match_operand:DI 0 "se_register_operand" "d"))]
- "Pmode == DImode"
- "%*j\\t%0"
- [(set_attr "type" "jump")
- (set_attr "mode" "none")])
+(define_expand "seq"
+ [(set (match_operand:SI 0 "register_operand")
+ (eq:SI (match_dup 1)
+ (match_dup 2)))]
+ ""
+ { if (mips_expand_scc (EQ, operands[0])) DONE; else FAIL; })
+
+(define_insn "*seq_zero_<GPR:mode><GPR2:mode>"
+ [(set (match_operand:GPR2 0 "register_operand" "=d")
+ (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
+ (const_int 0)))]
+ "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
+ "sltu\t%0,%1,1"
+ [(set_attr "type" "slt")
+ (set_attr "mode" "<GPR:MODE>")])
+
+(define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16"
+ [(set (match_operand:GPR2 0 "register_operand" "=t")
+ (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
+ (const_int 0)))]
+ "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
+ "sltu\t%1,1"
+ [(set_attr "type" "slt")
+ (set_attr "mode" "<GPR:MODE>")])
+
+;; Generate sltiu unless using seq results in better code.
+(define_insn "*seq_<GPR:mode><GPR2:mode>_seq"
+ [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
+ (eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
+ (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
+ "ISA_HAS_SEQ_SNE"
+ "@
+ seq\t%0,%1,%2
+ sltiu\t%0,%1,1
+ seqi\t%0,%1,%2"
+ [(set_attr "type" "slt")
+ (set_attr "mode" "<GPR:MODE>")])
-(define_expand "tablejump"
- [(set (pc)
- (match_operand 0 "register_operand" "d"))
- (use (label_ref (match_operand 1 "" "")))]
+;; "sne" uses sltu instructions in which the first operand is $0.
+;; This isn't possible in mips16 code.
+
+(define_expand "sne"
+ [(set (match_operand:SI 0 "register_operand")
+ (ne:SI (match_dup 1)
+ (match_dup 2)))]
+ "!TARGET_MIPS16"
+ { if (mips_expand_scc (NE, operands[0])) DONE; else FAIL; })
+
+(define_insn "*sne_zero_<GPR:mode><GPR2:mode>"
+ [(set (match_operand:GPR2 0 "register_operand" "=d")
+ (ne:GPR2 (match_operand:GPR 1 "register_operand" "d")
+ (const_int 0)))]
+ "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
+ "sltu\t%0,%.,%1"
+ [(set_attr "type" "slt")
+ (set_attr "mode" "<GPR:MODE>")])
+
+;; Generate sltu unless using sne results in better code.
+(define_insn "*sne_<GPR:mode><GPR2:mode>_sne"
+ [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
+ (ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
+ (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
+ "ISA_HAS_SEQ_SNE"
+ "@
+ sne\t%0,%1,%2
+ sltu\t%0,%.,%1
+ snei\t%0,%1,%2"
+ [(set_attr "type" "slt")
+ (set_attr "mode" "<GPR:MODE>")])
+
+(define_expand "sgt<u>"
+ [(set (match_operand:SI 0 "register_operand")
+ (any_gt:SI (match_dup 1)
+ (match_dup 2)))]
""
- "
-{
- if (operands[0]) /* eliminate unused code warnings */
- {
- if (TARGET_MIPS16)
- {
- if (GET_MODE (operands[0]) != HImode)
- abort ();
- if (!(Pmode == DImode))
- emit_insn (gen_tablejump_mips161 (operands[0], operands[1]));
- else
- emit_insn (gen_tablejump_mips162 (operands[0], operands[1]));
- DONE;
- }
+ { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
- if (GET_MODE (operands[0]) != Pmode)
- abort ();
+(define_insn "*sgt<u>_<GPR:mode><GPR2:mode>"
+ [(set (match_operand:GPR2 0 "register_operand" "=d")
+ (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
+ "!TARGET_MIPS16"
+ "slt<u>\t%0,%z2,%1"
+ [(set_attr "type" "slt")
+ (set_attr "mode" "<GPR:MODE>")])
+
+(define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16"
+ [(set (match_operand:GPR2 0 "register_operand" "=t")
+ (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "register_operand" "d")))]
+ "TARGET_MIPS16"
+ "slt<u>\t%2,%1"
+ [(set_attr "type" "slt")
+ (set_attr "mode" "<GPR:MODE>")])
- if (! flag_pic)
- {
- if (!(Pmode == DImode))
- emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
- else
- emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
- }
- else
- {
- if (!(Pmode == DImode))
- emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1]));
- else
- emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1]));
- }
+(define_expand "sge<u>"
+ [(set (match_operand:SI 0 "register_operand")
+ (any_ge:SI (match_dup 1)
+ (match_dup 2)))]
+ ""
+ { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
- DONE;
- }
-}")
+(define_insn "*sge<u>_<GPR:mode><GPR2:mode>"
+ [(set (match_operand:GPR2 0 "register_operand" "=d")
+ (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d")
+ (const_int 1)))]
+ "!TARGET_MIPS16"
+ "slt<u>\t%0,%.,%1"
+ [(set_attr "type" "slt")
+ (set_attr "mode" "<GPR:MODE>")])
-(define_insn "tablejump_internal1"
- [(set (pc)
- (match_operand:SI 0 "register_operand" "d"))
- (use (label_ref (match_operand 1 "" "")))]
- "!(Pmode == DImode)"
- "%*j\\t%0"
- [(set_attr "type" "jump")
- (set_attr "mode" "none")])
+(define_expand "slt<u>"
+ [(set (match_operand:SI 0 "register_operand")
+ (any_lt:SI (match_dup 1)
+ (match_dup 2)))]
+ ""
+ { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
-(define_insn "tablejump_internal2"
- [(set (pc)
- (match_operand:DI 0 "se_register_operand" "d"))
- (use (label_ref (match_operand 1 "" "")))]
- "Pmode == DImode"
- "%*j\\t%0"
- [(set_attr "type" "jump")
- (set_attr "mode" "none")])
+(define_insn "*slt<u>_<GPR:mode><GPR2:mode>"
+ [(set (match_operand:GPR2 0 "register_operand" "=d")
+ (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "arith_operand" "dI")))]
+ "!TARGET_MIPS16"
+ "slt<u>\t%0,%1,%2"
+ [(set_attr "type" "slt")
+ (set_attr "mode" "<GPR:MODE>")])
+
+(define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16"
+ [(set (match_operand:GPR2 0 "register_operand" "=t,t")
+ (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d")
+ (match_operand:GPR 2 "arith_operand" "d,I")))]
+ "TARGET_MIPS16"
+ "slt<u>\t%1,%2"
+ [(set_attr "type" "slt")
+ (set_attr "mode" "<GPR:MODE>")
+ (set_attr_alternative "length"
+ [(const_int 4)
+ (if_then_else (match_operand 2 "m16_uimm8_1")
+ (const_int 4)
+ (const_int 8))])])
-(define_expand "tablejump_internal3"
- [(parallel [(set (pc)
- (plus:SI (match_operand:SI 0 "register_operand" "d")
- (label_ref:SI (match_operand 1 "" ""))))
- (use (label_ref:SI (match_dup 1)))])]
+(define_expand "sle<u>"
+ [(set (match_operand:SI 0 "register_operand")
+ (any_le:SI (match_dup 1)
+ (match_dup 2)))]
""
- "")
+ { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
-(define_expand "tablejump_mips161"
- [(set (pc) (plus:SI (sign_extend:SI
- (match_operand:HI 0 "register_operand" "d"))
- (label_ref:SI (match_operand 1 "" ""))))]
- "TARGET_MIPS16 && !(Pmode == DImode)"
- "
+(define_insn "*sle<u>_<GPR:mode><GPR2:mode>"
+ [(set (match_operand:GPR2 0 "register_operand" "=d")
+ (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "sle_operand" "")))]
+ "!TARGET_MIPS16"
{
- if (operands[0]) /* eliminate unused code warnings. */
- {
- rtx t1, t2, t3;
-
- t1 = gen_reg_rtx (SImode);
- t2 = gen_reg_rtx (SImode);
- t3 = gen_reg_rtx (SImode);
- emit_insn (gen_extendhisi2 (t1, operands[0]));
- emit_move_insn (t2, gen_rtx (LABEL_REF, SImode, operands[1]));
- emit_insn (gen_addsi3 (t3, t1, t2));
- emit_jump_insn (gen_tablejump_internal1 (t3, operands[1]));
- DONE;
- }
-}")
-
-(define_expand "tablejump_mips162"
- [(set (pc) (plus:DI (sign_extend:DI
- (match_operand:HI 0 "register_operand" "d"))
- (label_ref:DI (match_operand 1 "" ""))))]
- "TARGET_MIPS16 && Pmode == DImode"
- "
+ operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
+ return "slt<u>\t%0,%1,%2";
+}
+ [(set_attr "type" "slt")
+ (set_attr "mode" "<GPR:MODE>")])
+
+(define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16"
+ [(set (match_operand:GPR2 0 "register_operand" "=t")
+ (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "sle_operand" "")))]
+ "TARGET_MIPS16"
{
- if (operands[0]) /* eliminate unused code warnings. */
- {
- rtx t1, t2, t3;
-
- t1 = gen_reg_rtx (DImode);
- t2 = gen_reg_rtx (DImode);
- t3 = gen_reg_rtx (DImode);
- emit_insn (gen_extendhidi2 (t1, operands[0]));
- emit_move_insn (t2, gen_rtx (LABEL_REF, DImode, operands[1]));
- emit_insn (gen_adddi3 (t3, t1, t2));
- emit_jump_insn (gen_tablejump_internal2 (t3, operands[1]));
- DONE;
- }
-}")
+ operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
+ return "slt<u>\t%1,%2";
+}
+ [(set_attr "type" "slt")
+ (set_attr "mode" "<GPR:MODE>")
+ (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
+ (const_int 4)
+ (const_int 8)))])
+\f
+;;
+;; ....................
+;;
+;; FLOATING POINT COMPARISONS
+;;
+;; ....................
+
+(define_insn "s<code>_<mode>"
+ [(set (match_operand:CC 0 "register_operand" "=z")
+ (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
+ (match_operand:SCALARF 2 "register_operand" "f")))]
+ ""
+ "c.<fcond>.<fmt>\t%Z0%1,%2"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
-;;; Make sure that this only matches the insn before ADDR_DIFF_VEC. Otherwise
-;;; it is not valid. ??? With the USE, the condition tests may not be required
-;;; any longer.
+(define_insn "s<code>_<mode>"
+ [(set (match_operand:CC 0 "register_operand" "=z")
+ (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
+ (match_operand:SCALARF 2 "register_operand" "f")))]
+ ""
+ "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
+\f
+;;
+;; ....................
+;;
+;; UNCONDITIONAL BRANCHES
+;;
+;; ....................
-;;; ??? The length depends on the ABI. It is two for o32, and one for n32.
-;;; We just use the conservative number here.
+;; Unconditional branches.
-(define_insn ""
+(define_insn "jump"
[(set (pc)
- (plus:SI (match_operand:SI 0 "register_operand" "d")
- (label_ref:SI (match_operand 1 "" ""))))
- (use (label_ref:SI (match_dup 1)))]
- "!(Pmode == DImode) && next_active_insn (insn) != 0
- && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
- && PREV_INSN (next_active_insn (insn)) == operands[1]"
- "*
-{
- /* .cpadd expands to add REG,REG,$gp when pic, and nothing when not pic. */
- if (mips_abi == ABI_32 || mips_abi == ABI_O64)
- output_asm_insn (\".cpadd\\t%0\", operands);
- return \"%*j\\t%0\";
-}"
+ (label_ref (match_operand 0 "" "")))]
+ "!TARGET_MIPS16"
+{
+ if (flag_pic)
+ {
+ if (get_attr_length (insn) <= 8)
+ return "%*b\t%l0%/";
+ else
+ {
+ output_asm_insn (mips_output_load_label (), operands);
+ return "%*jr\t%@%/%]";
+ }
+ }
+ else
+ return "%*j\t%l0%/";
+}
[(set_attr "type" "jump")
(set_attr "mode" "none")
- (set_attr "length" "8")])
-
-(define_expand "tablejump_internal4"
- [(parallel [(set (pc)
- (plus:DI (match_operand:DI 0 "se_register_operand" "d")
- (label_ref:DI (match_operand 1 "" ""))))
- (use (label_ref:DI (match_dup 1)))])]
- ""
- "")
+ (set (attr "length")
+ ;; We can't use `j' when emitting PIC. Emit a branch if it's
+ ;; in range, otherwise load the address of the branch target into
+ ;; $at and then jump to it.
+ (if_then_else
+ (ior (eq (symbol_ref "flag_pic") (const_int 0))
+ (lt (abs (minus (match_dup 0)
+ (plus (pc) (const_int 4))))
+ (const_int 131072)))
+ (const_int 4) (const_int 16)))])
-;;; Make sure that this only matches the insn before ADDR_DIFF_VEC. Otherwise
-;;; it is not valid. ??? With the USE, the condition tests may not be required
-;;; any longer.
+;; We need a different insn for the mips16, because a mips16 branch
+;; does not have a delay slot.
(define_insn ""
[(set (pc)
- (plus:DI (match_operand:DI 0 "se_register_operand" "d")
- (label_ref:DI (match_operand 1 "" ""))))
- (use (label_ref:DI (match_dup 1)))]
- "Pmode == DImode && next_active_insn (insn) != 0
- && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
- && PREV_INSN (next_active_insn (insn)) == operands[1]"
- "%*j\\t%0"
- [(set_attr "type" "jump")
- (set_attr "mode" "none")])
-
-;; Implement a switch statement when generating embedded PIC code.
-;; Switches are implemented by `tablejump' when not using -membedded-pic.
+ (label_ref (match_operand 0 "" "")))]
+ "TARGET_MIPS16"
+ "b\t%l0"
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
-(define_expand "casesi"
- [(set (match_dup 5)
- (minus:SI (match_operand:SI 0 "register_operand" "d")
- (match_operand:SI 1 "arith_operand" "dI")))
- (set (cc0)
- (compare:CC (match_dup 5)
- (match_operand:SI 2 "arith_operand" "")))
- (set (pc)
- (if_then_else (gtu (cc0)
- (const_int 0))
- (label_ref (match_operand 4 "" ""))
- (pc)))
- (parallel
- [(set (pc)
- (mem:SI (plus:SI (mult:SI (match_dup 5)
- (const_int 4))
- (label_ref (match_operand 3 "" "")))))
- (clobber (match_scratch:SI 6 ""))
- (clobber (reg:SI 31))])]
- "TARGET_EMBEDDED_PIC"
- "
+(define_expand "indirect_jump"
+ [(set (pc) (match_operand 0 "register_operand"))]
+ ""
{
- if (operands[0])
- {
- rtx reg = gen_reg_rtx (SImode);
-
- /* If the index is too large, go to the default label. */
- emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
- emit_insn (gen_cmpsi (reg, operands[2]));
- emit_insn (gen_bgtu (operands[4]));
-
- /* Do the PIC jump. */
- if (Pmode != DImode)
- emit_jump_insn (gen_casesi_internal (reg, operands[3],
- gen_reg_rtx (SImode)));
- else
- emit_jump_insn (gen_casesi_internal_di (reg, operands[3],
- gen_reg_rtx (DImode)));
+ operands[0] = force_reg (Pmode, operands[0]);
+ if (Pmode == SImode)
+ emit_jump_insn (gen_indirect_jumpsi (operands[0]));
+ else
+ emit_jump_insn (gen_indirect_jumpdi (operands[0]));
+ DONE;
+})
- DONE;
- }
-}")
+(define_insn "indirect_jump<mode>"
+ [(set (pc) (match_operand:P 0 "register_operand" "d"))]
+ ""
+ "%*j\t%0%/"
+ [(set_attr "type" "jump")
+ (set_attr "mode" "none")])
-;; An embedded PIC switch statement looks like this:
-;; bal $LS1
-;; sll $reg,$index,2
-;; $LS1:
-;; addu $reg,$reg,$31
-;; lw $reg,$L1-$LS1($reg)
-;; addu $reg,$reg,$31
-;; j $reg
-;; $L1:
-;; .word case1-$LS1
-;; .word case2-$LS1
-;; ...
-
-(define_insn "casesi_internal"
+(define_expand "tablejump"
[(set (pc)
- (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "d")
- (const_int 4))
- (label_ref (match_operand 1 "" "")))))
- (clobber (match_operand:SI 2 "register_operand" "=d"))
- (clobber (reg:SI 31))]
- "TARGET_EMBEDDED_PIC"
- "%(bal\\t%S1\;sll\\t%2,%0,2\\n%~%S1:\;addu\\t%2,%2,$31%)\;\\
-lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\\n\\t%*j\\t%2"
- [(set_attr "type" "jump")
- (set_attr "mode" "none")
- (set_attr "length" "24")])
+ (match_operand 0 "register_operand"))
+ (use (label_ref (match_operand 1 "")))]
+ ""
+{
+ if (TARGET_MIPS16_SHORT_JUMP_TABLES)
+ operands[0] = expand_binop (Pmode, add_optab,
+ convert_to_mode (Pmode, operands[0], false),
+ gen_rtx_LABEL_REF (Pmode, operands[1]),
+ 0, 0, OPTAB_WIDEN);
+ else if (TARGET_GPWORD)
+ operands[0] = expand_binop (Pmode, add_optab, operands[0],
+ pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
+ else if (TARGET_RTP_PIC)
+ {
+ /* When generating RTP PIC, we use case table entries that are relative
+ to the start of the function. Add the function's address to the
+ value we loaded. */
+ rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
+ operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
+ start, 0, 0, OPTAB_WIDEN);
+ }
+
+ if (Pmode == SImode)
+ emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
+ else
+ emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
+ DONE;
+})
-;; This code assumes that the table index will never be >= 29 bits wide,
-;; which allows the 'sign extend' from SI to DI be a no-op.
-(define_insn "casesi_internal_di"
+(define_insn "tablejump<mode>"
[(set (pc)
- (mem:DI (plus:DI (sign_extend:DI
- (mult:SI (match_operand:SI 0 "register_operand" "d")
- (const_int 8)))
- (label_ref (match_operand 1 "" "")))))
- (clobber (match_operand:DI 2 "register_operand" "=d"))
- (clobber (reg:DI 31))]
- "TARGET_EMBEDDED_PIC"
- "%(bal\\t%S1\;sll\\t%2,%0,3\\n%~%S1:\;daddu\\t%2,%2,$31%)\;\\
-ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
- [(set_attr "type" "jump")
- (set_attr "mode" "none")
- (set_attr "length" "24")])
+ (match_operand:P 0 "register_operand" "d"))
+ (use (label_ref (match_operand 1 "" "")))]
+ ""
+ "%*j\t%0%/"
+ [(set_attr "type" "jump")
+ (set_attr "mode" "none")])
-;; For o32/n32/n64, we save the gp in the jmp_buf as well. While it is
-;; possible to either pull it off the stack (in the o32 case) or recalculate
-;; it given t9 and our target label, it takes 3 or 4 insns to do so, and
-;; this is easy.
+;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
+;; While it is possible to either pull it off the stack (in the
+;; o32 case) or recalculate it given t9 and our target label,
+;; it takes 3 or 4 insns to do so.
(define_expand "builtin_setjmp_setup"
- [(unspec [(match_operand 0 "register_operand" "r")] 20)]
- "TARGET_ABICALLS"
- "
+ [(use (match_operand 0 "register_operand"))]
+ "TARGET_USE_GOT"
{
- if (Pmode == DImode)
- emit_insn (gen_builtin_setjmp_setup_64 (operands[0]));
- else
- emit_insn (gen_builtin_setjmp_setup_32 (operands[0]));
- DONE;
-}")
-
-(define_expand "builtin_setjmp_setup_32"
- [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
- (const_int 12)))
- (reg:SI 28))]
- "TARGET_ABICALLS && ! (Pmode == DImode)"
- "")
+ rtx addr;
-(define_expand "builtin_setjmp_setup_64"
- [(set (mem:DI (plus:DI (match_operand:DI 0 "register_operand" "r")
- (const_int 24)))
- (reg:DI 28))]
- "TARGET_ABICALLS && Pmode == DImode"
- "")
+ addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
+ mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
+ DONE;
+})
-;; For o32/n32/n64, we need to arrange for longjmp to put the
-;; target address in t9 so that we can use it for loading $gp.
+;; Restore the gp that we saved above. Despite the earlier comment, it seems
+;; that older code did recalculate the gp from $25. Continue to jump through
+;; $25 for compatibility (we lose nothing by doing so).
(define_expand "builtin_longjmp"
- [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
- "TARGET_ABICALLS"
- "
+ [(use (match_operand 0 "register_operand"))]
+ "TARGET_USE_GOT"
{
/* The elements of the buffer are, in order: */
- int W = (Pmode == DImode ? 8 : 4);
+ int W = GET_MODE_SIZE (Pmode);
rtx fp = gen_rtx_MEM (Pmode, operands[0]);
rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
- rtx pv = gen_rtx_REG (Pmode, 25);
- rtx gp = gen_rtx_REG (Pmode, 28);
-
- /* This bit is the same as expand_builtin_longjmp. */
- emit_move_insn (hard_frame_pointer_rtx, fp);
- emit_move_insn (pv, lab);
+ rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
+ /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
+ The target is bound to be using $28 as the global pointer
+ but the current function might not be. */
+ rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
+
+ /* This bit is similar to expand_builtin_longjmp except that it
+ restores $gp as well. */
+ mips_emit_move (hard_frame_pointer_rtx, fp);
+ mips_emit_move (pv, lab);
emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
- emit_move_insn (gp, gpv);
- emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
- emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
- emit_insn (gen_rtx_USE (VOIDmode, gp));
+ mips_emit_move (gp, gpv);
+ emit_use (hard_frame_pointer_rtx);
+ emit_use (stack_pointer_rtx);
+ emit_use (gp);
emit_indirect_jump (pv);
DONE;
-}")
+})
\f
;;
;; ....................
(define_expand "prologue"
[(const_int 1)]
""
- "
{
- if (mips_isa >= 0) /* avoid unused code warnings */
- {
- mips_expand_prologue ();
- DONE;
- }
-}")
+ mips_expand_prologue ();
+ DONE;
+})
;; Block any insns from being moved before this point, since the
;; profiling call to mcount can use various registers that aren't
;; saved or used to pass arguments.
(define_insn "blockage"
- [(unspec_volatile [(const_int 0)] 0)]
+ [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
""
""
- [(set_attr "type" "unknown")
- (set_attr "mode" "none")
- (set_attr "length" "0")])
+ [(set_attr "type" "ghost")
+ (set_attr "mode" "none")])
(define_expand "epilogue"
[(const_int 2)]
""
- "
{
- if (mips_isa >= 0) /* avoid unused code warnings */
- {
- mips_expand_epilogue ();
- DONE;
- }
-}")
+ mips_expand_epilogue (false);
+ DONE;
+})
+
+(define_expand "sibcall_epilogue"
+ [(const_int 2)]
+ ""
+{
+ mips_expand_epilogue (true);
+ DONE;
+})
;; Trivial return. Make it look like a normal return insn as that
-;; allows jump optimizations to work better .
-(define_insn "return"
+;; allows jump optimizations to work better.
+
+(define_expand "return"
[(return)]
"mips_can_use_return_insn ()"
- "%*j\\t$31"
+ { mips_expand_before_return (); })
+
+(define_insn "*return"
+ [(return)]
+ "mips_can_use_return_insn ()"
+ "%*j\t$31%/"
[(set_attr "type" "jump")
(set_attr "mode" "none")])
;; Normal return.
(define_insn "return_internal"
- [(use (match_operand 0 "pmode_register_operand" ""))
- (return)]
+ [(return)
+ (use (match_operand 0 "pmode_register_operand" ""))]
""
- "*
-{
- return \"%*j\\t%0\";
-}"
+ "%*j\t%0%/"
[(set_attr "type" "jump")
(set_attr "mode" "none")])
-;; When generating embedded PIC code we need to get the address of the
-;; current function. This specialized instruction does just that.
-
-(define_insn "get_fnaddr"
- [(set (match_operand 0 "register_operand" "=d")
- (unspec [(match_operand 1 "" "")] 1))
- (clobber (reg:SI 31))]
- "TARGET_EMBEDDED_PIC
- && GET_CODE (operands[1]) == SYMBOL_REF"
- "%($LF%= = . + 8\;bal\\t$LF%=\;la\\t%0,%1-$LF%=%)\;addu\\t%0,%0,$31"
- [(set_attr "type" "call")
- (set_attr "mode" "none")
- (set_attr "length" "16")])
-
;; This is used in compiling the unwind routines.
(define_expand "eh_return"
- [(use (match_operand 0 "general_operand" ""))
- (use (match_operand 1 "general_operand" ""))]
+ [(use (match_operand 0 "general_operand"))]
""
- "
{
- enum machine_mode gpr_mode = TARGET_64BIT ? DImode : SImode;
-
- if (GET_MODE (operands[1]) != gpr_mode)
- operands[1] = convert_to_mode (gpr_mode, operands[1], 0);
+ if (GET_MODE (operands[0]) != word_mode)
+ operands[0] = convert_to_mode (word_mode, operands[0], 0);
if (TARGET_64BIT)
- emit_insn (gen_eh_set_lr_di (operands[1]));
+ emit_insn (gen_eh_set_lr_di (operands[0]));
else
- emit_insn (gen_eh_set_lr_si (operands[1]));
-
- emit_move_insn (EH_RETURN_STACKADJ_RTX, operands[0]);
+ emit_insn (gen_eh_set_lr_si (operands[0]));
DONE;
-}")
+})
;; Clobber the return address on the stack. We can't expand this
;; until we know where it will be put in the stack frame.
(define_insn "eh_set_lr_si"
- [(unspec [(match_operand:SI 0 "register_operand" "r")] 3)
- (clobber (match_scratch:SI 1 "=&r"))]
+ [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
+ (clobber (match_scratch:SI 1 "=&d"))]
"! TARGET_64BIT"
"#")
(define_insn "eh_set_lr_di"
- [(unspec [(match_operand:DI 0 "register_operand" "r")] 3)
- (clobber (match_scratch:DI 1 "=&r"))]
+ [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
+ (clobber (match_scratch:DI 1 "=&d"))]
"TARGET_64BIT"
"#")
(define_split
- [(unspec [(match_operand 0 "register_operand" "")] 3)
- (clobber (match_scratch 1 ""))]
- "reload_completed && !TARGET_DEBUG_D_MODE"
+ [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
+ (clobber (match_scratch 1))]
+ "reload_completed"
[(const_int 0)]
- "
{
- HOST_WIDE_INT gp_offset;
- rtx base;
-
- compute_frame_size (get_frame_size ());
- if (((current_frame_info.mask >> 31) & 1) == 0)
- abort ();
- gp_offset = current_frame_info.gp_sp_offset;
-
- if (gp_offset < 32768)
- base = stack_pointer_rtx;
- else
- {
- base = operands[1];
- emit_move_insn (base, GEN_INT (gp_offset));
- if (Pmode == DImode)
- emit_insn (gen_adddi3 (base, base, stack_pointer_rtx));
- else
- emit_insn (gen_addsi3 (base, base, stack_pointer_rtx));
- gp_offset = 0;
- }
- emit_move_insn (gen_rtx_MEM (GET_MODE (operands[0]),
- plus_constant (base, gp_offset)),
- operands[0]);
+ mips_set_return_address (operands[0], operands[1]);
DONE;
-}")
-
-(define_insn "exception_receiver"
- [(unspec_volatile [(const_int 0)] 4)]
- "TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64)"
- "*
-{
- rtx loc;
-
- operands[0] = pic_offset_table_rtx;
- if (frame_pointer_needed)
- loc = hard_frame_pointer_rtx;
- else
- loc = stack_pointer_rtx;
- loc = plus_constant (loc, current_frame_info.args_size);
- operands[1] = gen_rtx_MEM (Pmode, loc);
-
- return mips_move_1word (operands, insn, 0);
-}"
- [(set_attr "type" "load")
- (set_attr "length" "8")])
-\f
-;;
-;; ....................
-;;
-;; FUNCTION CALLS
-;;
-;; ....................
-
-;; calls.c now passes a third argument, make saber happy
-
-(define_expand "call"
- [(parallel [(call (match_operand 0 "memory_operand" "m")
- (match_operand 1 "" "i"))
- (clobber (reg:SI 31))
- (use (match_operand 2 "" "")) ;; next_arg_reg
- (use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
- ""
- "
-{
- rtx addr;
-
- if (operands[0]) /* eliminate unused code warnings */
- {
- addr = XEXP (operands[0], 0);
- if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS))
- || ! call_insn_operand (addr, VOIDmode))
- XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
-
- /* In order to pass small structures by value in registers
- compatibly with the MIPS compiler, we need to shift the value
- into the high part of the register. Function_arg has encoded
- a PARALLEL rtx, holding a vector of adjustments to be made
- as the next_arg_reg variable, so we split up the insns,
- and emit them separately. */
-
- if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL)
- {
- rtvec adjust = XVEC (operands[2], 0);
- int num = GET_NUM_ELEM (adjust);
- int i;
-
- for (i = 0; i < num; i++)
- emit_insn (RTVEC_ELT (adjust, i));
- }
-
- if (TARGET_MIPS16
- && mips16_hard_float
- && operands[2] != 0
- && (int) GET_MODE (operands[2]) != 0)
- {
- if (build_mips16_call_stub (NULL_RTX, operands[0], operands[1],
- (int) GET_MODE (operands[2])))
- DONE;
- }
-
- emit_call_insn (gen_call_internal0 (operands[0], operands[1],
- gen_rtx_REG (SImode,
- GP_REG_FIRST + 31)));
- DONE;
- }
-}")
-
-(define_expand "call_internal0"
- [(parallel [(call (match_operand 0 "" "")
- (match_operand 1 "" ""))
- (clobber (match_operand:SI 2 "" ""))])]
- ""
- "")
-
-;; We need to recognize reg:SI 31 specially for the mips16, because we
-;; don't have a constraint letter for it.
-
-(define_insn ""
- [(call (mem (match_operand 0 "call_insn_operand" "ei"))
- (match_operand 1 "" "i"))
- (clobber (match_operand:SI 2 "register_operand" "=y"))]
- "TARGET_MIPS16 && !TARGET_ABICALLS && !TARGET_LONG_CALLS
- && GET_CODE (operands[2]) == REG && REGNO (operands[2]) == 31"
- "%*jal\\t%0"
- [(set_attr "type" "call")
- (set_attr "mode" "none")
- (set_attr "length" "8")])
-
-(define_insn "call_internal1"
- [(call (mem (match_operand 0 "call_insn_operand" "ri"))
- (match_operand 1 "" "i"))
- (clobber (match_operand:SI 2 "register_operand" "=d"))]
- "!TARGET_ABICALLS && !TARGET_LONG_CALLS"
- "*
-{
- register rtx target = operands[0];
-
- if (GET_CODE (target) == CONST_INT)
- return \"%[li\\t%@,%0\\n\\t%*jal\\t%2,%@%]\";
- else if (CONSTANT_ADDRESS_P (target))
- return \"%*jal\\t%0\";
- else
- return \"%*jal\\t%2,%0\";
-}"
- [(set_attr "type" "call")
- (set_attr "mode" "none")])
-
-(define_insn "call_internal2"
- [(call (mem (match_operand 0 "call_insn_operand" "ri"))
- (match_operand 1 "" "i"))
- (clobber (match_operand:SI 2 "register_operand" "=d"))]
- "TARGET_ABICALLS && !TARGET_LONG_CALLS"
- "*
-{
- register rtx target = operands[0];
-
- if (GET_CODE (target) == CONST_INT)
- return \"li\\t%^,%0\\n\\tjal\\t%2,%^\";
- else if (CONSTANT_ADDRESS_P (target))
- {
- if (GET_MODE (target) == SImode)
- return \"la\\t%^,%0\\n\\tjal\\t%2,%^\";
- else
- return \"dla\\t%^,%0\\n\\tjal\\t%2,%^\";
- }
- else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
- return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
- else
- return \"jal\\t%2,%0\";
-}"
- [(set_attr "type" "call")
- (set_attr "mode" "none")
- (set_attr "length" "8")])
-
-(define_insn "call_internal3a"
- [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
- (match_operand 1 "" "i"))
- (clobber (match_operand:SI 2 "register_operand" "=d"))]
- "!TARGET_MIPS16
- && !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS"
- "%*jal\\t%2,%0"
- [(set_attr "type" "call")
- (set_attr "mode" "none")])
-
-(define_insn "call_internal3b"
- [(call (mem:DI (match_operand:DI 0 "se_register_operand" "r"))
- (match_operand 1 "" "i"))
- (clobber (match_operand:SI 2 "register_operand" "=d"))]
- "!TARGET_MIPS16
- && Pmode == DImode && !TARGET_ABICALLS && TARGET_LONG_CALLS"
- "%*jal\\t%2,%0"
- [(set_attr "type" "call")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
-
-(define_insn "call_internal3c"
- [(call (mem:SI (match_operand:SI 0 "register_operand" "e"))
- (match_operand 1 "" "i"))
- (clobber (match_operand:SI 2 "register_operand" "=y"))]
- "TARGET_MIPS16 && !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS
- && GET_CODE (operands[2]) == REG && REGNO (operands[2]) == 31"
- "%*jal\\t%2,%0"
- [(set_attr "type" "call")
- (set_attr "mode" "none")])
-
-(define_insn "call_internal4a"
- [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
- (match_operand 1 "" "i"))
- (clobber (match_operand:SI 2 "register_operand" "=d"))]
- "!(Pmode == DImode) && TARGET_ABICALLS && TARGET_LONG_CALLS"
- "*
-{
- if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM)
- return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
- else
- return \"jal\\t%2,%0\";
-}"
- [(set_attr "type" "call")
- (set_attr "mode" "none")
- (set_attr "length" "8")])
-
-(define_insn "call_internal4b"
- [(call (mem:DI (match_operand:DI 0 "se_register_operand" "r"))
- (match_operand 1 "" "i"))
- (clobber (match_operand:SI 2 "register_operand" "=d"))]
- "Pmode == DImode && TARGET_ABICALLS && TARGET_LONG_CALLS"
- "*
-{
- if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM)
- return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
- else
- return \"jal\\t%2,%0\";
-}"
- [(set_attr "type" "call")
- (set_attr "mode" "none")
- (set_attr "length" "8")])
-
-;; calls.c now passes a fourth argument, make saber happy
-
-(define_expand "call_value"
- [(parallel [(set (match_operand 0 "register_operand" "=df")
- (call (match_operand 1 "memory_operand" "m")
- (match_operand 2 "" "i")))
- (clobber (reg:SI 31))
- (use (match_operand 3 "" ""))])] ;; next_arg_reg
- ""
- "
-{
- rtx addr;
-
- if (operands[0]) /* eliminate unused code warning */
- {
- addr = XEXP (operands[1], 0);
- if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS))
- || ! call_insn_operand (addr, VOIDmode))
- XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
-
- /* In order to pass small structures by value in registers
- compatibly with the MIPS compiler, we need to shift the value
- into the high part of the register. Function_arg has encoded
- a PARALLEL rtx, holding a vector of adjustments to be made
- as the next_arg_reg variable, so we split up the insns,
- and emit them separately. */
-
- if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL)
- {
- rtvec adjust = XVEC (operands[3], 0);
- int num = GET_NUM_ELEM (adjust);
- int i;
-
- for (i = 0; i < num; i++)
- emit_insn (RTVEC_ELT (adjust, i));
- }
-
- if (TARGET_MIPS16
- && mips16_hard_float
- && ((operands[3] != 0
- && (int) GET_MODE (operands[3]) != 0)
- || GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_FLOAT))
- {
- if (build_mips16_call_stub (operands[0], operands[1], operands[2],
- (operands[3] == 0 ? 0
- : (int) GET_MODE (operands[3]))))
- DONE;
- }
-
- /* Handle Irix6 function calls that have multiple non-contiguous
- results. */
- if (GET_CODE (operands[0]) == PARALLEL && XVECLEN (operands[0], 0) > 1)
- {
- emit_call_insn (gen_call_value_multiple_internal0
- (XEXP (XVECEXP (operands[0], 0, 0), 0),
- operands[1], operands[2],
- XEXP (XVECEXP (operands[0], 0, 1), 0),
- gen_rtx_REG (SImode, GP_REG_FIRST + 31)));
- DONE;
- }
-
- /* We have a call returning a DImode structure in an FP reg.
- Strip off the now unnecessary PARALLEL. */
- if (GET_CODE (operands[0]) == PARALLEL)
- operands[0] = XEXP (XVECEXP (operands[0], 0, 0), 0);
-
- emit_call_insn (gen_call_value_internal0 (operands[0], operands[1], operands[2],
- gen_rtx_REG (SImode,
- GP_REG_FIRST + 31)));
-
- DONE;
- }
-}")
-
-(define_expand "call_value_internal0"
- [(parallel [(set (match_operand 0 "" "")
- (call (match_operand 1 "" "")
- (match_operand 2 "" "")))
- (clobber (match_operand:SI 3 "" ""))])]
- ""
- "")
-
-;; Recognize $31 specially on the mips16, because we don't have a
-;; constraint letter for it.
-
-(define_insn ""
- [(set (match_operand 0 "register_operand" "=d")
- (call (mem (match_operand 1 "call_insn_operand" "ei"))
- (match_operand 2 "" "i")))
- (clobber (match_operand:SI 3 "register_operand" "=y"))]
- "TARGET_MIPS16 && !TARGET_ABICALLS && !TARGET_LONG_CALLS
- && GET_CODE (operands[3]) == REG && REGNO (operands[3]) == 31"
- "%*jal\\t%1"
- [(set_attr "type" "call")
- (set_attr "mode" "none")
- (set_attr "length" "8")])
+})
-(define_insn "call_value_internal1"
- [(set (match_operand 0 "register_operand" "=df")
- (call (mem (match_operand 1 "call_insn_operand" "ri"))
- (match_operand 2 "" "i")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_ABICALLS && !TARGET_LONG_CALLS"
- "*
+(define_expand "exception_receiver"
+ [(const_int 0)]
+ "TARGET_USE_GOT"
{
- register rtx target = operands[1];
+ /* See the comment above load_call<mode> for details. */
+ emit_insn (gen_set_got_version ());
- if (GET_CODE (target) == CONST_INT)
- return \"%[li\\t%@,%1\\n\\t%*jal\\t%3,%@%]\";
- else if (CONSTANT_ADDRESS_P (target))
- return \"%*jal\\t%1\";
- else
- return \"%*jal\\t%3,%1\";
-}"
- [(set_attr "type" "call")
- (set_attr "mode" "none")])
+ /* If we have a call-clobbered $gp, restore it from its save slot. */
+ if (HAVE_restore_gp)
+ emit_insn (gen_restore_gp ());
+ DONE;
+})
-(define_insn "call_value_internal2"
- [(set (match_operand 0 "register_operand" "=df")
- (call (mem (match_operand 1 "call_insn_operand" "ri"))
- (match_operand 2 "" "i")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "TARGET_ABICALLS && !TARGET_LONG_CALLS"
- "*
+(define_expand "nonlocal_goto_receiver"
+ [(const_int 0)]
+ "TARGET_USE_GOT"
+{
+ /* See the comment above load_call<mode> for details. */
+ emit_insn (gen_set_got_version ());
+ DONE;
+})
+
+;; Restore $gp from its .cprestore stack slot. The instruction remains
+;; volatile until all uses of $28 are exposed.
+(define_insn_and_split "restore_gp"
+ [(set (reg:SI 28)
+ (unspec_volatile:SI [(const_int 0)] UNSPEC_RESTORE_GP))
+ (clobber (match_scratch:SI 0 "=&d"))]
+ "TARGET_CALL_CLOBBERED_GP"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
{
- register rtx target = operands[1];
+ mips_restore_gp (operands[0]);
+ DONE;
+}
+ [(set_attr "type" "load")
+ (set_attr "length" "12")])
+\f
+;;
+;; ....................
+;;
+;; FUNCTION CALLS
+;;
+;; ....................
- if (GET_CODE (target) == CONST_INT)
- return \"li\\t%^,%1\\n\\tjal\\t%3,%^\";
- else if (CONSTANT_ADDRESS_P (target))
- {
- if (GET_MODE (target) == SImode)
- return \"la\\t%^,%1\\n\\tjal\\t%3,%^\";
- else
- return \"dla\\t%^,%1\\n\\tjal\\t%3,%^\";
- }
- else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
- return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
- else
- return \"jal\\t%3,%1\";
-}"
- [(set_attr "type" "call")
- (set_attr "mode" "none")
- (set_attr "length" "8")])
+;; Instructions to load a call address from the GOT. The address might
+;; point to a function or to a lazy binding stub. In the latter case,
+;; the stub will use the dynamic linker to resolve the function, which
+;; in turn will change the GOT entry to point to the function's real
+;; address.
+;;
+;; This means that every call, even pure and constant ones, can
+;; potentially modify the GOT entry. And once a stub has been called,
+;; we must not call it again.
+;;
+;; We represent this restriction using an imaginary, fixed, call-saved
+;; register called GOT_VERSION_REGNUM. The idea is to make the register
+;; live throughout the function and to change its value after every
+;; potential call site. This stops any rtx value that uses the register
+;; from being computed before an earlier call. To do this, we:
+;;
+;; - Ensure that the register is live on entry to the function,
+;; so that it is never thought to be used uninitalized.
+;;
+;; - Ensure that the register is live on exit from the function,
+;; so that it is live throughout.
+;;
+;; - Make each call (lazily-bound or not) use the current value
+;; of GOT_VERSION_REGNUM, so that updates of the register are
+;; not moved across call boundaries.
+;;
+;; - Add "ghost" definitions of the register to the beginning of
+;; blocks reached by EH and ABNORMAL_CALL edges, because those
+;; edges may involve calls that normal paths don't. (E.g. the
+;; unwinding code that handles a non-call exception may change
+;; lazily-bound GOT entries.) We do this by making the
+;; exception_receiver and nonlocal_goto_receiver expanders emit
+;; a set_got_version instruction.
+;;
+;; - After each call (lazily-bound or not), use a "ghost"
+;; update_got_version instruction to change the register's value.
+;; This instruction mimics the _possible_ effect of the dynamic
+;; resolver during the call and it remains live even if the call
+;; itself becomes dead.
+;;
+;; - Leave GOT_VERSION_REGNUM out of all register classes.
+;; The register is therefore not a valid register_operand
+;; and cannot be moved to or from other registers.
+
+;; Convenience expander that generates the rhs of a load_call<mode> insn.
+(define_expand "unspec_call<mode>"
+ [(unspec:P [(match_operand:P 0)
+ (match_operand:P 1)
+ (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL)])
+
+(define_insn "load_call<mode>"
+ [(set (match_operand:P 0 "register_operand" "=d")
+ (unspec:P [(match_operand:P 1 "register_operand" "d")
+ (match_operand:P 2 "immediate_operand" "")
+ (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))]
+ "TARGET_USE_GOT"
+ "<load>\t%0,%R2(%1)"
+ [(set_attr "got" "load")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "set_got_version"
+ [(set (reg:SI GOT_VERSION_REGNUM)
+ (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))]
+ "TARGET_USE_GOT"
+ ""
+ [(set_attr "type" "ghost")])
-(define_insn "call_value_internal3a"
- [(set (match_operand 0 "register_operand" "=df")
- (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
- (match_operand 2 "" "i")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_MIPS16
- && !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS"
- "%*jal\\t%3,%1"
- [(set_attr "type" "call")
- (set_attr "mode" "none")])
+(define_insn "update_got_version"
+ [(set (reg:SI GOT_VERSION_REGNUM)
+ (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))]
+ "TARGET_USE_GOT"
+ ""
+ [(set_attr "type" "ghost")])
+
+;; Sibling calls. All these patterns use jump instructions.
+
+;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
+;; addresses if a direct jump is acceptable. Since the 'S' constraint
+;; is defined in terms of call_insn_operand, the same is true of the
+;; constraints.
+
+;; When we use an indirect jump, we need a register that will be
+;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
+;; us to use $25 for this purpose -- and $25 is never clobbered by the
+;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
+;; as well.
+
+(define_expand "sibcall"
+ [(parallel [(call (match_operand 0 "")
+ (match_operand 1 ""))
+ (use (match_operand 2 "")) ;; next_arg_reg
+ (use (match_operand 3 ""))])] ;; struct_value_size_rtx
+ "TARGET_SIBCALLS"
+{
+ mips_expand_call (MIPS_CALL_SIBCALL, NULL_RTX, XEXP (operands[0], 0),
+ operands[1], operands[2], false);
+ DONE;
+})
+
+(define_insn "sibcall_internal"
+ [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
+ (match_operand 1 "" ""))]
+ "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
+ { return MIPS_CALL ("j", operands, 0); }
+ [(set_attr "type" "call")])
+
+(define_expand "sibcall_value"
+ [(parallel [(set (match_operand 0 "")
+ (call (match_operand 1 "")
+ (match_operand 2 "")))
+ (use (match_operand 3 ""))])] ;; next_arg_reg
+ "TARGET_SIBCALLS"
+{
+ mips_expand_call (MIPS_CALL_SIBCALL, operands[0], XEXP (operands[1], 0),
+ operands[2], operands[3], false);
+ DONE;
+})
-(define_insn "call_value_internal3b"
- [(set (match_operand 0 "register_operand" "=df")
- (call (mem:DI (match_operand:DI 1 "se_register_operand" "r"))
- (match_operand 2 "" "i")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_MIPS16
- && Pmode == DImode && !TARGET_ABICALLS && TARGET_LONG_CALLS"
- "%*jal\\t%3,%1"
- [(set_attr "type" "call")
- (set_attr "mode" "none")])
+(define_insn "sibcall_value_internal"
+ [(set (match_operand 0 "register_operand" "")
+ (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
+ (match_operand 2 "" "")))]
+ "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
+ { return MIPS_CALL ("j", operands, 1); }
+ [(set_attr "type" "call")])
-(define_insn "call_value_internal3c"
- [(set (match_operand 0 "register_operand" "=df")
- (call (mem:SI (match_operand:SI 1 "register_operand" "e"))
- (match_operand 2 "" "i")))
- (clobber (match_operand:SI 3 "register_operand" "=y"))]
- "TARGET_MIPS16 && !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS
- && GET_CODE (operands[3]) == REG && REGNO (operands[3]) == 31"
- "%*jal\\t%3,%1"
- [(set_attr "type" "call")
- (set_attr "mode" "none")])
+(define_insn "sibcall_value_multiple_internal"
+ [(set (match_operand 0 "register_operand" "")
+ (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
+ (match_operand 2 "" "")))
+ (set (match_operand 3 "register_operand" "")
+ (call (mem:SI (match_dup 1))
+ (match_dup 2)))]
+ "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
+ { return MIPS_CALL ("j", operands, 1); }
+ [(set_attr "type" "call")])
-(define_insn "call_value_internal4a"
- [(set (match_operand 0 "register_operand" "=df")
- (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
- (match_operand 2 "" "i")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!(Pmode == DImode) && TARGET_ABICALLS && TARGET_LONG_CALLS"
- "*
+(define_expand "call"
+ [(parallel [(call (match_operand 0 "")
+ (match_operand 1 ""))
+ (use (match_operand 2 "")) ;; next_arg_reg
+ (use (match_operand 3 ""))])] ;; struct_value_size_rtx
+ ""
{
- if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM)
- return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
- else
- return \"jal\\t%3,%1\";
-}"
- [(set_attr "type" "call")
- (set_attr "mode" "none")
- (set_attr "length" "8")])
+ mips_expand_call (MIPS_CALL_NORMAL, NULL_RTX, XEXP (operands[0], 0),
+ operands[1], operands[2], false);
+ DONE;
+})
-(define_insn "call_value_internal4b"
- [(set (match_operand 0 "register_operand" "=df")
- (call (mem:DI (match_operand:DI 1 "se_register_operand" "r"))
- (match_operand 2 "" "i")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "Pmode == DImode && TARGET_ABICALLS && TARGET_LONG_CALLS"
- "*
+;; This instruction directly corresponds to an assembly-language "jal".
+;; There are four cases:
+;;
+;; - -mno-abicalls:
+;; Both symbolic and register destinations are OK. The pattern
+;; always expands to a single mips instruction.
+;;
+;; - -mabicalls/-mno-explicit-relocs:
+;; Again, both symbolic and register destinations are OK.
+;; The call is treated as a multi-instruction black box.
+;;
+;; - -mabicalls/-mexplicit-relocs with n32 or n64:
+;; Only "jal $25" is allowed. This expands to a single "jalr $25"
+;; instruction.
+;;
+;; - -mabicalls/-mexplicit-relocs with o32 or o64:
+;; Only "jal $25" is allowed. The call is actually two instructions:
+;; "jalr $25" followed by an insn to reload $gp.
+;;
+;; In the last case, we can generate the individual instructions with
+;; a define_split. There are several things to be wary of:
+;;
+;; - We can't expose the load of $gp before reload. If we did,
+;; it might get removed as dead, but reload can introduce new
+;; uses of $gp by rematerializing constants.
+;;
+;; - We shouldn't restore $gp after calls that never return.
+;; It isn't valid to insert instructions between a noreturn
+;; call and the following barrier.
+;;
+;; - The splitter deliberately changes the liveness of $gp. The unsplit
+;; instruction preserves $gp and so have no effect on its liveness.
+;; But once we generate the separate insns, it becomes obvious that
+;; $gp is not live on entry to the call.
+;;
+;; ??? The operands[2] = insn check is a hack to make the original insn
+;; available to the splitter.
+(define_insn_and_split "call_internal"
+ [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
+ (match_operand 1 "" ""))
+ (clobber (reg:SI 31))]
+ ""
+ { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
+ "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
+ [(const_int 0)]
{
- if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM)
- return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
- else
- return \"jal\\t%3,%1\";
-}"
- [(set_attr "type" "call")
- (set_attr "mode" "none")
- (set_attr "length" "8")])
+ mips_split_call (operands[2], gen_call_split (operands[0], operands[1]));
+ DONE;
+}
+ [(set_attr "jal" "indirect,direct")])
+
+(define_insn "call_split"
+ [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
+ (match_operand 1 "" ""))
+ (clobber (reg:SI 31))
+ (clobber (reg:SI 28))]
+ "TARGET_SPLIT_CALLS"
+ { return MIPS_CALL ("jal", operands, 0); }
+ [(set_attr "type" "call")])
+
+;; A pattern for calls that must be made directly. It is used for
+;; MIPS16 calls that the linker may need to redirect to a hard-float
+;; stub; the linker relies on the call relocation type to detect when
+;; such redirection is needed.
+(define_insn_and_split "call_internal_direct"
+ [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
+ (match_operand 1))
+ (const_int 1)
+ (clobber (reg:SI 31))]
+ ""
+ { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
+ "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
+ [(const_int 0)]
+{
+ mips_split_call (operands[2],
+ gen_call_direct_split (operands[0], operands[1]));
+ DONE;
+}
+ [(set_attr "type" "call")])
+
+(define_insn "call_direct_split"
+ [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
+ (match_operand 1))
+ (const_int 1)
+ (clobber (reg:SI 31))
+ (clobber (reg:SI 28))]
+ "TARGET_SPLIT_CALLS"
+ { return MIPS_CALL ("jal", operands, 0); }
+ [(set_attr "type" "call")])
-(define_expand "call_value_multiple_internal0"
- [(parallel [(set (match_operand 0 "" "")
- (call (match_operand 1 "" "")
- (match_operand 2 "" "")))
- (set (match_operand 3 "" "")
- (call (match_dup 1)
- (match_dup 2)))
- (clobber (match_operand:SI 4 "" ""))])]
+(define_expand "call_value"
+ [(parallel [(set (match_operand 0 "")
+ (call (match_operand 1 "")
+ (match_operand 2 "")))
+ (use (match_operand 3 ""))])] ;; next_arg_reg
""
- "")
+{
+ mips_expand_call (MIPS_CALL_NORMAL, operands[0], XEXP (operands[1], 0),
+ operands[2], operands[3], false);
+ DONE;
+})
-;; ??? May eventually need all 6 versions of the call patterns with multiple
-;; return values.
-
-(define_insn "call_value_multiple_internal1"
- [(set (match_operand 0 "register_operand" "=df")
- (call (mem (match_operand 1 "call_insn_operand" "ri"))
- (match_operand 2 "" "i")))
- (set (match_operand 3 "register_operand" "=df")
- (call (mem (match_dup 1))
- (match_dup 2)))
- (clobber (match_operand:SI 4 "register_operand" "=d"))]
- "!TARGET_ABICALLS && !TARGET_LONG_CALLS"
- "*
-{
- register rtx target = operands[1];
-
- if (GET_CODE (target) == CONST_INT)
- return \"%[li\\t%@,%1\\n\\t%*jal\\t%4,%@%]\";
- else if (CONSTANT_ADDRESS_P (target))
- return \"%*jal\\t%1\";
- else
- return \"%*jal\\t%4,%1\";
-}"
- [(set_attr "type" "call")
- (set_attr "mode" "none")])
+;; See comment for call_internal.
+(define_insn_and_split "call_value_internal"
+ [(set (match_operand 0 "register_operand" "")
+ (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
+ (match_operand 2 "" "")))
+ (clobber (reg:SI 31))]
+ ""
+ { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
+ "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
+ [(const_int 0)]
+{
+ mips_split_call (operands[3],
+ gen_call_value_split (operands[0], operands[1],
+ operands[2]));
+ DONE;
+}
+ [(set_attr "jal" "indirect,direct")])
-(define_insn "call_value_multiple_internal2"
- [(set (match_operand 0 "register_operand" "=df")
- (call (mem (match_operand 1 "call_insn_operand" "ri"))
- (match_operand 2 "" "i")))
- (set (match_operand 3 "register_operand" "=df")
- (call (mem (match_dup 1))
- (match_dup 2)))
- (clobber (match_operand:SI 4 "register_operand" "=d"))]
- "TARGET_ABICALLS && !TARGET_LONG_CALLS"
- "*
-{
- register rtx target = operands[1];
-
- if (GET_CODE (target) == CONST_INT)
- return \"li\\t%^,%1\\n\\tjal\\t%4,%^\";
- else if (CONSTANT_ADDRESS_P (target))
- {
- if (GET_MODE (target) == SImode)
- return \"la\\t%^,%1\\n\\tjal\\t%4,%^\";
- else
- return \"la\\t%^,%1\\n\\tjal\\t%4,%^\";
- }
- else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
- return \"move\\t%^,%1\\n\\tjal\\t%4,%^\";
- else
- return \"jal\\t%4,%1\";
-}"
- [(set_attr "type" "call")
- (set_attr "mode" "none")
- (set_attr "length" "8")])
+(define_insn "call_value_split"
+ [(set (match_operand 0 "register_operand" "")
+ (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
+ (match_operand 2 "" "")))
+ (clobber (reg:SI 31))
+ (clobber (reg:SI 28))]
+ "TARGET_SPLIT_CALLS"
+ { return MIPS_CALL ("jal", operands, 1); }
+ [(set_attr "type" "call")])
+
+;; See call_internal_direct.
+(define_insn_and_split "call_value_internal_direct"
+ [(set (match_operand 0 "register_operand")
+ (call (mem:SI (match_operand 1 "const_call_insn_operand"))
+ (match_operand 2)))
+ (const_int 1)
+ (clobber (reg:SI 31))]
+ ""
+ { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
+ "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
+ [(const_int 0)]
+{
+ mips_split_call (operands[3],
+ gen_call_value_direct_split (operands[0], operands[1],
+ operands[2]));
+ DONE;
+}
+ [(set_attr "type" "call")])
+
+(define_insn "call_value_direct_split"
+ [(set (match_operand 0 "register_operand")
+ (call (mem:SI (match_operand 1 "const_call_insn_operand"))
+ (match_operand 2)))
+ (const_int 1)
+ (clobber (reg:SI 31))
+ (clobber (reg:SI 28))]
+ "TARGET_SPLIT_CALLS"
+ { return MIPS_CALL ("jal", operands, 1); }
+ [(set_attr "type" "call")])
+
+;; See comment for call_internal.
+(define_insn_and_split "call_value_multiple_internal"
+ [(set (match_operand 0 "register_operand" "")
+ (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
+ (match_operand 2 "" "")))
+ (set (match_operand 3 "register_operand" "")
+ (call (mem:SI (match_dup 1))
+ (match_dup 2)))
+ (clobber (reg:SI 31))]
+ ""
+ { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
+ "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
+ [(const_int 0)]
+{
+ mips_split_call (operands[4],
+ gen_call_value_multiple_split (operands[0], operands[1],
+ operands[2], operands[3]));
+ DONE;
+}
+ [(set_attr "jal" "indirect,direct")])
+(define_insn "call_value_multiple_split"
+ [(set (match_operand 0 "register_operand" "")
+ (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
+ (match_operand 2 "" "")))
+ (set (match_operand 3 "register_operand" "")
+ (call (mem:SI (match_dup 1))
+ (match_dup 2)))
+ (clobber (reg:SI 31))
+ (clobber (reg:SI 28))]
+ "TARGET_SPLIT_CALLS"
+ { return MIPS_CALL ("jal", operands, 1); }
+ [(set_attr "type" "call")])
;; Call subroutine returning any type.
(define_expand "untyped_call"
- [(parallel [(call (match_operand 0 "" "")
+ [(parallel [(call (match_operand 0 "")
(const_int 0))
- (match_operand 1 "" "")
- (match_operand 2 "" "")])]
+ (match_operand 1 "")
+ (match_operand 2 "")])]
""
- "
{
- if (operands[0]) /* silence statement not reached warnings */
- {
- int i;
+ int i;
- emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
-
- for (i = 0; i < XVECLEN (operands[2], 0); i++)
- {
- rtx set = XVECEXP (operands[2], 0, i);
- emit_move_insn (SET_DEST (set), SET_SRC (set));
- }
+ emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
- emit_insn (gen_blockage ());
- DONE;
+ for (i = 0; i < XVECLEN (operands[2], 0); i++)
+ {
+ rtx set = XVECEXP (operands[2], 0, i);
+ mips_emit_move (SET_DEST (set), SET_SRC (set));
}
-}")
+
+ emit_insn (gen_blockage ());
+ DONE;
+})
\f
;;
;; ....................
;; ....................
;;
+
+(define_insn "prefetch"
+ [(prefetch (match_operand:QI 0 "address_operand" "p")
+ (match_operand 1 "const_int_operand" "n")
+ (match_operand 2 "const_int_operand" "n"))]
+ "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
+{
+ if (TARGET_LOONGSON_2EF)
+ /* Loongson 2[ef] use load to $0 to perform prefetching. */
+ return "ld\t$0,%a0";
+ operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
+ return "pref\t%1,%a0";
+}
+ [(set_attr "type" "prefetch")])
+
+(define_insn "*prefetch_indexed_<mode>"
+ [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
+ (match_operand:P 1 "register_operand" "d"))
+ (match_operand 2 "const_int_operand" "n")
+ (match_operand 3 "const_int_operand" "n"))]
+ "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+{
+ operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
+ return "prefx\t%2,%1(%0)";
+}
+ [(set_attr "type" "prefetchx")])
+
(define_insn "nop"
[(const_int 0)]
""
[(set_attr "type" "nop")
(set_attr "mode" "none")])
-;; The MIPS chip does not seem to require stack probes.
-;;
-;; (define_expand "probe"
-;; [(set (match_dup 0)
-;; (match_dup 1))]
-;; ""
-;; "
-;; {
-;; operands[0] = gen_reg_rtx (SImode);
-;; operands[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
-;; MEM_VOLATILE_P (operands[1]) = TRUE;
-;;
-;; /* fall through and generate default code */
-;; }")
-;;
+;; Like nop, but commented out when outside a .set noreorder block.
+(define_insn "hazard_nop"
+ [(const_int 1)]
+ ""
+ {
+ if (set_noreorder)
+ return "nop";
+ else
+ return "#nop";
+ }
+ [(set_attr "type" "nop")])
\f
-;;
;; MIPS4 Conditional move instructions.
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (if_then_else:SI
- (match_operator 4 "equality_op"
- [(match_operand:SI 1 "register_operand" "d,d")
- (const_int 0)])
- (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
- (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
- "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
- "@
- mov%B4\\t%0,%z2,%1
- mov%b4\\t%0,%z3,%1"
- [(set_attr "type" "move")
- (set_attr "mode" "SI")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (if_then_else:SI
- (match_operator 4 "equality_op"
- [(match_operand:DI 1 "se_register_operand" "d,d")
- (const_int 0)])
- (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
- (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
- "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
- "@
- mov%B4\\t%0,%z2,%1
- mov%b4\\t%0,%z3,%1"
- [(set_attr "type" "move")
- (set_attr "mode" "SI")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (if_then_else:SI
- (match_operator 3 "equality_op" [(match_operand:CC 4
- "register_operand"
- "z,z")
- (const_int 0)])
- (match_operand:SI 1 "reg_or_0_operand" "dJ,0")
- (match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
- "@
- mov%T3\\t%0,%z1,%4
- mov%t3\\t%0,%z2,%4"
- [(set_attr "type" "move")
- (set_attr "mode" "SI")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (if_then_else:DI
- (match_operator 4 "equality_op"
- [(match_operand:SI 1 "register_operand" "d,d")
- (const_int 0)])
- (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
- (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
- "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
- "@
- mov%B4\\t%0,%z2,%1
- mov%b4\\t%0,%z3,%1"
- [(set_attr "type" "move")
- (set_attr "mode" "DI")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (if_then_else:DI
- (match_operator 4 "equality_op"
- [(match_operand:DI 1 "se_register_operand" "d,d")
- (const_int 0)])
- (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
- (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
- "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
- "@
- mov%B4\\t%0,%z2,%1
- mov%b4\\t%0,%z3,%1"
- [(set_attr "type" "move")
- (set_attr "mode" "DI")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (if_then_else:DI
- (match_operator 3 "equality_op" [(match_operand:CC 4
- "register_operand"
- "z,z")
- (const_int 0)])
- (match_operand:DI 1 "se_reg_or_0_operand" "dJ,0")
- (match_operand:DI 2 "se_reg_or_0_operand" "0,dJ")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_64BIT"
- "@
- mov%T3\\t%0,%z1,%4
- mov%t3\\t%0,%z2,%4"
- [(set_attr "type" "move")
- (set_attr "mode" "DI")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (if_then_else:SF
- (match_operator 4 "equality_op"
- [(match_operand:SI 1 "register_operand" "d,d")
- (const_int 0)])
- (match_operand:SF 2 "register_operand" "f,0")
- (match_operand:SF 3 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
- "@
- mov%B4.s\\t%0,%2,%1
- mov%b4.s\\t%0,%3,%1"
- [(set_attr "type" "move")
- (set_attr "mode" "SF")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (if_then_else:SF
- (match_operator 4 "equality_op"
- [(match_operand:DI 1 "se_register_operand" "d,d")
- (const_int 0)])
- (match_operand:SF 2 "register_operand" "f,0")
- (match_operand:SF 3 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
- "@
- mov%B4.s\\t%0,%2,%1
- mov%b4.s\\t%0,%3,%1"
- [(set_attr "type" "move")
- (set_attr "mode" "SF")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (if_then_else:SF
- (match_operator 3 "equality_op" [(match_operand:CC 4
- "register_operand"
- "z,z")
- (const_int 0)])
- (match_operand:SF 1 "register_operand" "f,0")
- (match_operand:SF 2 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
- "@
- mov%T3.s\\t%0,%1,%4
- mov%t3.s\\t%0,%2,%4"
- [(set_attr "type" "move")
- (set_attr "mode" "SF")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (if_then_else:DF
- (match_operator 4 "equality_op"
- [(match_operand:SI 1 "register_operand" "d,d")
- (const_int 0)])
- (match_operand:DF 2 "register_operand" "f,0")
- (match_operand:DF 3 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "@
- mov%B4.d\\t%0,%2,%1
- mov%b4.d\\t%0,%3,%1"
- [(set_attr "type" "move")
- (set_attr "mode" "DF")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (if_then_else:DF
- (match_operator 4 "equality_op"
- [(match_operand:DI 1 "se_register_operand" "d,d")
- (const_int 0)])
- (match_operand:DF 2 "register_operand" "f,0")
- (match_operand:DF 3 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+(define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (if_then_else:GPR
+ (match_operator:MOVECC 4 "equality_operator"
+ [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
+ (const_int 0)])
+ (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
+ (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
+ "ISA_HAS_CONDMOVE"
"@
- mov%B4.d\\t%0,%2,%1
- mov%b4.d\\t%0,%3,%1"
- [(set_attr "type" "move")
- (set_attr "mode" "DF")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (if_then_else:DF
- (match_operator 3 "equality_op" [(match_operand:CC 4
- "register_operand"
- "z,z")
- (const_int 0)])
- (match_operand:DF 1 "register_operand" "f,0")
- (match_operand:DF 2 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ mov%T4\t%0,%z2,%1
+ mov%t4\t%0,%z3,%1"
+ [(set_attr "type" "condmove")
+ (set_attr "mode" "<GPR:MODE>")])
+
+(define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
+ [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
+ (if_then_else:SCALARF
+ (match_operator:MOVECC 4 "equality_operator"
+ [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
+ (const_int 0)])
+ (match_operand:SCALARF 2 "register_operand" "f,0")
+ (match_operand:SCALARF 3 "register_operand" "0,f")))]
+ "ISA_HAS_FP_CONDMOVE"
"@
- mov%T3.d\\t%0,%1,%4
- mov%t3.d\\t%0,%2,%4"
- [(set_attr "type" "move")
- (set_attr "mode" "DF")])
+ mov%T4.<fmt>\t%0,%2,%1
+ mov%t4.<fmt>\t%0,%3,%1"
+ [(set_attr "type" "condmove")
+ (set_attr "mode" "<SCALARF:MODE>")])
;; These are the main define_expand's used to make conditional moves.
-(define_expand "movsicc"
- [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
- (set (match_operand:SI 0 "register_operand" "")
- (if_then_else:SI (match_dup 5)
- (match_operand:SI 2 "reg_or_0_operand" "")
- (match_operand:SI 3 "reg_or_0_operand" "")))]
- "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
- "
-{
- gen_conditional_move (operands);
- DONE;
-}")
-
-(define_expand "movdicc"
- [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
- (set (match_operand:DI 0 "register_operand" "")
- (if_then_else:DI (match_dup 5)
- (match_operand:DI 2 "se_reg_or_0_operand" "")
- (match_operand:DI 3 "se_reg_or_0_operand" "")))]
- "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
- "
-{
- if (mips_isa == 32)
- FAIL;
- gen_conditional_move (operands);
- DONE;
-}")
-
-(define_expand "movsfcc"
- [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
- (set (match_operand:SF 0 "register_operand" "")
- (if_then_else:SF (match_dup 5)
- (match_operand:SF 2 "register_operand" "")
- (match_operand:SF 3 "register_operand" "")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
- "
+(define_expand "mov<mode>cc"
+ [(set (match_dup 4) (match_operand 1 "comparison_operator"))
+ (set (match_operand:GPR 0 "register_operand")
+ (if_then_else:GPR (match_dup 5)
+ (match_operand:GPR 2 "reg_or_0_operand")
+ (match_operand:GPR 3 "reg_or_0_operand")))]
+ "ISA_HAS_CONDMOVE"
{
- gen_conditional_move (operands);
+ mips_expand_conditional_move (operands);
DONE;
-}")
+})
-(define_expand "movdfcc"
- [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
- (set (match_operand:DF 0 "register_operand" "")
- (if_then_else:DF (match_dup 5)
- (match_operand:DF 2 "register_operand" "")
- (match_operand:DF 3 "register_operand" "")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "
+(define_expand "mov<mode>cc"
+ [(set (match_dup 4) (match_operand 1 "comparison_operator"))
+ (set (match_operand:SCALARF 0 "register_operand")
+ (if_then_else:SCALARF (match_dup 5)
+ (match_operand:SCALARF 2 "register_operand")
+ (match_operand:SCALARF 3 "register_operand")))]
+ "ISA_HAS_FP_CONDMOVE"
{
- gen_conditional_move (operands);
+ mips_expand_conditional_move (operands);
DONE;
-}")
+})
\f
;;
;; ....................
;; ....................
;;
-(define_insn "consttable_qi"
- [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "=g")] 10)]
+(define_insn "consttable_int"
+ [(unspec_volatile [(match_operand 0 "consttable_operand" "")
+ (match_operand 1 "const_int_operand" "")]
+ UNSPEC_CONSTTABLE_INT)]
"TARGET_MIPS16"
- "*
{
- assemble_integer (operands[0], 1, BITS_PER_UNIT, 1);
- return \"\";
-}"
- [(set_attr "type" "unknown")
- (set_attr "mode" "QI")
- (set_attr "length" "8")])
-
-(define_insn "consttable_hi"
- [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "=g")] 11)]
- "TARGET_MIPS16"
- "*
-{
- assemble_integer (operands[0], 2, BITS_PER_UNIT * 2, 1);
- return \"\";
-}"
- [(set_attr "type" "unknown")
- (set_attr "mode" "HI")
- (set_attr "length" "8")])
-
-(define_insn "consttable_si"
- [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "=g")] 12)]
- "TARGET_MIPS16"
- "*
-{
- assemble_integer (operands[0], 4, BITS_PER_UNIT * 4, 1);
- return \"\";
-}"
- [(set_attr "type" "unknown")
- (set_attr "mode" "SI")
- (set_attr "length" "8")])
-
-(define_insn "consttable_di"
- [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "=g")] 13)]
- "TARGET_MIPS16"
- "*
-{
- assemble_integer (operands[0], 8, BITS_PER_UNIT * 8, 1);
- return \"\";
-}"
- [(set_attr "type" "unknown")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-(define_insn "consttable_sf"
- [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "=g")] 14)]
- "TARGET_MIPS16"
- "*
-{
- union real_extract u;
-
- if (GET_CODE (operands[0]) != CONST_DOUBLE)
- abort ();
- memcpy (&u, &CONST_DOUBLE_LOW (operands[0]), sizeof u);
- assemble_real (u.d, SFmode, GET_MODE_ALIGNMENT (SFmode));
- return \"\";
-}"
- [(set_attr "type" "unknown")
- (set_attr "mode" "SF")
- (set_attr "length" "8")])
+ assemble_integer (operands[0], INTVAL (operands[1]),
+ BITS_PER_UNIT * INTVAL (operands[1]), 1);
+ return "";
+}
+ [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
-(define_insn "consttable_df"
- [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "=g")] 15)]
+(define_insn "consttable_float"
+ [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
+ UNSPEC_CONSTTABLE_FLOAT)]
"TARGET_MIPS16"
- "*
{
- union real_extract u;
-
- if (GET_CODE (operands[0]) != CONST_DOUBLE)
- abort ();
- memcpy (&u, &CONST_DOUBLE_LOW (operands[0]), sizeof u);
- assemble_real (u.d, DFmode, GET_MODE_ALIGNMENT (DFmode));
- return \"\";
-}"
- [(set_attr "type" "unknown")
- (set_attr "mode" "DF")
- (set_attr "length" "16")])
-
-(define_insn "align_2"
- [(unspec_volatile [(const_int 0)] 16)]
- "TARGET_MIPS16"
- ".align 1"
- [(set_attr "type" "unknown")
- (set_attr "mode" "HI")
- (set_attr "length" "8")])
+ REAL_VALUE_TYPE d;
-(define_insn "align_4"
- [(unspec_volatile [(const_int 0)] 17)]
- "TARGET_MIPS16"
- ".align 2"
- [(set_attr "type" "unknown")
- (set_attr "mode" "SI")
- (set_attr "length" "8")])
+ gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
+ REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
+ assemble_real (d, GET_MODE (operands[0]),
+ GET_MODE_BITSIZE (GET_MODE (operands[0])));
+ return "";
+}
+ [(set (attr "length")
+ (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
-(define_insn "align_8"
- [(unspec_volatile [(const_int 0)] 18)]
- "TARGET_MIPS16"
- ".align 3"
- [(set_attr "type" "unknown")
- (set_attr "mode" "DI")
- (set_attr "length" "12")])
+(define_insn "align"
+ [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
+ ""
+ ".align\t%0"
+ [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
\f
+(define_split
+ [(match_operand 0 "small_data_pattern")]
+ "reload_completed"
+ [(match_dup 0)]
+ { operands[0] = mips_rewrite_small_data (operands[0]); })
+
;;
;; ....................
;;
-;; mips16 peepholes
+;; MIPS16e Save/Restore
;;
;; ....................
;;
-;; On the mips16, reload will sometimes decide that a pseudo register
-;; should go into $24, and then later on have to reload that register.
-;; When that happens, we get a load of a general register followed by
-;; a move from the general register to $24 followed by a branch.
-;; These peepholes catch the common case, and fix it to just use the
-;; general register for the branch.
-
-(define_peephole
- [(set (match_operand:SI 0 "register_operand" "=t")
- (match_operand:SI 1 "register_operand" "d"))
- (set (pc)
- (if_then_else (match_operator:SI 2 "equality_op" [(match_dup 0)
- (const_int 0)])
- (match_operand 3 "pc_or_label_operand" "")
- (match_operand 4 "pc_or_label_operand" "")))]
- "TARGET_MIPS16
- && GET_CODE (operands[0]) == REG
- && REGNO (operands[0]) == 24
- && dead_or_set_p (insn, operands[0])
- && GET_CODE (operands[1]) == REG
- && M16_REG_P (REGNO (operands[1]))"
- "*
-{
- if (operands[3] != pc_rtx)
- return \"%*b%C2z\\t%1,%3\";
- else
- return \"%*b%N2z\\t%1,%4\";
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")
- (set_attr "length" "8")])
+(define_insn "*mips16e_save_restore"
+ [(match_parallel 0 ""
+ [(set (match_operand:SI 1 "register_operand")
+ (plus:SI (match_dup 1)
+ (match_operand:SI 2 "const_int_operand")))])]
+ "operands[1] == stack_pointer_rtx
+ && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
+ { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
+ [(set_attr "type" "arith")
+ (set_attr "extended_mips16" "yes")])
+
+;; Thread-Local Storage
+
+;; The TLS base pointer is accessed via "rdhwr $3, $29". No current
+;; MIPS architecture defines this register, and no current
+;; implementation provides it; instead, any OS which supports TLS is
+;; expected to trap and emulate this instruction. rdhwr is part of the
+;; MIPS 32r2 specification, but we use it on any architecture because
+;; we expect it to be emulated. Use .set to force the assembler to
+;; accept it.
+;;
+;; We do not use a constraint to force the destination to be $3
+;; because $3 can appear explicitly as a function return value.
+;; If we leave the use of $3 implicit in the constraints until
+;; reload, we may end up making a $3 return value live across
+;; the instruction, leading to a spill failure when reloading it.
+(define_insn_and_split "tls_get_tp_<mode>"
+ [(set (match_operand:P 0 "register_operand" "=d")
+ (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
+ (clobber (reg:P TLS_GET_TP_REGNUM))]
+ "HAVE_AS_TLS && !TARGET_MIPS16"
+ "#"
+ "&& reload_completed"
+ [(set (reg:P TLS_GET_TP_REGNUM)
+ (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
+ (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
+ ""
+ [(set_attr "type" "unknown")
+ ; Since rdhwr always generates a trap for now, putting it in a delay
+ ; slot would make the kernel's emulation of it much slower.
+ (set_attr "can_delay" "no")
+ (set_attr "mode" "<MODE>")
+ (set_attr "length" "8")])
-(define_peephole
- [(set (match_operand:DI 0 "register_operand" "=t")
- (match_operand:DI 1 "register_operand" "d"))
- (set (pc)
- (if_then_else (match_operator:DI 2 "equality_op" [(match_dup 0)
- (const_int 0)])
- (match_operand 3 "pc_or_label_operand" "")
- (match_operand 4 "pc_or_label_operand" "")))]
- "TARGET_MIPS16 && TARGET_64BIT
- && GET_CODE (operands[0]) == REG
- && REGNO (operands[0]) == 24
- && dead_or_set_p (insn, operands[0])
- && GET_CODE (operands[1]) == REG
- && M16_REG_P (REGNO (operands[1]))"
- "*
-{
- if (operands[3] != pc_rtx)
- return \"%*b%C2z\\t%1,%3\";
- else
- return \"%*b%N2z\\t%1,%4\";
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")
- (set_attr "length" "8")])
+(define_insn "*tls_get_tp_<mode>_split"
+ [(set (reg:P TLS_GET_TP_REGNUM)
+ (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))]
+ "HAVE_AS_TLS && !TARGET_MIPS16"
+ ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop"
+ [(set_attr "type" "unknown")
+ ; See tls_get_tp_<mode>
+ (set_attr "can_delay" "no")
+ (set_attr "mode" "<MODE>")])
+\f
+;; Synchronization instructions.
-;; We can also have the reverse reload: reload will spill $24 into
-;; another register, and then do a branch on that register when it
-;; could have just stuck with $24.
+(include "sync.md")
-(define_peephole
- [(set (match_operand:SI 0 "register_operand" "=d")
- (match_operand:SI 1 "register_operand" "t"))
- (set (pc)
- (if_then_else (match_operator:SI 2 "equality_op" [(match_dup 0)
- (const_int 0)])
- (match_operand 3 "pc_or_label_operand" "")
- (match_operand 4 "pc_or_label_operand" "")))]
- "TARGET_MIPS16
- && GET_CODE (operands[1]) == REG
- && REGNO (operands[1]) == 24
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && dead_or_set_p (insn, operands[0])"
- "*
-{
- if (operands[3] != pc_rtx)
- return \"%*bt%C2z\\t%3\";
- else
- return \"%*bt%N2z\\t%4\";
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")
- (set_attr "length" "8")])
+; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
-(define_peephole
- [(set (match_operand:DI 0 "register_operand" "=d")
- (match_operand:DI 1 "register_operand" "t"))
- (set (pc)
- (if_then_else (match_operator:DI 2 "equality_op" [(match_dup 0)
- (const_int 0)])
- (match_operand 3 "pc_or_label_operand" "")
- (match_operand 4 "pc_or_label_operand" "")))]
- "TARGET_MIPS16 && TARGET_64BIT
- && GET_CODE (operands[1]) == REG
- && REGNO (operands[1]) == 24
- && GET_CODE (operands[0]) == REG
- && M16_REG_P (REGNO (operands[0]))
- && dead_or_set_p (insn, operands[0])"
- "*
-{
- if (operands[3] != pc_rtx)
- return \"%*bt%C2z\\t%3\";
- else
- return \"%*bt%N2z\\t%4\";
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")
- (set_attr "length" "8")])
+(include "mips-ps-3d.md")
-;; For the rare case where we need to load an address into a register
-;; that can not be recognized by the normal movsi/addsi instructions.
-;; I have no idea how many insns this can actually generate. It should
-;; be rare, so over-estimating as 10 instructions should not have any
-;; real performance impact.
-(define_insn "leasi"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (match_operand:SI 1 "address_operand" "p"))]
- "Pmode == SImode"
- "la %0,%a1"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "40")])
+; The MIPS DSP Instructions.
-;; Similarly for targets where we have 64bit pointers.
-(define_insn "leadi"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (match_operand:DI 1 "address_operand" "p"))]
- "Pmode == DImode"
- "la %0,%a1"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "40")])
+(include "mips-dsp.md")
+
+; The MIPS DSP REV 2 Instructions.
+
+(include "mips-dspr2.md")
+
+; MIPS fixed-point instructions.
+(include "mips-fixed.md")
+
+; ST-Microelectronics Loongson-2E/2F-specific patterns.
+(include "loongson.md")
projects / msp430-gcc.git / blobdiff