Let's let the compiler type system work for us. Instead of having a single

[tinyos-2.x.git] / tos / chips / msp430 / usci / Msp430SpiP.nc

diff --git a/tos/chips/msp430/usci/Msp430SpiP.nc b/tos/chips/msp430/usci/Msp430SpiP.nc
index fd57695a17e7905d3f5ac1fdcf4eb1f30765a3bc..2d8db430d41b9bca0375be9fd86533a0b5d03e2c 100644 (file)
--- a/tos/chips/msp430/usci/Msp430SpiP.nc
+++ b/tos/chips/msp430/usci/Msp430SpiP.nc
@@ -46,8 +46,7 @@ generic module Msp430SpiP() {
     interface HplMsp430GeneralIO as SIMO;
     interface HplMsp430GeneralIO as SOMI;
     interface HplMsp430GeneralIO as SCL;
-    interface AsyncConfigure<const msp430_usci_config_t*> as
-      Msp430UsciConfigure;
+    interface AsyncConfigure<const msp430_usci_spi_t*> as Configure;
     interface Counter<T32khz,uint16_6>
     interface ArbiterInfo;
   }
@@ -93,19 +92,19 @@ implementation {
   async command void ResourceConfigure.configure()
   {
     atomic {
-      const msp430_usci_config_t* config = call Msp430UsciConfigure.get();
+      const msp430_usci_spi_t* config = call Configure.get();
 
       call Registers.setCtl1(UCSWRST);
 
       /* Configure USCI registers */
-      call Registers.assignCtl0(config->spi.ctl0);
-      call Registers.assignCtl1(config->spi.ctl1|UCSWRST);
-      call Registers.assignBr0(config->spi.brx & 0xff);
-      call Registers.assignBr1(config->spi.brx >> 8);
-      call Registers.assignMctl(config->spi.mctl);
-      call Registers.assignIrtctl(config->spi.irtctl);
-      call Registers.assignIrrctl(config->spi.irrctl);
-      call Registers.assignAbctl(config->spi.abctl);
+      call Registers.assignCtl0(config->ctl0);
+      call Registers.assignCtl1(config->ctl1|UCSWRST);
+      call Registers.assignBr0(config->brx & 0xff);
+      call Registers.assignBr1(config->brx >> 8);
+      call Registers.assignMctl(config->mctl);
+      call Registers.assignIrtctl(config->irtctl);
+      call Registers.assignIrrctl(config->irrctl);
+      call Registers.assignAbctl(config->abctl);
       call Registers.clrStat(UCLISTEN);
 
       /* Save pin IO states */
@@ -115,8 +114,8 @@ implementation {
 
       /* Configure RX pin for UART use */
       call RXD.makeInput();
-      if (config->spi.ren & USCI_REN_RX) {
-       if (config->spi.ren & USCI_REN_RX_PULLUP)
+      if (config->ren & USCI_REN_RX) {
+       if (config->ren & USCI_REN_RX_PULLUP)
          call RXD.set();
        else
          call RXD.clr();
@@ -129,8 +128,8 @@ implementation {
        */
 
       /* Configure TX pin for UART use */
-      if (config->spi.ren & USCI_REN_TX) {
-       if (config->spi.ren & USCI_REN_TX_PULLUP)
+      if (config->ren & USCI_REN_TX) {
+       if (config->ren & USCI_REN_TX_PULLUP)
          call TXD.set();
        else
          call TXD.clr();
@@ -283,19 +282,14 @@ implementation {
       signal UartStream.receivedByte(byte);
   }
 
-  default async command const msp430_usci_config_t* Msp430UsciConfigure.get()
+  default async command const msp430_usci_spi_t* Configure.get()
   {
-    const static msp430_usci_config_t def = { 
-      spi: {
-       ctl0: UCMODE_0,         /* async, lsb first, 8N1 */
-       ctl1: UCSWRST|UCSSEL_1, /* clock spi from SMCLK */
-       brx: UBRX_32768HZ_9600,
-       mctl: UMCTL_32768HZ_9600,
-       irtctl: 0,
-       irrctl: 0,
-       abctl: 0,
-       ren: USCI_REN_NONE
-      }
+    const static msp430_usci_spi_t def = { 
+      ctl0: UCMODE_0,          /* async, lsb first, 8N1 */
+      ctl1: UCSWRST|UCSSEL_1,  /* clock spi from SMCLK */
+      brx: UBRX_32768HZ_9600,
+      mctl: UMCTL_32768HZ_9600, /* ??? */
+      ren: USCI_REN_NONE
     };
 
     return &def;