Let's let the compiler type system work for us. Instead of having a single

[tinyos-2.x.git] / tos / chips / msp430 / usci / Msp430UartP.nc

diff --git a/tos/chips/msp430/usci/Msp430UartP.nc b/tos/chips/msp430/usci/Msp430UartP.nc
index 8fe6bee02377f6fbbb0dd571a441893e1f8440ce..49dc1f1bac92445a9579b14ba43c63fa796e8c91 100644 (file)
--- a/tos/chips/msp430/usci/Msp430UartP.nc
+++ b/tos/chips/msp430/usci/Msp430UartP.nc
@@ -44,8 +44,7 @@ generic module Msp430UartP() {
     interface HplMsp430UsciInt as Interrupts;
     interface HplMsp430GeneralIO as RXD;
     interface HplMsp430GeneralIO as TXD;
-    interface AsyncConfigure<const msp430_usci_config_t*> as
-      Msp430UsciConfigure;
+    interface AsyncConfigure<const msp430_usci_uart_t*> as Configure;
     interface Counter<T32khz,uint16_t>;
     interface ArbiterInfo;
   }
@@ -91,19 +90,19 @@ implementation {
   async command void ResourceConfigure.configure()
   {
     atomic {
-      const msp430_usci_config_t* config = call Msp430UsciConfigure.get();
+      const msp430_usci_uart_t* config = call Configure.get();
 
       call Registers.setCtl1(UCSWRST);
 
       /* Configure USCI registers */
-      call Registers.assignCtl0(config->uart.ctl0);
-      call Registers.assignCtl1(config->uart.ctl1|UCSWRST);
-      call Registers.assignBr0(config->uart.brx & 0xff);
-      call Registers.assignBr1(config->uart.brx >> 8);
-      call Registers.assignMctl(config->uart.mctl);
-      call Registers.assignIrtctl(config->uart.irtctl);
-      call Registers.assignIrrctl(config->uart.irrctl);
-      call Registers.assignAbctl(config->uart.abctl);
+      call Registers.assignCtl0(config->ctl0);
+      call Registers.assignCtl1(config->ctl1|UCSWRST);
+      call Registers.assignBr0(config->brx & 0xff);
+      call Registers.assignBr1(config->brx >> 8);
+      call Registers.assignMctl(config->mctl);
+      call Registers.assignIrtctl(config->irtctl);
+      call Registers.assignIrrctl(config->irrctl);
+      call Registers.assignAbctl(config->abctl);
       call Registers.clrStat(UCLISTEN);
 
       /* Save pin IO states */
@@ -113,8 +112,8 @@ implementation {
 
       /* Configure RX pin for UART use */
       call RXD.makeInput();
-      if (config->uart.ren & USCI_REN_RX) {
-       if (config->uart.ren & USCI_REN_RX_PULLUP)
+      if (config->ren & USCI_REN_RX) {
+       if (config->ren & USCI_REN_RX_PULLUP)
          call RXD.set();
        else
          call RXD.clr();
@@ -127,8 +126,8 @@ implementation {
        */
 
       /* Configure TX pin for UART use */
-      if (config->uart.ren & USCI_REN_TX) {
-       if (config->uart.ren & USCI_REN_TX_PULLUP)
+      if (config->ren & USCI_REN_TX) {
+       if (config->ren & USCI_REN_TX_PULLUP)
          call TXD.set();
        else
          call TXD.clr();
@@ -281,19 +280,17 @@ implementation {
       signal UartStream.receivedByte(byte);
   }
 
-  default async command const msp430_usci_config_t* Msp430UsciConfigure.get()
+  default async command const msp430_usci_uart_t* Configure.get()
   {
-    const static msp430_usci_config_t def = { 
-      uart: {
-       ctl0: UCMODE_0,         /* async, lsb first, 8N1 */
-       ctl1: UCSWRST|UCSSEL_1, /* clock uart from SMCLK */
-       brx: UBRX_32768HZ_9600,
-       mctl: UMCTL_32768HZ_9600,
-       irtctl: 0,
-       irrctl: 0,
-       abctl: 0,
-       ren: USCI_REN_NONE
-      }
+    const static msp430_usci_uart_t def = { 
+      ctl0: UCMODE_0,          /* async, lsb first, 8N1 */
+      ctl1: UCSWRST|UCSSEL_1,  /* clock uart from SMCLK */
+      brx: UBRX_32768HZ_9600,
+      mctl: UMCTL_32768HZ_9600,
+      irtctl: 0,
+      irrctl: 0,
+      abctl: 0,
+      ren: USCI_REN_NONE
     };
 
     return &def;