-// $Id$ \r
-\r
-/* tab:4\r
- * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By\r
- * downloading, copying, installing or using the software you agree to\r
- * this license. If you do not agree to this license, do not download,\r
- * install, copy or use the software.\r
- *\r
- * Intel Open Source License \r
- *\r
- * Copyright (c) 2002 Intel Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * \r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * Neither the name of the Intel Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- * \r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * \r
- * \r
- */\r
-/*\r
- *\r
- * Authors: Phil Buonadonna\r
- *\r
- * Edits: Josh Herbach\r
- * Revised: 09/02/2005\r
- */\r
-\r
-module HplPXA27xInterruptM\r
-{\r
- provides {\r
- interface HplPXA27xInterrupt as PXA27xIrq[uint8_t id];\r
- interface HplPXA27xInterruptCntl;\r
- }\r
-}\r
-\r
-implementation \r
-{\r
-\r
- uint32_t getICHP() {\r
- uint32_t val;\r
-\r
- asm volatile ("mrc p6,0,%0,c5,c0,0\n\t":"=r" (val));\r
- return val;\r
- }\r
-\r
- /* Core PXA27X interrupt dispatch vectors */\r
- /* DO NOT change the name of these functions */\r
- void hplarmv_irq() __attribute__ ((interrupt ("IRQ"))) @C() @atomic_hwevent() {\r
-\r
- uint32_t IRQPending;\r
-\r
- IRQPending = getICHP(); // Determine which interrupt to service\r
- IRQPending >>= 16; // Right justify to the IRQ portion\r
-\r
- while (IRQPending & (1 << 15)) {\r
- uint8_t PeripheralID = (IRQPending & 0x3f); // Get rid of the Valid bit\r
- signal PXA27xIrq.fired[PeripheralID](); // Handler is responsible for clearing interrupt\r
- IRQPending = getICHP(); // Determine which interrupt to service\r
- IRQPending >>= 16; // Right justify to the IRQ portion\r
- }\r
-\r
- return;\r
- }\r
-\r
- void hplarmv_fiq() __attribute__ ((interrupt ("FIQ"))) @C() @atomic_hwevent() {\r
-\r
- } \r
-\r
- static uint8_t usedPriorities = 0;\r
-\r
- /* Helper functions */\r
- /* NOTE: Read-back of all register writes is necessary to ensure the data latches */\r
-\r
- error_t allocate(uint8_t id, bool level, uint8_t priority)\r
- {\r
- uint32_t tmp;\r
- error_t error = FAIL;\r
-\r
- atomic{\r
- uint8_t i;\r
- if(usedPriorities == 0){//assumed that the table will have some entries\r
- uint8_t PriorityTable[40], DuplicateTable[40];\r
- for(i = 0; i < 40; i++){\r
- DuplicateTable[i] = PriorityTable[i] = 0xFF;\r
- }\r
- \r
- for(i = 0; i < 40; i++)\r
- if(TOSH_IRP_TABLE[i] != 0xff){\r
- if(PriorityTable[TOSH_IRP_TABLE[i]] != 0xFF)/*duplicate priorities\r
- in the table, mark \r
- for later fixing*/\r
- DuplicateTable[i] = PriorityTable[TOSH_IRP_TABLE[i]];\r
- else\r
- PriorityTable[TOSH_IRP_TABLE[i]] = i;\r
- }\r
- \r
- //compress table\r
- for(i = 0; i < 40; i++){\r
- if(PriorityTable[i] != 0xff){\r
- PriorityTable[usedPriorities] = PriorityTable[i];\r
- if(i != usedPriorities)\r
- PriorityTable[i] = 0xFF;\r
- usedPriorities++;\r
- }\r
- }\r
-\r
- for(i = 0; i < 40; i++)\r
- if(DuplicateTable[i] != 0xFF){\r
- uint8_t j, ExtraTable[40];\r
- for(j = 0; DuplicateTable[i] != PriorityTable[j]; j++);\r
- memcpy(ExtraTable + j + 1, PriorityTable + j, usedPriorities - j);\r
- memcpy(PriorityTable + j + 1, ExtraTable + j + 1, \r
- usedPriorities - j);\r
- PriorityTable[j] = i;\r
- usedPriorities++;\r
- }\r
-\r
- for(i = 0; i < usedPriorities; i++){\r
- IPR(i) = (IPR_VALID | PriorityTable[i]);\r
- tmp = IPR(i);\r
- }\r
- }\r
-\r
- if (id < 34){\r
- if(priority == 0xff){\r
- priority = usedPriorities;\r
- usedPriorities++;\r
- IPR(priority) = (IPR_VALID | (id));\r
- tmp = IPR(priority);\r
- }\r
- if (level) {\r
- _ICLR(id) |= _PPID_Bit(id);\r
- tmp = _ICLR(id);\r
- } \r
- \r
- error = SUCCESS;\r
- }\r
- }\r
- return error;\r
- }\r
- \r
- void enable(uint8_t id)\r
- {\r
- uint32_t tmp;\r
- atomic {\r
- if (id < 34) {\r
- _ICMR(id) |= _PPID_Bit(id);\r
- tmp = _ICMR(id);\r
- }\r
- }\r
- return;\r
- }\r
-\r
- void disable(uint8_t id)\r
- {\r
- uint32_t tmp;\r
- atomic {\r
- if (id < 34) {\r
- _ICMR(id) &= ~(_PPID_Bit(id));\r
- tmp = _ICMR(id);\r
- }\r
- }\r
- return;\r
- }\r
-\r
- /* Interface implementation */\r
-\r
- async command error_t PXA27xIrq.allocate[uint8_t id]()\r
- {\r
- return allocate(id, FALSE, TOSH_IRP_TABLE[id]);\r
- }\r
-\r
- async command void PXA27xIrq.enable[uint8_t id]()\r
- {\r
- enable(id);\r
- return;\r
- }\r
-\r
- async command void PXA27xIrq.disable[uint8_t id]()\r
- {\r
- disable(id);\r
- return;\r
- }\r
-\r
- async command void HplPXA27xInterruptCntl.setICCR_DIM(bool flag) {\r
-\r
- if (flag) {\r
- ICCR |= ICCR_DIM;\r
- }\r
- else {\r
- ICCR = 0;\r
- }\r
- return;\r
-\r
- }\r
-\r
- async command bool HplPXA27xInterruptCntl.getICCR_DIM() {\r
- bool result = FALSE;\r
-\r
- if (ICCR & ICCR_DIM) {\r
- result = TRUE;\r
- }\r
-\r
- return result;\r
- }\r
-\r
- default async event void PXA27xIrq.fired[uint8_t id]() \r
- {\r
- return;\r
- }\r
-\r
-}\r
+// $Id$
+
+/* tab:4
+ * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
+ * downloading, copying, installing or using the software you agree to
+ * this license. If you do not agree to this license, do not download,
+ * install, copy or use the software.
+ *
+ * Intel Open Source License
+ *
+ * Copyright (c) 2002 Intel Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ */
+/*
+ *
+ * Authors: Phil Buonadonna
+ *
+ * Edits: Josh Herbach
+ * Revised: 09/02/2005
+ */
+
+module HplPXA27xInterruptM
+{
+ provides {
+ interface HplPXA27xInterrupt as PXA27xIrq[uint8_t id];
+ interface HplPXA27xInterruptCntl;
+ }
+}
+
+implementation
+{
+
+ uint32_t getICHP() {
+ uint32_t val;
+
+ asm volatile ("mrc p6,0,%0,c5,c0,0\n\t":"=r" (val));
+ return val;
+ }
+
+ /* Core PXA27X interrupt dispatch vectors */
+ /* DO NOT change the name of these functions */
+ void hplarmv_irq() __attribute__ ((interrupt ("IRQ"))) @C() @atomic_hwevent() {
+
+ uint32_t IRQPending;
+
+ IRQPending = getICHP(); // Determine which interrupt to service
+ IRQPending >>= 16; // Right justify to the IRQ portion
+
+ while (IRQPending & (1 << 15)) {
+ uint8_t PeripheralID = (IRQPending & 0x3f); // Get rid of the Valid bit
+ signal PXA27xIrq.fired[PeripheralID](); // Handler is responsible for clearing interrupt
+ IRQPending = getICHP(); // Determine which interrupt to service
+ IRQPending >>= 16; // Right justify to the IRQ portion
+ }
+
+ return;
+ }
+
+ void hplarmv_fiq() __attribute__ ((interrupt ("FIQ"))) @C() @atomic_hwevent() {
+
+ }
+
+ static uint8_t usedPriorities = 0;
+
+ /* Helper functions */
+ /* NOTE: Read-back of all register writes is necessary to ensure the data latches */
+
+ error_t allocate(uint8_t id, bool level, uint8_t priority)
+ {
+ uint32_t tmp;
+ error_t error = FAIL;
+
+ atomic{
+ uint8_t i;
+ if(usedPriorities == 0){//assumed that the table will have some entries
+ uint8_t PriorityTable[40], DuplicateTable[40];
+ for(i = 0; i < 40; i++){
+ DuplicateTable[i] = PriorityTable[i] = 0xFF;
+ }
+
+ for(i = 0; i < 40; i++)
+ if(TOSH_IRP_TABLE[i] != 0xff){
+ if(PriorityTable[TOSH_IRP_TABLE[i]] != 0xFF)/*duplicate priorities
+ in the table, mark
+ for later fixing*/
+ DuplicateTable[i] = PriorityTable[TOSH_IRP_TABLE[i]];
+ else
+ PriorityTable[TOSH_IRP_TABLE[i]] = i;
+ }
+
+ //compress table
+ for(i = 0; i < 40; i++){
+ if(PriorityTable[i] != 0xff){
+ PriorityTable[usedPriorities] = PriorityTable[i];
+ if(i != usedPriorities)
+ PriorityTable[i] = 0xFF;
+ usedPriorities++;
+ }
+ }
+
+ for(i = 0; i < 40; i++)
+ if(DuplicateTable[i] != 0xFF){
+ uint8_t j, ExtraTable[40];
+ for(j = 0; DuplicateTable[i] != PriorityTable[j]; j++);
+ memcpy(ExtraTable + j + 1, PriorityTable + j, usedPriorities - j);
+ memcpy(PriorityTable + j + 1, ExtraTable + j + 1,
+ usedPriorities - j);
+ PriorityTable[j] = i;
+ usedPriorities++;
+ }
+
+ for(i = 0; i < usedPriorities; i++){
+ IPR(i) = (IPR_VALID | PriorityTable[i]);
+ tmp = IPR(i);
+ }
+ }
+
+ if (id < 34){
+ if(priority == 0xff){
+ priority = usedPriorities;
+ usedPriorities++;
+ IPR(priority) = (IPR_VALID | (id));
+ tmp = IPR(priority);
+ }
+ if (level) {
+ _ICLR(id) |= _PPID_Bit(id);
+ tmp = _ICLR(id);
+ }
+
+ error = SUCCESS;
+ }
+ }
+ return error;
+ }
+
+ void enable(uint8_t id)
+ {
+ uint32_t tmp;
+ atomic {
+ if (id < 34) {
+ _ICMR(id) |= _PPID_Bit(id);
+ tmp = _ICMR(id);
+ }
+ }
+ return;
+ }
+
+ void disable(uint8_t id)
+ {
+ uint32_t tmp;
+ atomic {
+ if (id < 34) {
+ _ICMR(id) &= ~(_PPID_Bit(id));
+ tmp = _ICMR(id);
+ }
+ }
+ return;
+ }
+
+ /* Interface implementation */
+
+ async command error_t PXA27xIrq.allocate[uint8_t id]()
+ {
+ return allocate(id, FALSE, TOSH_IRP_TABLE[id]);
+ }
+
+ async command void PXA27xIrq.enable[uint8_t id]()
+ {
+ enable(id);
+ return;
+ }
+
+ async command void PXA27xIrq.disable[uint8_t id]()
+ {
+ disable(id);
+ return;
+ }
+
+ async command void HplPXA27xInterruptCntl.setICCR_DIM(bool flag) {
+
+ if (flag) {
+ ICCR |= ICCR_DIM;
+ }
+ else {
+ ICCR = 0;
+ }
+ return;
+
+ }
+
+ async command bool HplPXA27xInterruptCntl.getICCR_DIM() {
+ bool result = FALSE;
+
+ if (ICCR & ICCR_DIM) {
+ result = TRUE;
+ }
+
+ return result;
+ }
+
+ default async event void PXA27xIrq.fired[uint8_t id]()
+ {
+ return;
+ }
+
+}
projects / tinyos-2.x.git / blobdiff