-/* $Id$ */\r
-/*\r
- * Copyright (c) 2005 Arch Rock Corporation \r
- * All rights reserved. \r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * \r
- * Neither the name of the Arch Rock Corporation nor the names of its\r
- * contributors may be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED\r
- * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\r
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\r
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
- * DAMAGE.\r
- */\r
-/**\r
- * This Hal module implements the TinyOS 2.0 I2CPacket interface over\r
- * the PXA27x I2C Hpl\r
- *\r
- * @author Phil Buonadonna\r
- */\r
-\r
-#include <I2C.h>\r
-\r
-generic module HalPXA27xI2CMasterP(bool fast_mode)\r
-{\r
- provides interface Init;\r
- provides interface I2CPacket<TI2CBasicAddr>;\r
-\r
- uses interface HplPXA27xI2C as I2C;\r
-\r
- uses interface HplPXA27xGPIOPin as I2CSCL;\r
- uses interface HplPXA27xGPIOPin as I2CSDA;\r
-\r
-}\r
-\r
-implementation\r
-{\r
- // These states don't necessarily reflect the state of the I2C bus, rather the state of this\r
- // module WRT an operation. I.E. the module might be in STATE_IDLE, but the I2C bus still\r
- // held by the master for a continued read.\r
- enum {\r
- I2C_STATE_IDLE,\r
- I2C_STATE_READSTART,\r
- I2C_STATE_READ,\r
- I2C_STATE_READEND,\r
- I2C_STATE_WRITE,\r
- I2C_STATE_WRITEEND,\r
- I2C_STATE_ERROR\r
- };\r
-\r
- uint8_t mI2CState;\r
- uint16_t mCurTargetAddr;\r
- uint8_t *mCurBuf, mCurBufLen, mCurBufIndex;\r
- i2c_flags_t mCurFlags;\r
- uint32_t mBaseICRFlags;\r
-\r
- static void readNextByte() {\r
- if (mCurBufIndex >= (mCurBufLen - 1)) {\r
- atomic { mI2CState = I2C_STATE_READEND; }\r
- if (mCurFlags & I2C_STOP) {\r
- call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_DRFIE | ICR_ACKNAK | ICR_TB | ICR_STOP));\r
- }\r
- else if (mCurFlags & I2C_ACK_END) {\r
- call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_DRFIE | ICR_TB));\r
- }\r
- else {\r
- call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_DRFIE | ICR_ACKNAK | ICR_TB));\r
- }\r
- }\r
- else {\r
- atomic { mI2CState = I2C_STATE_READ; }\r
- call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_DRFIE | ICR_TB));\r
- }\r
- return;\r
- }\r
-\r
- static void writeNextByte() {\r
- if (mCurBufIndex >= mCurBufLen) {\r
- atomic { mI2CState = I2C_STATE_WRITEEND; }\r
- \r
- if (mCurFlags & I2C_STOP) {\r
- call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_TB | ICR_ITEIE | ICR_STOP));\r
- }\r
- \r
- else {\r
- call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_ITEIE | ICR_TB));\r
- }\r
- \r
- }\r
- else {\r
- call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_ITEIE |ICR_TB));\r
- }\r
- return;\r
- }\r
- \r
- static error_t startI2CTransact(uint8_t nextState, uint16_t addr, uint8_t length, uint8_t *data, \r
- i2c_flags_t flags, bool bRnW) {\r
- error_t error = SUCCESS;\r
- uint8_t tmpAddr;\r
-\r
- if ((data == NULL) || (length == 0)) {\r
- return EINVAL;\r
- }\r
-\r
- atomic {\r
- if (mI2CState == I2C_STATE_IDLE) {\r
- mI2CState = nextState;\r
- mCurTargetAddr = addr;\r
- mCurBuf = data;\r
- mCurBufLen = length;\r
- mCurBufIndex = 0;\r
- mCurFlags = flags;\r
- }\r
- else {\r
- error = EBUSY;\r
- }\r
- }\r
- if (error) {\r
- return error;\r
- }\r
-\r
- if (flags & I2C_START) {\r
-\r
- tmpAddr = (bRnW) ? 0x1 : 0x0;\r
- tmpAddr |= ((addr << 1) & 0xFE);\r
- call I2C.setIDBR(tmpAddr);\r
- call I2C.setICR( mBaseICRFlags | ICR_ITEIE | ICR_TB | ICR_START);\r
- }\r
- else if (bRnW) {\r
- atomic {\r
- readNextByte();\r
- }\r
- }\r
- else {\r
- atomic {\r
- writeNextByte();\r
- }\r
- }\r
- return error;\r
- }\r
-\r
-\r
- task void handleReadError() {\r
- call I2C.setISAR(0x7F0);\r
- call I2C.setICR(mBaseICRFlags | ICR_MA);\r
- call I2C.setICR(ICR_UR);\r
- call I2C.setICR(mBaseICRFlags);\r
- atomic {\r
- mI2CState = I2C_STATE_IDLE;\r
- signal I2CPacket.readDone(FAIL,mCurTargetAddr,mCurBufLen,mCurBuf);\r
- }\r
- return;\r
- }\r
- \r
- task void handleWriteError() {\r
- call I2C.setISAR(0x7F0);\r
- call I2C.setICR(mBaseICRFlags | ICR_MA);\r
- call I2C.setICR(ICR_UR);\r
- call I2C.setICR(mBaseICRFlags);\r
- atomic {\r
- mI2CState = I2C_STATE_IDLE;\r
- signal I2CPacket.writeDone(FAIL,mCurTargetAddr,mCurBufLen,mCurBuf);\r
- }\r
- return;\r
- }\r
-\r
- command error_t Init.init() {\r
- atomic {\r
- mBaseICRFlags = (fast_mode) ? (ICR_FM | ICR_BEIE | ICR_IUE | ICR_SCLE) : (ICR_BEIE | ICR_IUE | ICR_SCLE);\r
-\r
- call I2CSCL.setGAFRpin(I2C_SCL_ALTFN);\r
- call I2CSCL.setGPDRbit(TRUE);\r
- call I2CSDA.setGAFRpin(I2C_SDA_ALTFN);\r
- call I2CSDA.setGPDRbit(TRUE);\r
-\r
- mI2CState = I2C_STATE_IDLE;\r
- call I2C.setISAR(0);\r
- call I2C.setICR(mBaseICRFlags | ICR_ITEIE | ICR_DRFIE);\r
- } \r
- return SUCCESS;\r
- }\r
-\r
- async command error_t I2CPacket.read(i2c_flags_t flags, uint16_t addr, uint8_t length, uint8_t* data) {\r
- error_t error = SUCCESS;\r
-\r
- if ((flags & I2C_ACK_END) && (flags & I2C_STOP)) {\r
- error = EINVAL;\r
- return error;\r
- }\r
-\r
- if (flags & I2C_START) {\r
- error = startI2CTransact(I2C_STATE_READSTART,addr,length,data,flags,TRUE);\r
- }\r
- else {\r
- error = startI2CTransact(I2C_STATE_READ,addr,length,data,flags,TRUE);\r
- }\r
- \r
- return error;\r
- }\r
-\r
- async command error_t I2CPacket.write(i2c_flags_t flags, uint16_t addr, uint8_t length, uint8_t* data) {\r
- error_t error = SUCCESS;\r
-\r
- error = startI2CTransact(I2C_STATE_WRITE,addr,length,data,flags,FALSE);\r
-\r
- return error;\r
- }\r
-\r
- async event void I2C.interruptI2C() {\r
- uint32_t valISR;\r
-\r
- // PXA27x Devel Guide is wrong. You have to write to the ISR to clear the bits.\r
- valISR = call I2C.getISR();\r
- call I2C.setISR(ISR_ITE | ISR_IRF);\r
-\r
- // turn off DRFIE and ITEIE\r
- //call I2C.setICR((call I2C.getICR()) & ~(ICR_DRFIE | ICR_ITEIE));\r
- //call I2C.setICR(mBaseICRFlags);\r
-\r
- switch (mI2CState) {\r
- case I2C_STATE_IDLE:\r
- // Should never get here. Reset all pending interrupts.\r
- break;\r
-\r
- case I2C_STATE_READSTART:\r
- if (valISR & (ISR_BED | ISR_ALD)) {\r
- mI2CState = I2C_STATE_ERROR;\r
- post handleReadError();\r
- break;\r
- }\r
- readNextByte();\r
- break;\r
-\r
- case I2C_STATE_READ:\r
- if (valISR & (ISR_BED | ISR_ALD)) {\r
- mI2CState = I2C_STATE_ERROR;\r
- post handleReadError();\r
- break;\r
- }\r
- mCurBuf[mCurBufIndex] = call I2C.getIDBR();\r
- mCurBufIndex++;\r
- readNextByte();\r
- break;\r
-\r
- case I2C_STATE_READEND:\r
- if (valISR & (ISR_BED | ISR_ALD)) {\r
- mI2CState = I2C_STATE_ERROR;\r
- post handleReadError();\r
- break;\r
- }\r
- mCurBuf[mCurBufIndex] = call I2C.getIDBR();\r
- mI2CState = I2C_STATE_IDLE;\r
- signal I2CPacket.readDone(SUCCESS,mCurTargetAddr,mCurBufLen,mCurBuf);\r
- break;\r
-\r
- case I2C_STATE_WRITE:\r
- if (valISR & (ISR_BED | ISR_ALD)) {\r
- mI2CState = I2C_STATE_ERROR;\r
- post handleWriteError();\r
- break;\r
- }\r
- call I2C.setIDBR(mCurBuf[mCurBufIndex]);\r
- mCurBufIndex++;\r
- writeNextByte();\r
-\r
- break;\r
-\r
- case I2C_STATE_WRITEEND:\r
- if (valISR & (ISR_BED | ISR_ALD)) {\r
- mI2CState = I2C_STATE_ERROR;\r
- post handleWriteError();\r
- break;\r
- }\r
- mI2CState= I2C_STATE_IDLE;\r
- //call I2C.setICR(call I2C.getICR() & ~I2C_STOP);\r
- call I2C.setICR(mBaseICRFlags);\r
- signal I2CPacket.writeDone(SUCCESS,mCurTargetAddr,mCurBufLen,mCurBuf);\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- \r
- return;\r
- }\r
-\r
- default async event void I2CPacket.readDone(error_t error, uint16_t addr, \r
- uint8_t length, uint8_t* data) {\r
- return;\r
- }\r
-\r
- default async event void I2CPacket.writeDone(error_t error, uint16_t addr, \r
- uint8_t length, uint8_t* data) { \r
- return;\r
- }\r
-\r
- async event void I2CSDA.interruptGPIOPin() {}\r
- async event void I2CSCL.interruptGPIOPin() {}\r
-}\r
+/* $Id$ */
+/*
+ * Copyright (c) 2005 Arch Rock Corporation
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of the Arch Rock Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
+ * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+/**
+ * This Hal module implements the TinyOS 2.0 I2CPacket interface over
+ * the PXA27x I2C Hpl
+ *
+ * @author Phil Buonadonna
+ */
+
+#include <I2C.h>
+
+generic module HalPXA27xI2CMasterP(bool fast_mode)
+{
+ provides interface Init;
+ provides interface I2CPacket<TI2CBasicAddr>;
+
+ uses interface HplPXA27xI2C as I2C;
+
+ uses interface HplPXA27xGPIOPin as I2CSCL;
+ uses interface HplPXA27xGPIOPin as I2CSDA;
+
+}
+
+implementation
+{
+ // These states don't necessarily reflect the state of the I2C bus, rather the state of this
+ // module WRT an operation. I.E. the module might be in STATE_IDLE, but the I2C bus still
+ // held by the master for a continued read.
+ enum {
+ I2C_STATE_IDLE,
+ I2C_STATE_READSTART,
+ I2C_STATE_READ,
+ I2C_STATE_READEND,
+ I2C_STATE_WRITE,
+ I2C_STATE_WRITEEND,
+ I2C_STATE_ERROR
+ };
+
+ uint8_t mI2CState;
+ uint16_t mCurTargetAddr;
+ uint8_t *mCurBuf, mCurBufLen, mCurBufIndex;
+ i2c_flags_t mCurFlags;
+ uint32_t mBaseICRFlags;
+
+ static void readNextByte() {
+ if (mCurBufIndex >= (mCurBufLen - 1)) {
+ atomic { mI2CState = I2C_STATE_READEND; }
+ if (mCurFlags & I2C_STOP) {
+ call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_DRFIE | ICR_ACKNAK | ICR_TB | ICR_STOP));
+ }
+ else if (mCurFlags & I2C_ACK_END) {
+ call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_DRFIE | ICR_TB));
+ }
+ else {
+ call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_DRFIE | ICR_ACKNAK | ICR_TB));
+ }
+ }
+ else {
+ atomic { mI2CState = I2C_STATE_READ; }
+ call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_DRFIE | ICR_TB));
+ }
+ return;
+ }
+
+ static void writeNextByte() {
+ if (mCurBufIndex >= mCurBufLen) {
+ atomic { mI2CState = I2C_STATE_WRITEEND; }
+
+ if (mCurFlags & I2C_STOP) {
+ call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_TB | ICR_ITEIE | ICR_STOP));
+ }
+
+ else {
+ call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_ITEIE | ICR_TB));
+ }
+
+ }
+ else {
+ call I2C.setICR((mBaseICRFlags) | (ICR_ALDIE | ICR_ITEIE |ICR_TB));
+ }
+ return;
+ }
+
+ static error_t startI2CTransact(uint8_t nextState, uint16_t addr, uint8_t length, uint8_t *data,
+ i2c_flags_t flags, bool bRnW) {
+ error_t error = SUCCESS;
+ uint8_t tmpAddr;
+
+ if ((data == NULL) || (length == 0)) {
+ return EINVAL;
+ }
+
+ atomic {
+ if (mI2CState == I2C_STATE_IDLE) {
+ mI2CState = nextState;
+ mCurTargetAddr = addr;
+ mCurBuf = data;
+ mCurBufLen = length;
+ mCurBufIndex = 0;
+ mCurFlags = flags;
+ }
+ else {
+ error = EBUSY;
+ }
+ }
+ if (error) {
+ return error;
+ }
+
+ if (flags & I2C_START) {
+
+ tmpAddr = (bRnW) ? 0x1 : 0x0;
+ tmpAddr |= ((addr << 1) & 0xFE);
+ call I2C.setIDBR(tmpAddr);
+ call I2C.setICR( mBaseICRFlags | ICR_ITEIE | ICR_TB | ICR_START);
+ }
+ else if (bRnW) {
+ atomic {
+ readNextByte();
+ }
+ }
+ else {
+ atomic {
+ writeNextByte();
+ }
+ }
+ return error;
+ }
+
+
+ task void handleReadError() {
+ call I2C.setISAR(0x7F0);
+ call I2C.setICR(mBaseICRFlags | ICR_MA);
+ call I2C.setICR(ICR_UR);
+ call I2C.setICR(mBaseICRFlags);
+ atomic {
+ mI2CState = I2C_STATE_IDLE;
+ signal I2CPacket.readDone(FAIL,mCurTargetAddr,mCurBufLen,mCurBuf);
+ }
+ return;
+ }
+
+ task void handleWriteError() {
+ call I2C.setISAR(0x7F0);
+ call I2C.setICR(mBaseICRFlags | ICR_MA);
+ call I2C.setICR(ICR_UR);
+ call I2C.setICR(mBaseICRFlags);
+ atomic {
+ mI2CState = I2C_STATE_IDLE;
+ signal I2CPacket.writeDone(FAIL,mCurTargetAddr,mCurBufLen,mCurBuf);
+ }
+ return;
+ }
+
+ command error_t Init.init() {
+ atomic {
+ mBaseICRFlags = (fast_mode) ? (ICR_FM | ICR_BEIE | ICR_IUE | ICR_SCLE) : (ICR_BEIE | ICR_IUE | ICR_SCLE);
+
+ call I2CSCL.setGAFRpin(I2C_SCL_ALTFN);
+ call I2CSCL.setGPDRbit(TRUE);
+ call I2CSDA.setGAFRpin(I2C_SDA_ALTFN);
+ call I2CSDA.setGPDRbit(TRUE);
+
+ mI2CState = I2C_STATE_IDLE;
+ call I2C.setISAR(0);
+ call I2C.setICR(mBaseICRFlags | ICR_ITEIE | ICR_DRFIE);
+ }
+ return SUCCESS;
+ }
+
+ async command error_t I2CPacket.read(i2c_flags_t flags, uint16_t addr, uint8_t length, uint8_t* data) {
+ error_t error = SUCCESS;
+
+ if ((flags & I2C_ACK_END) && (flags & I2C_STOP)) {
+ error = EINVAL;
+ return error;
+ }
+
+ if (flags & I2C_START) {
+ error = startI2CTransact(I2C_STATE_READSTART,addr,length,data,flags,TRUE);
+ }
+ else {
+ error = startI2CTransact(I2C_STATE_READ,addr,length,data,flags,TRUE);
+ }
+
+ return error;
+ }
+
+ async command error_t I2CPacket.write(i2c_flags_t flags, uint16_t addr, uint8_t length, uint8_t* data) {
+ error_t error = SUCCESS;
+
+ error = startI2CTransact(I2C_STATE_WRITE,addr,length,data,flags,FALSE);
+
+ return error;
+ }
+
+ async event void I2C.interruptI2C() {
+ uint32_t valISR;
+
+ // PXA27x Devel Guide is wrong. You have to write to the ISR to clear the bits.
+ valISR = call I2C.getISR();
+ call I2C.setISR(ISR_ITE | ISR_IRF);
+
+ // turn off DRFIE and ITEIE
+ //call I2C.setICR((call I2C.getICR()) & ~(ICR_DRFIE | ICR_ITEIE));
+ //call I2C.setICR(mBaseICRFlags);
+
+ switch (mI2CState) {
+ case I2C_STATE_IDLE:
+ // Should never get here. Reset all pending interrupts.
+ break;
+
+ case I2C_STATE_READSTART:
+ if (valISR & (ISR_BED | ISR_ALD)) {
+ mI2CState = I2C_STATE_ERROR;
+ post handleReadError();
+ break;
+ }
+ readNextByte();
+ break;
+
+ case I2C_STATE_READ:
+ if (valISR & (ISR_BED | ISR_ALD)) {
+ mI2CState = I2C_STATE_ERROR;
+ post handleReadError();
+ break;
+ }
+ mCurBuf[mCurBufIndex] = call I2C.getIDBR();
+ mCurBufIndex++;
+ readNextByte();
+ break;
+
+ case I2C_STATE_READEND:
+ if (valISR & (ISR_BED | ISR_ALD)) {
+ mI2CState = I2C_STATE_ERROR;
+ post handleReadError();
+ break;
+ }
+ mCurBuf[mCurBufIndex] = call I2C.getIDBR();
+ mI2CState = I2C_STATE_IDLE;
+ signal I2CPacket.readDone(SUCCESS,mCurTargetAddr,mCurBufLen,mCurBuf);
+ break;
+
+ case I2C_STATE_WRITE:
+ if (valISR & (ISR_BED | ISR_ALD)) {
+ mI2CState = I2C_STATE_ERROR;
+ post handleWriteError();
+ break;
+ }
+ call I2C.setIDBR(mCurBuf[mCurBufIndex]);
+ mCurBufIndex++;
+ writeNextByte();
+
+ break;
+
+ case I2C_STATE_WRITEEND:
+ if (valISR & (ISR_BED | ISR_ALD)) {
+ mI2CState = I2C_STATE_ERROR;
+ post handleWriteError();
+ break;
+ }
+ mI2CState= I2C_STATE_IDLE;
+ //call I2C.setICR(call I2C.getICR() & ~I2C_STOP);
+ call I2C.setICR(mBaseICRFlags);
+ signal I2CPacket.writeDone(SUCCESS,mCurTargetAddr,mCurBufLen,mCurBuf);
+ break;
+
+ default:
+ break;
+ }
+
+
+ return;
+ }
+
+ default async event void I2CPacket.readDone(error_t error, uint16_t addr,
+ uint8_t length, uint8_t* data) {
+ return;
+ }
+
+ default async event void I2CPacket.writeDone(error_t error, uint16_t addr,
+ uint8_t length, uint8_t* data) {
+ return;
+ }
+
+ async event void I2CSDA.interruptGPIOPin() {}
+ async event void I2CSCL.interruptGPIOPin() {}
+}
projects / tinyos-2.x.git / blobdiff