* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-
+
/**
* This BusyWait interface is solely designed for use in providing the
* necessary 5us timing when bit-banging the SHT1X sensibus clock pin in
* is designed for such platforms. Platforms using higher performance
* microprocessors may need to override this component with a platform-specific
* one to provide the necessary wait time.
- *
+ *
* @author R. Steve McKown <rsmckown@gmail.com>
*/
-
+
module SensirionBusyWaitC {
provides interface BusyWait<TMicro, uint8_t>;
}