MSP430REG_NORACE(TBCTL);
MSP430REG_NORACE(TBIV);
+ #if defined(__MSP430_HAS_BC2__) /* basic clock module+ */
+ #define FIRST_STEP 0x1000
+ #else /* orig basic clock module */
+ #define RSEL3 0
+ #define FIRST_STEP 0x800
+ #endif
+
enum
{
+ DCOX = DCO2 + DCO1 + DCO0,
+ MODX = MOD4 + MOD3 + MOD2 + MOD1 + MOD0,
+ RSELX = RSEL3 + RSEL2 + RSEL1 + RSEL0,
ACLK_CALIB_PERIOD = 8,
TARGET_DCO_DELTA = (TARGET_DCO_KHZ / ACLK_KHZ) * ACLK_CALIB_PERIOD,
};
// .XTS = 0; set low frequency mode for LXFT1
// .DIVA = 0; set the divisor on ACLK to 1
// .RSEL, do not modify
- BCSCTL1 = XT2OFF | (BCSCTL1 & (RSEL2|RSEL1|RSEL0));
+ BCSCTL1 = XT2OFF | (BCSCTL1 & RSELX);
// BCSCTL2
// .SELM = 0; select DCOCLK as source for MCLK
void set_dco_calib( int calib )
{
- BCSCTL1 = (BCSCTL1 & ~0x07) | ((calib >> 8) & 0x07);
+ BCSCTL1 = (BCSCTL1 & ~RSELX) | ((calib >> 8) & RSELX);
DCOCTL = calib & 0xff;
}
// Binary search for RSEL,DCO,DCOMOD.
// It's okay that RSEL isn't monotonic.
- for( calib=0,step=0x800; step!=0; step>>=1 )
+ for( calib=0,step=FIRST_STEP; step!=0; step>>=1 )
{
// if the step is not past the target, commit it
if( test_calib_busywait_delta(calib|step) <= TARGET_DCO_DELTA )
calib |= step;
}
- // if DCOx is 7 (0x0e0 in calib), then the 5-bit MODx is not useable, set it to 0
- if( (calib & 0x0e0) == 0x0e0 )
- calib &= ~0x01f;
+ // if DCOx is all 1s in calib, then MODx is not useable, set it to 0
+ if( (calib & DCOX) == DCOX )
+ calib &= ~MODX;
set_dco_calib( calib );
}