ensure visibility of atomic statement effects

diff --git a/tos/chips/atm128/atm128hardware.h b/tos/chips/atm128/atm128hardware.h
index cfc7eaf7f372ce17ef5c38c0dbaf1a5898878611..3e4bb03094a572b87d0e10ab43b96156219635d4 100644 (file)
--- a/tos/chips/atm128/atm128hardware.h
+++ b/tos/chips/atm128/atm128hardware.h
@@ -104,6 +104,7 @@ __nesc_atomic_start(void) @spontaneous()
 {
     __nesc_atomic_t result = SREG;
     __nesc_disable_interrupt();
+    asm volatile("" : : : "memory"); /* ensure atomic section effect visibility */
     return result;
 }
 
@@ -111,6 +112,7 @@ __nesc_atomic_start(void) @spontaneous()
 inline void 
 __nesc_atomic_end(__nesc_atomic_t original_SREG) @spontaneous()
 {
+  asm volatile("" : : : "memory"); /* ensure atomic section effect visibility */
   SREG = original_SREG;
 }
 #endif

diff --git a/tos/chips/msp430/msp430hardware.h b/tos/chips/msp430/msp430hardware.h
index 9d0cedd87662664b5af6f38f5019666ef1f72d4b..f25590227755246597c673a51a4f47a6ab1d1491 100644 (file)
--- a/tos/chips/msp430/msp430hardware.h
+++ b/tos/chips/msp430/msp430hardware.h
@@ -211,11 +211,13 @@ __nesc_atomic_t __nesc_atomic_start(void) @spontaneous()
 {
   __nesc_atomic_t result = ((READ_SR & SR_GIE) != 0);
   __nesc_disable_interrupt();
+  asm volatile("" : : : "memory"); /* ensure atomic section effect visibility */
   return result;
 }
 
 void __nesc_atomic_end(__nesc_atomic_t reenable_interrupts) @spontaneous()
 {
+  asm volatile("" : : : "memory"); /* ensure atomic section effect visibility */
   if( reenable_interrupts )
     __nesc_enable_interrupt();
 }

diff --git a/tos/chips/pxa27x/pxa27xhardware.h b/tos/chips/pxa27x/pxa27xhardware.h
index a2c36918d115e1bcade708beaf4ebbfe653dc351..04d056ba47a0176b7df863958ef07d378e8ec397 100644 (file)
--- a/tos/chips/pxa27x/pxa27xhardware.h
+++ b/tos/chips/pxa27x/pxa27xhardware.h
@@ -104,6 +104,7 @@ inline __nesc_atomic_t __nesc_atomic_start(void) __attribute__((spontaneous))
                : "=r" (result) , "=r" (temp)
                : "0" (result) , "1" (temp) , "i" (ARM_CPSR_INT_MASK)
                );
+  asm volatile("" : : : "memory"); /* ensure atomic section effect visibility */
   return result;
 }
 
@@ -111,6 +112,7 @@ inline void __nesc_atomic_end(__nesc_atomic_t oldState) __attribute__((spontaneo
 {
   uint32_t  statusReg = 0;
   //make sure that we only mess with the INT bit
+  asm volatile("" : : : "memory"); /* ensure atomic section effect visibility */
   oldState &= ARM_CPSR_INT_MASK;
   asm volatile (
                "mrs %0,CPSR\n\t"