*
* TODO: Implement error checking via UCxxSTAT
*
+ * NOTE: Define NO_REN_ON_SPI to disable PxREN bits when SPI is acquired.
+ *
* @author R. Steve McKown <rsmckown@gmail.com>
*/
BLOCKSIZE_DEFAULT = 64,
/* Bit positions in m_pins */
- PINS_STE = 1,
+ PINS_STE = 0,
PINS_SOMI,
PINS_SIMO,
PINS_CLK,
+#ifdef NO_REN_ON_SPI
+ PINS_RENADDR, /* This gets added to store the PxREN bit */
+#endif
};
uint8_t m_pins;
/* Configure pins for SPI, saving prior pin states */
m_pins = 0;
+#ifdef NO_REN_ON_SPI
+ /* - First save off and disable PxREN bits */
+ if (is4pin() && call STE.isRen()) {
+ m_pins |= (1 << (PINS_STE + PINS_RENADDR));
+ call STE.disableRen();
+ }
+ if (call SOMI.isRen()) {
+ m_pins |= (1 << (PINS_SOMI + PINS_RENADDR));
+ call SOMI.disableRen();
+ }
+ if (call SIMO.isRen()) {
+ m_pins |= (1 << (PINS_SIMO + PINS_RENADDR));
+ call SIMO.disableRen();
+ }
+ if (call CLK.isRen()) {
+ m_pins |= (1 << (PINS_CLK + PINS_RENADDR));
+ call CLK.disableRen();
+ }
+#endif
+ /* - Then save off IOFunc state and enable ModuleFunc */
if (is4pin() && call STE.isIOFunc()) {
m_pins |= (1 << PINS_STE);
call STE.selectModuleFunc();
call Registers.clrIfgRx();
/* Restore pins to their pre-configure state */
+ /* - First restore IOFunc states */
if (is4pin() && (m_pins & (1 << PINS_STE)))
call STE.selectIOFunc();
if (m_pins & (1 << PINS_SIMO))
call SOMI.selectIOFunc();
if (m_pins & (1 << PINS_CLK))
call CLK.selectIOFunc();
+ /* - Then restore PxREN bits */
+#ifdef NO_REN_ON_SPI
+ if (is4pin() && (m_pins & (1 << (PINS_STE + PINS_RENADDR))))
+ call STE.enableRen();
+ if (m_pins & (1 << (PINS_SIMO + PINS_RENADDR)))
+ call SIMO.enableRen();
+ if (m_pins & (1 << (PINS_SOMI + PINS_RENADDR)))
+ call SOMI.enableRen();
+ if (m_pins & (1 << (PINS_CLK + PINS_RENADDR)))
+ call CLK.enableRen();
+#endif
}
}
tmp = call Registers.getRxbuf();
if (m_rxBuf)
m_rxBuf[m_pos - 1] = call Registers.getRxbuf();
+ while (!call Registers.getIfgTx() && !call Registers.getCtl1(UCSWRST));
call Registers.setTxbuf(m_txBuf ? m_txBuf[m_pos] : 0);
}
}