--- /dev/null
+#if !defined(__MSP430_HEADERS_COMPB_H__)
+#define __MSP430_HEADERS_COMPB_H__
+
+/* compb.h
+ *
+ * mspgcc project: MSP430 device headers
+ * Comparator B
+ *
+ * Based on cc430x613x.h version 1.5 by Texas Instruments
+ *
+ * Peter A. Bigot <pab@peoplepowerco.com>
+ *
+ */
+
+/* Switches:
+__MSP430_HAS_COMPB__ -- defined to indicate availability of module
+__MSP430_COMPB_BASE__ - base address of COMPB module
+*/
+
+#if defined(__MSP430_COMPB_BASE__)
+
+#define CBCTL0_ __MSP430_COMPB_BASE__ + 0x00 /* Comparator B Control Register 0 */
+sfrw(CBCTL0, CBCTL0_);
+#define CBCTL0_L_ __MSP430_COMPB_BASE__ + 0x00
+sfrb(CBCTL0_L, CBCTL0_L_);
+#define CBCTL0_H_ __MSP430_COMPB_BASE__ + 0x01
+sfrb(CBCTL0_H, CBCTL0_H_);
+#define CBCTL1_ __MSP430_COMPB_BASE__ + 0x02 /* Comparator B Control Register 1 */
+sfrw(CBCTL1, CBCTL1_);
+#define CBCTL1_L_ __MSP430_COMPB_BASE__ + 0x02
+sfrb(CBCTL1_L, CBCTL1_L_);
+#define CBCTL1_H_ __MSP430_COMPB_BASE__ + 0x03
+sfrb(CBCTL1_H, CBCTL1_H_);
+#define CBCTL2_ __MSP430_COMPB_BASE__ + 0x04 /* Comparator B Control Register 2 */
+sfrw(CBCTL2, CBCTL2_);
+#define CBCTL2_L_ __MSP430_COMPB_BASE__ + 0x04
+sfrb(CBCTL2_L, CBCTL2_L_);
+#define CBCTL2_H_ __MSP430_COMPB_BASE__ + 0x05
+sfrb(CBCTL2_H, CBCTL2_H_);
+#define CBCTL3_ __MSP430_COMPB_BASE__ + 0x06 /* Comparator B Control Register 3 */
+sfrw(CBCTL3, CBCTL3_);
+#define CBCTL3_L_ __MSP430_COMPB_BASE__ + 0x06
+sfrb(CBCTL3_L, CBCTL3_L_);
+#define CBCTL3_H_ __MSP430_COMPB_BASE__ + 0x07
+sfrb(CBCTL3_H, CBCTL3_H_);
+#define CBINT_ __MSP430_COMPB_BASE__ + 0x0c /* Comparator B Interrupt Register */
+sfrw(CBINT, CBINT_);
+#define CBINT_L_ __MSP430_COMPB_BASE__ + 0x0c
+sfrb(CBINT_L, CBINT_L_);
+#define CBINT_H_ __MSP430_COMPB_BASE__ + 0x0d
+sfrb(CBINT_H, CBINT_H_);
+#define CBIV_ __MSP430_COMPB_BASE__ + 0x0e /* Comparator B Interrupt Vector Word */
+sfrw(CBIV, CBIV_);
+#define CBIV_L_ __MSP430_COMPB_BASE__ + 0x0e
+sfrb(CBIV_L, CBIV_L_);
+#define CBIV_H_ __MSP430_COMPB_BASE__ + 0x0f
+sfrb(CBIV_H, CBIV_H_);
+
+/* CBCTL0 Control Bits */
+#define CBIPSEL0 (0x0001) /* Comp. B Pos. Channel Input Select 0 */
+#define CBIPSEL1 (0x0002) /* Comp. B Pos. Channel Input Select 1 */
+#define CBIPSEL2 (0x0004) /* Comp. B Pos. Channel Input Select 2 */
+#define CBIPSEL3 (0x0008) /* Comp. B Pos. Channel Input Select 3 */
+//#define RESERVED (0x0010) /* Comp. B */
+//#define RESERVED (0x0020) /* Comp. B */
+//#define RESERVED (0x0040) /* Comp. B */
+#define CBIPEN (0x0080) /* Comp. B Pos. Channel Input Enalbe */
+#define CBIMSEL0 (0x0100) /* Comp. B Neg. Channel Input Select 0 */
+#define CBIMSEL1 (0x0200) /* Comp. B Neg. Channel Input Select 1 */
+#define CBIMSEL2 (0x0400) /* Comp. B Neg. Channel Input Select 2 */
+#define CBIMSEL3 (0x0800) /* Comp. B Neg. Channel Input Select 3 */
+//#define RESERVED (0x1000) /* Comp. B */
+//#define RESERVED (0x2000) /* Comp. B */
+//#define RESERVED (0x4000) /* Comp. B */
+#define CBIMEN (0x8000) /* Comp. B Neg. Channel Input Enalbe */
+
+/* CBCTL0 Control Bits */
+#define CBIPSEL0_L (0x0001) /* Comp. B Pos. Channel Input Select 0 */
+#define CBIPSEL1_L (0x0002) /* Comp. B Pos. Channel Input Select 1 */
+#define CBIPSEL2_L (0x0004) /* Comp. B Pos. Channel Input Select 2 */
+#define CBIPSEL3_L (0x0008) /* Comp. B Pos. Channel Input Select 3 */
+//#define RESERVED (0x0010) /* Comp. B */
+//#define RESERVED (0x0020) /* Comp. B */
+//#define RESERVED (0x0040) /* Comp. B */
+#define CBIPEN_L (0x0080) /* Comp. B Pos. Channel Input Enalbe */
+//#define RESERVED (0x1000) /* Comp. B */
+//#define RESERVED (0x2000) /* Comp. B */
+//#define RESERVED (0x4000) /* Comp. B */
+
+/* CBCTL0 Control Bits */
+//#define RESERVED (0x0010) /* Comp. B */
+//#define RESERVED (0x0020) /* Comp. B */
+//#define RESERVED (0x0040) /* Comp. B */
+#define CBIMSEL0_H (0x0001) /* Comp. B Neg. Channel Input Select 0 */
+#define CBIMSEL1_H (0x0002) /* Comp. B Neg. Channel Input Select 1 */
+#define CBIMSEL2_H (0x0004) /* Comp. B Neg. Channel Input Select 2 */
+#define CBIMSEL3_H (0x0008) /* Comp. B Neg. Channel Input Select 3 */
+//#define RESERVED (0x1000) /* Comp. B */
+//#define RESERVED (0x2000) /* Comp. B */
+//#define RESERVED (0x4000) /* Comp. B */
+#define CBIMEN_H (0x0080) /* Comp. B Neg. Channel Input Enalbe */
+
+#define CBIPSEL_0 (0x0000) /* Comp. B V+ terminal Input Select: Channel 0 */
+#define CBIPSEL_1 (0x0001) /* Comp. B V+ terminal Input Select: Channel 1 */
+#define CBIPSEL_2 (0x0002) /* Comp. B V+ terminal Input Select: Channel 2 */
+#define CBIPSEL_3 (0x0003) /* Comp. B V+ terminal Input Select: Channel 3 */
+#define CBIPSEL_4 (0x0004) /* Comp. B V+ terminal Input Select: Channel 4 */
+#define CBIPSEL_5 (0x0005) /* Comp. B V+ terminal Input Select: Channel 5 */
+#define CBIPSEL_6 (0x0006) /* Comp. B V+ terminal Input Select: Channel 6 */
+#define CBIPSEL_7 (0x0007) /* Comp. B V+ terminal Input Select: Channel 7 */
+#define CBIPSEL_8 (0x0008) /* Comp. B V+ terminal Input Select: Channel 8 */
+#define CBIPSEL_9 (0x0009) /* Comp. B V+ terminal Input Select: Channel 9 */
+#define CBIPSEL_10 (0x000A) /* Comp. B V+ terminal Input Select: Channel 10 */
+#define CBIPSEL_11 (0x000B) /* Comp. B V+ terminal Input Select: Channel 11 */
+#define CBIPSEL_12 (0x000C) /* Comp. B V+ terminal Input Select: Channel 12 */
+#define CBIPSEL_13 (0x000D) /* Comp. B V+ terminal Input Select: Channel 13 */
+#define CBIPSEL_14 (0x000E) /* Comp. B V+ terminal Input Select: Channel 14 */
+#define CBIPSEL_15 (0x000F) /* Comp. B V+ terminal Input Select: Channel 15 */
+
+#define CBIMSEL_0 (0x0000) /* Comp. B V- Terminal Input Select: Channel 0 */
+#define CBIMSEL_1 (0x0100) /* Comp. B V- Terminal Input Select: Channel 1 */
+#define CBIMSEL_2 (0x0200) /* Comp. B V- Terminal Input Select: Channel 2 */
+#define CBIMSEL_3 (0x0300) /* Comp. B V- Terminal Input Select: Channel 3 */
+#define CBIMSEL_4 (0x0400) /* Comp. B V- Terminal Input Select: Channel 4 */
+#define CBIMSEL_5 (0x0500) /* Comp. B V- Terminal Input Select: Channel 5 */
+#define CBIMSEL_6 (0x0600) /* Comp. B V- Terminal Input Select: Channel 6 */
+#define CBIMSEL_7 (0x0700) /* Comp. B V- Terminal Input Select: Channel 7 */
+#define CBIMSEL_8 (0x0800) /* Comp. B V- terminal Input Select: Channel 8 */
+#define CBIMSEL_9 (0x0900) /* Comp. B V- terminal Input Select: Channel 9 */
+#define CBIMSEL_10 (0x0A00) /* Comp. B V- terminal Input Select: Channel 10 */
+#define CBIMSEL_11 (0x0B00) /* Comp. B V- terminal Input Select: Channel 11 */
+#define CBIMSEL_12 (0x0C00) /* Comp. B V- terminal Input Select: Channel 12 */
+#define CBIMSEL_13 (0x0D00) /* Comp. B V- terminal Input Select: Channel 13 */
+#define CBIMSEL_14 (0x0E00) /* Comp. B V- terminal Input Select: Channel 14 */
+#define CBIMSEL_15 (0x0F00) /* Comp. B V- terminal Input Select: Channel 15 */
+
+/* CBCTL1 Control Bits */
+#define CBOUT (0x0001) /* Comp. B Output */
+#define CBOUTPOL (0x0002) /* Comp. B Output Polarity */
+#define CBF (0x0004) /* Comp. B Enable Output Filter */
+#define CBIES (0x0008) /* Comp. B Interrupt Edge Select */
+#define CBSHORT (0x0010) /* Comp. B Input Short */
+#define CBEX (0x0020) /* Comp. B Exchange Inputs */
+#define CBFDLY0 (0x0040) /* Comp. B Filter delay Bit 0 */
+#define CBFDLY1 (0x0080) /* Comp. B Filter delay Bit 1 */
+#define CBPWRMD0 (0x0100) /* Comp. B Power Mode Bit 0 */
+#define CBPWRMD1 (0x0200) /* Comp. B Power Mode Bit 1 */
+#define CBON (0x0400) /* Comp. B enable */
+#define CBMRVL (0x0800) /* Comp. B CBMRV Level */
+#define CBMRVS (0x1000) /* Comp. B Output selects between VREF0 or VREF1*/
+//#define RESERVED (0x2000) /* Comp. B */
+//#define RESERVED (0x4000) /* Comp. B */
+//#define RESERVED (0x8000) /* Comp. B */
+
+/* CBCTL1 Control Bits */
+#define CBOUT_L (0x0001) /* Comp. B Output */
+#define CBOUTPOL_L (0x0002) /* Comp. B Output Polarity */
+#define CBF_L (0x0004) /* Comp. B Enable Output Filter */
+#define CBIES_L (0x0008) /* Comp. B Interrupt Edge Select */
+#define CBSHORT_L (0x0010) /* Comp. B Input Short */
+#define CBEX_L (0x0020) /* Comp. B Exchange Inputs */
+#define CBFDLY0_L (0x0040) /* Comp. B Filter delay Bit 0 */
+#define CBFDLY1_L (0x0080) /* Comp. B Filter delay Bit 1 */
+//#define RESERVED (0x2000) /* Comp. B */
+//#define RESERVED (0x4000) /* Comp. B */
+//#define RESERVED (0x8000) /* Comp. B */
+
+/* CBCTL1 Control Bits */
+#define CBPWRMD0_H (0x0001) /* Comp. B Power Mode Bit 0 */
+#define CBPWRMD1_H (0x0002) /* Comp. B Power Mode Bit 1 */
+#define CBON_H (0x0004) /* Comp. B enable */
+#define CBMRVL_H (0x0008) /* Comp. B CBMRV Level */
+#define CBMRVS_H (0x0010) /* Comp. B Output selects between VREF0 or VREF1*/
+//#define RESERVED (0x2000) /* Comp. B */
+//#define RESERVED (0x4000) /* Comp. B */
+//#define RESERVED (0x8000) /* Comp. B */
+
+#define CBFDLY_0 (0x0000) /* Comp. B Filter delay 0 : 450ns */
+#define CBFDLY_1 (0x0040) /* Comp. B Filter delay 1 : 900ns */
+#define CBFDLY_2 (0x0080) /* Comp. B Filter delay 2 : 1800ns */
+#define CBFDLY_3 (0x00C0) /* Comp. B Filter delay 3 : 3600ns */
+
+#define CBPWRMD_0 (0x0000) /* Comp. B Power Mode 0 : High speed */
+#define CBPWRMD_1 (0x0100) /* Comp. B Power Mode 1 : Normal */
+#define CBPWRMD_2 (0x0200) /* Comp. B Power Mode 2 : Ultra-Low*/
+#define CBPWRMD_3 (0x0300) /* Comp. B Power Mode 3 : Reserved */
+
+/* CBCTL2 Control Bits */
+#define CBREF00 (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */
+#define CBREF01 (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */
+#define CBREF02 (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */
+#define CBREF03 (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */
+#define CBREF04 (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */
+#define CBRSEL (0x0020) /* Comp. B Reference select */
+#define CBRS0 (0x0040) /* Comp. B Reference Source Bit : 0 */
+#define CBRS1 (0x0080) /* Comp. B Reference Source Bit : 1 */
+#define CBREF10 (0x0100) /* Comp. B Reference 1 Resistor Select Bit : 0 */
+#define CBREF11 (0x0200) /* Comp. B Reference 1 Resistor Select Bit : 1 */
+#define CBREF12 (0x0400) /* Comp. B Reference 1 Resistor Select Bit : 2 */
+#define CBREF13 (0x0800) /* Comp. B Reference 1 Resistor Select Bit : 3 */
+#define CBREF14 (0x1000) /* Comp. B Reference 1 Resistor Select Bit : 4 */
+#define CBREFL0 (0x2000) /* Comp. B Reference voltage level Bit : 0 */
+#define CBREFL1 (0x4000) /* Comp. B Reference voltage level Bit : 1 */
+#define CBREFACC (0x8000) /* Comp. B Reference Accuracy */
+
+/* CBCTL2 Control Bits */
+#define CBREF00_L (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */
+#define CBREF01_L (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */
+#define CBREF02_L (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */
+#define CBREF03_L (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */
+#define CBREF04_L (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */
+#define CBRSEL_L (0x0020) /* Comp. B Reference select */
+#define CBRS0_L (0x0040) /* Comp. B Reference Source Bit : 0 */
+#define CBRS1_L (0x0080) /* Comp. B Reference Source Bit : 1 */
+
+/* CBCTL2 Control Bits */
+#define CBREF10_H (0x0001) /* Comp. B Reference 1 Resistor Select Bit : 0 */
+#define CBREF11_H (0x0002) /* Comp. B Reference 1 Resistor Select Bit : 1 */
+#define CBREF12_H (0x0004) /* Comp. B Reference 1 Resistor Select Bit : 2 */
+#define CBREF13_H (0x0008) /* Comp. B Reference 1 Resistor Select Bit : 3 */
+#define CBREF14_H (0x0010) /* Comp. B Reference 1 Resistor Select Bit : 4 */
+#define CBREFL0_H (0x0020) /* Comp. B Reference voltage level Bit : 0 */
+#define CBREFL1_H (0x0040) /* Comp. B Reference voltage level Bit : 1 */
+#define CBREFACC_H (0x0080) /* Comp. B Reference Accuracy */
+
+#define CBREF0_0 (0x0000) /* Comp. B Int. Ref.0 Select 0 : 1/32 */
+#define CBREF0_1 (0x0001) /* Comp. B Int. Ref.0 Select 1 : 2/32 */
+#define CBREF0_2 (0x0002) /* Comp. B Int. Ref.0 Select 2 : 3/32 */
+#define CBREF0_3 (0x0003) /* Comp. B Int. Ref.0 Select 3 : 4/32 */
+#define CBREF0_4 (0x0004) /* Comp. B Int. Ref.0 Select 4 : 5/32 */
+#define CBREF0_5 (0x0005) /* Comp. B Int. Ref.0 Select 5 : 6/32 */
+#define CBREF0_6 (0x0006) /* Comp. B Int. Ref.0 Select 6 : 7/32 */
+#define CBREF0_7 (0x0007) /* Comp. B Int. Ref.0 Select 7 : 8/32 */
+#define CBREF0_8 (0x0008) /* Comp. B Int. Ref.0 Select 0 : 9/32 */
+#define CBREF0_9 (0x0009) /* Comp. B Int. Ref.0 Select 1 : 10/32 */
+#define CBREF0_10 (0x000A) /* Comp. B Int. Ref.0 Select 2 : 11/32 */
+#define CBREF0_11 (0x000B) /* Comp. B Int. Ref.0 Select 3 : 12/32 */
+#define CBREF0_12 (0x000C) /* Comp. B Int. Ref.0 Select 4 : 13/32 */
+#define CBREF0_13 (0x000D) /* Comp. B Int. Ref.0 Select 5 : 14/32 */
+#define CBREF0_14 (0x000E) /* Comp. B Int. Ref.0 Select 6 : 15/32 */
+#define CBREF0_15 (0x000F) /* Comp. B Int. Ref.0 Select 7 : 16/32 */
+#define CBREF0_16 (0x0010) /* Comp. B Int. Ref.0 Select 0 : 17/32 */
+#define CBREF0_17 (0x0011) /* Comp. B Int. Ref.0 Select 1 : 18/32 */
+#define CBREF0_18 (0x0012) /* Comp. B Int. Ref.0 Select 2 : 19/32 */
+#define CBREF0_19 (0x0013) /* Comp. B Int. Ref.0 Select 3 : 20/32 */
+#define CBREF0_20 (0x0014) /* Comp. B Int. Ref.0 Select 4 : 21/32 */
+#define CBREF0_21 (0x0015) /* Comp. B Int. Ref.0 Select 5 : 22/32 */
+#define CBREF0_22 (0x0016) /* Comp. B Int. Ref.0 Select 6 : 23/32 */
+#define CBREF0_23 (0x0017) /* Comp. B Int. Ref.0 Select 7 : 24/32 */
+#define CBREF0_24 (0x0018) /* Comp. B Int. Ref.0 Select 0 : 25/32 */
+#define CBREF0_25 (0x0019) /* Comp. B Int. Ref.0 Select 1 : 26/32 */
+#define CBREF0_26 (0x001A) /* Comp. B Int. Ref.0 Select 2 : 27/32 */
+#define CBREF0_27 (0x001B) /* Comp. B Int. Ref.0 Select 3 : 28/32 */
+#define CBREF0_28 (0x001C) /* Comp. B Int. Ref.0 Select 4 : 29/32 */
+#define CBREF0_29 (0x001D) /* Comp. B Int. Ref.0 Select 5 : 30/32 */
+#define CBREF0_30 (0x001E) /* Comp. B Int. Ref.0 Select 6 : 31/32 */
+#define CBREF0_31 (0x001F) /* Comp. B Int. Ref.0 Select 7 : 32/32 */
+
+#define CBRS_0 (0x0000) /* Comp. B Reference Source 0 : Off */
+#define CBRS_1 (0x0040) /* Comp. B Reference Source 1 : Vcc */
+#define CBRS_2 (0x0080) /* Comp. B Reference Source 2 : Shared Ref. */
+#define CBRS_3 (0x00C0) /* Comp. B Reference Source 3 : Shared Ref. / Off */
+
+#define CBREF1_0 (0x0000) /* Comp. B Int. Ref.1 Select 0 : 1/32 */
+#define CBREF1_1 (0x0100) /* Comp. B Int. Ref.1 Select 1 : 2/32 */
+#define CBREF1_2 (0x0200) /* Comp. B Int. Ref.1 Select 2 : 3/32 */
+#define CBREF1_3 (0x0300) /* Comp. B Int. Ref.1 Select 3 : 4/32 */
+#define CBREF1_4 (0x0400) /* Comp. B Int. Ref.1 Select 4 : 5/32 */
+#define CBREF1_5 (0x0500) /* Comp. B Int. Ref.1 Select 5 : 6/32 */
+#define CBREF1_6 (0x0600) /* Comp. B Int. Ref.1 Select 6 : 7/32 */
+#define CBREF1_7 (0x0700) /* Comp. B Int. Ref.1 Select 7 : 8/32 */
+#define CBREF1_8 (0x0800) /* Comp. B Int. Ref.1 Select 0 : 9/32 */
+#define CBREF1_9 (0x0900) /* Comp. B Int. Ref.1 Select 1 : 10/32 */
+#define CBREF1_10 (0x0A00) /* Comp. B Int. Ref.1 Select 2 : 11/32 */
+#define CBREF1_11 (0x0B00) /* Comp. B Int. Ref.1 Select 3 : 12/32 */
+#define CBREF1_12 (0x0C00) /* Comp. B Int. Ref.1 Select 4 : 13/32 */
+#define CBREF1_13 (0x0D00) /* Comp. B Int. Ref.1 Select 5 : 14/32 */
+#define CBREF1_14 (0x0E00) /* Comp. B Int. Ref.1 Select 6 : 15/32 */
+#define CBREF1_15 (0x0F00) /* Comp. B Int. Ref.1 Select 7 : 16/32 */
+#define CBREF1_16 (0x1000) /* Comp. B Int. Ref.1 Select 0 : 17/32 */
+#define CBREF1_17 (0x1100) /* Comp. B Int. Ref.1 Select 1 : 18/32 */
+#define CBREF1_18 (0x1200) /* Comp. B Int. Ref.1 Select 2 : 19/32 */
+#define CBREF1_19 (0x1300) /* Comp. B Int. Ref.1 Select 3 : 20/32 */
+#define CBREF1_20 (0x1400) /* Comp. B Int. Ref.1 Select 4 : 21/32 */
+#define CBREF1_21 (0x1500) /* Comp. B Int. Ref.1 Select 5 : 22/32 */
+#define CBREF1_22 (0x1600) /* Comp. B Int. Ref.1 Select 6 : 23/32 */
+#define CBREF1_23 (0x1700) /* Comp. B Int. Ref.1 Select 7 : 24/32 */
+#define CBREF1_24 (0x1800) /* Comp. B Int. Ref.1 Select 0 : 25/32 */
+#define CBREF1_25 (0x1900) /* Comp. B Int. Ref.1 Select 1 : 26/32 */
+#define CBREF1_26 (0x1A00) /* Comp. B Int. Ref.1 Select 2 : 27/32 */
+#define CBREF1_27 (0x1B00) /* Comp. B Int. Ref.1 Select 3 : 28/32 */
+#define CBREF1_28 (0x1C00) /* Comp. B Int. Ref.1 Select 4 : 29/32 */
+#define CBREF1_29 (0x1D00) /* Comp. B Int. Ref.1 Select 5 : 30/32 */
+#define CBREF1_30 (0x1E00) /* Comp. B Int. Ref.1 Select 6 : 31/32 */
+#define CBREF1_31 (0x1F00) /* Comp. B Int. Ref.1 Select 7 : 32/32 */
+
+#define CBREFL_0 (0x0000) /* Comp. B Reference voltage level 0 : None */
+#define CBREFL_1 (0x2000) /* Comp. B Reference voltage level 1 : 1.5V */
+#define CBREFL_2 (0x4000) /* Comp. B Reference voltage level 2 : 2.0V */
+#define CBREFL_3 (0x6000) /* Comp. B Reference voltage level 3 : 2.5V */
+
+#define CBPD0 (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */
+#define CBPD1 (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */
+#define CBPD2 (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */
+#define CBPD3 (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */
+#define CBPD4 (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */
+#define CBPD5 (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */
+#define CBPD6 (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */
+#define CBPD7 (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */
+#define CBPD8 (0x0100) /* Comp. B Disable Input Buffer of Port Register .8 */
+#define CBPD9 (0x0200) /* Comp. B Disable Input Buffer of Port Register .9 */
+#define CBPD10 (0x0400) /* Comp. B Disable Input Buffer of Port Register .10 */
+#define CBPD11 (0x0800) /* Comp. B Disable Input Buffer of Port Register .11 */
+#define CBPD12 (0x1000) /* Comp. B Disable Input Buffer of Port Register .12 */
+#define CBPD13 (0x2000) /* Comp. B Disable Input Buffer of Port Register .13 */
+#define CBPD14 (0x4000) /* Comp. B Disable Input Buffer of Port Register .14 */
+#define CBPD15 (0x8000) /* Comp. B Disable Input Buffer of Port Register .15 */
+
+#define CBPD0_L (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */
+#define CBPD1_L (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */
+#define CBPD2_L (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */
+#define CBPD3_L (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */
+#define CBPD4_L (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */
+#define CBPD5_L (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */
+#define CBPD6_L (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */
+#define CBPD7_L (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */
+
+#define CBPD8_H (0x0001) /* Comp. B Disable Input Buffer of Port Register .8 */
+#define CBPD9_H (0x0002) /* Comp. B Disable Input Buffer of Port Register .9 */
+#define CBPD10_H (0x0004) /* Comp. B Disable Input Buffer of Port Register .10 */
+#define CBPD11_H (0x0008) /* Comp. B Disable Input Buffer of Port Register .11 */
+#define CBPD12_H (0x0010) /* Comp. B Disable Input Buffer of Port Register .12 */
+#define CBPD13_H (0x0020) /* Comp. B Disable Input Buffer of Port Register .13 */
+#define CBPD14_H (0x0040) /* Comp. B Disable Input Buffer of Port Register .14 */
+#define CBPD15_H (0x0080) /* Comp. B Disable Input Buffer of Port Register .15 */
+
+/* CBINT Control Bits */
+#define CBIFG (0x0001) /* Comp. B Interrupt Flag */
+#define CBIIFG (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */
+//#define RESERVED (0x0004) /* Comp. B */
+//#define RESERVED (0x0008) /* Comp. B */
+//#define RESERVED (0x0010) /* Comp. B */
+//#define RESERVED (0x0020) /* Comp. B */
+//#define RESERVED (0x0040) /* Comp. B */
+//#define RESERVED (0x0080) /* Comp. B */
+#define CBIE (0x0100) /* Comp. B Interrupt Enable */
+#define CBIIE (0x0200) /* Comp. B Interrupt Enable Inverted Polarity */
+//#define RESERVED (0x0400) /* Comp. B */
+//#define RESERVED (0x0800) /* Comp. B */
+//#define RESERVED (0x1000) /* Comp. B */
+//#define RESERVED (0x2000) /* Comp. B */
+//#define RESERVED (0x4000) /* Comp. B */
+//#define RESERVED (0x8000) /* Comp. B */
+
+/* CBINT Control Bits */
+#define CBIFG_L (0x0001) /* Comp. B Interrupt Flag */
+#define CBIIFG_L (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */
+//#define RESERVED (0x0004) /* Comp. B */
+//#define RESERVED (0x0008) /* Comp. B */
+//#define RESERVED (0x0010) /* Comp. B */
+//#define RESERVED (0x0020) /* Comp. B */
+//#define RESERVED (0x0040) /* Comp. B */
+//#define RESERVED (0x0080) /* Comp. B */
+//#define RESERVED (0x0400) /* Comp. B */
+//#define RESERVED (0x0800) /* Comp. B */
+//#define RESERVED (0x1000) /* Comp. B */
+//#define RESERVED (0x2000) /* Comp. B */
+//#define RESERVED (0x4000) /* Comp. B */
+//#define RESERVED (0x8000) /* Comp. B */
+
+/* CBINT Control Bits */
+//#define RESERVED (0x0004) /* Comp. B */
+//#define RESERVED (0x0008) /* Comp. B */
+//#define RESERVED (0x0010) /* Comp. B */
+//#define RESERVED (0x0020) /* Comp. B */
+//#define RESERVED (0x0040) /* Comp. B */
+//#define RESERVED (0x0080) /* Comp. B */
+#define CBIE_H (0x0001) /* Comp. B Interrupt Enable */
+#define CBIIE_H (0x0002) /* Comp. B Interrupt Enable Inverted Polarity */
+//#define RESERVED (0x0400) /* Comp. B */
+//#define RESERVED (0x0800) /* Comp. B */
+//#define RESERVED (0x1000) /* Comp. B */
+//#define RESERVED (0x2000) /* Comp. B */
+//#define RESERVED (0x4000) /* Comp. B */
+//#define RESERVED (0x8000) /* Comp. B */
+
+/* CBIV Definitions */
+#define CBIV_NONE (0x0000) /* No Interrupt pending */
+#define CBIV_CBIFG (0x0002) /* CBIFG */
+#define CBIV_CBIIFG (0x0004) /* CBIIFG */
+
+#endif /* __MSP430_COMPB_BASE__ */
+
+#endif /* __MSP430_HEADERS_COMPB_H__ */
+
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