--- /dev/null
+# Ignore these files in a msp430-libc development area
+# NOTE: Only files that should be ignored in all TinyOS development areas
+# should be listed here. Files that are relevant to individual developers,
+# such as Emacs or vi backup files, should be listed in .git/info/exclude.
+#
+# Directories named build
+Build/
--- /dev/null
+#if !defined(__msp430_cc430)
+#define __msp430_cc430
+
+/* cc430_.h
+ *
+ * mspgcc project: MSP430 device headers
+ * CC430 family header
+ * Data from CC430 User's Guide (SLAU259) and the CC430F[56]1[23]x data sheet
+ *
+ * 2009-12-20 - Peter Bigot (pab@peoplepowerco.com)
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * This file supports all CC430 chips, but should not be included
+ * directly. Access it through one of the standard TI header names
+ * (cc430x513x.h, cc430x612x.h, ...)
+ */
+
+#include <iomacros.h>
+
+#define __MSP430_SFR_BASE__ 0x0100
+#define __MSP430_PMM_BASE__ 0x0120
+#define __MSP430_HAS_FLASH2__
+#define __MSP430_CRC16_BASE__ 0x0150
+// RAM Control: not supported
+#define __MSP430_WDT_A_BASE__ 0x0150 /* NB: Subtract 0x0C for compatibility with 1xx architecture */
+#define __MSP430_UCS_BASE__ 0x0160
+#define __MSP430_SYS_BASE__ 0x0180
+
+#define __MSP430_HAS_REF__
+#define __MSP430_REF_BASE__ 0x01b0
+
+#define __MSP430_PORT_MAPPING_BASE__ 0x01c0
+#define __MSP430_PORT1_MAPPING_BASE__ 0x01c8
+#define __MSP430_PORT2_MAPPING_BASE__ 0x01d0
+#define __MSP430_PORT3_MAPPING_BASE__ 0x01d8
+
+#define __MSP430_PORT1_BASE__ 0x0200
+#define __MSP430_HAS_PORT1_R__
+#define __MSP430_PORT2_BASE__ 0x0200
+#define __MSP430_HAS_PORT2_R__
+#define __MSP430_PORT3_BASE__ 0x0220
+#define __MSP430_HAS_PORT3_R__
+#if ! defined(__cc430x513x)
+#define __MSP430_PORT4_BASE__ 0x0220
+#define __MSP430_HAS_PORT4_R__
+#endif // ! __cc430x513x
+#define __MSP430_PORT5_BASE__ 0x0240
+#define __MSP430_PORTJ_BASE__ 0x0320
+
+#define __MSP430_HAS_T0A5__
+#define __MSP430_T0A_BASE__ 0x0340
+#define __MSP430_HAS_T1A3__
+#define __MSP430_T1A_BASE__ 0x0380
+
+#define __MSP430_HAS_RTC__
+#define __MSP430_RTC_BASE__ 0x04a0
+
+#define __MSP430_MPY32_BASE__ 0x04C0
+
+#define __MSP430_HAS_DMAX_3__
+#define __MSP430_DMA_BASE__ 0x0500
+
+#define __MSP430_HAS_USCI_A0__
+#define __MSP430_HAS_USCI_B0__
+#define __MSP430_USCI0_BASE__ 0x05c0
+
+#if defined(__CC430_6135__) \
+ || defined(__CC430_5137__) || defined(__CC430_6137__)
+#define __MSP430_HAS_ADC12_PLUS__
+#define __MSP430_ADC12_PLUS_BASE__ 0x0700
+#endif // CC430F513x and CC430F613x only
+
+#define __MSP430_HAS_COMPB__
+#define __MSP430_COMPB_BASE__ 0x08c0
+
+#define __MSP430_AES_BASE__ 0x09c0
+
+#if defined(__cc430x612x) || defined(__cc430x613x)
+#define __MSP430_HAS_LCD_B__
+#define __MSP430_LCD_B_BASE__ 0x0a00
+#endif // CC430F612x and CC430F613x only
+// Radio interface: not supported
+#define __MSP430_CC1101_BASE__ 0x0f00
+
+/* Interrupt vectors */
+#define AES_VECTOR 0x5a /* 0xFFDA AES */
+#define RTC_VECTOR 0x5c /* 0xFFDC RTC */
+#define LCD_B_VECTOR 0x5e /* 0xFFDE LCD B */
+#define PORT2_VECTOR 0x60 /* 0xFFE0 Port 2 */
+#define PORT1_VECTOR 0x62 /* 0xFFE2 Port 1 */
+#define TIMER1_A1_VECTOR 0x64 /* 0xFFE4 Timer1_A3 CC1-2, TA1 */
+#define TIMER1_A0_VECTOR 0x66 /* 0xFFE6 Timer1_A3 CC0 */
+#define DMA_VECTOR 0x68 /* 0xFFE8 DMA */
+#define CC1101_VECTOR 0x6a /* 0xFFEA CC1101 Radio Interface */
+#define TIMER0_A1_VECTOR 0x6c /* 0xFFEC Timer0_A5 CC1-4, TA */
+#define TIMER0_A0_VECTOR 0x6e /* 0xFFEE Timer0_A5 CC0 */
+#define ADC12_VECTOR 0x70 /* 0xFFF0 ADC */
+#define USCI_B0_VECTOR 0x72 /* 0xFFF2 USCI B0 Receive/Transmit */
+#define USCI_A0_VECTOR 0x74 /* 0xFFF4 USCI A0 Receive/Transmit */
+#define WDT_VECTOR 0x76 /* 0xFFF6 Watchdog Timer */
+#define COMP_B_VECTOR 0x78 /* 0xFFF8 Comparator B */
+#define UNMI_VECTOR 0x7a /* 0xFFFA User Non-maskable */
+#define SYSNMI_VECTOR 0x7c /* 0xFFFC System Non-maskable */
+#define RESET_VECTOR 0x7e /* 0xFFFE Reset [Highest Priority] */
+
+#include <msp430/common.h>
+#include <msp430/sfr.h>
+#include <msp430/pmm.h>
+#include <msp430/flash.h>
+#include <msp430/crc16.h>
+#include <msp430/wdt_a.h>
+#include <msp430/unified_clock_system.h>
+#include <msp430/sys.h>
+#include <msp430/ref.h>
+#include <msp430/pmcontrol.h>
+#include <msp430/gpio_5xxx.h>
+#include <msp430/timera.h>
+#include <msp430/rtc.h>
+#include <msp430/mpy32.h>
+#include <msp430/dmax.h>
+#include <msp430/usci_5xx.h>
+#include <msp430/adc12_plus.h>
+#include <msp430/compb.h>
+#include <msp430/aes.h>
+#include <msp430/lcd_b.h>
+#include <msp430/rf1a.h>
+
+
+/* SYSRSTIV Definitions. Not added to <msp430/sys.h> because the
+ * values are device-dependent. */
+#define SYSRSTIV_NONE (0x0000) /* No Interrupt pending */
+#define SYSRSTIV_BOR (0x0002) /* SYSRSTIV : BOR */
+#define SYSRSTIV_RSTNMI (0x0004) /* SYSRSTIV : RST/NMI */
+#define SYSRSTIV_DOBOR (0x0006) /* SYSRSTIV : Do BOR */
+#define SYSRSTIV_LPM5WU (0x0008) /* SYSRSTIV : Port LPM5 Wake Up */
+#define SYSRSTIV_SECYV (0x000A) /* SYSRSTIV : Security violation */
+#define SYSRSTIV_SVSL (0x000C) /* SYSRSTIV : SVSL */
+#define SYSRSTIV_SVSH (0x000E) /* SYSRSTIV : SVSH */
+#define SYSRSTIV_SVML_OVP (0x0010) /* SYSRSTIV : SVML_OVP */
+#define SYSRSTIV_SVMH_OVP (0x0012) /* SYSRSTIV : SVMH_OVP */
+#define SYSRSTIV_DOPOR (0x0014) /* SYSRSTIV : Do POR */
+#define SYSRSTIV_WDTTO (0x0016) /* SYSRSTIV : WDT Time out */
+#define SYSRSTIV_WDTKEY (0x0018) /* SYSRSTIV : WDTKEY violation */
+#define SYSRSTIV_KEYV (0x001A) /* SYSRSTIV : Flash Key violation */
+#define SYSRSTIV_PLLUL (0x001C) /* SYSRSTIV : PLL unlock */
+#define SYSRSTIV_PERF (0x001E) /* SYSRSTIV : peripheral/config area fetch */
+#define SYSRSTIV_PSSKEY (0x0020) /* SYSRSTIV : PSSKEY violation */
+
+/* Port mapping controller functions for chips */
+#define PM_NONE 0
+#define PM_CBOUT0 1
+#define PM_TA0CLK 1
+#define PM_CBOUT1 2
+#define PM_TA1CLK 2
+#define PM_ACLK 3
+#define PM_MCLK 4
+#define PM_SMCLK 5
+#define PM_RTCCLK 6
+#define PM_ADC12CLK 7 // added per data sheet, not in TI
+#define PM_MODCLK 7
+#define PM_DMAE0 7
+#define PM_SVMOUT 8
+#define PM_TA0CCR0A 9
+#define PM_TA0CCR1A 10
+#define PM_TA0CCR2A 11
+#define PM_TA0CCR3A 12
+#define PM_TA0CCR4A 13
+#define PM_TA1CCR0A 14
+#define PM_TA1CCR1A 15
+#define PM_TA1CCR2A 16
+#define PM_UCA0RXD 17
+#define PM_UCA0SOMI 17
+#define PM_UCA0TXD 18
+#define PM_UCA0SIMO 18
+#define PM_UCA0CLK 19
+#define PM_UCB0STE 19
+#define PM_UCB0SOMI 20
+#define PM_UCB0SCL 20
+#define PM_UCB0SIMO 21
+#define PM_UCB0SDA 21
+#define PM_UCB0CLK 22
+#define PM_UCA0STE 22
+#define PM_RFGDO0 23
+#define PM_RFGDO1 24
+#define PM_RFGDO2 25
+#define PM_ANALOG 31
+
+#endif /* __msp430_cc430 */
--- /dev/null
+#if !defined(__cc430x513x)
+#define __cc430x513x
+
+/* Separate for TI compatibility, but for maintainability everything's
+ * in one file. */
+#include <cc430_.h>
+
+#endif /* __cc430x513x */
--- /dev/null
+#if !defined(__cc430x612x)
+#define __cc430x612x
+
+/* Separate for TI compatibility, but for maintainability everything's
+ * in one file. */
+#include <cc430_.h>
+
+#endif /* __cc430x612x */
--- /dev/null
+#if !defined(__cc430x613x)
+#define __cc430x613x
+
+/* Separate for TI compatibility, but for maintainability everything's
+ * in one file. */
+#include <cc430_.h>
+
+#endif /* __cc430x613x */
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $Id: io.h,v 1.17 2008/05/15 00:54:32 cliechti Exp $
+ * $Id: io.h,v 1.19 2009/01/11 23:11:48 sb-sf Exp $
*/
#ifndef _IO_H_
#elif defined(__MSP430_2101__) || defined(__MSP430_2111__) || defined(__MSP430_2121__) || defined(__MSP430_2131__)
#include <msp430x21x1.h>
+#elif defined(__MSP430_2112__) || defined(__MSP430_2122__) || defined(__MSP430_2132__)
+#include <msp430x21x2.h>
+
#elif defined(__MSP430_2232__) || defined(__MSP430_2252__) || defined(__MSP430_2272__)
#include <msp430x22x2.h>
#elif defined(__MSP430_4250__) || defined(__MSP430_4260__) || defined(__MSP430_4270__)
#include <msp430x42x0.h>
-#elif defined(__MSP430_E423__) || defined(__MSP430_E425__) || defined(__MSP430_E427__)
+#elif defined(__MSP430_G4250__) || defined(__MSP430_G4260__) || defined(__MSP430_G4270__)
+#include <msp430xG42x0.h>
+
+#elif defined(__MSP430_E423__) || defined(__MSP430_E425__) || defined(__MSP430_E427__) \
+ || defined(__MSP430_E4232__) || defined(__MSP430_E4242__) || defined(__MSP430_E4252__) || defined(__MSP430_E4272__)
#include <msp430xE42x.h>
#elif defined(__MSP430_W423__) || defined(__MSP430_W425__) || defined(__MSP430_W427__)
#elif defined(__MSP430_G437__) || defined(__MSP430_G438__) || defined(__MSP430_G439__)
#include <msp430xG43x.h>
-#elif defined(__MSP430_435__) || defined(__MSP430_436__) || defined(__MSP430_437__)
+#elif defined(__MSP430_435__) || defined(__MSP430_436__) || defined(__MSP430_437__) \
+ || defined(__MSP430_4351__) || defined(__MSP430_4361__) || defined(__MSP430_4371__)
#include <msp430x43x.h>
#elif defined(__MSP430_447__) || defined(__MSP430_448__) || defined(__MSP430_449__)
#elif defined(__MSP430_G4616__) || defined(__MSP430_G4617__) || defined(__MSP430_G4618__) || defined(__MSP430_G4619__)
#include <msp430xG461x.h>
+#elif defined(__MSP430_4783__) || defined(__MSP430_4784__) || defined(__MSP430_4793__) || defined(__MSP430_4794__) \
+ || defined(__MSP430_47166__) || defined(__MSP430_47176__) || defined(__MSP430_47186__) || defined(__MSP430_47196__) \
+ || defined(__MSP430_47167__) || defined(__MSP430_47177__) || defined(__MSP430_47187__) || defined(__MSP430_47197__)
+#include <msp430x47xx.h>
+
+#elif defined(__MSP430_5418__) || defined(__MSP430_5419__) \
+ || defined(__MSP430_5435__) || defined(__MSP430_5436__) || defined(__MSP430_5437__) || defined(__MSP430_5438__)
+#include <msp430x54xx.h>
+
+#elif defined(__CC430_5137__)
+#include <cc430x513x.h>
+
+#elif defined(__CC430_6125__) || defined(__CC430_6126__) || defined(__CC430_6127__)
+#include <cc430x612x.h>
+
+#elif defined(__CC430_6135__) || defined(__CC430_6137__)
+#include <cc430x613x.h>
+
#else
#warning "Unknown arch! Please check"
#include <iomacros.h>
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $Id: iomacros.h,v 1.35 2008/05/26 20:27:51 cliechti Exp $
+ * $Id: iomacros.h,v 1.36 2008/10/09 15:00:13 sb-sf Exp $
*/
#if !defined(__IOMACROS_H_)
#define __IOMACROS_H_
-#if !defined(_GNU_ASSEMBLER_)
+#if !defined(__ASSEMBLER__)
#include <sys/inttypes.h>
#define __bis_SR_register(x) __asm__ __volatile__("bis %0, r2" : : "ir" ((uint16_t) x))
#define __bic_SR_register(x) __asm__ __volatile__("bic %0, r2" : : "ir" ((uint16_t) x))
-#if __GNUC_MINOR__ >= 4
+#if __GNUC__ >= 4
extern void __bis_sr_irq(int);
extern void __bic_sr_irq(int);
#define sfrw_(x,x_) \
extern "C" volatile unsigned int x asm(#x_)
-#if defined(__MSP430X__)
+#if defined(__MSP430X__) || defined(__MSP430X2__)
#define sfra_(x,x_) \
extern "C" volatile unsigned long int x asm(#x_)
#endif
#define sfrw_(x,x_) \
volatile unsigned int x asm(#x_)
-#if defined(__MSP430X__)
+#if defined(__MSP430X__) || defined(__MSP430X2__)
#define sfra_(x,x_) \
volatile unsigned long int x asm(#x_)
#endif
#define sfrw(x,x_) sfrw_(x,x_)
-#if defined(__MSP430X__)
+#if defined(__MSP430X__) ||defined(__MSP430X2__)
#define sfra(x,x_) sfra_(x,x_)
#endif
#define MARK_VOLATILE __asm__ __volatile__("; volatile")
-#endif /* not _GNU_ASSEMBLER_ */
+#endif /* not __ASSEMBLER__ */
/*
* Defines for assembler.
* Hope there is a better way to do this.
*/
-#if defined(_GNU_ASSEMBLER_)
+#if defined(__ASSEMBLER__)
#define sfrb(x,x_) x=x_
#define sfrw(x,x_) x=x_
-#if defined(__MSP430X__)
+#if defined(__MSP430X__) ||defined(__MSP430X2__)
#define sfra(x,x_) x=x_
#endif
* (c) 2002 by Steve Underwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: adc10.h,v 1.8 2008/05/22 16:01:19 cliechti Exp $
+ * $Id: adc10.h,v 1.9 2008/10/09 15:00:14 sb-sf Exp $
*/
/* Switches: none */
#define ADC10SA_ 0x01BC /* ADC10 Data Transfer Start Address */
sfrw(ADC10SA, ADC10SA_);
-#ifndef _GNU_ASSEMBLER_
+#ifndef __ASSEMBLER__
/* Structured declaration */
typedef struct {
volatile unsigned
* (c) 2002 by M. P. Ashton <data@ieee.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: adc12.h,v 1.10 2006/01/12 00:47:21 cliechti Exp $
+ * $Id: adc12.h,v 1.11 2008/10/09 15:00:14 sb-sf Exp $
*/
/* Switches: none */
#define ADC12IV_ 0x01A8 /* ADC12 Interrupt Vector Word */
sfrw(ADC12IV,ADC12IV_);
-#ifndef _GNU_ASSEMBLER_
+#ifndef __ASSEMBLER__
/* Structured declaration */
typedef struct {
volatile unsigned
#endif
#define ADC12MEM_ 0x0140 /* ADC12 Conversion Memory */
-#ifdef _GNU_ASSEMBLER_
+#ifdef __ASSEMBLER__
#define ADC12MEM ADC12MEM_ /* ADC12 Conversion Memory (for assembler) */
#else
#define ADC12MEM ((int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */
sfrw(ADC12MEM15,ADC12MEM15_);
#define ADC12MCTL_ 0x0080 /* ADC12 Memory Control */
-#ifdef _GNU_ASSEMBLER_
+#ifdef __ASSEMBLER__
#define ADC12MCTL ADC12MCTL_ /* ADC12 Memory Control (for assembler) */
#else
#define ADC12MCTL ((char*) ADC12MCTL_) /* ADC12 Memory Control (for C) */
--- /dev/null
+#if !defined(__MSP430_HEADERS_ADC12_PLUS_H__)
+#define __MSP430_HEADERS_ADC12_PLUS_H__
+
+/* adc12_plus.h
+ *
+ * mspgcc project: MSP430 device headers
+ * High-performance 12-bit analog-to-digital converter
+ *
+ * NB: The contents of this file are similar to those of
+ * <msp430/adc12.h>, but are derived directly from the TI headers.
+ * Consequently, the names of several constants have changed
+ * (generally, to add a prefix ADC12). Don't include both.
+ *
+ * Based on cc430x613x.h version 1.5 by Texas Instruments
+ *
+ * Peter A. Bigot <pab@peoplepowerco.com>
+ *
+ */
+
+/* Switches:
+__MSP430_HAS_ADC12_PLUS__ - definition to show module available
+__MSP430_ADC12_PLUS_BASE__ - base address of ADC_A module
+*/
+
+#if defined(__MSP430_ADC12_PLUS_BASE__)
+
+#define ADC12CTL0_ __MSP430_ADC12_PLUS_BASE__ + 0x00 /* ADC12+ Control 0 */
+sfrw(ADC12CTL0, ADC12CTL0_);
+#define ADC12CTL0_L_ __MSP430_ADC12_PLUS_BASE__ + 0x00
+sfrb(ADC12CTL0_L, ADC12CTL0_L_);
+#define ADC12CTL0_H_ __MSP430_ADC12_PLUS_BASE__ + 0x01
+sfrb(ADC12CTL0_H, ADC12CTL0_H_);
+#define ADC12CTL1_ __MSP430_ADC12_PLUS_BASE__ + 0x02 /* ADC12+ Control 1 */
+sfrw(ADC12CTL1, ADC12CTL1_);
+#define ADC12CTL1_L_ __MSP430_ADC12_PLUS_BASE__ + 0x02
+sfrb(ADC12CTL1_L, ADC12CTL1_L_);
+#define ADC12CTL1_H_ __MSP430_ADC12_PLUS_BASE__ + 0x03
+sfrb(ADC12CTL1_H, ADC12CTL1_H_);
+#define ADC12CTL2_ __MSP430_ADC12_PLUS_BASE__ + 0x04 /* ADC12+ Control 2 */
+sfrw(ADC12CTL2, ADC12CTL2_);
+#define ADC12CTL2_L_ __MSP430_ADC12_PLUS_BASE__ + 0x04
+sfrb(ADC12CTL2_L, ADC12CTL2_L_);
+#define ADC12CTL2_H_ __MSP430_ADC12_PLUS_BASE__ + 0x05
+sfrb(ADC12CTL2_H, ADC12CTL2_H_);
+#define ADC12IFG_ __MSP430_ADC12_PLUS_BASE__ + 0x0a /* ADC12+ Interrupt Flag */
+sfrw(ADC12IFG, ADC12IFG_);
+#define ADC12IFG_L_ __MSP430_ADC12_PLUS_BASE__ + 0x0a
+sfrb(ADC12IFG_L, ADC12IFG_L_);
+#define ADC12IFG_H_ __MSP430_ADC12_PLUS_BASE__ + 0x0b
+sfrb(ADC12IFG_H, ADC12IFG_H_);
+#define ADC12IE_ __MSP430_ADC12_PLUS_BASE__ + 0x0c /* ADC12+ Interrupt Enable */
+sfrw(ADC12IE, ADC12IE_);
+#define ADC12IE_L_ __MSP430_ADC12_PLUS_BASE__ + 0x0c
+sfrb(ADC12IE_L, ADC12IE_L_);
+#define ADC12IE_H_ __MSP430_ADC12_PLUS_BASE__ + 0x0d
+sfrb(ADC12IE_H, ADC12IE_H_);
+#define ADC12IV_ __MSP430_ADC12_PLUS_BASE__ + 0x0e /* ADC12+ Interrupt Vector Word */
+sfrw(ADC12IV, ADC12IV_);
+#define ADC12IV_L_ __MSP430_ADC12_PLUS_BASE__ + 0x0e
+sfrb(ADC12IV_L, ADC12IV_L_);
+#define ADC12IV_H_ __MSP430_ADC12_PLUS_BASE__ + 0x0f
+sfrb(ADC12IV_H, ADC12IV_H_);
+
+#define ADC12MEM0_ __MSP430_ADC12_PLUS_BASE__ + 0x20 /* ADC12 Conversion Memory 0 */
+sfrw(ADC12MEM0, ADC12MEM0_);
+#define ADC12MEM0_L_ __MSP430_ADC12_PLUS_BASE__ + 0x20
+sfrb(ADC12MEM0_L, ADC12MEM0_L_);
+#define ADC12MEM0_H_ __MSP430_ADC12_PLUS_BASE__ + 0x21
+sfrb(ADC12MEM0_H, ADC12MEM0_H_);
+#define ADC12MEM1_ __MSP430_ADC12_PLUS_BASE__ + 0x21 /* ADC12 Conversion Memory 1 */
+sfrw(ADC12MEM1, ADC12MEM1_);
+#define ADC12MEM1_L_ __MSP430_ADC12_PLUS_BASE__ + 0x21
+sfrb(ADC12MEM1_L, ADC12MEM1_L_);
+#define ADC12MEM1_H_ __MSP430_ADC12_PLUS_BASE__ + 0x22
+sfrb(ADC12MEM1_H, ADC12MEM1_H_);
+#define ADC12MEM2_ __MSP430_ADC12_PLUS_BASE__ + 0x22 /* ADC12 Conversion Memory 2 */
+sfrw(ADC12MEM2, ADC12MEM2_);
+#define ADC12MEM2_L_ __MSP430_ADC12_PLUS_BASE__ + 0x22
+sfrb(ADC12MEM2_L, ADC12MEM2_L_);
+#define ADC12MEM2_H_ __MSP430_ADC12_PLUS_BASE__ + 0x23
+sfrb(ADC12MEM2_H, ADC12MEM2_H_);
+#define ADC12MEM3_ __MSP430_ADC12_PLUS_BASE__ + 0x23 /* ADC12 Conversion Memory 3 */
+sfrw(ADC12MEM3, ADC12MEM3_);
+#define ADC12MEM3_L_ __MSP430_ADC12_PLUS_BASE__ + 0x23
+sfrb(ADC12MEM3_L, ADC12MEM3_L_);
+#define ADC12MEM3_H_ __MSP430_ADC12_PLUS_BASE__ + 0x24
+sfrb(ADC12MEM3_H, ADC12MEM3_H_);
+#define ADC12MEM4_ __MSP430_ADC12_PLUS_BASE__ + 0x24 /* ADC12 Conversion Memory 4 */
+sfrw(ADC12MEM4, ADC12MEM4_);
+#define ADC12MEM4_L_ __MSP430_ADC12_PLUS_BASE__ + 0x24
+sfrb(ADC12MEM4_L, ADC12MEM4_L_);
+#define ADC12MEM4_H_ __MSP430_ADC12_PLUS_BASE__ + 0x25
+sfrb(ADC12MEM4_H, ADC12MEM4_H_);
+#define ADC12MEM5_ __MSP430_ADC12_PLUS_BASE__ + 0x25 /* ADC12 Conversion Memory 5 */
+sfrw(ADC12MEM5, ADC12MEM5_);
+#define ADC12MEM5_L_ __MSP430_ADC12_PLUS_BASE__ + 0x25
+sfrb(ADC12MEM5_L, ADC12MEM5_L_);
+#define ADC12MEM5_H_ __MSP430_ADC12_PLUS_BASE__ + 0x26
+sfrb(ADC12MEM5_H, ADC12MEM5_H_);
+#define ADC12MEM6_ __MSP430_ADC12_PLUS_BASE__ + 0x26 /* ADC12 Conversion Memory 6 */
+sfrw(ADC12MEM6, ADC12MEM6_);
+#define ADC12MEM6_L_ __MSP430_ADC12_PLUS_BASE__ + 0x26
+sfrb(ADC12MEM6_L, ADC12MEM6_L_);
+#define ADC12MEM6_H_ __MSP430_ADC12_PLUS_BASE__ + 0x27
+sfrb(ADC12MEM6_H, ADC12MEM6_H_);
+#define ADC12MEM7_ __MSP430_ADC12_PLUS_BASE__ + 0x27 /* ADC12 Conversion Memory 7 */
+sfrw(ADC12MEM7, ADC12MEM7_);
+#define ADC12MEM7_L_ __MSP430_ADC12_PLUS_BASE__ + 0x27
+sfrb(ADC12MEM7_L, ADC12MEM7_L_);
+#define ADC12MEM7_H_ __MSP430_ADC12_PLUS_BASE__ + 0x28
+sfrb(ADC12MEM7_H, ADC12MEM7_H_);
+#define ADC12MEM8_ __MSP430_ADC12_PLUS_BASE__ + 0x28 /* ADC12 Conversion Memory 8 */
+sfrw(ADC12MEM8, ADC12MEM8_);
+#define ADC12MEM8_L_ __MSP430_ADC12_PLUS_BASE__ + 0x28
+sfrb(ADC12MEM8_L, ADC12MEM8_L_);
+#define ADC12MEM8_H_ __MSP430_ADC12_PLUS_BASE__ + 0x29
+sfrb(ADC12MEM8_H, ADC12MEM8_H_);
+#define ADC12MEM9_ __MSP430_ADC12_PLUS_BASE__ + 0x29 /* ADC12 Conversion Memory 9 */
+sfrw(ADC12MEM9, ADC12MEM9_);
+#define ADC12MEM9_L_ __MSP430_ADC12_PLUS_BASE__ + 0x29
+sfrb(ADC12MEM9_L, ADC12MEM9_L_);
+#define ADC12MEM9_H_ __MSP430_ADC12_PLUS_BASE__ + 0x2a
+sfrb(ADC12MEM9_H, ADC12MEM9_H_);
+#define ADC12MEM10_ __MSP430_ADC12_PLUS_BASE__ + 0x2a /* ADC12 Conversion Memory 10 */
+sfrw(ADC12MEM10, ADC12MEM10_);
+#define ADC12MEM10_L_ __MSP430_ADC12_PLUS_BASE__ + 0x2a
+sfrb(ADC12MEM10_L, ADC12MEM10_L_);
+#define ADC12MEM10_H_ __MSP430_ADC12_PLUS_BASE__ + 0x2b
+sfrb(ADC12MEM10_H, ADC12MEM10_H_);
+#define ADC12MEM11_ __MSP430_ADC12_PLUS_BASE__ + 0x2b /* ADC12 Conversion Memory 11 */
+sfrw(ADC12MEM11, ADC12MEM11_);
+#define ADC12MEM11_L_ __MSP430_ADC12_PLUS_BASE__ + 0x2b
+sfrb(ADC12MEM11_L, ADC12MEM11_L_);
+#define ADC12MEM11_H_ __MSP430_ADC12_PLUS_BASE__ + 0x2c
+sfrb(ADC12MEM11_H, ADC12MEM11_H_);
+#define ADC12MEM12_ __MSP430_ADC12_PLUS_BASE__ + 0x2c /* ADC12 Conversion Memory 12 */
+sfrw(ADC12MEM12, ADC12MEM12_);
+#define ADC12MEM12_L_ __MSP430_ADC12_PLUS_BASE__ + 0x2c
+sfrb(ADC12MEM12_L, ADC12MEM12_L_);
+#define ADC12MEM12_H_ __MSP430_ADC12_PLUS_BASE__ + 0x2d
+sfrb(ADC12MEM12_H, ADC12MEM12_H_);
+#define ADC12MEM13_ __MSP430_ADC12_PLUS_BASE__ + 0x2d /* ADC12 Conversion Memory 13 */
+sfrw(ADC12MEM13, ADC12MEM13_);
+#define ADC12MEM13_L_ __MSP430_ADC12_PLUS_BASE__ + 0x2d
+sfrb(ADC12MEM13_L, ADC12MEM13_L_);
+#define ADC12MEM13_H_ __MSP430_ADC12_PLUS_BASE__ + 0x2e
+sfrb(ADC12MEM13_H, ADC12MEM13_H_);
+#define ADC12MEM14_ __MSP430_ADC12_PLUS_BASE__ + 0x2e /* ADC12 Conversion Memory 14 */
+sfrw(ADC12MEM14, ADC12MEM14_);
+#define ADC12MEM14_L_ __MSP430_ADC12_PLUS_BASE__ + 0x2e
+sfrb(ADC12MEM14_L, ADC12MEM14_L_);
+#define ADC12MEM14_H_ __MSP430_ADC12_PLUS_BASE__ + 0x2f
+sfrb(ADC12MEM14_H, ADC12MEM14_H_);
+#define ADC12MEM15_ __MSP430_ADC12_PLUS_BASE__ + 0x2f /* ADC12 Conversion Memory 15 */
+sfrw(ADC12MEM15, ADC12MEM15_);
+#define ADC12MEM15_L_ __MSP430_ADC12_PLUS_BASE__ + 0x2f
+sfrb(ADC12MEM15_L, ADC12MEM15_L_);
+#define ADC12MEM15_H_ __MSP430_ADC12_PLUS_BASE__ + 0x30
+sfrb(ADC12MEM15_H, ADC12MEM15_H_);
+#define ADC12MEM_ ADC12MEM /* ADC12 Conversion Memory */
+#ifdef __ASM_HEADER__
+#define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */
+#else
+#define ADC12MEM ((int*) &ADC12MEM0) /* ADC12 Conversion Memory (for C) */
+#endif
+
+#define ADC12MCTL0_ __MSP430_ADC12_PLUS_BASE__ + 0x10 /* ADC12 Memory Control 0 */
+sfrb(ADC12MCTL0, ADC12MCTL0_);
+#define ADC12MCTL1_ __MSP430_ADC12_PLUS_BASE__ + 0x11 /* ADC12 Memory Control 1 */
+sfrb(ADC12MCTL1, ADC12MCTL1_);
+#define ADC12MCTL2_ __MSP430_ADC12_PLUS_BASE__ + 0x12 /* ADC12 Memory Control 2 */
+sfrb(ADC12MCTL2, ADC12MCTL2_);
+#define ADC12MCTL3_ __MSP430_ADC12_PLUS_BASE__ + 0x13 /* ADC12 Memory Control 3 */
+sfrb(ADC12MCTL3, ADC12MCTL3_);
+#define ADC12MCTL4_ __MSP430_ADC12_PLUS_BASE__ + 0x14 /* ADC12 Memory Control 4 */
+sfrb(ADC12MCTL4, ADC12MCTL4_);
+#define ADC12MCTL5_ __MSP430_ADC12_PLUS_BASE__ + 0x15 /* ADC12 Memory Control 5 */
+sfrb(ADC12MCTL5, ADC12MCTL5_);
+#define ADC12MCTL6_ __MSP430_ADC12_PLUS_BASE__ + 0x16 /* ADC12 Memory Control 6 */
+sfrb(ADC12MCTL6, ADC12MCTL6_);
+#define ADC12MCTL7_ __MSP430_ADC12_PLUS_BASE__ + 0x17 /* ADC12 Memory Control 7 */
+sfrb(ADC12MCTL7, ADC12MCTL7_);
+#define ADC12MCTL8_ __MSP430_ADC12_PLUS_BASE__ + 0x18 /* ADC12 Memory Control 8 */
+sfrb(ADC12MCTL8, ADC12MCTL8_);
+#define ADC12MCTL9_ __MSP430_ADC12_PLUS_BASE__ + 0x19 /* ADC12 Memory Control 9 */
+sfrb(ADC12MCTL9, ADC12MCTL9_);
+#define ADC12MCTL10_ __MSP430_ADC12_PLUS_BASE__ + 0x1a /* ADC12 Memory Control 10 */
+sfrb(ADC12MCTL10, ADC12MCTL10_);
+#define ADC12MCTL11_ __MSP430_ADC12_PLUS_BASE__ + 0x1b /* ADC12 Memory Control 11 */
+sfrb(ADC12MCTL11, ADC12MCTL11_);
+#define ADC12MCTL12_ __MSP430_ADC12_PLUS_BASE__ + 0x1c /* ADC12 Memory Control 12 */
+sfrb(ADC12MCTL12, ADC12MCTL12_);
+#define ADC12MCTL13_ __MSP430_ADC12_PLUS_BASE__ + 0x1d /* ADC12 Memory Control 13 */
+sfrb(ADC12MCTL13, ADC12MCTL13_);
+#define ADC12MCTL14_ __MSP430_ADC12_PLUS_BASE__ + 0x1e /* ADC12 Memory Control 14 */
+sfrb(ADC12MCTL14, ADC12MCTL14_);
+#define ADC12MCTL15_ __MSP430_ADC12_PLUS_BASE__ + 0x1f /* ADC12 Memory Control 15 */
+sfrb(ADC12MCTL15, ADC12MCTL15_);
+#define ADC12MCTL_ ADC12MCTL /* ADC12 Memory Control */
+#ifdef __ASM_HEADER__
+#define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */
+#else
+#define ADC12MCTL ((char*) ADC12MCTL0) /* ADC12 Memory Control (for C) */
+#endif
+
+/* ADC12CTL0 Control Bits */
+#define ADC12SC (0x001) /* ADC12 Start Conversion */
+#define ADC12ENC (0x002) /* ADC12 Enable Conversion */
+#define ADC12TOVIE (0x004) /* ADC12 Timer Overflow interrupt enable */
+#define ADC12OVIE (0x008) /* ADC12 Overflow interrupt enable */
+#define ADC12ON (0x010) /* ADC12 On/enable */
+#define ADC12REFON (0x020) /* ADC12 Reference on */
+#define ADC12REF2_5V (0x040) /* ADC12 Ref 0:1.5V / 1:2.5V */
+#define ADC12MSC (0x080) /* ADC12 Multiple SampleConversion */
+#define ADC12SHT00 (0x0100) /* ADC12 Sample Hold 0 Select 0 */
+#define ADC12SHT01 (0x0200) /* ADC12 Sample Hold 0 Select 1 */
+#define ADC12SHT02 (0x0400) /* ADC12 Sample Hold 0 Select 2 */
+#define ADC12SHT03 (0x0800) /* ADC12 Sample Hold 0 Select 3 */
+#define ADC12SHT10 (0x1000) /* ADC12 Sample Hold 0 Select 0 */
+#define ADC12SHT11 (0x2000) /* ADC12 Sample Hold 1 Select 1 */
+#define ADC12SHT12 (0x4000) /* ADC12 Sample Hold 2 Select 2 */
+#define ADC12SHT13 (0x8000) /* ADC12 Sample Hold 3 Select 3 */
+
+/* ADC12CTL0 Control Bits */
+#define ADC12SC_L (0x0001) /* ADC12 Start Conversion */
+#define ADC12ENC_L (0x0002) /* ADC12 Enable Conversion */
+#define ADC12TOVIE_L (0x0004) /* ADC12 Timer Overflow interrupt enable */
+#define ADC12OVIE_L (0x0008) /* ADC12 Overflow interrupt enable */
+#define ADC12ON_L (0x0010) /* ADC12 On/enable */
+#define ADC12REFON_L (0x0020) /* ADC12 Reference on */
+#define ADC12REF2_5V_L (0x0040) /* ADC12 Ref 0:1.5V / 1:2.5V */
+#define ADC12MSC_L (0x0080) /* ADC12 Multiple SampleConversion */
+
+/* ADC12CTL0 Control Bits */
+#define ADC12SHT00_H (0x0001) /* ADC12 Sample Hold 0 Select 0 */
+#define ADC12SHT01_H (0x0002) /* ADC12 Sample Hold 0 Select 1 */
+#define ADC12SHT02_H (0x0004) /* ADC12 Sample Hold 0 Select 2 */
+#define ADC12SHT03_H (0x0008) /* ADC12 Sample Hold 0 Select 3 */
+#define ADC12SHT10_H (0x0010) /* ADC12 Sample Hold 0 Select 0 */
+#define ADC12SHT11_H (0x0020) /* ADC12 Sample Hold 1 Select 1 */
+#define ADC12SHT12_H (0x0040) /* ADC12 Sample Hold 2 Select 2 */
+#define ADC12SHT13_H (0x0080) /* ADC12 Sample Hold 3 Select 3 */
+
+#define ADC12SHT0_0 (0*0x100u)
+#define ADC12SHT0_1 (1*0x100u)
+#define ADC12SHT0_2 (2*0x100u)
+#define ADC12SHT0_3 (3*0x100u)
+#define ADC12SHT0_4 (4*0x100u)
+#define ADC12SHT0_5 (5*0x100u)
+#define ADC12SHT0_6 (6*0x100u)
+#define ADC12SHT0_7 (7*0x100u)
+#define ADC12SHT0_8 (8*0x100u)
+#define ADC12SHT0_9 (9*0x100u)
+#define ADC12SHT0_10 (10*0x100u)
+#define ADC12SHT0_11 (11*0x100u)
+#define ADC12SHT0_12 (12*0x100u)
+#define ADC12SHT0_13 (13*0x100u)
+#define ADC12SHT0_14 (14*0x100u)
+#define ADC12SHT0_15 (15*0x100u)
+
+#define ADC12SHT1_0 (0*0x1000u)
+#define ADC12SHT1_1 (1*0x1000u)
+#define ADC12SHT1_2 (2*0x1000u)
+#define ADC12SHT1_3 (3*0x1000u)
+#define ADC12SHT1_4 (4*0x1000u)
+#define ADC12SHT1_5 (5*0x1000u)
+#define ADC12SHT1_6 (6*0x1000u)
+#define ADC12SHT1_7 (7*0x1000u)
+#define ADC12SHT1_8 (8*0x1000u)
+#define ADC12SHT1_9 (9*0x1000u)
+#define ADC12SHT1_10 (10*0x1000u)
+#define ADC12SHT1_11 (11*0x1000u)
+#define ADC12SHT1_12 (12*0x1000u)
+#define ADC12SHT1_13 (13*0x1000u)
+#define ADC12SHT1_14 (14*0x1000u)
+#define ADC12SHT1_15 (15*0x1000u)
+
+/* ADC12CTL1 Control Bits */
+#define ADC12BUSY (0x0001) /* ADC12 Busy */
+#define ADC12CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select 0 */
+#define ADC12CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select 1 */
+#define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select 0 */
+#define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select 1 */
+#define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select 0 */
+#define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select 1 */
+#define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select 2 */
+#define ADC12ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */
+#define ADC12SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */
+#define ADC12SHS0 (0x0400) /* ADC12 Sample/Hold Source 0 */
+#define ADC12SHS1 (0x0800) /* ADC12 Sample/Hold Source 1 */
+#define ADC12CSTARTADD0 (0x1000) /* ADC12 Conversion Start Address 0 */
+#define ADC12CSTARTADD1 (0x2000) /* ADC12 Conversion Start Address 1 */
+#define ADC12CSTARTADD2 (0x4000) /* ADC12 Conversion Start Address 2 */
+#define ADC12CSTARTADD3 (0x8000) /* ADC12 Conversion Start Address 3 */
+
+/* ADC12CTL1 Control Bits */
+#define ADC12BUSY_L (0x0001) /* ADC12 Busy */
+#define ADC12CONSEQ0_L (0x0002) /* ADC12 Conversion Sequence Select 0 */
+#define ADC12CONSEQ1_L (0x0004) /* ADC12 Conversion Sequence Select 1 */
+#define ADC12SSEL0_L (0x0008) /* ADC12 Clock Source Select 0 */
+#define ADC12SSEL1_L (0x0010) /* ADC12 Clock Source Select 1 */
+#define ADC12DIV0_L (0x0020) /* ADC12 Clock Divider Select 0 */
+#define ADC12DIV1_L (0x0040) /* ADC12 Clock Divider Select 1 */
+#define ADC12DIV2_L (0x0080) /* ADC12 Clock Divider Select 2 */
+
+/* ADC12CTL1 Control Bits */
+#define ADC12ISSH_H (0x0001) /* ADC12 Invert Sample Hold Signal */
+#define ADC12SHP_H (0x0002) /* ADC12 Sample/Hold Pulse Mode */
+#define ADC12SHS0_H (0x0004) /* ADC12 Sample/Hold Source 0 */
+#define ADC12SHS1_H (0x0008) /* ADC12 Sample/Hold Source 1 */
+#define ADC12CSTARTADD0_H (0x0010) /* ADC12 Conversion Start Address 0 */
+#define ADC12CSTARTADD1_H (0x0020) /* ADC12 Conversion Start Address 1 */
+#define ADC12CSTARTADD2_H (0x0040) /* ADC12 Conversion Start Address 2 */
+#define ADC12CSTARTADD3_H (0x0080) /* ADC12 Conversion Start Address 3 */
+
+#define ADC12CONSEQ_0 (0*2u)
+#define ADC12CONSEQ_1 (1*2u)
+#define ADC12CONSEQ_2 (2*2u)
+#define ADC12CONSEQ_3 (3*2u)
+#define ADC12SSEL_0 (0*8u)
+#define ADC12SSEL_1 (1*8u)
+#define ADC12SSEL_2 (2*8u)
+#define ADC12SSEL_3 (3*8u)
+#define ADC12DIV_0 (0*0x20u)
+#define ADC12DIV_1 (1*0x20u)
+#define ADC12DIV_2 (2*0x20u)
+#define ADC12DIV_3 (3*0x20u)
+#define ADC12DIV_4 (4*0x20u)
+#define ADC12DIV_5 (5*0x20u)
+#define ADC12DIV_6 (6*0x20u)
+#define ADC12DIV_7 (7*0x20u)
+#define ADC12SHS_0 (0*0x400u)
+#define ADC12SHS_1 (1*0x400u)
+#define ADC12SHS_2 (2*0x400u)
+#define ADC12SHS_3 (3*0x400u)
+#define ADC12CSTARTADD_0 (0*0x1000u)
+#define ADC12CSTARTADD_1 (1*0x1000u)
+#define ADC12CSTARTADD_2 (2*0x1000u)
+#define ADC12CSTARTADD_3 (3*0x1000u)
+#define ADC12CSTARTADD_4 (4*0x1000u)
+#define ADC12CSTARTADD_5 (5*0x1000u)
+#define ADC12CSTARTADD_6 (6*0x1000u)
+#define ADC12CSTARTADD_7 (7*0x1000u)
+#define ADC12CSTARTADD_8 (8*0x1000u)
+#define ADC12CSTARTADD_9 (9*0x1000u)
+#define ADC12CSTARTADD_10 (10*0x1000u)
+#define ADC12CSTARTADD_11 (11*0x1000u)
+#define ADC12CSTARTADD_12 (12*0x1000u)
+#define ADC12CSTARTADD_13 (13*0x1000u)
+#define ADC12CSTARTADD_14 (14*0x1000u)
+#define ADC12CSTARTADD_15 (15*0x1000u)
+
+/* ADC12CTL2 Control Bits */
+#define ADC12REFBURST (0x0001) /* ADC12+ Reference Burst */
+#define ADC12REFOUT (0x0002) /* ADC12+ Reference Out */
+#define ADC12SR (0x0004) /* ADC12+ Sampling Rate */
+#define ADC12DF (0x0008) /* ADC12+ Data Format */
+#define ADC12RES0 (0x0010) /* ADC12+ Resolution Bit: 0 */
+#define ADC12RES1 (0x0020) /* ADC12+ Resolution Bit: 1 */
+#define ADC12TCOFF (0x0080) /* ADC12+ Temperature Sensor Off */
+#define ADC12PDIV (0x0100) /* ADC12+ predivider 0:/1 1:/4 */
+
+/* ADC12CTL2 Control Bits */
+#define ADC12REFBURST_L (0x0001) /* ADC12+ Reference Burst */
+#define ADC12REFOUT_L (0x0002) /* ADC12+ Reference Out */
+#define ADC12SR_L (0x0004) /* ADC12+ Sampling Rate */
+#define ADC12DF_L (0x0008) /* ADC12+ Data Format */
+#define ADC12RES0_L (0x0010) /* ADC12+ Resolution Bit: 0 */
+#define ADC12RES1_L (0x0020) /* ADC12+ Resolution Bit: 1 */
+#define ADC12TCOFF_L (0x0080) /* ADC12+ Temperature Sensor Off */
+
+/* ADC12CTL2 Control Bits */
+#define ADC12PDIV_H (0x0001) /* ADC12+ predivider 0:/1 1:/4 */
+
+#define ADC12RES_0 (0x0000) /* ADC12+ Resolution : 8 Bit */
+#define ADC12RES_1 (0x0010) /* ADC12+ Resolution : 10 Bit */
+#define ADC12RES_2 (0x0020) /* ADC12+ Resolution : 12 Bit */
+#define ADC12RES_3 (0x0030) /* ADC12+ Resolution : reserved */
+
+/* ADC12MCTLx Control Bits */
+#define ADC12INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */
+#define ADC12INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */
+#define ADC12INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */
+#define ADC12INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */
+#define ADC12SREF0 (0x0010) /* ADC12 Select Reference Bit 0 */
+#define ADC12SREF1 (0x0020) /* ADC12 Select Reference Bit 1 */
+#define ADC12SREF2 (0x0040) /* ADC12 Select Reference Bit 2 */
+#define ADC12EOS (0x0080) /* ADC12 End of Sequence */
+
+#define ADC12INCH_0 (0)
+#define ADC12INCH_1 (1)
+#define ADC12INCH_2 (2)
+#define ADC12INCH_3 (3)
+#define ADC12INCH_4 (4)
+#define ADC12INCH_5 (5)
+#define ADC12INCH_6 (6)
+#define ADC12INCH_7 (7)
+#define ADC12INCH_8 (8)
+#define ADC12INCH_9 (9)
+#define ADC12INCH_10 (10)
+#define ADC12INCH_11 (11)
+#define ADC12INCH_12 (12)
+#define ADC12INCH_13 (13)
+#define ADC12INCH_14 (14)
+#define ADC12INCH_15 (15)
+
+#define ADC12SREF_0 (0*0x10u)
+#define ADC12SREF_1 (1*0x10u)
+#define ADC12SREF_2 (2*0x10u)
+#define ADC12SREF_3 (3*0x10u)
+#define ADC12SREF_4 (4*0x10u)
+#define ADC12SREF_5 (5*0x10u)
+#define ADC12SREF_6 (6*0x10u)
+#define ADC12SREF_7 (7*0x10u)
+
+/* ADC12IV Definitions */
+#define ADC12IV_NONE (0x0000) /* No Interrupt pending */
+#define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */
+#define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */
+#define ADC12IV_ADC12IFG0 (0x0006) /* ADC12IFG0 */
+#define ADC12IV_ADC12IFG1 (0x0008) /* ADC12IFG1 */
+#define ADC12IV_ADC12IFG2 (0x000A) /* ADC12IFG2 */
+#define ADC12IV_ADC12IFG3 (0x000C) /* ADC12IFG3 */
+#define ADC12IV_ADC12IFG4 (0x000E) /* ADC12IFG4 */
+#define ADC12IV_ADC12IFG5 (0x0010) /* ADC12IFG5 */
+#define ADC12IV_ADC12IFG6 (0x0012) /* ADC12IFG6 */
+#define ADC12IV_ADC12IFG7 (0x0014) /* ADC12IFG7 */
+#define ADC12IV_ADC12IFG8 (0x0016) /* ADC12IFG8 */
+#define ADC12IV_ADC12IFG9 (0x0018) /* ADC12IFG9 */
+#define ADC12IV_ADC12IFG10 (0x001A) /* ADC12IFG10 */
+#define ADC12IV_ADC12IFG11 (0x001C) /* ADC12IFG11 */
+#define ADC12IV_ADC12IFG12 (0x001E) /* ADC12IFG12 */
+#define ADC12IV_ADC12IFG13 (0x0020) /* ADC12IFG13 */
+#define ADC12IV_ADC12IFG14 (0x0022) /* ADC12IFG14 */
+#define ADC12IV_ADC12IFG15 (0x0024) /* ADC12IFG15 */
+
+#endif /* __MSP430_ADC12_PLUS_BASE__ */
+
+#endif /* __MSP430_HEADERS_ADC12_PLUS_H__ */
+
--- /dev/null
+#ifndef __MSP430_HEADERS_AES_H
+#define __MSP430_HEADERS_AES_H
+
+/* aes.h
+*
+* mspgcc project: MSP430 device headers
+* Advanced Enscription Standard module
+* Based on cc430x613x.h version 1.5 by Texas Instruments
+*
+* Peter A. Bigot <pab@peoplepowerco.com>
+*/
+
+/* Switches:
+
+__MSP430_AES_BASE__ - base address of the port mapping control module, present if defined
+
+*/
+
+#if defined(__MSP430_AES_BASE__)
+
+/************************************************************
+* AES Accelerator
+************************************************************/
+#define __MSP430_HAS_AES__ /* Definition to show that Module is available */
+
+#define AESACTL0_ __MSP430_AES_BASE__ + 0x00 /* AES accelerator control register 0 */
+sfrw(AESACTL0, AESACTL0_);
+#define AESACTL0_L_ __MSP430_AES_BASE__ + 0x00
+sfrb(AESACTL0_L, AESACTL0_L_);
+#define AESACTL0_H_ __MSP430_AES_BASE__ + 0x01
+sfrb(AESACTL0_H, AESACTL0_H_);
+#define AESASTAT_ __MSP430_AES_BASE__ + 0x04 /* AES accelerator status register */
+sfrw(AESASTAT, AESASTAT_);
+#define AESASTAT_L_ __MSP430_AES_BASE__ + 0x04
+sfrb(AESASTAT_L, AESASTAT_L_);
+#define AESASTAT_H_ __MSP430_AES_BASE__ + 0x05
+sfrb(AESASTAT_H, AESASTAT_H_);
+#define AESAKEY_ __MSP430_AES_BASE__ + 0x06 /* AES accelerator key register */
+sfrw(AESAKEY, AESAKEY_);
+#define AESAKEY_L_ __MSP430_AES_BASE__ + 0x06
+sfrb(AESAKEY_L, AESAKEY_L_);
+#define AESAKEY_H_ __MSP430_AES_BASE__ + 0x07
+sfrb(AESAKEY_H, AESAKEY_H_);
+#define AESADIN_ __MSP430_AES_BASE__ + 0x08 /* AES accelerator data in register */
+sfrw(AESADIN, AESADIN_);
+#define AESADIN_L_ __MSP430_AES_BASE__ + 0x08
+sfrb(AESADIN_L, AESADIN_L_);
+#define AESADIN_H_ __MSP430_AES_BASE__ + 0x09
+sfrb(AESADIN_H, AESADIN_H_);
+#define AESADOUT_ __MSP430_AES_BASE__ + 0x0a /* AES accelerator data out register */
+sfrw(AESADOUT, AESADOUT_);
+#define AESADOUT_L_ __MSP430_AES_BASE__ + 0x0a
+sfrb(AESADOUT_L, AESADOUT_L_);
+#define AESADOUT_H_ __MSP430_AES_BASE__ + 0x0b
+sfrb(AESADOUT_H, AESADOUT_H_);
+
+/* AESACTL0 Control Bits */
+#define AESOP0 (0x0001) /* AES Operation Bit: 0 */
+#define AESOP1 (0x0002) /* AES Operation Bit: 1 */
+#define AESSWRST (0x0080) /* AES Software Reset */
+#define AESRDYIFG (0x0100) /* AES ready interrupt flag */
+#define AESERRFG (0x0800) /* AES Error Flag */
+#define AESRDYIE (0x1000) /* AES ready interrupt enable*/
+
+/* AESACTL0 Control Bits */
+#define AESOP0_L (0x0001) /* AES Operation Bit: 0 */
+#define AESOP1_L (0x0002) /* AES Operation Bit: 1 */
+#define AESSWRST_L (0x0080) /* AES Software Reset */
+
+/* AESACTL0 Control Bits */
+#define AESRDYIFG_H (0x0001) /* AES ready interrupt flag */
+#define AESERRFG_H (0x0008) /* AES Error Flag */
+#define AESRDYIE_H (0x0010) /* AES ready interrupt enable*/
+
+#define AESOP_0 (0x0000) /* AES Operation: Encrypt */
+#define AESOP_1 (0x0001) /* AES Operation: Decrypt (same Key) */
+#define AESOP_2 (0x0002) /* AES Operation: Decrypt (frist round Key) */
+#define AESOP_3 (0x0003) /* AES Operation: Generate first round Key */
+
+/* AESASTAT Control Bits */
+#define AESBUSY (0x0001) /* AES Busy */
+#define AESKEYWR (0x0002) /* AES All 16 bytes written to AESAKEY */
+#define AESDINWR (0x0004) /* AES All 16 bytes written to AESADIN */
+#define AESDOUTRD (0x0008) /* AES All 16 bytes read from AESADOUT */
+#define AESKEYCNT0 (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */
+#define AESKEYCNT1 (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */
+#define AESKEYCNT2 (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */
+#define AESKEYCNT3 (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */
+#define AESDINCNT0 (0x0100) /* AES Bytes written via AESADIN Bit: 0 */
+#define AESDINCNT1 (0x0200) /* AES Bytes written via AESADIN Bit: 1 */
+#define AESDINCNT2 (0x0400) /* AES Bytes written via AESADIN Bit: 2 */
+#define AESDINCNT3 (0x0800) /* AES Bytes written via AESADIN Bit: 3 */
+#define AESDOUTCNT0 (0x1000) /* AES Bytes read via AESADOUT Bit: 0 */
+#define AESDOUTCNT1 (0x2000) /* AES Bytes read via AESADOUT Bit: 1 */
+#define AESDOUTCNT2 (0x4000) /* AES Bytes read via AESADOUT Bit: 2 */
+#define AESDOUTCNT3 (0x8000) /* AES Bytes read via AESADOUT Bit: 3 */
+
+/* AESASTAT Control Bits */
+#define AESBUSY_L (0x0001) /* AES Busy */
+#define AESKEYWR_L (0x0002) /* AES All 16 bytes written to AESAKEY */
+#define AESDINWR_L (0x0004) /* AES All 16 bytes written to AESADIN */
+#define AESDOUTRD_L (0x0008) /* AES All 16 bytes read from AESADOUT */
+#define AESKEYCNT0_L (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */
+#define AESKEYCNT1_L (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */
+#define AESKEYCNT2_L (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */
+#define AESKEYCNT3_L (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */
+
+/* AESASTAT Control Bits */
+#define AESDINCNT0_H (0x0001) /* AES Bytes written via AESADIN Bit: 0 */
+#define AESDINCNT1_H (0x0002) /* AES Bytes written via AESADIN Bit: 1 */
+#define AESDINCNT2_H (0x0004) /* AES Bytes written via AESADIN Bit: 2 */
+#define AESDINCNT3_H (0x0008) /* AES Bytes written via AESADIN Bit: 3 */
+#define AESDOUTCNT0_H (0x0010) /* AES Bytes read via AESADOUT Bit: 0 */
+#define AESDOUTCNT1_H (0x0020) /* AES Bytes read via AESADOUT Bit: 1 */
+#define AESDOUTCNT2_H (0x0040) /* AES Bytes read via AESADOUT Bit: 2 */
+#define AESDOUTCNT3_H (0x0080) /* AES Bytes read via AESADOUT Bit: 3 */
+
+#endif /* __MSP430_AES_BASE__ */
+
+#endif /* __MSP430_HEADERS_AES_H */
* (c) 2002 by M. P. Ashton <data@ieee.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: common.h,v 1.5 2006/01/12 00:47:21 cliechti Exp $
+ * $Id: common.h,v 1.6 2008/10/09 15:00:14 sb-sf Exp $
*/
/* Switches: none */
#define SCG0 0x0040
#define SCG1 0x0080
-#ifdef _GNU_ASSEMBLER_ /* Begin #defines for assembler */
+#ifdef __ASSEMBLER__ /* Begin #defines for assembler */
#define LPM0 CPUOFF
#define LPM1 SCG0+CPUOFF
#define LPM2 SCG1+CPUOFF
#define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */
#endif /* End #defines for C */
+#if ! defined(__MSP430_WDT_A_BASE__)
+/* Excluded for 5xx architectures where watchdog timer is at a
+ * different address. Use <msp430/wdt_a.h>. */
+
#define WDTCTL_ 0x0120 /* Watchdog Timer Control */
sfrw (WDTCTL,WDTCTL_);
/* The bit names have been prefixed with "WDT" */
#define WDTIS_2 0x0002
#define WDTIS_3 0x0003
+#endif /* __MSP430_WDT_A_BASE__ */
/* Backwards compatibility to older versions of the header files.
Please consider using the new names.
#define __msp430_have_timerb7
#endif
+/* Compatibity with TI standard definitions */
+#if defined(__MSP430X2__)
+#define __MSP430_HAS_MSP430XV2_CPU__ 1
+#endif
+
+#if defined(__MSP430X__)
+#define __MSP430_HAS_MSP430X_CPU__ 1
+#endif
+
#endif
--- /dev/null
+#if !defined(__MSP430_HEADERS_COMPB_H__)
+#define __MSP430_HEADERS_COMPB_H__
+
+/* compb.h
+ *
+ * mspgcc project: MSP430 device headers
+ * Comparator B
+ *
+ * Based on cc430x613x.h version 1.5 by Texas Instruments
+ *
+ * Peter A. Bigot <pab@peoplepowerco.com>
+ *
+ */
+
+/* Switches:
+__MSP430_HAS_COMPB__ -- defined to indicate availability of module
+__MSP430_COMPB_BASE__ - base address of COMPB module
+*/
+
+#if defined(__MSP430_COMPB_BASE__)
+
+#define CBCTL0_ __MSP430_COMPB_BASE__ + 0x00 /* Comparator B Control Register 0 */
+sfrw(CBCTL0, CBCTL0_);
+#define CBCTL0_L_ __MSP430_COMPB_BASE__ + 0x00
+sfrb(CBCTL0_L, CBCTL0_L_);
+#define CBCTL0_H_ __MSP430_COMPB_BASE__ + 0x01
+sfrb(CBCTL0_H, CBCTL0_H_);
+#define CBCTL1_ __MSP430_COMPB_BASE__ + 0x02 /* Comparator B Control Register 1 */
+sfrw(CBCTL1, CBCTL1_);
+#define CBCTL1_L_ __MSP430_COMPB_BASE__ + 0x02
+sfrb(CBCTL1_L, CBCTL1_L_);
+#define CBCTL1_H_ __MSP430_COMPB_BASE__ + 0x03
+sfrb(CBCTL1_H, CBCTL1_H_);
+#define CBCTL2_ __MSP430_COMPB_BASE__ + 0x04 /* Comparator B Control Register 2 */
+sfrw(CBCTL2, CBCTL2_);
+#define CBCTL2_L_ __MSP430_COMPB_BASE__ + 0x04
+sfrb(CBCTL2_L, CBCTL2_L_);
+#define CBCTL2_H_ __MSP430_COMPB_BASE__ + 0x05
+sfrb(CBCTL2_H, CBCTL2_H_);
+#define CBCTL3_ __MSP430_COMPB_BASE__ + 0x06 /* Comparator B Control Register 3 */
+sfrw(CBCTL3, CBCTL3_);
+#define CBCTL3_L_ __MSP430_COMPB_BASE__ + 0x06
+sfrb(CBCTL3_L, CBCTL3_L_);
+#define CBCTL3_H_ __MSP430_COMPB_BASE__ + 0x07
+sfrb(CBCTL3_H, CBCTL3_H_);
+#define CBINT_ __MSP430_COMPB_BASE__ + 0x0c /* Comparator B Interrupt Register */
+sfrw(CBINT, CBINT_);
+#define CBINT_L_ __MSP430_COMPB_BASE__ + 0x0c
+sfrb(CBINT_L, CBINT_L_);
+#define CBINT_H_ __MSP430_COMPB_BASE__ + 0x0d
+sfrb(CBINT_H, CBINT_H_);
+#define CBIV_ __MSP430_COMPB_BASE__ + 0x0e /* Comparator B Interrupt Vector Word */
+sfrw(CBIV, CBIV_);
+#define CBIV_L_ __MSP430_COMPB_BASE__ + 0x0e
+sfrb(CBIV_L, CBIV_L_);
+#define CBIV_H_ __MSP430_COMPB_BASE__ + 0x0f
+sfrb(CBIV_H, CBIV_H_);
+
+/* CBCTL0 Control Bits */
+#define CBIPSEL0 (0x0001) /* Comp. B Pos. Channel Input Select 0 */
+#define CBIPSEL1 (0x0002) /* Comp. B Pos. Channel Input Select 1 */
+#define CBIPSEL2 (0x0004) /* Comp. B Pos. Channel Input Select 2 */
+#define CBIPSEL3 (0x0008) /* Comp. B Pos. Channel Input Select 3 */
+//#define RESERVED (0x0010) /* Comp. B */
+//#define RESERVED (0x0020) /* Comp. B */
+//#define RESERVED (0x0040) /* Comp. B */
+#define CBIPEN (0x0080) /* Comp. B Pos. Channel Input Enalbe */
+#define CBIMSEL0 (0x0100) /* Comp. B Neg. Channel Input Select 0 */
+#define CBIMSEL1 (0x0200) /* Comp. B Neg. Channel Input Select 1 */
+#define CBIMSEL2 (0x0400) /* Comp. B Neg. Channel Input Select 2 */
+#define CBIMSEL3 (0x0800) /* Comp. B Neg. Channel Input Select 3 */
+//#define RESERVED (0x1000) /* Comp. B */
+//#define RESERVED (0x2000) /* Comp. B */
+//#define RESERVED (0x4000) /* Comp. B */
+#define CBIMEN (0x8000) /* Comp. B Neg. Channel Input Enalbe */
+
+/* CBCTL0 Control Bits */
+#define CBIPSEL0_L (0x0001) /* Comp. B Pos. Channel Input Select 0 */
+#define CBIPSEL1_L (0x0002) /* Comp. B Pos. Channel Input Select 1 */
+#define CBIPSEL2_L (0x0004) /* Comp. B Pos. Channel Input Select 2 */
+#define CBIPSEL3_L (0x0008) /* Comp. B Pos. Channel Input Select 3 */
+//#define RESERVED (0x0010) /* Comp. B */
+//#define RESERVED (0x0020) /* Comp. B */
+//#define RESERVED (0x0040) /* Comp. B */
+#define CBIPEN_L (0x0080) /* Comp. B Pos. Channel Input Enalbe */
+//#define RESERVED (0x1000) /* Comp. B */
+//#define RESERVED (0x2000) /* Comp. B */
+//#define RESERVED (0x4000) /* Comp. B */
+
+/* CBCTL0 Control Bits */
+//#define RESERVED (0x0010) /* Comp. B */
+//#define RESERVED (0x0020) /* Comp. B */
+//#define RESERVED (0x0040) /* Comp. B */
+#define CBIMSEL0_H (0x0001) /* Comp. B Neg. Channel Input Select 0 */
+#define CBIMSEL1_H (0x0002) /* Comp. B Neg. Channel Input Select 1 */
+#define CBIMSEL2_H (0x0004) /* Comp. B Neg. Channel Input Select 2 */
+#define CBIMSEL3_H (0x0008) /* Comp. B Neg. Channel Input Select 3 */
+//#define RESERVED (0x1000) /* Comp. B */
+//#define RESERVED (0x2000) /* Comp. B */
+//#define RESERVED (0x4000) /* Comp. B */
+#define CBIMEN_H (0x0080) /* Comp. B Neg. Channel Input Enalbe */
+
+#define CBIPSEL_0 (0x0000) /* Comp. B V+ terminal Input Select: Channel 0 */
+#define CBIPSEL_1 (0x0001) /* Comp. B V+ terminal Input Select: Channel 1 */
+#define CBIPSEL_2 (0x0002) /* Comp. B V+ terminal Input Select: Channel 2 */
+#define CBIPSEL_3 (0x0003) /* Comp. B V+ terminal Input Select: Channel 3 */
+#define CBIPSEL_4 (0x0004) /* Comp. B V+ terminal Input Select: Channel 4 */
+#define CBIPSEL_5 (0x0005) /* Comp. B V+ terminal Input Select: Channel 5 */
+#define CBIPSEL_6 (0x0006) /* Comp. B V+ terminal Input Select: Channel 6 */
+#define CBIPSEL_7 (0x0007) /* Comp. B V+ terminal Input Select: Channel 7 */
+#define CBIPSEL_8 (0x0008) /* Comp. B V+ terminal Input Select: Channel 8 */
+#define CBIPSEL_9 (0x0009) /* Comp. B V+ terminal Input Select: Channel 9 */
+#define CBIPSEL_10 (0x000A) /* Comp. B V+ terminal Input Select: Channel 10 */
+#define CBIPSEL_11 (0x000B) /* Comp. B V+ terminal Input Select: Channel 11 */
+#define CBIPSEL_12 (0x000C) /* Comp. B V+ terminal Input Select: Channel 12 */
+#define CBIPSEL_13 (0x000D) /* Comp. B V+ terminal Input Select: Channel 13 */
+#define CBIPSEL_14 (0x000E) /* Comp. B V+ terminal Input Select: Channel 14 */
+#define CBIPSEL_15 (0x000F) /* Comp. B V+ terminal Input Select: Channel 15 */
+
+#define CBIMSEL_0 (0x0000) /* Comp. B V- Terminal Input Select: Channel 0 */
+#define CBIMSEL_1 (0x0100) /* Comp. B V- Terminal Input Select: Channel 1 */
+#define CBIMSEL_2 (0x0200) /* Comp. B V- Terminal Input Select: Channel 2 */
+#define CBIMSEL_3 (0x0300) /* Comp. B V- Terminal Input Select: Channel 3 */
+#define CBIMSEL_4 (0x0400) /* Comp. B V- Terminal Input Select: Channel 4 */
+#define CBIMSEL_5 (0x0500) /* Comp. B V- Terminal Input Select: Channel 5 */
+#define CBIMSEL_6 (0x0600) /* Comp. B V- Terminal Input Select: Channel 6 */
+#define CBIMSEL_7 (0x0700) /* Comp. B V- Terminal Input Select: Channel 7 */
+#define CBIMSEL_8 (0x0800) /* Comp. B V- terminal Input Select: Channel 8 */
+#define CBIMSEL_9 (0x0900) /* Comp. B V- terminal Input Select: Channel 9 */
+#define CBIMSEL_10 (0x0A00) /* Comp. B V- terminal Input Select: Channel 10 */
+#define CBIMSEL_11 (0x0B00) /* Comp. B V- terminal Input Select: Channel 11 */
+#define CBIMSEL_12 (0x0C00) /* Comp. B V- terminal Input Select: Channel 12 */
+#define CBIMSEL_13 (0x0D00) /* Comp. B V- terminal Input Select: Channel 13 */
+#define CBIMSEL_14 (0x0E00) /* Comp. B V- terminal Input Select: Channel 14 */
+#define CBIMSEL_15 (0x0F00) /* Comp. B V- terminal Input Select: Channel 15 */
+
+/* CBCTL1 Control Bits */
+#define CBOUT (0x0001) /* Comp. B Output */
+#define CBOUTPOL (0x0002) /* Comp. B Output Polarity */
+#define CBF (0x0004) /* Comp. B Enable Output Filter */
+#define CBIES (0x0008) /* Comp. B Interrupt Edge Select */
+#define CBSHORT (0x0010) /* Comp. B Input Short */
+#define CBEX (0x0020) /* Comp. B Exchange Inputs */
+#define CBFDLY0 (0x0040) /* Comp. B Filter delay Bit 0 */
+#define CBFDLY1 (0x0080) /* Comp. B Filter delay Bit 1 */
+#define CBPWRMD0 (0x0100) /* Comp. B Power Mode Bit 0 */
+#define CBPWRMD1 (0x0200) /* Comp. B Power Mode Bit 1 */
+#define CBON (0x0400) /* Comp. B enable */
+#define CBMRVL (0x0800) /* Comp. B CBMRV Level */
+#define CBMRVS (0x1000) /* Comp. B Output selects between VREF0 or VREF1*/
+//#define RESERVED (0x2000) /* Comp. B */
+//#define RESERVED (0x4000) /* Comp. B */
+//#define RESERVED (0x8000) /* Comp. B */
+
+/* CBCTL1 Control Bits */
+#define CBOUT_L (0x0001) /* Comp. B Output */
+#define CBOUTPOL_L (0x0002) /* Comp. B Output Polarity */
+#define CBF_L (0x0004) /* Comp. B Enable Output Filter */
+#define CBIES_L (0x0008) /* Comp. B Interrupt Edge Select */
+#define CBSHORT_L (0x0010) /* Comp. B Input Short */
+#define CBEX_L (0x0020) /* Comp. B Exchange Inputs */
+#define CBFDLY0_L (0x0040) /* Comp. B Filter delay Bit 0 */
+#define CBFDLY1_L (0x0080) /* Comp. B Filter delay Bit 1 */
+//#define RESERVED (0x2000) /* Comp. B */
+//#define RESERVED (0x4000) /* Comp. B */
+//#define RESERVED (0x8000) /* Comp. B */
+
+/* CBCTL1 Control Bits */
+#define CBPWRMD0_H (0x0001) /* Comp. B Power Mode Bit 0 */
+#define CBPWRMD1_H (0x0002) /* Comp. B Power Mode Bit 1 */
+#define CBON_H (0x0004) /* Comp. B enable */
+#define CBMRVL_H (0x0008) /* Comp. B CBMRV Level */
+#define CBMRVS_H (0x0010) /* Comp. B Output selects between VREF0 or VREF1*/
+//#define RESERVED (0x2000) /* Comp. B */
+//#define RESERVED (0x4000) /* Comp. B */
+//#define RESERVED (0x8000) /* Comp. B */
+
+#define CBFDLY_0 (0x0000) /* Comp. B Filter delay 0 : 450ns */
+#define CBFDLY_1 (0x0040) /* Comp. B Filter delay 1 : 900ns */
+#define CBFDLY_2 (0x0080) /* Comp. B Filter delay 2 : 1800ns */
+#define CBFDLY_3 (0x00C0) /* Comp. B Filter delay 3 : 3600ns */
+
+#define CBPWRMD_0 (0x0000) /* Comp. B Power Mode 0 : High speed */
+#define CBPWRMD_1 (0x0100) /* Comp. B Power Mode 1 : Normal */
+#define CBPWRMD_2 (0x0200) /* Comp. B Power Mode 2 : Ultra-Low*/
+#define CBPWRMD_3 (0x0300) /* Comp. B Power Mode 3 : Reserved */
+
+/* CBCTL2 Control Bits */
+#define CBREF00 (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */
+#define CBREF01 (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */
+#define CBREF02 (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */
+#define CBREF03 (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */
+#define CBREF04 (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */
+#define CBRSEL (0x0020) /* Comp. B Reference select */
+#define CBRS0 (0x0040) /* Comp. B Reference Source Bit : 0 */
+#define CBRS1 (0x0080) /* Comp. B Reference Source Bit : 1 */
+#define CBREF10 (0x0100) /* Comp. B Reference 1 Resistor Select Bit : 0 */
+#define CBREF11 (0x0200) /* Comp. B Reference 1 Resistor Select Bit : 1 */
+#define CBREF12 (0x0400) /* Comp. B Reference 1 Resistor Select Bit : 2 */
+#define CBREF13 (0x0800) /* Comp. B Reference 1 Resistor Select Bit : 3 */
+#define CBREF14 (0x1000) /* Comp. B Reference 1 Resistor Select Bit : 4 */
+#define CBREFL0 (0x2000) /* Comp. B Reference voltage level Bit : 0 */
+#define CBREFL1 (0x4000) /* Comp. B Reference voltage level Bit : 1 */
+#define CBREFACC (0x8000) /* Comp. B Reference Accuracy */
+
+/* CBCTL2 Control Bits */
+#define CBREF00_L (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */
+#define CBREF01_L (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */
+#define CBREF02_L (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */
+#define CBREF03_L (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */
+#define CBREF04_L (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */
+#define CBRSEL_L (0x0020) /* Comp. B Reference select */
+#define CBRS0_L (0x0040) /* Comp. B Reference Source Bit : 0 */
+#define CBRS1_L (0x0080) /* Comp. B Reference Source Bit : 1 */
+
+/* CBCTL2 Control Bits */
+#define CBREF10_H (0x0001) /* Comp. B Reference 1 Resistor Select Bit : 0 */
+#define CBREF11_H (0x0002) /* Comp. B Reference 1 Resistor Select Bit : 1 */
+#define CBREF12_H (0x0004) /* Comp. B Reference 1 Resistor Select Bit : 2 */
+#define CBREF13_H (0x0008) /* Comp. B Reference 1 Resistor Select Bit : 3 */
+#define CBREF14_H (0x0010) /* Comp. B Reference 1 Resistor Select Bit : 4 */
+#define CBREFL0_H (0x0020) /* Comp. B Reference voltage level Bit : 0 */
+#define CBREFL1_H (0x0040) /* Comp. B Reference voltage level Bit : 1 */
+#define CBREFACC_H (0x0080) /* Comp. B Reference Accuracy */
+
+#define CBREF0_0 (0x0000) /* Comp. B Int. Ref.0 Select 0 : 1/32 */
+#define CBREF0_1 (0x0001) /* Comp. B Int. Ref.0 Select 1 : 2/32 */
+#define CBREF0_2 (0x0002) /* Comp. B Int. Ref.0 Select 2 : 3/32 */
+#define CBREF0_3 (0x0003) /* Comp. B Int. Ref.0 Select 3 : 4/32 */
+#define CBREF0_4 (0x0004) /* Comp. B Int. Ref.0 Select 4 : 5/32 */
+#define CBREF0_5 (0x0005) /* Comp. B Int. Ref.0 Select 5 : 6/32 */
+#define CBREF0_6 (0x0006) /* Comp. B Int. Ref.0 Select 6 : 7/32 */
+#define CBREF0_7 (0x0007) /* Comp. B Int. Ref.0 Select 7 : 8/32 */
+#define CBREF0_8 (0x0008) /* Comp. B Int. Ref.0 Select 0 : 9/32 */
+#define CBREF0_9 (0x0009) /* Comp. B Int. Ref.0 Select 1 : 10/32 */
+#define CBREF0_10 (0x000A) /* Comp. B Int. Ref.0 Select 2 : 11/32 */
+#define CBREF0_11 (0x000B) /* Comp. B Int. Ref.0 Select 3 : 12/32 */
+#define CBREF0_12 (0x000C) /* Comp. B Int. Ref.0 Select 4 : 13/32 */
+#define CBREF0_13 (0x000D) /* Comp. B Int. Ref.0 Select 5 : 14/32 */
+#define CBREF0_14 (0x000E) /* Comp. B Int. Ref.0 Select 6 : 15/32 */
+#define CBREF0_15 (0x000F) /* Comp. B Int. Ref.0 Select 7 : 16/32 */
+#define CBREF0_16 (0x0010) /* Comp. B Int. Ref.0 Select 0 : 17/32 */
+#define CBREF0_17 (0x0011) /* Comp. B Int. Ref.0 Select 1 : 18/32 */
+#define CBREF0_18 (0x0012) /* Comp. B Int. Ref.0 Select 2 : 19/32 */
+#define CBREF0_19 (0x0013) /* Comp. B Int. Ref.0 Select 3 : 20/32 */
+#define CBREF0_20 (0x0014) /* Comp. B Int. Ref.0 Select 4 : 21/32 */
+#define CBREF0_21 (0x0015) /* Comp. B Int. Ref.0 Select 5 : 22/32 */
+#define CBREF0_22 (0x0016) /* Comp. B Int. Ref.0 Select 6 : 23/32 */
+#define CBREF0_23 (0x0017) /* Comp. B Int. Ref.0 Select 7 : 24/32 */
+#define CBREF0_24 (0x0018) /* Comp. B Int. Ref.0 Select 0 : 25/32 */
+#define CBREF0_25 (0x0019) /* Comp. B Int. Ref.0 Select 1 : 26/32 */
+#define CBREF0_26 (0x001A) /* Comp. B Int. Ref.0 Select 2 : 27/32 */
+#define CBREF0_27 (0x001B) /* Comp. B Int. Ref.0 Select 3 : 28/32 */
+#define CBREF0_28 (0x001C) /* Comp. B Int. Ref.0 Select 4 : 29/32 */
+#define CBREF0_29 (0x001D) /* Comp. B Int. Ref.0 Select 5 : 30/32 */
+#define CBREF0_30 (0x001E) /* Comp. B Int. Ref.0 Select 6 : 31/32 */
+#define CBREF0_31 (0x001F) /* Comp. B Int. Ref.0 Select 7 : 32/32 */
+
+#define CBRS_0 (0x0000) /* Comp. B Reference Source 0 : Off */
+#define CBRS_1 (0x0040) /* Comp. B Reference Source 1 : Vcc */
+#define CBRS_2 (0x0080) /* Comp. B Reference Source 2 : Shared Ref. */
+#define CBRS_3 (0x00C0) /* Comp. B Reference Source 3 : Shared Ref. / Off */
+
+#define CBREF1_0 (0x0000) /* Comp. B Int. Ref.1 Select 0 : 1/32 */
+#define CBREF1_1 (0x0100) /* Comp. B Int. Ref.1 Select 1 : 2/32 */
+#define CBREF1_2 (0x0200) /* Comp. B Int. Ref.1 Select 2 : 3/32 */
+#define CBREF1_3 (0x0300) /* Comp. B Int. Ref.1 Select 3 : 4/32 */
+#define CBREF1_4 (0x0400) /* Comp. B Int. Ref.1 Select 4 : 5/32 */
+#define CBREF1_5 (0x0500) /* Comp. B Int. Ref.1 Select 5 : 6/32 */
+#define CBREF1_6 (0x0600) /* Comp. B Int. Ref.1 Select 6 : 7/32 */
+#define CBREF1_7 (0x0700) /* Comp. B Int. Ref.1 Select 7 : 8/32 */
+#define CBREF1_8 (0x0800) /* Comp. B Int. Ref.1 Select 0 : 9/32 */
+#define CBREF1_9 (0x0900) /* Comp. B Int. Ref.1 Select 1 : 10/32 */
+#define CBREF1_10 (0x0A00) /* Comp. B Int. Ref.1 Select 2 : 11/32 */
+#define CBREF1_11 (0x0B00) /* Comp. B Int. Ref.1 Select 3 : 12/32 */
+#define CBREF1_12 (0x0C00) /* Comp. B Int. Ref.1 Select 4 : 13/32 */
+#define CBREF1_13 (0x0D00) /* Comp. B Int. Ref.1 Select 5 : 14/32 */
+#define CBREF1_14 (0x0E00) /* Comp. B Int. Ref.1 Select 6 : 15/32 */
+#define CBREF1_15 (0x0F00) /* Comp. B Int. Ref.1 Select 7 : 16/32 */
+#define CBREF1_16 (0x1000) /* Comp. B Int. Ref.1 Select 0 : 17/32 */
+#define CBREF1_17 (0x1100) /* Comp. B Int. Ref.1 Select 1 : 18/32 */
+#define CBREF1_18 (0x1200) /* Comp. B Int. Ref.1 Select 2 : 19/32 */
+#define CBREF1_19 (0x1300) /* Comp. B Int. Ref.1 Select 3 : 20/32 */
+#define CBREF1_20 (0x1400) /* Comp. B Int. Ref.1 Select 4 : 21/32 */
+#define CBREF1_21 (0x1500) /* Comp. B Int. Ref.1 Select 5 : 22/32 */
+#define CBREF1_22 (0x1600) /* Comp. B Int. Ref.1 Select 6 : 23/32 */
+#define CBREF1_23 (0x1700) /* Comp. B Int. Ref.1 Select 7 : 24/32 */
+#define CBREF1_24 (0x1800) /* Comp. B Int. Ref.1 Select 0 : 25/32 */
+#define CBREF1_25 (0x1900) /* Comp. B Int. Ref.1 Select 1 : 26/32 */
+#define CBREF1_26 (0x1A00) /* Comp. B Int. Ref.1 Select 2 : 27/32 */
+#define CBREF1_27 (0x1B00) /* Comp. B Int. Ref.1 Select 3 : 28/32 */
+#define CBREF1_28 (0x1C00) /* Comp. B Int. Ref.1 Select 4 : 29/32 */
+#define CBREF1_29 (0x1D00) /* Comp. B Int. Ref.1 Select 5 : 30/32 */
+#define CBREF1_30 (0x1E00) /* Comp. B Int. Ref.1 Select 6 : 31/32 */
+#define CBREF1_31 (0x1F00) /* Comp. B Int. Ref.1 Select 7 : 32/32 */
+
+#define CBREFL_0 (0x0000) /* Comp. B Reference voltage level 0 : None */
+#define CBREFL_1 (0x2000) /* Comp. B Reference voltage level 1 : 1.5V */
+#define CBREFL_2 (0x4000) /* Comp. B Reference voltage level 2 : 2.0V */
+#define CBREFL_3 (0x6000) /* Comp. B Reference voltage level 3 : 2.5V */
+
+#define CBPD0 (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */
+#define CBPD1 (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */
+#define CBPD2 (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */
+#define CBPD3 (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */
+#define CBPD4 (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */
+#define CBPD5 (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */
+#define CBPD6 (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */
+#define CBPD7 (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */
+#define CBPD8 (0x0100) /* Comp. B Disable Input Buffer of Port Register .8 */
+#define CBPD9 (0x0200) /* Comp. B Disable Input Buffer of Port Register .9 */
+#define CBPD10 (0x0400) /* Comp. B Disable Input Buffer of Port Register .10 */
+#define CBPD11 (0x0800) /* Comp. B Disable Input Buffer of Port Register .11 */
+#define CBPD12 (0x1000) /* Comp. B Disable Input Buffer of Port Register .12 */
+#define CBPD13 (0x2000) /* Comp. B Disable Input Buffer of Port Register .13 */
+#define CBPD14 (0x4000) /* Comp. B Disable Input Buffer of Port Register .14 */
+#define CBPD15 (0x8000) /* Comp. B Disable Input Buffer of Port Register .15 */
+
+#define CBPD0_L (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */
+#define CBPD1_L (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */
+#define CBPD2_L (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */
+#define CBPD3_L (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */
+#define CBPD4_L (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */
+#define CBPD5_L (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */
+#define CBPD6_L (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */
+#define CBPD7_L (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */
+
+#define CBPD8_H (0x0001) /* Comp. B Disable Input Buffer of Port Register .8 */
+#define CBPD9_H (0x0002) /* Comp. B Disable Input Buffer of Port Register .9 */
+#define CBPD10_H (0x0004) /* Comp. B Disable Input Buffer of Port Register .10 */
+#define CBPD11_H (0x0008) /* Comp. B Disable Input Buffer of Port Register .11 */
+#define CBPD12_H (0x0010) /* Comp. B Disable Input Buffer of Port Register .12 */
+#define CBPD13_H (0x0020) /* Comp. B Disable Input Buffer of Port Register .13 */
+#define CBPD14_H (0x0040) /* Comp. B Disable Input Buffer of Port Register .14 */
+#define CBPD15_H (0x0080) /* Comp. B Disable Input Buffer of Port Register .15 */
+
+/* CBINT Control Bits */
+#define CBIFG (0x0001) /* Comp. B Interrupt Flag */
+#define CBIIFG (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */
+//#define RESERVED (0x0004) /* Comp. B */
+//#define RESERVED (0x0008) /* Comp. B */
+//#define RESERVED (0x0010) /* Comp. B */
+//#define RESERVED (0x0020) /* Comp. B */
+//#define RESERVED (0x0040) /* Comp. B */
+//#define RESERVED (0x0080) /* Comp. B */
+#define CBIE (0x0100) /* Comp. B Interrupt Enable */
+#define CBIIE (0x0200) /* Comp. B Interrupt Enable Inverted Polarity */
+//#define RESERVED (0x0400) /* Comp. B */
+//#define RESERVED (0x0800) /* Comp. B */
+//#define RESERVED (0x1000) /* Comp. B */
+//#define RESERVED (0x2000) /* Comp. B */
+//#define RESERVED (0x4000) /* Comp. B */
+//#define RESERVED (0x8000) /* Comp. B */
+
+/* CBINT Control Bits */
+#define CBIFG_L (0x0001) /* Comp. B Interrupt Flag */
+#define CBIIFG_L (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */
+//#define RESERVED (0x0004) /* Comp. B */
+//#define RESERVED (0x0008) /* Comp. B */
+//#define RESERVED (0x0010) /* Comp. B */
+//#define RESERVED (0x0020) /* Comp. B */
+//#define RESERVED (0x0040) /* Comp. B */
+//#define RESERVED (0x0080) /* Comp. B */
+//#define RESERVED (0x0400) /* Comp. B */
+//#define RESERVED (0x0800) /* Comp. B */
+//#define RESERVED (0x1000) /* Comp. B */
+//#define RESERVED (0x2000) /* Comp. B */
+//#define RESERVED (0x4000) /* Comp. B */
+//#define RESERVED (0x8000) /* Comp. B */
+
+/* CBINT Control Bits */
+//#define RESERVED (0x0004) /* Comp. B */
+//#define RESERVED (0x0008) /* Comp. B */
+//#define RESERVED (0x0010) /* Comp. B */
+//#define RESERVED (0x0020) /* Comp. B */
+//#define RESERVED (0x0040) /* Comp. B */
+//#define RESERVED (0x0080) /* Comp. B */
+#define CBIE_H (0x0001) /* Comp. B Interrupt Enable */
+#define CBIIE_H (0x0002) /* Comp. B Interrupt Enable Inverted Polarity */
+//#define RESERVED (0x0400) /* Comp. B */
+//#define RESERVED (0x0800) /* Comp. B */
+//#define RESERVED (0x1000) /* Comp. B */
+//#define RESERVED (0x2000) /* Comp. B */
+//#define RESERVED (0x4000) /* Comp. B */
+//#define RESERVED (0x8000) /* Comp. B */
+
+/* CBIV Definitions */
+#define CBIV_NONE (0x0000) /* No Interrupt pending */
+#define CBIV_CBIFG (0x0002) /* CBIFG */
+#define CBIV_CBIIFG (0x0004) /* CBIIFG */
+
+#endif /* __MSP430_COMPB_BASE__ */
+
+#endif /* __MSP430_HEADERS_COMPB_H__ */
+
--- /dev/null
+# Copyright (c) 2009-2010 People Power Co.
+# All rights reserved.
+#
+# This open source code was developed with funding from People Power Company.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# - Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# - Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the
+# distribution.
+# - Neither the name of the People Power Corporation nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# PEOPLE POWER CO. OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+# OF THE POSSIBILITY OF SUCH DAMAGE
+#
+
+"""Convert Texas Instruments header file sections to MSPGCC-format
+header files.
+
+To generate an MSPGCC header file derived from a TI header file,
+create a foo.h.in file containing the MSPGCC header for module foo,
+along with the necessary conditional inclusion directives. Into the
+body, stick the extracted text from the relevant section of the TI
+chip-specific header for a chip that incorporates the module. Update
+the address maps in this script to define the offsets for memory
+locations in this module, and run the script on the input file to
+generate the header.
+
+@author Peter A. Bigot <pab@peoplepowerco.com>
+"""
+
+import sys
+import re
+
+inf = file(sys.argv[1])
+
+# Regular expressions to recognize and extract the relevant pieces of
+# TI address definitions
+re20 = re.compile('^SFR_20BIT\((\w*)\);\s*(/\*.*\*/)')
+re16 = re.compile('^SFR_16BIT\((\w*)\);\s*(/\*.*\*/)')
+re8 = re.compile('^SFR_8BIT\((\w*)\);\s*(/\*.*\*/)')
+
+tagmap = { }
+addrmap = { }
+
+def addAddressMap (module_tag, local_map, map_tag=None):
+ global addrmap
+ global tagmap
+ if map_tag is None:
+ map_tag = module_tag
+ for (tag, offset) in local_map.items():
+ gtag = '%s%s' % (module_tag, tag)
+ addrmap[gtag] = offset
+ tagmap[gtag] = map_tag
+
+addAddressMap('RF1A', { 'IFCTL0' : 0,
+ 'IFCTL1' : 2,
+ 'IFCTL2' : 4,
+ 'IFERR' : 6,
+ 'IFERRV' : 0x0c,
+ 'IFIV' : 0x0e,
+ 'INSTRW' : 0x10,
+ 'INSTR1W' : 0x12,
+ 'INSTR2W' : 0x14,
+ 'DINW' : 0x16,
+ 'STAT0W' : 0x20,
+ 'STAT1W' : 0x22,
+ 'STAT2W' : 0x24,
+ 'DOUT0W' : 0x28,
+ 'DOUT1W' : 0x2A,
+ 'DOUT2W' : 0x2C,
+ 'IN' : 0x30,
+ 'IFG' : 0x32,
+ 'IES' : 0x34,
+ 'IE' : 0x36,
+ 'IV' : 0x38,
+ 'RXFIFO' : 0x3c,
+ 'TXFIFO' : 0x3e })
+addAddressMap('AES', { 'ACTL0' : 0x00,
+ 'ASTAT' : 0x04,
+ 'AKEY' : 0x06,
+ 'ADIN' : 0x08,
+ 'ADOUT' : 0x0a })
+addAddressMap('RTC', { 'CTL01' : 0x00,
+ 'CTL23' : 0x02,
+ 'PS0CTL' : 0x08,
+ 'PS1CTL' : 0x0a,
+ 'PS' : 0x0c,
+ 'IV' : 0x0e,
+ 'TIM0': 0x10,
+ 'TIM1' : 0x12,
+ 'DATE' : 0x14,
+ 'YEAR' : 0x16,
+ 'AMINHR' : 0x18,
+ 'ADOWDAY' : 0x1A })
+
+addAddressMap('LCDB', { 'CTL0' : 0x00,
+ 'CTL1' : 0x02,
+ 'BLKCTL' : 0x04,
+ 'MEMCTL' : 0x06,
+ 'VCTL' : 0x08,
+ 'PCTL0' : 0x0a,
+ 'PCTL1' : 0x0c,
+ 'PCTL2' : 0x0e,
+ 'PCTL3' : 0x10,
+ 'CPCTL' : 0x12,
+ 'IV' : 0x1e }, map_tag='LCD_B' )
+# LCD memory
+addAddressMap('LCD', dict([( 'M%d' % (1+_i), 0x20 + _i) for _i in xrange(26) ]), 'LCD_B')
+# LCD blinking memory
+addAddressMap('LCDB', dict([( 'M%d' % (1+_i), 0x40 + _i) for _i in xrange(26) ]), 'LCD_B')
+
+addAddressMap('REF', { 'CTL0' : 0x00 })
+
+addAddressMap('ADC12', { 'CTL0' : 0x00,
+ 'CTL1' : 0x02,
+ 'CTL2' : 0x04,
+ 'IFG' : 0x0a,
+ 'IE' : 0x0c,
+ 'IV' : 0x0e }, map_tag='ADC12_PLUS')
+addAddressMap('ADC12MEM', dict([( '%d' % (_i,), 0x20 + _i) for _i in xrange(16) ]), map_tag='ADC12_PLUS')
+addAddressMap('ADC12MCTL', dict([( '%d' % (_i,), 0x10 + _i) for _i in xrange(16) ]), map_tag='ADC12_PLUS')
+
+addAddressMap('DMA', { 'CTL0' : 0x00,
+ 'CTL1' : 0x02,
+ 'CTL2' : 0x04,
+ 'CTL3' : 0x06,
+ 'CTL4' : 0x08,
+ 'IV' : 0x0e })
+for ch in xrange(8):
+ offset = 0x0 * (1 + ch)
+ addAddressMap('DMA%d' % ch, { 'CTL' : 0x00 + offset,
+ 'SA' : 0x02 + offset,
+ 'DA' : 0x06 + offset,
+ 'SZ' : 0x0a + offset },
+ map_tag='DMA')
+
+for usci in xrange(4):
+ for (mtype, offs) in ( ('A', 0x00) , ( 'B', 0x20) ):
+ addAddressMap('UC%c%d' % (mtype, usci),
+ { 'CTLW0' : 0x00 + offs,
+ 'CTL1' : 0x00 + offs, # yes, CTL1 is at offset 0
+ 'CTL0' : 0x01 + offs, # yes, CTL0 is at offset 1
+ 'BRW' : 0x06 + offs,
+ 'BR0' : 0x06 + offs,
+ 'BR1' : 0x07 + offs,
+ 'MCTL' : 0x08 + offs,
+ 'STAT' : 0x0a + offs,
+ 'RXBUF' : 0x0c + offs,
+ 'TXBUF' : 0x0e + offs,
+ 'ICTL' : 0x1c + offs,
+ 'IFG' : 0x1d + offs,
+ 'IV' : 0x1e + offs },
+ map_tag='USCI%d' % (usci,))
+ # USCI UART-mode
+ addAddressMap('UCA%d' % (usci,),
+ { 'ABCTL' : 0x10,
+ 'IRCTL' : 0x12,
+ 'IRTCTL' : 0x12,
+ 'IRRCTL' : 0x13 },
+ map_tag='USCI%d' % (usci,))
+ # USCI I2C mode
+ addAddressMap('UCB%d' % (usci,),
+ { 'I2COA' : 0x30,
+ 'I2CSA' : 0x32 },
+ map_tag='USCI%d' % (usci,))
+
+addAddressMap('CB', { 'CTL0' : 0x00,
+ 'CTL1' : 0x02,
+ 'CTL2' : 0x04,
+ 'CTL3' : 0x06,
+ 'INT' : 0x0c,
+ 'IV' : 0x0e },
+ map_tag='COMPB')
+
+
+for ln in inf.readlines():
+ word_id = 'w'
+ mo = re16.match(ln)
+ if not mo:
+ # NOTE: Headers generated for MSP430X will need hand-editing
+ # to support on MSP430. If __MSP430_HAS_DMAX_3__ is defined,
+ # include both the 20- and 16-bit names as generated.
+ # Otherwise, use the 20-bit name on the 16-bit register.
+ mo = re20.match(ln)
+ word_id = 'a'
+ if mo:
+ (tag, comment) = mo.groups()
+ xtag = tag
+ addr = addrmap.get(xtag)
+ if (addr is None) and xtag.endswith('L'):
+ xtag = xtag[:-1]
+ addr = addrmap[xtag]
+ maptag = tagmap[xtag]
+ if 'a' == word_id:
+ print '#if defined(__MSP430_HAS_DMAX_3__)'
+ print '''#define %s_ __MSP430_%s_BASE__ + 0x%02x %s
+sfr%s(%s, %s_);''' % (tag, maptag, addr, comment, word_id, tag, tag)
+ if 'a' == word_id:
+ print '#endif // __MSP430_HAS_DMAX_3__'
+ continue
+ mo = re8.match(ln)
+ if mo:
+ (tag, comment) = mo.groups()
+ assert tag.find('_'), tag
+ maptag = tagmap.get(tag)
+ if tag.find('_'):
+ try:
+ (rtag, stag) = tag.split('_')
+ addr = addrmap[rtag]
+ maptag = tagmap[rtag]
+ if 'H' == stag:
+ addr += 1
+ comment = ''
+ except ValueError:
+ addr = addrmap[tag]
+ else:
+ addr = addrmap[tag]
+ print '''#define %s_ __MSP430_%s_BASE__ + 0x%02x %s
+sfrb(%s, %s_);''' % (tag, maptag, addr, comment, tag, tag)
+ continue
+ print ln[:-1]
--- /dev/null
+#ifndef __MSP430_HEADERS_CRC16_H
+#define __MSP430_HEADERS_CRC16_H
+
+/* crc16.h
+ *
+ * mspgcc project: MSP430 device headers
+ * hardware CRC module
+ *
+ * (c) 2009 by J.M.Gross <mspgcc@grossibaer.de>
+ * Originally based on MSP430x5xx Family User's Guide (slau208b).
+ *
+ * $Id: crc16.h,v 1.0 2009/10/08 23:00:38 Exp $
+ */
+
+/* Switches:
+
+__MSP430_CRC16_BASE__ - base address of CRC16 module.
+
+*/
+
+#if defined(__MSP430_CRC16_BASE__)
+#define CRCDI_ __MSP430_CRC16_BASE__ + 0x00 /* CRC Data in (word) */
+sfrw(CRCDI, CRCDI_);
+sfrb(CRCDI_L, CRCDI_);
+sfrb(CRCDI_H, CRCDI_+1);
+#define CRCDIRB_ __MSP430_CRC16_BASE__ + 0x02 /* CRC Data in reverse bit(word) */
+sfrw(CRCDIRB, CRCDIRB_);
+sfrb(CRCDIRB_L, CRCDIRB_);
+sfrb(CRCDIRB_H, CRCDIRB_+1);
+#define CRCINIRES_ __MSP430_CRC16_BASE__ + 0x04 /* CRC initialisation and result */
+sfrw(CRCINIRES, CRCINIRES_);
+sfrb(CRCINIRES_L, CRCINIRES_);
+sfrb(CRCINIRES_H, CRCINIRES_+1);
+#define CRCRESR_ __MSP430_CRC16_BASE__ + 0x06 /* CRC result reverse */
+sfrw(CRCRESR, CRCRESR_);
+sfrb(CRCRESR_L, CRCRESR_);
+sfrb(CRCRESR_H, CRCRESR_+1);
+#endif
+
+#endif /* __MSP430_HEADERS_CRC16_H */
* (c) 2002 by Steve Udnerwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: dma.h,v 1.7 2007/07/11 17:38:19 coppice Exp $
+ * $Id: dma.h,v 1.8 2008/11/07 08:28:40 sb-sf Exp $
*/
-/* Switches: none */
+/* Switches:
+
+__MSP430_HAS_DMAIV__ - if the device has a DMAIV register
+__MSP430_HAS_DMA_3__ - if module has 16-bit address registers
+__MSP430_HAS_DMAX_3__ - if module has 20-bit address registers (430X core)
+
+ */
#define DMACTL0_ 0x0122 /* DMA module control 0 */
sfrw(DMACTL0,DMACTL0_);
#define DMACTL1_ 0x0124 /* DMA module control 1 */
sfrw(DMACTL1, DMACTL1_);
+#if defined(__MSP430_HAS_DMAIV__)
+#define DMAIV_ 0x0126 /* DMA module interrupt vector word */
+sfrw(DMAIV, DMAIV_);
+#endif
#if defined(__MSP430_HAS_DMA_3__)
#define DMA0CTL_ 0x01E0 /* DMA channel 0 control */
sfrw(DMA2SZ, DMA2SZ_);
#endif
-#define SREF_0 (0<<4)
-#define SREF_1 (1<<4)
-#define SREF_2 (2<<4)
-#define SREF_3 (3<<4)
-#define SREF_4 (4<<4)
-#define SREF_5 (5<<4)
-#define SREF_6 (6<<4)
-#define SREF_7 (7<<4)
-#define EOS 0x80
-
#define DMA0TSEL0 0x0001 /* DMA channel 0 transfer select bit 0 */
#define DMA0TSEL1 0x0002 /* DMA channel 0 transfer select bit 1 */
#define DMA0TSEL2 0x0004 /* DMA channel 0 transfer select bit 2 */
--- /dev/null
+#if !defined(__MSP430_HEADERS_DMAX_H__)
+#define __MSP430_HEADERS_DMAX_H__
+
+/* dmax.h
+ *
+ * mspgcc project: MSP430 device headers
+ * Real-Time Clock
+ *
+ * Based on cc430x613x.h version 1.5 by Texas Instruments
+ *
+ * NOTE: This header file is intended for 16- and 20-bit MSP430X
+ * processors. For systems that support only 8-bit memory access, use
+ * <msp430/dma.h>.
+ *
+ * Peter A. Bigot <pab@peoplepowerco.com>
+ *
+ */
+
+/* Switches:
+__MSP430_HAS_DMA_3__ - if module has 16-bit address registers
+__MSP430_HAS_DMAX_3__ - if module has 20-bit address registers (430X core)
+__MSP430_DMA_BASE__ - base address of DMA module
+*/
+
+#if defined(__MSP430_DMA_BASE__)
+
+#define DMACTL0_ __MSP430_DMA_BASE__ + 0x00 /* DMA Module Control 0 */
+sfrw(DMACTL0, DMACTL0_);
+#define DMACTL0_L_ __MSP430_DMA_BASE__ + 0x00
+sfrb(DMACTL0_L, DMACTL0_L_);
+#define DMACTL0_H_ __MSP430_DMA_BASE__ + 0x01
+sfrb(DMACTL0_H, DMACTL0_H_);
+#define DMACTL1_ __MSP430_DMA_BASE__ + 0x02 /* DMA Module Control 1 */
+sfrw(DMACTL1, DMACTL1_);
+#define DMACTL1_L_ __MSP430_DMA_BASE__ + 0x02
+sfrb(DMACTL1_L, DMACTL1_L_);
+#define DMACTL1_H_ __MSP430_DMA_BASE__ + 0x03
+sfrb(DMACTL1_H, DMACTL1_H_);
+#define DMACTL2_ __MSP430_DMA_BASE__ + 0x04 /* DMA Module Control 2 */
+sfrw(DMACTL2, DMACTL2_);
+#define DMACTL2_L_ __MSP430_DMA_BASE__ + 0x04
+sfrb(DMACTL2_L, DMACTL2_L_);
+#define DMACTL2_H_ __MSP430_DMA_BASE__ + 0x05
+sfrb(DMACTL2_H, DMACTL2_H_);
+#define DMACTL3_ __MSP430_DMA_BASE__ + 0x06 /* DMA Module Control 3 */
+sfrw(DMACTL3, DMACTL3_);
+#define DMACTL3_L_ __MSP430_DMA_BASE__ + 0x06
+sfrb(DMACTL3_L, DMACTL3_L_);
+#define DMACTL3_H_ __MSP430_DMA_BASE__ + 0x07
+sfrb(DMACTL3_H, DMACTL3_H_);
+#define DMACTL4_ __MSP430_DMA_BASE__ + 0x08 /* DMA Module Control 4 */
+sfrw(DMACTL4, DMACTL4_);
+#define DMACTL4_L_ __MSP430_DMA_BASE__ + 0x08
+sfrb(DMACTL4_L, DMACTL4_L_);
+#define DMACTL4_H_ __MSP430_DMA_BASE__ + 0x09
+sfrb(DMACTL4_H, DMACTL4_H_);
+#define DMAIV_ __MSP430_DMA_BASE__ + 0x0e /* DMA Interrupt Vector Word */
+sfrw(DMAIV, DMAIV_);
+#define DMAIV_L_ __MSP430_DMA_BASE__ + 0x0e
+sfrb(DMAIV_L, DMAIV_L_);
+#define DMAIV_H_ __MSP430_DMA_BASE__ + 0x0f
+sfrb(DMAIV_H, DMAIV_H_);
+
+#define DMA0CTL_ __MSP430_DMA_BASE__ + 0x00 /* DMA Channel 0 Control */
+sfrw(DMA0CTL, DMA0CTL_);
+#define DMA0CTL_L_ __MSP430_DMA_BASE__ + 0x00
+sfrb(DMA0CTL_L, DMA0CTL_L_);
+#define DMA0CTL_H_ __MSP430_DMA_BASE__ + 0x01
+sfrb(DMA0CTL_H, DMA0CTL_H_);
+
+#define DMA0SA_ __MSP430_DMA_BASE__ + 0x02 /* DMA Channel 0 Source Address */
+#if defined(__MSP430_HAS_DMAX_3__)
+sfra(DMA0SA, DMA0SA_);
+#define DMA0SAL_ __MSP430_DMA_BASE__ + 0x02 /* DMA Channel 0 Source Address */
+sfrw(DMA0SAL, DMA0SAL_);
+#else // __MSP430_HAS_DMAX_3__
+sfrw(DMA0SA, DMA0SA_);
+#endif // __MSP430_HAS_DMAX_3__
+
+#define DMA0DA_ __MSP430_DMA_BASE__ + 0x06 /* DMA Channel 0 Destination Address */
+#if defined(__MSP430_HAS_DMAX_3__)
+sfra(DMA0DA, DMA0DA_);
+#define DMA0DAL_ __MSP430_DMA_BASE__ + 0x06 /* DMA Channel 0 Destination Address */
+sfrw(DMA0DAL, DMA0DAL_);
+#else // __MSP430_HAS_DMAX_3__
+sfrw(DMA0DA, DMA0DA_);
+#endif // __MSP430_HAS_DMAX_3__
+
+#define DMA0SZ_ __MSP430_DMA_BASE__ + 0x0a /* DMA Channel 0 Transfer Size */
+sfrw(DMA0SZ, DMA0SZ_);
+#define DMA0SZ_L_ __MSP430_DMA_BASE__ + 0x0a
+sfrb(DMA0SZ_L, DMA0SZ_L_);
+#define DMA0SZ_H_ __MSP430_DMA_BASE__ + 0x0b
+sfrb(DMA0SZ_H, DMA0SZ_H_);
+
+#define DMA1CTL_ __MSP430_DMA_BASE__ + 0x00 /* DMA Channel 1 Control */
+sfrw(DMA1CTL, DMA1CTL_);
+#define DMA1CTL_L_ __MSP430_DMA_BASE__ + 0x00
+sfrb(DMA1CTL_L, DMA1CTL_L_);
+#define DMA1CTL_H_ __MSP430_DMA_BASE__ + 0x01
+sfrb(DMA1CTL_H, DMA1CTL_H_);
+#if defined(__MSP430_HAS_DMAX_3__)
+#define DMA1SA_ __MSP430_DMA_BASE__ + 0x02 /* DMA Channel 1 Source Address */
+sfra(DMA1SA, DMA1SA_);
+#endif // __MSP430_HAS_DMAX_3__
+#define DMA1SAL_ __MSP430_DMA_BASE__ + 0x02 /* DMA Channel 1 Source Address */
+sfrw(DMA1SAL, DMA1SAL_);
+
+#define DMA1DA_ __MSP430_DMA_BASE__ + 0x06 /* DMA Channel 1 Destination Address */
+#if defined(__MSP430_HAS_DMAX_3__)
+sfra(DMA1DA, DMA1DA_);
+#define DMA1DAL_ __MSP430_DMA_BASE__ + 0x06 /* DMA Channel 1 Destination Address */
+sfrw(DMA1DAL, DMA1DAL_);
+#else // __MSP430_HAS_DMAX_3__
+sfrw(DMA1DA, DMA1DA_);
+#endif // __MSP430_HAS_DMAX_3__
+
+#define DMA1SZ_ __MSP430_DMA_BASE__ + 0x0a /* DMA Channel 1 Transfer Size */
+sfrw(DMA1SZ, DMA1SZ_);
+#define DMA1SZ_L_ __MSP430_DMA_BASE__ + 0x0a
+sfrb(DMA1SZ_L, DMA1SZ_L_);
+#define DMA1SZ_H_ __MSP430_DMA_BASE__ + 0x0b
+sfrb(DMA1SZ_H, DMA1SZ_H_);
+
+#define DMA2CTL_ __MSP430_DMA_BASE__ + 0x00 /* DMA Channel 2 Control */
+sfrw(DMA2CTL, DMA2CTL_);
+#define DMA2CTL_L_ __MSP430_DMA_BASE__ + 0x00
+sfrb(DMA2CTL_L, DMA2CTL_L_);
+#define DMA2CTL_H_ __MSP430_DMA_BASE__ + 0x01
+sfrb(DMA2CTL_H, DMA2CTL_H_);
+
+#define DMA2SA_ __MSP430_DMA_BASE__ + 0x02 /* DMA Channel 2 Source Address */
+#if defined(__MSP430_HAS_DMAX_3__)
+sfra(DMA2SA, DMA2SA_);
+#define DMA2SAL_ __MSP430_DMA_BASE__ + 0x02 /* DMA Channel 2 Source Address */
+sfrw(DMA2SAL, DMA2SAL_);
+#else // __MSP430_HAS_DMAX_3__
+sfrw(DMA2SA, DMA2SA_);
+#endif // __MSP430_HAS_DMAX_3__
+
+#define DMA2DA_ __MSP430_DMA_BASE__ + 0x06 /* DMA Channel 2 Destination Address */
+#if defined(__MSP430_HAS_DMAX_3__)
+sfra(DMA2DA, DMA2DA_);
+#define DMA2DAL_ __MSP430_DMA_BASE__ + 0x06 /* DMA Channel 2 Destination Address */
+sfrw(DMA2DAL, DMA2DAL_);
+#else // __MSP430_HAS_DMAX_3__
+sfrw(DMA2DA, DMA2DA_);
+#endif // __MSP430_HAS_DMAX_3__
+
+#define DMA2SZ_ __MSP430_DMA_BASE__ + 0x0a /* DMA Channel 2 Transfer Size */
+sfrw(DMA2SZ, DMA2SZ_);
+#define DMA2SZ_L_ __MSP430_DMA_BASE__ + 0x0a
+sfrb(DMA2SZ_L, DMA2SZ_L_);
+#define DMA2SZ_H_ __MSP430_DMA_BASE__ + 0x0b
+sfrb(DMA2SZ_H, DMA2SZ_H_);
+
+/* DMACTL0 Control Bits */
+#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */
+#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */
+#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */
+#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */
+#define DMA0TSEL4 (0x0010) /* DMA channel 0 transfer select bit 4 */
+#define DMA1TSEL0 (0x0100) /* DMA channel 1 transfer select bit 0 */
+#define DMA1TSEL1 (0x0200) /* DMA channel 1 transfer select bit 1 */
+#define DMA1TSEL2 (0x0400) /* DMA channel 1 transfer select bit 2 */
+#define DMA1TSEL3 (0x0800) /* DMA channel 1 transfer select bit 3 */
+#define DMA1TSEL4 (0x1000) /* DMA channel 1 transfer select bit 4 */
+
+/* DMACTL0 Control Bits */
+#define DMA0TSEL0_L (0x0001) /* DMA channel 0 transfer select bit 0 */
+#define DMA0TSEL1_L (0x0002) /* DMA channel 0 transfer select bit 1 */
+#define DMA0TSEL2_L (0x0004) /* DMA channel 0 transfer select bit 2 */
+#define DMA0TSEL3_L (0x0008) /* DMA channel 0 transfer select bit 3 */
+#define DMA0TSEL4_L (0x0010) /* DMA channel 0 transfer select bit 4 */
+
+/* DMACTL0 Control Bits */
+#define DMA1TSEL0_H (0x0001) /* DMA channel 1 transfer select bit 0 */
+#define DMA1TSEL1_H (0x0002) /* DMA channel 1 transfer select bit 1 */
+#define DMA1TSEL2_H (0x0004) /* DMA channel 1 transfer select bit 2 */
+#define DMA1TSEL3_H (0x0008) /* DMA channel 1 transfer select bit 3 */
+#define DMA1TSEL4_H (0x0010) /* DMA channel 1 transfer select bit 4 */
+
+/* DMACTL01 Control Bits */
+#define DMA2TSEL0 (0x0001) /* DMA channel 2 transfer select bit 0 */
+#define DMA2TSEL1 (0x0002) /* DMA channel 2 transfer select bit 1 */
+#define DMA2TSEL2 (0x0004) /* DMA channel 2 transfer select bit 2 */
+#define DMA2TSEL3 (0x0008) /* DMA channel 2 transfer select bit 3 */
+#define DMA2TSEL4 (0x0010) /* DMA channel 2 transfer select bit 4 */
+
+/* DMACTL01 Control Bits */
+#define DMA2TSEL0_L (0x0001) /* DMA channel 2 transfer select bit 0 */
+#define DMA2TSEL1_L (0x0002) /* DMA channel 2 transfer select bit 1 */
+#define DMA2TSEL2_L (0x0004) /* DMA channel 2 transfer select bit 2 */
+#define DMA2TSEL3_L (0x0008) /* DMA channel 2 transfer select bit 3 */
+#define DMA2TSEL4_L (0x0010) /* DMA channel 2 transfer select bit 4 */
+
+/* DMACTL01 Control Bits */
+
+/* DMACTL4 Control Bits */
+#define ENNMI (0x0001) /* Enable NMI interruption of DMA */
+#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */
+#define DMARMWDIS (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
+
+/* DMACTL4 Control Bits */
+#define ENNMI_L (0x0001) /* Enable NMI interruption of DMA */
+#define ROUNDROBIN_L (0x0002) /* Round-Robin DMA channel priorities */
+#define DMARMWDIS_L (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
+
+/* DMACTL4 Control Bits */
+
+/* DMAxCTL Control Bits */
+#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */
+#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */
+#define DMAIE (0x0004) /* DMA interrupt enable */
+#define DMAIFG (0x0008) /* DMA interrupt flag */
+#define DMAEN (0x0010) /* DMA enable */
+#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */
+#define DMASRCBYTE (0x0040) /* DMA source byte */
+#define DMADSTBYTE (0x0080) /* DMA destination byte */
+#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */
+#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */
+#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */
+#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */
+#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */
+#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */
+#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */
+
+/* DMAxCTL Control Bits */
+#define DMAREQ_L (0x0001) /* Initiate DMA transfer with DMATSEL */
+#define DMAABORT_L (0x0002) /* DMA transfer aborted by NMI */
+#define DMAIE_L (0x0004) /* DMA interrupt enable */
+#define DMAIFG_L (0x0008) /* DMA interrupt flag */
+#define DMAEN_L (0x0010) /* DMA enable */
+#define DMALEVEL_L (0x0020) /* DMA level sensitive trigger select */
+#define DMASRCBYTE_L (0x0040) /* DMA source byte */
+#define DMADSTBYTE_L (0x0080) /* DMA destination byte */
+
+/* DMAxCTL Control Bits */
+#define DMASRCINCR0_H (0x0001) /* DMA source increment bit 0 */
+#define DMASRCINCR1_H (0x0002) /* DMA source increment bit 1 */
+#define DMADSTINCR0_H (0x0004) /* DMA destination increment bit 0 */
+#define DMADSTINCR1_H (0x0008) /* DMA destination increment bit 1 */
+#define DMADT0_H (0x0010) /* DMA transfer mode bit 0 */
+#define DMADT1_H (0x0020) /* DMA transfer mode bit 1 */
+#define DMADT2_H (0x0040) /* DMA transfer mode bit 2 */
+
+#define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */
+#define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */
+#define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */
+#define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */
+
+#define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */
+#define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */
+#define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */
+#define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */
+
+#define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */
+#define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */
+#define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */
+#define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */
+
+#define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */
+#define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */
+#define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */
+#define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */
+#define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */
+#define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */
+#define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */
+#define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */
+
+/* DMAIV Definitions */
+#define DMAIV_NONE (0x0000) /* No Interrupt pending */
+#define DMAIV_DMA0IFG (0x0002) /* DMA0IFG*/
+#define DMAIV_DMA1IFG (0x0004) /* DMA1IFG*/
+#define DMAIV_DMA2IFG (0x0006) /* DMA2IFG*/
+
+#define DMA0TSEL_0 (0*0x0001u) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */
+#define DMA0TSEL_1 (1*0x0001u) /* DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG) */
+#define DMA0TSEL_2 (2*0x0001u) /* DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG) */
+#define DMA0TSEL_3 (3*0x0001u) /* DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG) */
+#define DMA0TSEL_4 (4*0x0001u) /* DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG) */
+#define DMA0TSEL_5 (5*0x0001u) /* DMA channel 0 transfer select 5: TimerB (TB0CCR0.IFG) */
+#define DMA0TSEL_6 (6*0x0001u) /* DMA channel 0 transfer select 6: TimerB (TB0CCR2.IFG) */
+#define DMA0TSEL_7 (7*0x0001u) /* DMA channel 0 transfer select 7: Reserved */
+#define DMA0TSEL_8 (8*0x0001u) /* DMA channel 0 transfer select 8: Reserved */
+#define DMA0TSEL_9 (9*0x0001u) /* DMA channel 0 transfer select 9: Reserved */
+#define DMA0TSEL_10 (10*0x0001u) /* DMA channel 0 transfer select 10: Reserved */
+#define DMA0TSEL_11 (11*0x0001u) /* DMA channel 0 transfer select 11: Reserved */
+#define DMA0TSEL_12 (12*0x0001u) /* DMA channel 0 transfer select 12: Reserved */
+#define DMA0TSEL_13 (13*0x0001u) /* DMA channel 0 transfer select 13: Reserved */
+#define DMA0TSEL_14 (14*0x0001u) /* DMA channel 0 transfer select 14: RFRXIFG */
+#define DMA0TSEL_15 (15*0x0001u) /* DMA channel 0 transfer select 15: RFTXIFG */
+#define DMA0TSEL_16 (16*0x0001u) /* DMA channel 0 transfer select 16: USCIA0 receive */
+#define DMA0TSEL_17 (17*0x0001u) /* DMA channel 0 transfer select 17: USCIA0 transmit */
+#define DMA0TSEL_18 (18*0x0001u) /* DMA channel 0 transfer select 18: USCIB0 receive */
+#define DMA0TSEL_19 (19*0x0001u) /* DMA channel 0 transfer select 19: USCIB0 transmit */
+#define DMA0TSEL_20 (20*0x0001u) /* DMA channel 0 transfer select 20: Reserved */
+#define DMA0TSEL_21 (21*0x0001u) /* DMA channel 0 transfer select 21: Reserved */
+#define DMA0TSEL_22 (22*0x0001u) /* DMA channel 0 transfer select 22: Reserved */
+#define DMA0TSEL_23 (23*0x0001u) /* DMA channel 0 transfer select 23: Reserved */
+#define DMA0TSEL_24 (24*0x0001u) /* DMA channel 0 transfer select 24: ADC12IFGx */
+#define DMA0TSEL_25 (25*0x0001u) /* DMA channel 0 transfer select 25: Reserved */
+#define DMA0TSEL_26 (26*0x0001u) /* DMA channel 0 transfer select 26: Reserved */
+#define DMA0TSEL_27 (27*0x0001u) /* DMA channel 0 transfer select 27: Reserved */
+#define DMA0TSEL_28 (28*0x0001u) /* DMA channel 0 transfer select 28: Reserved */
+#define DMA0TSEL_29 (29*0x0001u) /* DMA channel 0 transfer select 29: Multiplier ready */
+#define DMA0TSEL_30 (30*0x0001u) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
+#define DMA0TSEL_31 (31*0x0001u) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA1TSEL_0 (0*0x0100u) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */
+#define DMA1TSEL_1 (1*0x0100u) /* DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG) */
+#define DMA1TSEL_2 (2*0x0100u) /* DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG) */
+#define DMA1TSEL_3 (3*0x0100u) /* DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG) */
+#define DMA1TSEL_4 (4*0x0100u) /* DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG) */
+#define DMA1TSEL_5 (5*0x0100u) /* DMA channel 1 transfer select 5: TimerB (TB0CCR0.IFG) */
+#define DMA1TSEL_6 (6*0x0100u) /* DMA channel 1 transfer select 6: TimerB (TB0CCR2.IFG) */
+#define DMA1TSEL_7 (7*0x0100u) /* DMA channel 1 transfer select 7: Reserved */
+#define DMA1TSEL_8 (8*0x0100u) /* DMA channel 1 transfer select 8: Reserved */
+#define DMA1TSEL_9 (9*0x0100u) /* DMA channel 1 transfer select 9: Reserved */
+#define DMA1TSEL_10 (10*0x0100u) /* DMA channel 1 transfer select 10: Reserved */
+#define DMA1TSEL_11 (11*0x0100u) /* DMA channel 1 transfer select 11: Reserved */
+#define DMA1TSEL_12 (12*0x0100u) /* DMA channel 1 transfer select 12: Reserved */
+#define DMA1TSEL_13 (13*0x0100u) /* DMA channel 1 transfer select 13: Reserved */
+#define DMA1TSEL_14 (14*0x0100u) /* DMA channel 1 transfer select 14: RFRXIFG */
+#define DMA1TSEL_15 (15*0x0100u) /* DMA channel 1 transfer select 15: RFTXIFG */
+#define DMA1TSEL_16 (16*0x0100u) /* DMA channel 1 transfer select 16: USCIA0 receive */
+#define DMA1TSEL_17 (17*0x0100u) /* DMA channel 1 transfer select 17: USCIA0 transmit */
+#define DMA1TSEL_18 (18*0x0100u) /* DMA channel 1 transfer select 18: USCIB0 receive */
+#define DMA1TSEL_19 (19*0x0100u) /* DMA channel 1 transfer select 19: USCIB0 transmit */
+#define DMA1TSEL_20 (20*0x0100u) /* DMA channel 1 transfer select 20: Reserved */
+#define DMA1TSEL_21 (21*0x0100u) /* DMA channel 1 transfer select 21: Reserved */
+#define DMA1TSEL_22 (22*0x0100u) /* DMA channel 1 transfer select 22: Reserved */
+#define DMA1TSEL_23 (23*0x0100u) /* DMA channel 1 transfer select 23: Reserved */
+#define DMA1TSEL_24 (24*0x0100u) /* DMA channel 1 transfer select 24: ADC12IFGx */
+#define DMA1TSEL_25 (25*0x0100u) /* DMA channel 1 transfer select 25: Reserved */
+#define DMA1TSEL_26 (26*0x0100u) /* DMA channel 1 transfer select 26: Reserved */
+#define DMA1TSEL_27 (27*0x0100u) /* DMA channel 1 transfer select 27: Reserved */
+#define DMA1TSEL_28 (28*0x0100u) /* DMA channel 1 transfer select 28: Reserved */
+#define DMA1TSEL_29 (29*0x0100u) /* DMA channel 1 transfer select 29: Multiplier ready */
+#define DMA1TSEL_30 (30*0x0100u) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
+#define DMA1TSEL_31 (31*0x0100u) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA2TSEL_0 (0*0x0001u) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */
+#define DMA2TSEL_1 (1*0x0001u) /* DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG) */
+#define DMA2TSEL_2 (2*0x0001u) /* DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG) */
+#define DMA2TSEL_3 (3*0x0001u) /* DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG) */
+#define DMA2TSEL_4 (4*0x0001u) /* DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG) */
+#define DMA2TSEL_5 (5*0x0001u) /* DMA channel 2 transfer select 5: TimerB (TB0CCR0.IFG) */
+#define DMA2TSEL_6 (6*0x0001u) /* DMA channel 2 transfer select 6: TimerB (TB0CCR2.IFG) */
+#define DMA2TSEL_7 (7*0x0001u) /* DMA channel 2 transfer select 7: Reserved */
+#define DMA2TSEL_8 (8*0x0001u) /* DMA channel 2 transfer select 8: Reserved */
+#define DMA2TSEL_9 (9*0x0001u) /* DMA channel 2 transfer select 9: Reserved */
+#define DMA2TSEL_10 (10*0x0001u) /* DMA channel 2 transfer select 10: Reserved */
+#define DMA2TSEL_11 (11*0x0001u) /* DMA channel 2 transfer select 11: Reserved */
+#define DMA2TSEL_12 (12*0x0001u) /* DMA channel 2 transfer select 12: Reserved */
+#define DMA2TSEL_13 (13*0x0001u) /* DMA channel 2 transfer select 13: Reserved */
+#define DMA2TSEL_14 (14*0x0001u) /* DMA channel 2 transfer select 14: RFRXIFG */
+#define DMA2TSEL_15 (15*0x0001u) /* DMA channel 2 transfer select 15: RFTXIFG */
+#define DMA2TSEL_16 (16*0x0001u) /* DMA channel 2 transfer select 16: USCIA0 receive */
+#define DMA2TSEL_17 (17*0x0001u) /* DMA channel 2 transfer select 17: USCIA0 transmit */
+#define DMA2TSEL_18 (18*0x0001u) /* DMA channel 2 transfer select 18: USCIB0 receive */
+#define DMA2TSEL_19 (19*0x0001u) /* DMA channel 2 transfer select 19: USCIB0 transmit */
+#define DMA2TSEL_20 (20*0x0001u) /* DMA channel 2 transfer select 20: Reserved */
+#define DMA2TSEL_21 (21*0x0001u) /* DMA channel 2 transfer select 21: Reserved */
+#define DMA2TSEL_22 (22*0x0001u) /* DMA channel 2 transfer select 22: Reserved */
+#define DMA2TSEL_23 (23*0x0001u) /* DMA channel 2 transfer select 23: Reserved */
+#define DMA2TSEL_24 (24*0x0001u) /* DMA channel 2 transfer select 24: ADC12IFGx */
+#define DMA2TSEL_25 (25*0x0001u) /* DMA channel 2 transfer select 25: Reserved */
+#define DMA2TSEL_26 (26*0x0001u) /* DMA channel 2 transfer select 26: Reserved */
+#define DMA2TSEL_27 (27*0x0001u) /* DMA channel 2 transfer select 27: Reserved */
+#define DMA2TSEL_28 (28*0x0001u) /* DMA channel 2 transfer select 28: Reserved */
+#define DMA2TSEL_29 (29*0x0001u) /* DMA channel 2 transfer select 29: Multiplier ready */
+#define DMA2TSEL_30 (30*0x0001u) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
+#define DMA2TSEL_31 (31*0x0001u) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA0TSEL__DMA_REQ (0*0x0001u) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */
+#define DMA0TSEL__TA0CCR0 (1*0x0001u) /* DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG) */
+#define DMA0TSEL__TA0CCR2 (2*0x0001u) /* DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG) */
+#define DMA0TSEL__TA1CCR0 (3*0x0001u) /* DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG) */
+#define DMA0TSEL__TA1CCR2 (4*0x0001u) /* DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG) */
+#define DMA0TSEL__TB0CCR0 (5*0x0001u) /* DMA channel 0 transfer select 5: TimerB (TB0CCR0.IFG) */
+#define DMA0TSEL__TB0CCR2 (6*0x0001u) /* DMA channel 0 transfer select 6: TimerB (TB0CCR2.IFG) */
+#define DMA0TSEL__RES7 (7*0x0001u) /* DMA channel 0 transfer select 7: Reserved */
+#define DMA0TSEL__RES8 (8*0x0001u) /* DMA channel 0 transfer select 8: Reserved */
+#define DMA0TSEL__RES9 (9*0x0001u) /* DMA channel 0 transfer select 9: Reserved */
+#define DMA0TSEL__RES10 (10*0x0001u) /* DMA channel 0 transfer select 10: Reserved */
+#define DMA0TSEL__RES11 (11*0x0001u) /* DMA channel 0 transfer select 11: Reserved */
+#define DMA0TSEL__RES12 (12*0x0001u) /* DMA channel 0 transfer select 12: Reserved */
+#define DMA0TSEL__RES13 (13*0x0001u) /* DMA channel 0 transfer select 13: Reserved */
+#define DMA0TSEL__RFRXIFG (14*0x0001u) /* DMA channel 0 transfer select 14: RFRXIFG */
+#define DMA0TSEL__RFTXIFG (15*0x0001u) /* DMA channel 0 transfer select 15: RFTXIFG */
+#define DMA0TSEL__USCIA0RX (16*0x0001u) /* DMA channel 0 transfer select 16: USCIA0 receive */
+#define DMA0TSEL__USCIA0TX (17*0x0001u) /* DMA channel 0 transfer select 17: USCIA0 transmit */
+#define DMA0TSEL__USCIB0RX (18*0x0001u) /* DMA channel 0 transfer select 18: USCIB0 receive */
+#define DMA0TSEL__USCIB0TX (19*0x0001u) /* DMA channel 0 transfer select 19: USCIB0 transmit */
+#define DMA0TSEL__RES20 (20*0x0001u) /* DMA channel 0 transfer select 20: Reserved */
+#define DMA0TSEL__RES21 (21*0x0001u) /* DMA channel 0 transfer select 21: Reserved */
+#define DMA0TSEL__RES22 (22*0x0001u) /* DMA channel 0 transfer select 22: Reserved */
+#define DMA0TSEL__RES23 (23*0x0001u) /* DMA channel 0 transfer select 23: Reserved */
+#define DMA0TSEL__ADC12IFG (24*0x0001u) /* DMA channel 0 transfer select 24: ADC12IFGx */
+#define DMA0TSEL__RES25 (25*0x0001u) /* DMA channel 0 transfer select 25: Reserved */
+#define DMA0TSEL__RES26 (26*0x0001u) /* DMA channel 0 transfer select 26: Reserved */
+#define DMA0TSEL__RES27 (27*0x0001u) /* DMA channel 0 transfer select 27: Reserved */
+#define DMA0TSEL__RES28 (28*0x0001u) /* DMA channel 0 transfer select 28: Reserved */
+#define DMA0TSEL__MPY (29*0x0001u) /* DMA channel 0 transfer select 29: Multiplier ready */
+#define DMA0TSEL__DMA2IFG (30*0x0001u) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
+#define DMA0TSEL__DMAE0 (31*0x0001u) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA1TSEL__DMA_REQ (0*0x0100u) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */
+#define DMA1TSEL__TA0CCR0 (1*0x0100u) /* DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG) */
+#define DMA1TSEL__TA0CCR2 (2*0x0100u) /* DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG) */
+#define DMA1TSEL__TA1CCR0 (3*0x0100u) /* DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG) */
+#define DMA1TSEL__TA1CCR2 (4*0x0100u) /* DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG) */
+#define DMA1TSEL__TB0CCR0 (5*0x0100u) /* DMA channel 1 transfer select 5: TimerB (TB0CCR0.IFG) */
+#define DMA1TSEL__TB0CCR2 (6*0x0100u) /* DMA channel 1 transfer select 6: TimerB (TB0CCR2.IFG) */
+#define DMA1TSEL__RES7 (7*0x0100u) /* DMA channel 1 transfer select 7: Reserved */
+#define DMA1TSEL__RES8 (8*0x0100u) /* DMA channel 1 transfer select 8: Reserved */
+#define DMA1TSEL__RES9 (9*0x0100u) /* DMA channel 1 transfer select 9: Reserved */
+#define DMA1TSEL__RES10 (10*0x0100u) /* DMA channel 1 transfer select 10: Reserved */
+#define DMA1TSEL__RES11 (11*0x0100u) /* DMA channel 1 transfer select 11: Reserved */
+#define DMA1TSEL__RES12 (12*0x0100u) /* DMA channel 1 transfer select 12: Reserved */
+#define DMA1TSEL__RES13 (13*0x0100u) /* DMA channel 1 transfer select 13: Reserved */
+#define DMA1TSEL__RFRXIFG (14*0x0100u) /* DMA channel 1 transfer select 14: RFRXIFG */
+#define DMA1TSEL__RFTXIFG (15*0x0100u) /* DMA channel 1 transfer select 15: RFTXIFG */
+#define DMA1TSEL__USCIA0RX (16*0x0100u) /* DMA channel 1 transfer select 16: USCIA0 receive */
+#define DMA1TSEL__USCIA0TX (17*0x0100u) /* DMA channel 1 transfer select 17: USCIA0 transmit */
+#define DMA1TSEL__USCIB0RX (18*0x0100u) /* DMA channel 1 transfer select 18: USCIB0 receive */
+#define DMA1TSEL__USCIB0TX (19*0x0100u) /* DMA channel 1 transfer select 19: USCIB0 transmit */
+#define DMA1TSEL__RES20 (20*0x0100u) /* DMA channel 1 transfer select 20: Reserved */
+#define DMA1TSEL__RES21 (21*0x0100u) /* DMA channel 1 transfer select 21: Reserved */
+#define DMA1TSEL__RES22 (22*0x0100u) /* DMA channel 1 transfer select 22: Reserved */
+#define DMA1TSEL__RES23 (23*0x0100u) /* DMA channel 1 transfer select 23: Reserved */
+#define DMA1TSEL__ADC12IFG (24*0x0100u) /* DMA channel 1 transfer select 24: ADC12IFGx */
+#define DMA1TSEL__RES25 (25*0x0100u) /* DMA channel 1 transfer select 25: Reserved */
+#define DMA1TSEL__RES26 (26*0x0100u) /* DMA channel 1 transfer select 26: Reserved */
+#define DMA1TSEL__RES27 (27*0x0100u) /* DMA channel 1 transfer select 27: Reserved */
+#define DMA1TSEL__RES28 (28*0x0100u) /* DMA channel 1 transfer select 28: Reserved */
+#define DMA1TSEL__MPY (29*0x0100u) /* DMA channel 1 transfer select 29: Multiplier ready */
+#define DMA1TSEL__DMA0IFG (30*0x0100u) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
+#define DMA1TSEL__DMAE0 (31*0x0100u) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA2TSEL__DMA_REQ (0*0x0001u) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */
+#define DMA2TSEL__TA0CCR0 (1*0x0001u) /* DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG) */
+#define DMA2TSEL__TA0CCR2 (2*0x0001u) /* DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG) */
+#define DMA2TSEL__TA1CCR0 (3*0x0001u) /* DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG) */
+#define DMA2TSEL__TA1CCR2 (4*0x0001u) /* DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG) */
+#define DMA2TSEL__TB0CCR0 (5*0x0001u) /* DMA channel 2 transfer select 5: TimerB (TB0CCR0.IFG) */
+#define DMA2TSEL__TB0CCR2 (6*0x0001u) /* DMA channel 2 transfer select 6: TimerB (TB0CCR2.IFG) */
+#define DMA2TSEL__RES7 (7*0x0001u) /* DMA channel 2 transfer select 7: Reserved */
+#define DMA2TSEL__RES8 (8*0x0001u) /* DMA channel 2 transfer select 8: Reserved */
+#define DMA2TSEL__RES9 (9*0x0001u) /* DMA channel 2 transfer select 9: Reserved */
+#define DMA2TSEL__RES10 (10*0x0001u) /* DMA channel 2 transfer select 10: Reserved */
+#define DMA2TSEL__RES11 (11*0x0001u) /* DMA channel 2 transfer select 11: Reserved */
+#define DMA2TSEL__RES12 (12*0x0001u) /* DMA channel 2 transfer select 12: Reserved */
+#define DMA2TSEL__RES13 (13*0x0001u) /* DMA channel 2 transfer select 13: Reserved */
+#define DMA2TSEL__RFRXIFG (14*0x0001u) /* DMA channel 2 transfer select 14: RFRXIFG */
+#define DMA2TSEL__RFTXIFG (15*0x0001u) /* DMA channel 2 transfer select 15: RFTXIFG */
+#define DMA2TSEL__USCIA0RX (16*0x0001u) /* DMA channel 2 transfer select 16: USCIA0 receive */
+#define DMA2TSEL__USCIA0TX (17*0x0001u) /* DMA channel 2 transfer select 17: USCIA0 transmit */
+#define DMA2TSEL__USCIB0RX (18*0x0001u) /* DMA channel 2 transfer select 18: USCIB0 receive */
+#define DMA2TSEL__USCIB0TX (19*0x0001u) /* DMA channel 2 transfer select 19: USCIB0 transmit */
+#define DMA2TSEL__RES20 (20*0x0001u) /* DMA channel 2 transfer select 20: Reserved */
+#define DMA2TSEL__RES21 (21*0x0001u) /* DMA channel 2 transfer select 21: Reserved */
+#define DMA2TSEL__RES22 (22*0x0001u) /* DMA channel 2 transfer select 22: Reserved */
+#define DMA2TSEL__RES23 (23*0x0001u) /* DMA channel 2 transfer select 23: Reserved */
+#define DMA2TSEL__ADC12IFG (24*0x0001u) /* DMA channel 2 transfer select 24: ADC12IFGx */
+#define DMA2TSEL__RES25 (25*0x0001u) /* DMA channel 2 transfer select 25: Reserved */
+#define DMA2TSEL__RES26 (26*0x0001u) /* DMA channel 2 transfer select 26: Reserved */
+#define DMA2TSEL__RES27 (27*0x0001u) /* DMA channel 2 transfer select 27: Reserved */
+#define DMA2TSEL__RES28 (28*0x0001u) /* DMA channel 2 transfer select 28: Reserved */
+#define DMA2TSEL__MPY (29*0x0001u) /* DMA channel 2 transfer select 29: Multiplier ready */
+#define DMA2TSEL__DMA1IFG (30*0x0001u) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
+#define DMA2TSEL__DMAE0 (31*0x0001u) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
+
+#endif /* __MSP430_DMA_BASE__ */
+
+#endif /* __MSP430_HEADERS_DMAX_H__ */
+
* (c) 2003 by Steve Underwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: esp430e.h,v 1.5 2006/12/26 10:33:14 coppice Exp $
+ * $Id: esp430e.h,v 1.6 2008/10/09 15:00:14 sb-sf Exp $
*/
/* Switches: none */
#define ESP430_STAT1 RET1 /* STATUS1 of ESP430 */
#define WAVEFSV1 RET2 /* Waveform Sample V1 offset corrected*/
#define WAVEFSI1 RET5 /* Waveform Sample I1 offset corrected*/
+#if defined __MSP430_HAS_ESP430E1A__
#define WAVEFSI2 RET6 /* Waveform Sample I2 offset corrected*/
+#endif
#define ACTENERGY1_LO RET8 /* Active energy I1 Low Word */
#define ACTENERGY1_HI RET9 /* Active energy I1 High Word */
+#if defined __MSP430_HAS_ESP430E1A__
#define ACTENERGY2_LO RET10 /* Active energy I2 Low Word */
#define ACTENERGY2_HI RET11 /* Active energy I2 High Word*/
+#endif
#define REACTENERGY_LO RET12 /* Reactive energy Low Word */
#define REACTENERGY_HI RET13 /* Reactive energy High Word */
#define APPENERGY_LO RET14 /* Apparent energy Low Word */
#define APPENERGY_HI RET15 /* Apparent energy High Word */
#define ACTENSPER1_LO RET16 /* Active energy I1 for last mains period Low Word */
#define ACTENSPER1_HI RET17 /* Active energy I1 for last mains period High Word */
+#if defined __MSP430_HAS_ESP430E1A__
#define ACTENSPER2_LO RET18 /* Active energy I2 for last mains period Low Word */
#define ACTENSPER2_HI RET19 /* Active energy I2 for last mains period High Word */
+#elif defined __MSP430_HAS_ESP430E1B__
+#define IRMS_2_LO RET18 /* RMS_2 Low Word */
+#define IRMS_2_HI RET19 /* RMS_2 High Word */
+#endif
#define POWERFCT RET20 /* Power factor */
#define CAPIND RET21 /* Power factor: neg: inductive pos: cap. (LowByte)*/
#define MAINSPERIOD RET22 /* Mains period */
*
* mspgcc project: MSP430 device headers
* GPIO module header
- *
+ *
+ * 2009-06-04 - THLN
+ * - for msp430x47xx
+ * - __MSP430_HAS_PORT9_R__ and __MSP430_HAS_PORT10_R__ added
+ *
* 2008-06-04 - TonyB (tony.borries@gmail.com)
* - for msp430x2618 (and possibly others)
* - define __MSP430_HAS_PORT7_R__ and __MSP430_HAS_PORT7_R__
* (c) 2002 by M. P. Ashton <data@ieee.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: gpio.h,v 1.7 2008/06/16 23:22:19 cliechti Exp $
+ * $Id: gpio.h,v 1.8 2009/06/04 21:34:29 cliechti Exp $
*/
/* Switches:
__MSP430_HAS_PORT7_R__ - if device has port 7 with pull-downs
__MSP430_HAS_PORT8__ - if device has port 8
__MSP430_HAS_PORT8_R__ - if device has port 8 with pull-downs
-__MSP430_HAS_PORTA__ - if device has port A (16 bit view of ports 7 & 8)
+__MSP430_HAS_PORTA__ - if device has port A (16 bit view of ports
+7 & 8)
__MSP430_HAS_PORT9__ - if device has port 9
+__MSP430_HAS_PORT9_R__ - if device has port 9 with pull-downs
__MSP430_HAS_PORT10__ - if device has port 10
-__MSP430_HAS_PORTB__ - if device has port B (16 bit view of ports 9 & 10)
+__MSP430_HAS_PORT10_R__ - if device has port 10 with pull-downs
+__MSP430_HAS_PORTB__ - if device has port B (16 bit view of ports
+9 & 10)
Note: these only make sense if the port itself is present. Also note that
-the port resistor enable registers for ports 3-6 overlap with port 0 registers,
+the port resistor enable registers for ports 3-6 overlap with port 0
+registers,
so any device that has these resistors will not have port 0.
*/
sfrb(PAIN, PAIN_);
#endif
-#if defined(__MSP430_HAS_PORT9__)
+#if defined(__MSP430_HAS_PORT9__) || defined(__MSP430_HAS_PORT9_R__)
#define P9IN_ 0x0008 /* Port 9 Input */
sfrb(P9IN, P9IN_);
#define P9OUT_ 0x000A /* Port 9 Output */
sfrb(P9DIR, P9DIR_);
#define P9SEL_ 0x000E /* Port 9 Selection */
sfrb(P9SEL, P9SEL_);
+
+#if defined(__MSP430_HAS_PORT9_R__)
+#define P9REN_ 0x0016 /* Port 9 Resistor enable */
+sfrb(P9REN, P9REN_);
+#endif
+
#endif
-#if defined(__MSP430_HAS_PORT10__)
+#if defined(__MSP430_HAS_PORT10__) || defined(__MSP430_HAS_PORT10_R__)
#define P10IN_ 0x0009 /* Port 10 Input */
sfrb(P10IN, P10IN_);
#define P10OUT_ 0x000B /* Port 10 Output */
sfrb(P10DIR, P10DIR_);
#define P10SEL_ 0x000F /* Port 10 Selection */
sfrb(P10SEL, P10SEL_);
+
+#if defined(__MSP430_HAS_PORT10_R__)
+#define P10REN_ 0x0017 /* Port 10 Resistor enable */
+sfrb(P10REN, P10REN_);
+#endif
+
#endif
#if defined(__MSP430_HAS_PORTB__)
--- /dev/null
+#ifndef __MSP430_HEADERS_GPIO_5XXX_H
+#define __MSP430_HEADERS_GPIO_5XXX_H
+
+/* gpio_5xxx.h
+ *
+ * mspgcc project: MSP430 device headers
+ * Digital I/O
+ *
+ * (c) 2008 by Sergey A. Borshch <sb-sf@sourceforge.net>
+ * Originally based in MSP430F543x datasheet (slas609)
+ * and MSP430x5xx Family User's Guide (slau208).
+ *
+ * 2009-10-08 - modifications by J.M.Gross <mspgcc@grossibaer.de>
+ * - added PORTA..PORTE definitions
+ *
+ * $Id: gpio_5xxx.h,v 1.2 2008/12/07 23:00:38 sb-sf Exp $
+ */
+
+/* Switches:
+
+__MSP430_PORT1_BASE__ - base address of PORT1 module. PORT1 present in device if defined
+__MSP430_PORT2_BASE__ - base address of PORT2 module. PORT2 present in device if defined
+__MSP430_PORT3_BASE__ - base address of PORT3 module. PORT3 present in device if defined
+__MSP430_PORT4_BASE__ - base address of PORT4 module. PORT4 present in device if defined
+__MSP430_PORT5_BASE__ - base address of PORT5 module. PORT5 present in device if defined
+__MSP430_PORT6_BASE__ - base address of PORT6 module. PORT6 present in device if defined
+__MSP430_PORT7_BASE__ - base address of PORT7 module. PORT7 present in device if defined
+__MSP430_PORT8_BASE__ - base address of PORT8 module. PORT8 present in device if defined
+__MSP430_PORT9_BASE__ - base address of PORT9 module. PORT9 present in device if defined
+__MSP430_PORT10_BASE__ - base address of PORT10 module. PORT10 present in device if defined
+__MSP430_PORT11_BASE__ - base address of PORT11 module. PORT11 present in device if defined
+__MSP430_PORTJ_BASE__ - base address of PORTJ module. PORTJ present in device if defined
+
+*/
+
+#if defined(__MSP430_PORT1_BASE__)
+#define P1IN_ __MSP430_PORT1_BASE__ + 0x00 /* Port 1 Input */
+sfrb(P1IN, P1IN_);
+#define P1OUT_ __MSP430_PORT1_BASE__ + 0x02 /* Port 1 Output */
+sfrb(P1OUT, P1OUT_);
+#define P1DIR_ __MSP430_PORT1_BASE__ + 0x04 /* Port 1 Direction */
+sfrb(P1DIR, P1DIR_);
+#define P1REN_ __MSP430_PORT1_BASE__ + 0x06 /* Port 1 Resistor enable */
+sfrb(P1REN, P1REN_);
+#define P1DS_ __MSP430_PORT1_BASE__ + 0x08 /* Port 1 Drive strength */
+sfrb(P1DS, P1DS_);
+#define P1SEL_ __MSP430_PORT1_BASE__ + 0x0A /* Port 1 Selection */
+sfrb(P1SEL, P1SEL_);
+#define P1IV_ __MSP430_PORT1_BASE__ + 0x0E /* Port 1 Interrupt vector word */
+sfrb(P1IV, P1IV_);
+#define P1IES_ __MSP430_PORT1_BASE__ + 0x18 /* Port 1 Interrupt Edge Select */
+sfrb(P1IES, P1IES_);
+#define P1IE_ __MSP430_PORT1_BASE__ + 0x1A /* Port 1 Interrupt Enable */
+sfrb(P1IE, P1IE_);
+#define P1IFG_ __MSP430_PORT1_BASE__ + 0x1C /* Port 1 Interrupt Flag */
+sfrb(P1IFG, P1IFG_);
+#endif
+
+#if defined(__MSP430_PORT2_BASE__)
+#define P2IN_ __MSP430_PORT2_BASE__ + 0x01 /* Port 2 Input */
+sfrb(P2IN, P2IN_);
+#define P2OUT_ __MSP430_PORT2_BASE__ + 0x03 /* Port 2 Output */
+sfrb(P2OUT, P2OUT_);
+#define P2DIR_ __MSP430_PORT2_BASE__ + 0x05 /* Port 2 Direction */
+sfrb(P2DIR, P2DIR_);
+#define P2REN_ __MSP430_PORT2_BASE__ + 0x07 /* Port 2 Resistor enable */
+sfrb(P2REN, P2REN_);
+#define P2DS_ __MSP430_PORT2_BASE__ + 0x09 /* Port 2 Drive strength */
+sfrb(P2DS, P2DS_);
+#define P2SEL_ __MSP430_PORT2_BASE__ + 0x0B /* Port 2 Selection */
+sfrb(P2SEL, P2SEL_);
+#define P2IV_ __MSP430_PORT2_BASE__ + 0x1E /* Port 2 Interrupt vector word */
+sfrb(P2IV, P2IV_);
+#define P2IES_ __MSP430_PORT2_BASE__ + 0x19 /* Port 2 Interrupt Edge Select */
+sfrb(P2IES, P2IES_);
+#define P2IE_ __MSP430_PORT2_BASE__ + 0x1B /* Port 2 Interrupt Enable */
+sfrb(P2IE, P2IE_);
+#define P2IFG_ __MSP430_PORT2_BASE__ + 0x1D /* Port 2 Interrupt Flag */
+sfrb(P2IFG, P2IFG_);
+#if defined(__MSP430_PORT1_BASE__) /* if there is Port1 and Port2 then there is PortA */
+sfrw(PAIN, P1IN_);
+sfrw(PAOUT, P1OUT_);
+sfrw(PADIR, P1DIR_);
+sfrw(PAREN, P1REN_);
+sfrw(PADS, P1DS_);
+sfrw(PASEL, P1SEL_);
+#endif
+#endif
+
+#if defined(__MSP430_PORT3_BASE__)
+#define P3IN_ __MSP430_PORT3_BASE__ + 0x00 /* Port 3 Input */
+sfrb(P3IN, P3IN_);
+#define P3OUT_ __MSP430_PORT3_BASE__ + 0x02 /* Port 3 Output */
+sfrb(P3OUT, P3OUT_);
+#define P3DIR_ __MSP430_PORT3_BASE__ + 0x04 /* Port 3 Direction */
+sfrb(P3DIR, P3DIR_);
+#define P3REN_ __MSP430_PORT3_BASE__ + 0x06 /* Port 3 Resistor enable */
+sfrb(P3REN, P3REN_);
+#define P3DS_ __MSP430_PORT3_BASE__ + 0x08 /* Port 3 Drive strength */
+sfrb(P3DS, P3DS_);
+#define P3SEL_ __MSP430_PORT3_BASE__ + 0x0A /* Port 3 Selection */
+sfrb(P3SEL, P3SEL_);
+#endif
+
+#if defined(__MSP430_PORT4_BASE__)
+#define P4IN_ __MSP430_PORT4_BASE__ + 0x01 /* Port 4 Input */
+sfrb(P4IN, P4IN_);
+#define P4OUT_ __MSP430_PORT4_BASE__ + 0x03 /* Port 4 Output */
+sfrb(P4OUT, P4OUT_);
+#define P4DIR_ __MSP430_PORT4_BASE__ + 0x05 /* Port 4 Direction */
+sfrb(P4DIR, P4DIR_);
+#define P4REN_ __MSP430_PORT4_BASE__ + 0x07 /* Port 4 Resistor enable */
+sfrb(P4REN, P4REN_);
+#define P4DS_ __MSP430_PORT4_BASE__ + 0x09 /* Port 4 Drive strength */
+sfrb(P4DS, P4DS_);
+#define P4SEL_ __MSP430_PORT4_BASE__ + 0x0B /* Port 4 Selection */
+sfrb(P4SEL, P4SEL_);
+#if defined(__MSP430_PORT3_BASE__) /* if there is Port1 and Port2 then there is PortA */
+sfrw(PBIN, P3IN_);
+sfrw(PBOUT, P3OUT_);
+sfrw(PBDIR, P3DIR_);
+sfrw(PBREN, P3REN_);
+sfrw(PBDS, P3DS_);
+sfrw(PBSEL, P3SEL_);
+#endif
+#endif
+
+#if defined(__MSP430_PORT5_BASE__)
+#define P5IN_ __MSP430_PORT5_BASE__ + 0x00 /* Port 5 Input */
+sfrb(P5IN, P5IN_);
+#define P5OUT_ __MSP430_PORT5_BASE__ + 0x02 /* Port 5 Output */
+sfrb(P5OUT, P5OUT_);
+#define P5DIR_ __MSP430_PORT5_BASE__ + 0x04 /* Port 5 Direction */
+sfrb(P5DIR, P5DIR_);
+#define P5REN_ __MSP430_PORT5_BASE__ + 0x06 /* Port 5 Resistor enable */
+sfrb(P5REN, P5REN_);
+#define P5DS_ __MSP430_PORT5_BASE__ + 0x08 /* Port 5 Drive strength */
+sfrb(P5DS, P5DS_);
+#define P5SEL_ __MSP430_PORT5_BASE__ + 0x0A /* Port 5 Selection */
+sfrb(P5SEL, P5SEL_);
+#endif
+
+#if defined(__MSP430_PORT6_BASE__)
+#define P6IN_ __MSP430_PORT6_BASE__ + 0x01 /* Port 6 Input */
+sfrb(P6IN, P6IN_);
+#define P6OUT_ __MSP430_PORT6_BASE__ + 0x03 /* Port 6 Output */
+sfrb(P6OUT, P6OUT_);
+#define P6DIR_ __MSP430_PORT6_BASE__ + 0x05 /* Port 6 Direction */
+sfrb(P6DIR, P6DIR_);
+#define P6REN_ __MSP430_PORT6_BASE__ + 0x07 /* Port 6 Resistor enable */
+sfrb(P6REN, P6REN_);
+#define P6DS_ __MSP430_PORT6_BASE__ + 0x09 /* Port 6 Drive strength */
+sfrb(P6DS, P6DS_);
+#define P6SEL_ __MSP430_PORT6_BASE__ + 0x0B /* Port 6 Selection */
+sfrb(P6SEL, P6SEL_);
+#if defined(__MSP430_PORT5_BASE__) /* if there is Port1 and Port2 then there is PortA */
+sfrw(PCIN, P5IN_);
+sfrw(PCOUT, P5OUT_);
+sfrw(PCDIR, P5DIR_);
+sfrw(PCREN, P5REN_);
+sfrw(PCDS, P5DS_);
+sfrw(PCSEL, P5SEL_);
+#endif
+#endif
+
+#if defined(__MSP430_PORT7_BASE__)
+#define P7IN_ __MSP430_PORT7_BASE__ + 0x00 /* Port 7 Input */
+sfrb(P7IN, P7IN_);
+#define P7OUT_ __MSP430_PORT7_BASE__ + 0x02 /* Port 7 Output */
+sfrb(P7OUT, P7OUT_);
+#define P7DIR_ __MSP430_PORT7_BASE__ + 0x04 /* Port 7 Direction */
+sfrb(P7DIR, P7DIR_);
+#define P7REN_ __MSP430_PORT7_BASE__ + 0x06 /* Port 7 Resistor enable */
+sfrb(P7REN, P7REN_);
+#define P7DS_ __MSP430_PORT7_BASE__ + 0x08 /* Port 7 Drive strength */
+sfrb(P7DS, P7DS_);
+#define P7SEL_ __MSP430_PORT7_BASE__ + 0x0A /* Port 7 Selection */
+sfrb(P7SEL, P7SEL_);
+#endif
+
+#if defined(__MSP430_PORT8_BASE__)
+#define P8IN_ __MSP430_PORT8_BASE__ + 0x01 /* Port 8 Input */
+sfrb(P8IN, P8IN_);
+#define P8OUT_ __MSP430_PORT8_BASE__ + 0x03 /* Port 8 Output */
+sfrb(P8OUT, P8OUT_);
+#define P8DIR_ __MSP430_PORT8_BASE__ + 0x05 /* Port 8 Direction */
+sfrb(P8DIR, P8DIR_);
+#define P8REN_ __MSP430_PORT8_BASE__ + 0x07 /* Port 8 Resistor enable */
+sfrb(P8REN, P8REN_);
+#define P8DS_ __MSP430_PORT8_BASE__ + 0x09 /* Port 8 Drive strength */
+sfrb(P8DS, P8DS_);
+#define P8SEL_ __MSP430_PORT8_BASE__ + 0x0B /* Port 8 Selection */
+sfrb(P8SEL, P8SEL_);
+#if defined(__MSP430_PORT7_BASE__) /* if there is Port1 and Port2 then there is PortA */
+sfrw(PDIN, P7IN_);
+sfrw(PDOUT, P7OUT_);
+sfrw(PDDIR, P7DIR_);
+sfrw(PDREN, P7REN_);
+sfrw(PDDS, P7DS_);
+sfrw(PDSEL, P7SEL_);
+#endif
+#endif
+
+#if defined(__MSP430_PORT9_BASE__)
+#define P9IN_ __MSP430_PORT9_BASE__ + 0x00 /* Port 9 Input */
+sfrb(P9IN, P9IN_);
+#define P9OUT_ __MSP430_PORT9_BASE__ + 0x02 /* Port 9 Output */
+sfrb(P9OUT, P9OUT_);
+#define P9DIR_ __MSP430_PORT9_BASE__ + 0x04 /* Port 9 Direction */
+sfrb(P9DIR, P9DIR_);
+#define P9REN_ __MSP430_PORT9_BASE__ + 0x06 /* Port 9 Resistor enable */
+sfrb(P9REN, P9REN_);
+#define P9DS_ __MSP430_PORT9_BASE__ + 0x08 /* Port 9 Drive strength */
+sfrb(P9DS, P9DS_);
+#define P9SEL_ __MSP430_PORT9_BASE__ + 0x0A /* Port 9 Selection */
+sfrb(P9SEL, P9SEL_);
+#endif
+
+#if defined(__MSP430_PORT10_BASE__)
+#define P10IN_ __MSP430_PORT10_BASE__ + 0x01 /* Port 10 Input */
+sfrb(P10IN, P10IN_);
+#define P10OUT_ __MSP430_PORT10_BASE__ + 0x03 /* Port 10 Output */
+sfrb(P10OUT, P10OUT_);
+#define P10DIR_ __MSP430_PORT10_BASE__ + 0x05 /* Port 10 Direction */
+sfrb(P10DIR, P10DIR_);
+#define P10REN_ __MSP430_PORT10_BASE__ + 0x07 /* Port 10 Resistor enable */
+sfrb(P10REN, P10REN_);
+#define P10DS_ __MSP430_PORT10_BASE__ + 0x09 /* Port 10 Drive strength */
+sfrb(P10DS, P10DS_);
+#define P10SEL_ __MSP430_PORT10_BASE__ + 0x0B /* Port 10 Selection */
+sfrb(P10SEL, P10SEL_);
+#if defined(__MSP430_PORT9_BASE__) /* if there is Port1 and Port2 then there is PortA */
+sfrw(PEIN, P9IN_);
+sfrw(PEOUT, P9OUT_);
+sfrw(PEDIR, P9DIR_);
+sfrw(PEREN, P9REN_);
+sfrw(PEDS, P9DS_);
+sfrw(PESEL, P9SEL_);
+#endif
+#endif
+
+#if defined(__MSP430_PORT11_BASE__)
+#define P11IN_ __MSP430_PORT11_BASE__ + 0x00 /* Port 11 Input */
+sfrb(P11IN, P11IN_);
+#define P11OUT_ __MSP430_PORT11_BASE__ + 0x02 /* Port 11 Output */
+sfrb(P11OUT, P11OUT_);
+#define P11DIR_ __MSP430_PORT11_BASE__ + 0x04 /* Port 11 Direction */
+sfrb(P11DIR, P11DIR_);
+#define P11REN_ __MSP430_PORT11_BASE__ + 0x06 /* Port 11 Resistor enable */
+sfrb(P11REN, P11REN_);
+#define P11DS_ __MSP430_PORT11_BASE__ + 0x08 /* Port 11 Drive strength */
+sfrb(P11DS, P11DS_);
+#define P11SEL_ __MSP430_PORT11_BASE__ + 0x0A /* Port 11 Selection */
+sfrb(P11SEL, P11SEL_);
+#endif
+
+#if defined(__MSP430_PORTJ_BASE__)
+#define PJIN_ __MSP430_PORTJ_BASE__ + 0x00 /* Port J Input */
+sfrb(PJIN, PJIN_);
+#define PJOUT_ __MSP430_PORTJ_BASE__ + 0x02 /* Port J Output */
+sfrb(PJOUT, PJOUT_);
+#define PJDIR_ __MSP430_PORTJ_BASE__ + 0x04 /* Port J Direction */
+sfrb(PJDIR, PJDIR_);
+#define PJREN_ __MSP430_PORTJ_BASE__ + 0x06 /* Port J Resistor enable */
+sfrb(PJREN, PJREN_);
+#define PJDS_ __MSP430_PORTJ_BASE__ + 0x08 /* Port J Drive strength */
+sfrb(PJDS, PJDS_);
+#endif
+
+#endif /* __MSP430_HEADERS_GPIO5_XXX_H */
/*
- * $Id: iostructures.h,v 1.10 2006/04/11 08:01:55 cliechti Exp $
+ * $Id: iostructures.h,v 1.11 2008/10/09 15:00:14 sb-sf Exp $
*/
-#ifndef _GNU_ASSEMBLER_
+#ifndef __ASSEMBLER__
#ifndef __IOSTRUCTURES_H__
#define __IOSTRUCTURES_H__
#endif /* __IOSTRUCTURES_H__ */
-#endif /* GNU_ASSEMBLER */
+#endif /* __ASSEMBLER__ */
* (c) 2002 by M. P. Ashton <data@ieee.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: lcd.h,v 1.6 2005/03/11 15:49:50 coppice Exp $
+ * $Id: lcd.h,v 1.7 2008/10/09 15:00:14 sb-sf Exp $
*/
/* Switches:
#define LCDOGOFF (LCDP2|LCDP1|LCDP0) /* S0 - S39 */
#define LCDMEM_ LCD_BASE+1 /* LCD memory */
-#if defined(_GNU_ASSEMBLER_)
+#if defined(__ASSEMBLER__)
#define LCDMEM LCDMEM_ /* LCD memory (for assembler) */
#else
#define LCDMEM ((char*) LCDMEM_) /* LCD memory (for C) */
* (c) 2005 by Steve Underwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: lcd_a.h,v 1.3 2006/01/25 16:39:10 coppice Exp $
+ * $Id: lcd_a.h,v 1.4 2008/10/09 15:00:14 sb-sf Exp $
*/
/* Switches: none */
#define VLCD_3_44 (15<<1) /* VLCD = 3.44V */
#define LCDMEM_ LCD_BASE+1 /* LCD memory */
-#ifdef _GNU_ASSEMBLER_
+#ifdef __ASSEMBLER__
#define LCDMEM LCDMEM_ /* LCD memory (for assembler) */
#else
#define LCDMEM ((char*) LCDMEM_) /* LCD memory (for C) */
--- /dev/null
+#if !defined(__MSP430_HEADERS_LCD_B_H__)
+#define __MSP430_HEADERS_LCD_B_H__
+
+/* lcd_b.h
+ *
+ * mspgcc project: MSP430 device headers
+ * LCD_B
+ *
+ * Based on cc430x613x.h version 1.5 by Texas Instruments
+ *
+ * Peter A. Bigot <pab@peoplepowerco.com>
+ *
+ */
+
+/* Switches:
+__MSP430_HAS_LCD_B__ -- defined to indicate availability of module
+__MSP430_LCD_B_BASE__ -- base address of LCD_B module
+*/
+
+#if defined(__MSP430_LCD_B_BASE__)
+
+#define LCDBCTL0_ __MSP430_LCD_B_BASE__ + 0x00 /* LCD_B Control Register 0 */
+sfrw(LCDBCTL0, LCDBCTL0_);
+#define LCDBCTL0_L_ __MSP430_LCD_B_BASE__ + 0x00
+sfrb(LCDBCTL0_L, LCDBCTL0_L_);
+#define LCDBCTL0_H_ __MSP430_LCD_B_BASE__ + 0x01
+sfrb(LCDBCTL0_H, LCDBCTL0_H_);
+#define LCDBCTL1_ __MSP430_LCD_B_BASE__ + 0x02 /* LCD_B Control Register 1 */
+sfrw(LCDBCTL1, LCDBCTL1_);
+#define LCDBCTL1_L_ __MSP430_LCD_B_BASE__ + 0x02
+sfrb(LCDBCTL1_L, LCDBCTL1_L_);
+#define LCDBCTL1_H_ __MSP430_LCD_B_BASE__ + 0x03
+sfrb(LCDBCTL1_H, LCDBCTL1_H_);
+#define LCDBBLKCTL_ __MSP430_LCD_B_BASE__ + 0x04 /* LCD_B blinking control register */
+sfrw(LCDBBLKCTL, LCDBBLKCTL_);
+#define LCDBBLKCTL_L_ __MSP430_LCD_B_BASE__ + 0x04
+sfrb(LCDBBLKCTL_L, LCDBBLKCTL_L_);
+#define LCDBBLKCTL_H_ __MSP430_LCD_B_BASE__ + 0x05
+sfrb(LCDBBLKCTL_H, LCDBBLKCTL_H_);
+#define LCDBMEMCTL_ __MSP430_LCD_B_BASE__ + 0x06 /* LCD_B memory control register */
+sfrw(LCDBMEMCTL, LCDBMEMCTL_);
+#define LCDBMEMCTL_L_ __MSP430_LCD_B_BASE__ + 0x06
+sfrb(LCDBMEMCTL_L, LCDBMEMCTL_L_);
+#define LCDBMEMCTL_H_ __MSP430_LCD_B_BASE__ + 0x07
+sfrb(LCDBMEMCTL_H, LCDBMEMCTL_H_);
+#define LCDBVCTL_ __MSP430_LCD_B_BASE__ + 0x08 /* LCD_B Voltage Control Register */
+sfrw(LCDBVCTL, LCDBVCTL_);
+#define LCDBVCTL_L_ __MSP430_LCD_B_BASE__ + 0x08
+sfrb(LCDBVCTL_L, LCDBVCTL_L_);
+#define LCDBVCTL_H_ __MSP430_LCD_B_BASE__ + 0x09
+sfrb(LCDBVCTL_H, LCDBVCTL_H_);
+#define LCDBPCTL0_ __MSP430_LCD_B_BASE__ + 0x0a /* LCD_B Port Control Register 0 */
+sfrw(LCDBPCTL0, LCDBPCTL0_);
+#define LCDBPCTL0_L_ __MSP430_LCD_B_BASE__ + 0x0a
+sfrb(LCDBPCTL0_L, LCDBPCTL0_L_);
+#define LCDBPCTL0_H_ __MSP430_LCD_B_BASE__ + 0x0b
+sfrb(LCDBPCTL0_H, LCDBPCTL0_H_);
+#define LCDBPCTL1_ __MSP430_LCD_B_BASE__ + 0x0c /* LCD_B Port Control Register 1 */
+sfrw(LCDBPCTL1, LCDBPCTL1_);
+#define LCDBPCTL1_L_ __MSP430_LCD_B_BASE__ + 0x0c
+sfrb(LCDBPCTL1_L, LCDBPCTL1_L_);
+#define LCDBPCTL1_H_ __MSP430_LCD_B_BASE__ + 0x0d
+sfrb(LCDBPCTL1_H, LCDBPCTL1_H_);
+#define LCDBPCTL2_ __MSP430_LCD_B_BASE__ + 0x0e /* LCD_B Port Control Register 2 */
+sfrw(LCDBPCTL2, LCDBPCTL2_);
+#define LCDBPCTL2_L_ __MSP430_LCD_B_BASE__ + 0x0e
+sfrb(LCDBPCTL2_L, LCDBPCTL2_L_);
+#define LCDBPCTL2_H_ __MSP430_LCD_B_BASE__ + 0x0f
+sfrb(LCDBPCTL2_H, LCDBPCTL2_H_);
+#define LCDBPCTL3_ __MSP430_LCD_B_BASE__ + 0x10 /* LCD_B Port Control Register 3 */
+sfrw(LCDBPCTL3, LCDBPCTL3_);
+#define LCDBPCTL3_L_ __MSP430_LCD_B_BASE__ + 0x10
+sfrb(LCDBPCTL3_L, LCDBPCTL3_L_);
+#define LCDBPCTL3_H_ __MSP430_LCD_B_BASE__ + 0x11
+sfrb(LCDBPCTL3_H, LCDBPCTL3_H_);
+#define LCDBCPCTL_ __MSP430_LCD_B_BASE__ + 0x12 /* LCD_B Charge Pump Control Register 3 */
+sfrw(LCDBCPCTL, LCDBCPCTL_);
+#define LCDBCPCTL_L_ __MSP430_LCD_B_BASE__ + 0x12
+sfrb(LCDBCPCTL_L, LCDBCPCTL_L_);
+#define LCDBCPCTL_H_ __MSP430_LCD_B_BASE__ + 0x13
+sfrb(LCDBCPCTL_H, LCDBCPCTL_H_);
+#define LCDBIV_ __MSP430_LCD_B_BASE__ + 0x1e /* LCD_B Interrupt Vector Register */
+sfrw(LCDBIV, LCDBIV_);
+
+// LCDBCTL0
+#define LCDON (0x0001) /* LCD_B LCD On */
+#define LCDSON (0x0004) /* LCD_B LCD Segments On */
+#define LCDMX0 (0x0008) /* LCD_B Mux Rate Bit: 0 */
+#define LCDMX1 (0x0010) /* LCD_B Mux Rate Bit: 1 */
+//#define RESERVED (0x0020) /* LCD_B RESERVED */
+//#define RESERVED (0x0040) /* LCD_B RESERVED */
+#define LCDSSEL (0x0080) /* LCD_B Clock Select */
+#define LCDPRE0 (0x0100) /* LCD_B LCD frequency pre-scaler Bit: 0 */
+#define LCDPRE1 (0x0200) /* LCD_B LCD frequency pre-scaler Bit: 1 */
+#define LCDPRE2 (0x0400) /* LCD_B LCD frequency pre-scaler Bit: 2 */
+#define LCDDIV0 (0x0800) /* LCD_B LCD frequency divider Bit: 0 */
+#define LCDDIV1 (0x1000) /* LCD_B LCD frequency divider Bit: 1 */
+#define LCDDIV2 (0x2000) /* LCD_B LCD frequency divider Bit: 2 */
+#define LCDDIV3 (0x4000) /* LCD_B LCD frequency divider Bit: 3 */
+#define LCDDIV4 (0x8000) /* LCD_B LCD frequency divider Bit: 4 */
+
+// LCDBCTL0
+#define LCDON_L (0x0001) /* LCD_B LCD On */
+#define LCDSON_L (0x0004) /* LCD_B LCD Segments On */
+#define LCDMX0_L (0x0008) /* LCD_B Mux Rate Bit: 0 */
+#define LCDMX1_L (0x0010) /* LCD_B Mux Rate Bit: 1 */
+//#define RESERVED (0x0020) /* LCD_B RESERVED */
+//#define RESERVED (0x0040) /* LCD_B RESERVED */
+#define LCDSSEL_L (0x0080) /* LCD_B Clock Select */
+
+// LCDBCTL0
+//#define RESERVED (0x0020) /* LCD_B RESERVED */
+//#define RESERVED (0x0040) /* LCD_B RESERVED */
+#define LCDPRE0_H (0x0001) /* LCD_B LCD frequency pre-scaler Bit: 0 */
+#define LCDPRE1_H (0x0002) /* LCD_B LCD frequency pre-scaler Bit: 1 */
+#define LCDPRE2_H (0x0004) /* LCD_B LCD frequency pre-scaler Bit: 2 */
+#define LCDDIV0_H (0x0008) /* LCD_B LCD frequency divider Bit: 0 */
+#define LCDDIV1_H (0x0010) /* LCD_B LCD frequency divider Bit: 1 */
+#define LCDDIV2_H (0x0020) /* LCD_B LCD frequency divider Bit: 2 */
+#define LCDDIV3_H (0x0040) /* LCD_B LCD frequency divider Bit: 3 */
+#define LCDDIV4_H (0x0080) /* LCD_B LCD frequency divider Bit: 4 */
+
+#define LCDPRE_0 (0x0000) /* LCD_B LCD frequency pre-scaler: /1 */
+#define LCDPRE_1 (0x0100) /* LCD_B LCD frequency pre-scaler: /2 */
+#define LCDPRE_2 (0x0200) /* LCD_B LCD frequency pre-scaler: /4 */
+#define LCDPRE_3 (0x0300) /* LCD_B LCD frequency pre-scaler: /8 */
+#define LCDPRE_4 (0x0400) /* LCD_B LCD frequency pre-scaler: /16 */
+#define LCDPRE_5 (0x0500) /* LCD_B LCD frequency pre-scaler: /32 */
+#define LCDPRE__1 (0x0000) /* LCD_B LCD frequency pre-scaler: /1 */
+#define LCDPRE__2 (0x0100) /* LCD_B LCD frequency pre-scaler: /2 */
+#define LCDPRE__4 (0x0200) /* LCD_B LCD frequency pre-scaler: /4 */
+#define LCDPRE__8 (0x0300) /* LCD_B LCD frequency pre-scaler: /8 */
+#define LCDPRE__16 (0x0400) /* LCD_B LCD frequency pre-scaler: /16 */
+#define LCDPRE__32 (0x0500) /* LCD_B LCD frequency pre-scaler: /32 */
+
+#define LCDDIV_0 (0x0000) /* LCD_B LCD frequency divider: /1 */
+#define LCDDIV_1 (0x0800) /* LCD_B LCD frequency divider: /2 */
+#define LCDDIV_2 (0x1000) /* LCD_B LCD frequency divider: /3 */
+#define LCDDIV_3 (0x1800) /* LCD_B LCD frequency divider: /4 */
+#define LCDDIV_4 (0x2000) /* LCD_B LCD frequency divider: /5 */
+#define LCDDIV_5 (0x2800) /* LCD_B LCD frequency divider: /6 */
+#define LCDDIV_6 (0x3000) /* LCD_B LCD frequency divider: /7 */
+#define LCDDIV_7 (0x3800) /* LCD_B LCD frequency divider: /8 */
+#define LCDDIV_8 (0x4000) /* LCD_B LCD frequency divider: /9 */
+#define LCDDIV_9 (0x4800) /* LCD_B LCD frequency divider: /10 */
+#define LCDDIV_10 (0x5000) /* LCD_B LCD frequency divider: /11 */
+#define LCDDIV_11 (0x5800) /* LCD_B LCD frequency divider: /12 */
+#define LCDDIV_12 (0x6000) /* LCD_B LCD frequency divider: /13 */
+#define LCDDIV_13 (0x6800) /* LCD_B LCD frequency divider: /14 */
+#define LCDDIV_14 (0x7000) /* LCD_B LCD frequency divider: /15 */
+#define LCDDIV_15 (0x7800) /* LCD_B LCD frequency divider: /16 */
+#define LCDDIV_16 (0x8000) /* LCD_B LCD frequency divider: /17 */
+#define LCDDIV_17 (0x8800) /* LCD_B LCD frequency divider: /18 */
+#define LCDDIV_18 (0x9000) /* LCD_B LCD frequency divider: /19 */
+#define LCDDIV_19 (0x9800) /* LCD_B LCD frequency divider: /20 */
+#define LCDDIV_20 (0xA000) /* LCD_B LCD frequency divider: /21 */
+#define LCDDIV_21 (0xA800) /* LCD_B LCD frequency divider: /22 */
+#define LCDDIV_22 (0xB000) /* LCD_B LCD frequency divider: /23 */
+#define LCDDIV_23 (0xB800) /* LCD_B LCD frequency divider: /24 */
+#define LCDDIV_24 (0xC000) /* LCD_B LCD frequency divider: /25 */
+#define LCDDIV_25 (0xC800) /* LCD_B LCD frequency divider: /26 */
+#define LCDDIV_26 (0xD000) /* LCD_B LCD frequency divider: /27 */
+#define LCDDIV_27 (0xD800) /* LCD_B LCD frequency divider: /28 */
+#define LCDDIV_28 (0xE000) /* LCD_B LCD frequency divider: /29 */
+#define LCDDIV_29 (0xE800) /* LCD_B LCD frequency divider: /30 */
+#define LCDDIV_30 (0xF000) /* LCD_B LCD frequency divider: /31 */
+#define LCDDIV_31 (0xF800) /* LCD_B LCD frequency divider: /32 */
+#define LCDDIV__1 (0x0000) /* LCD_B LCD frequency divider: /1 */
+#define LCDDIV__2 (0x0800) /* LCD_B LCD frequency divider: /2 */
+#define LCDDIV__3 (0x1000) /* LCD_B LCD frequency divider: /3 */
+#define LCDDIV__4 (0x1800) /* LCD_B LCD frequency divider: /4 */
+#define LCDDIV__5 (0x2000) /* LCD_B LCD frequency divider: /5 */
+#define LCDDIV__6 (0x2800) /* LCD_B LCD frequency divider: /6 */
+#define LCDDIV__7 (0x3000) /* LCD_B LCD frequency divider: /7 */
+#define LCDDIV__8 (0x3800) /* LCD_B LCD frequency divider: /8 */
+#define LCDDIV__9 (0x4000) /* LCD_B LCD frequency divider: /9 */
+#define LCDDIV__10 (0x4800) /* LCD_B LCD frequency divider: /10 */
+#define LCDDIV__11 (0x5000) /* LCD_B LCD frequency divider: /11 */
+#define LCDDIV__12 (0x5800) /* LCD_B LCD frequency divider: /12 */
+#define LCDDIV__13 (0x6000) /* LCD_B LCD frequency divider: /13 */
+#define LCDDIV__14 (0x6800) /* LCD_B LCD frequency divider: /14 */
+#define LCDDIV__15 (0x7000) /* LCD_B LCD frequency divider: /15 */
+#define LCDDIV__16 (0x7800) /* LCD_B LCD frequency divider: /16 */
+#define LCDDIV__17 (0x8000) /* LCD_B LCD frequency divider: /17 */
+#define LCDDIV__18 (0x8800) /* LCD_B LCD frequency divider: /18 */
+#define LCDDIV__19 (0x9000) /* LCD_B LCD frequency divider: /19 */
+#define LCDDIV__20 (0x9800) /* LCD_B LCD frequency divider: /20 */
+#define LCDDIV__21 (0xA000) /* LCD_B LCD frequency divider: /21 */
+#define LCDDIV__22 (0xA800) /* LCD_B LCD frequency divider: /22 */
+#define LCDDIV__23 (0xB000) /* LCD_B LCD frequency divider: /23 */
+#define LCDDIV__24 (0xB800) /* LCD_B LCD frequency divider: /24 */
+#define LCDDIV__25 (0xC000) /* LCD_B LCD frequency divider: /25 */
+#define LCDDIV__26 (0xC800) /* LCD_B LCD frequency divider: /26 */
+#define LCDDIV__27 (0xD000) /* LCD_B LCD frequency divider: /27 */
+#define LCDDIV__28 (0xD800) /* LCD_B LCD frequency divider: /28 */
+#define LCDDIV__29 (0xE000) /* LCD_B LCD frequency divider: /29 */
+#define LCDDIV__30 (0xE800) /* LCD_B LCD frequency divider: /30 */
+#define LCDDIV__31 (0xF000) /* LCD_B LCD frequency divider: /31 */
+#define LCDDIV__32 (0xF800) /* LCD_B LCD frequency divider: /32 */
+
+/* Display modes coded with Bits 2-4 */
+#define LCDSTATIC (LCDSON)
+#define LCD2MUX (LCDMX0+LCDSON)
+#define LCD3MUX (LCDMX1+LCDSON)
+#define LCD4MUX (LCDMX1+LCDMX0+LCDSON)
+
+// LCDBCTL1
+#define LCDFRMIFG (0x0001) /* LCD_B LCD frame interrupt flag */
+#define LCDBLKOFFIFG (0x0002) /* LCD_B LCD blinking off interrupt flag, */
+#define LCDBLKONIFG (0x0004) /* LCD_B LCD blinking on interrupt flag, */
+#define LCDNOCAPIFG (0x0008) /* LCD_B No cpacitance connected interrupt flag */
+#define LCDFRMIE (0x0100) /* LCD_B LCD frame interrupt enable */
+#define LCDBLKOFFIE (0x0200) /* LCD_B LCD blinking off interrupt flag, */
+#define LCDBLKONIE (0x0400) /* LCD_B LCD blinking on interrupt flag, */
+#define LCDNOCAPIE (0x0800) /* LCD_B No cpacitance connected interrupt enable */
+
+// LCDBCTL1
+#define LCDFRMIFG_L (0x0001) /* LCD_B LCD frame interrupt flag */
+#define LCDBLKOFFIFG_L (0x0002) /* LCD_B LCD blinking off interrupt flag, */
+#define LCDBLKONIFG_L (0x0004) /* LCD_B LCD blinking on interrupt flag, */
+#define LCDNOCAPIFG_L (0x0008) /* LCD_B No cpacitance connected interrupt flag */
+
+// LCDBCTL1
+#define LCDFRMIE_H (0x0001) /* LCD_B LCD frame interrupt enable */
+#define LCDBLKOFFIE_H (0x0002) /* LCD_B LCD blinking off interrupt flag, */
+#define LCDBLKONIE_H (0x0004) /* LCD_B LCD blinking on interrupt flag, */
+#define LCDNOCAPIE_H (0x0008) /* LCD_B No cpacitance connected interrupt enable */
+
+// LCDBBLKCTL
+#define LCDBLKMOD0 (0x0001) /* LCD_B Blinking mode Bit: 0 */
+#define LCDBLKMOD1 (0x0002) /* LCD_B Blinking mode Bit: 1 */
+#define LCDBLKPRE0 (0x0004) /* LCD_B Clock pre-scaler for blinking frequency Bit: 0 */
+#define LCDBLKPRE1 (0x0008) /* LCD_B Clock pre-scaler for blinking frequency Bit: 1 */
+#define LCDBLKPRE2 (0x0010) /* LCD_B Clock pre-scaler for blinking frequency Bit: 2 */
+#define LCDBLKDIV0 (0x0020) /* LCD_B Clock divider for blinking frequency Bit: 0 */
+#define LCDBLKDIV1 (0x0040) /* LCD_B Clock divider for blinking frequency Bit: 1 */
+#define LCDBLKDIV2 (0x0080) /* LCD_B Clock divider for blinking frequency Bit: 2 */
+
+// LCDBBLKCTL
+#define LCDBLKMOD0_L (0x0001) /* LCD_B Blinking mode Bit: 0 */
+#define LCDBLKMOD1_L (0x0002) /* LCD_B Blinking mode Bit: 1 */
+#define LCDBLKPRE0_L (0x0004) /* LCD_B Clock pre-scaler for blinking frequency Bit: 0 */
+#define LCDBLKPRE1_L (0x0008) /* LCD_B Clock pre-scaler for blinking frequency Bit: 1 */
+#define LCDBLKPRE2_L (0x0010) /* LCD_B Clock pre-scaler for blinking frequency Bit: 2 */
+#define LCDBLKDIV0_L (0x0020) /* LCD_B Clock divider for blinking frequency Bit: 0 */
+#define LCDBLKDIV1_L (0x0040) /* LCD_B Clock divider for blinking frequency Bit: 1 */
+#define LCDBLKDIV2_L (0x0080) /* LCD_B Clock divider for blinking frequency Bit: 2 */
+
+// LCDBBLKCTL
+
+#define LCDBLKMOD_0 (0x0000) /* LCD_B Blinking mode: Off */
+#define LCDBLKMOD_1 (0x0001) /* LCD_B Blinking mode: Individual */
+#define LCDBLKMOD_2 (0x0002) /* LCD_B Blinking mode: All */
+#define LCDBLKMOD_3 (0x0003) /* LCD_B Blinking mode: Switching */
+
+// LCDBMEMCTL
+#define LCDDISP (0x0001) /* LCD_B LCD memory registers for display */
+#define LCDCLRM (0x0002) /* LCD_B Clear LCD memory */
+#define LCDCLRBM (0x0004) /* LCD_B Clear LCD blinking memory */
+
+// LCDBMEMCTL
+#define LCDDISP_L (0x0001) /* LCD_B LCD memory registers for display */
+#define LCDCLRM_L (0x0002) /* LCD_B Clear LCD memory */
+#define LCDCLRBM_L (0x0004) /* LCD_B Clear LCD blinking memory */
+
+// LCDBMEMCTL
+
+// LCDBVCTL
+#define LCD2B (0x0001) /* Selects 1/2 bias. */
+#define VLCDREF0 (0x0002) /* Selects reference voltage for regulated charge pump: 0 */
+#define VLCDREF1 (0x0004) /* Selects reference voltage for regulated charge pump: 1 */
+#define LCDCPEN (0x0008) /* LCD Voltage Charge Pump Enable. */
+#define VLCDEXT (0x0010) /* Select external source for VLCD. */
+#define LCDEXTBIAS (0x0020) /* V2 - V4 voltage select. */
+#define R03EXT (0x0040) /* Selects external connections for LCD mid voltages. */
+#define LCDREXT (0x0080) /* Selects external connection for lowest LCD voltage. */
+#define VLCD0 (0x0200) /* VLCD select: 0 */
+#define VLCD1 (0x0400) /* VLCD select: 1 */
+#define VLCD2 (0x0800) /* VLCD select: 2 */
+#define VLCD3 (0x1000) /* VLCD select: 3 */
+
+// LCDBVCTL
+#define LCD2B_L (0x0001) /* Selects 1/2 bias. */
+#define VLCDREF0_L (0x0002) /* Selects reference voltage for regulated charge pump: 0 */
+#define VLCDREF1_L (0x0004) /* Selects reference voltage for regulated charge pump: 1 */
+#define LCDCPEN_L (0x0008) /* LCD Voltage Charge Pump Enable. */
+#define VLCDEXT_L (0x0010) /* Select external source for VLCD. */
+#define LCDEXTBIAS_L (0x0020) /* V2 - V4 voltage select. */
+#define R03EXT_L (0x0040) /* Selects external connections for LCD mid voltages. */
+#define LCDREXT_L (0x0080) /* Selects external connection for lowest LCD voltage. */
+
+// LCDBVCTL
+#define VLCD0_H (0x0002) /* VLCD select: 0 */
+#define VLCD1_H (0x0004) /* VLCD select: 1 */
+#define VLCD2_H (0x0008) /* VLCD select: 2 */
+#define VLCD3_H (0x0010) /* VLCD select: 3 */
+
+/* Reference voltage source select for the regulated charge pump */
+#define VLCDREF_0 (0<<1) /* Internal */
+#define VLCDREF_1 (1<<1) /* External */
+#define VLCDREF_2 (2<<1) /* Reserved */
+#define VLCDREF_3 (3<<1) /* Reserved */
+
+/* Charge pump voltage selections */
+#define VLCD_0 (0<<9) /* Charge pump disabled */
+#define VLCD_1 (1<<9) /* VLCD = 2.60V */
+#define VLCD_2 (2<<9) /* VLCD = 2.66V */
+#define VLCD_3 (3<<9) /* VLCD = 2.72V */
+#define VLCD_4 (4<<9) /* VLCD = 2.78V */
+#define VLCD_5 (5<<9) /* VLCD = 2.84V */
+#define VLCD_6 (6<<9) /* VLCD = 2.90V */
+#define VLCD_7 (7<<9) /* VLCD = 2.96V */
+#define VLCD_8 (8<<9) /* VLCD = 3.02V */
+#define VLCD_9 (9<<9) /* VLCD = 3.08V */
+#define VLCD_10 (10<<9) /* VLCD = 3.14V */
+#define VLCD_11 (11<<9) /* VLCD = 3.20V */
+#define VLCD_12 (12<<9) /* VLCD = 3.26V */
+#define VLCD_13 (12<<9) /* VLCD = 3.32V */
+#define VLCD_14 (13<<9) /* VLCD = 3.38V */
+#define VLCD_15 (15<<9) /* VLCD = 3.44V */
+
+#define VLCD_DISABLED (0<<9) /* Charge pump disabled */
+#define VLCD_2_60 (1<<9) /* VLCD = 2.60V */
+#define VLCD_2_66 (2<<9) /* VLCD = 2.66V */
+#define VLCD_2_72 (3<<9) /* VLCD = 2.72V */
+#define VLCD_2_78 (4<<9) /* VLCD = 2.78V */
+#define VLCD_2_84 (5<<9) /* VLCD = 2.84V */
+#define VLCD_2_90 (6<<9) /* VLCD = 2.90V */
+#define VLCD_2_96 (7<<9) /* VLCD = 2.96V */
+#define VLCD_3_02 (8<<9) /* VLCD = 3.02V */
+#define VLCD_3_08 (9<<9) /* VLCD = 3.08V */
+#define VLCD_3_14 (10<<9) /* VLCD = 3.14V */
+#define VLCD_3_20 (11<<9) /* VLCD = 3.20V */
+#define VLCD_3_26 (12<<9) /* VLCD = 3.26V */
+#define VLCD_3_32 (12<<9) /* VLCD = 3.32V */
+#define VLCD_3_38 (13<<9) /* VLCD = 3.38V */
+#define VLCD_3_44 (15<<9) /* VLCD = 3.44V */
+
+// LCDBPCTL0
+#define LCDS0 (0x0001) /* LCD Segment 0 enable. */
+#define LCDS1 (0x0002) /* LCD Segment 1 enable. */
+#define LCDS2 (0x0004) /* LCD Segment 2 enable. */
+#define LCDS3 (0x0008) /* LCD Segment 3 enable. */
+#define LCDS4 (0x0010) /* LCD Segment 4 enable. */
+#define LCDS5 (0x0020) /* LCD Segment 5 enable. */
+#define LCDS6 (0x0040) /* LCD Segment 6 enable. */
+#define LCDS7 (0x0080) /* LCD Segment 7 enable. */
+#define LCDS8 (0x0100) /* LCD Segment 8 enable. */
+#define LCDS9 (0x0200) /* LCD Segment 9 enable. */
+#define LCDS10 (0x0400) /* LCD Segment 10 enable. */
+#define LCDS11 (0x0800) /* LCD Segment 11 enable. */
+#define LCDS12 (0x1000) /* LCD Segment 12 enable. */
+#define LCDS13 (0x2000) /* LCD Segment 13 enable. */
+#define LCDS14 (0x4000) /* LCD Segment 14 enable. */
+#define LCDS15 (0x8000) /* LCD Segment 15 enable. */
+
+// LCDBPCTL0
+#define LCDS0_L (0x0001) /* LCD Segment 0 enable. */
+#define LCDS1_L (0x0002) /* LCD Segment 1 enable. */
+#define LCDS2_L (0x0004) /* LCD Segment 2 enable. */
+#define LCDS3_L (0x0008) /* LCD Segment 3 enable. */
+#define LCDS4_L (0x0010) /* LCD Segment 4 enable. */
+#define LCDS5_L (0x0020) /* LCD Segment 5 enable. */
+#define LCDS6_L (0x0040) /* LCD Segment 6 enable. */
+#define LCDS7_L (0x0080) /* LCD Segment 7 enable. */
+
+// LCDBPCTL0
+#define LCDS8_H (0x0001) /* LCD Segment 8 enable. */
+#define LCDS9_H (0x0002) /* LCD Segment 9 enable. */
+#define LCDS10_H (0x0004) /* LCD Segment 10 enable. */
+#define LCDS11_H (0x0008) /* LCD Segment 11 enable. */
+#define LCDS12_H (0x0010) /* LCD Segment 12 enable. */
+#define LCDS13_H (0x0020) /* LCD Segment 13 enable. */
+#define LCDS14_H (0x0040) /* LCD Segment 14 enable. */
+#define LCDS15_H (0x0080) /* LCD Segment 15 enable. */
+
+// LCDBPCTL1
+#define LCDS16 (0x0001) /* LCD Segment 16 enable. */
+#define LCDS17 (0x0002) /* LCD Segment 17 enable. */
+#define LCDS18 (0x0004) /* LCD Segment 18 enable. */
+#define LCDS19 (0x0008) /* LCD Segment 19 enable. */
+#define LCDS20 (0x0010) /* LCD Segment 20 enable. */
+#define LCDS21 (0x0020) /* LCD Segment 21 enable. */
+#define LCDS22 (0x0040) /* LCD Segment 22 enable. */
+#define LCDS23 (0x0080) /* LCD Segment 23 enable. */
+#define LCDS24 (0x0100) /* LCD Segment 24 enable. */
+#define LCDS25 (0x0200) /* LCD Segment 25 enable. */
+#define LCDS26 (0x0400) /* LCD Segment 26 enable. */
+#define LCDS27 (0x0800) /* LCD Segment 27 enable. */
+#define LCDS28 (0x1000) /* LCD Segment 28 enable. */
+#define LCDS29 (0x2000) /* LCD Segment 29 enable. */
+#define LCDS30 (0x4000) /* LCD Segment 30 enable. */
+#define LCDS31 (0x8000) /* LCD Segment 31 enable. */
+
+// LCDBPCTL1
+#define LCDS16_L (0x0001) /* LCD Segment 16 enable. */
+#define LCDS17_L (0x0002) /* LCD Segment 17 enable. */
+#define LCDS18_L (0x0004) /* LCD Segment 18 enable. */
+#define LCDS19_L (0x0008) /* LCD Segment 19 enable. */
+#define LCDS20_L (0x0010) /* LCD Segment 20 enable. */
+#define LCDS21_L (0x0020) /* LCD Segment 21 enable. */
+#define LCDS22_L (0x0040) /* LCD Segment 22 enable. */
+#define LCDS23_L (0x0080) /* LCD Segment 23 enable. */
+
+// LCDBPCTL1
+#define LCDS24_H (0x0001) /* LCD Segment 24 enable. */
+#define LCDS25_H (0x0002) /* LCD Segment 25 enable. */
+#define LCDS26_H (0x0004) /* LCD Segment 26 enable. */
+#define LCDS27_H (0x0008) /* LCD Segment 27 enable. */
+#define LCDS28_H (0x0010) /* LCD Segment 28 enable. */
+#define LCDS29_H (0x0020) /* LCD Segment 29 enable. */
+#define LCDS30_H (0x0040) /* LCD Segment 30 enable. */
+#define LCDS31_H (0x0080) /* LCD Segment 31 enable. */
+
+// LCDBPCTL2
+#define LCDS32 (0x0001) /* LCD Segment 32 enable. */
+#define LCDS33 (0x0002) /* LCD Segment 33 enable. */
+#define LCDS34 (0x0004) /* LCD Segment 34 enable. */
+#define LCDS35 (0x0008) /* LCD Segment 35 enable. */
+#define LCDS36 (0x0010) /* LCD Segment 36 enable. */
+#define LCDS37 (0x0020) /* LCD Segment 37 enable. */
+#define LCDS38 (0x0040) /* LCD Segment 38 enable. */
+#define LCDS39 (0x0080) /* LCD Segment 39 enable. */
+#define LCDS40 (0x0100) /* LCD Segment 40 enable. */
+#define LCDS41 (0x0200) /* LCD Segment 41 enable. */
+#define LCDS42 (0x0400) /* LCD Segment 42 enable. */
+#define LCDS43 (0x0800) /* LCD Segment 43 enable. */
+#define LCDS44 (0x1000) /* LCD Segment 44 enable. */
+#define LCDS45 (0x2000) /* LCD Segment 45 enable. */
+#define LCDS46 (0x4000) /* LCD Segment 46 enable. */
+#define LCDS47 (0x8000) /* LCD Segment 47 enable. */
+
+// LCDBPCTL2
+#define LCDS32_L (0x0001) /* LCD Segment 32 enable. */
+#define LCDS33_L (0x0002) /* LCD Segment 33 enable. */
+#define LCDS34_L (0x0004) /* LCD Segment 34 enable. */
+#define LCDS35_L (0x0008) /* LCD Segment 35 enable. */
+#define LCDS36_L (0x0010) /* LCD Segment 36 enable. */
+#define LCDS37_L (0x0020) /* LCD Segment 37 enable. */
+#define LCDS38_L (0x0040) /* LCD Segment 38 enable. */
+#define LCDS39_L (0x0080) /* LCD Segment 39 enable. */
+
+// LCDBPCTL2
+#define LCDS40_H (0x0001) /* LCD Segment 40 enable. */
+#define LCDS41_H (0x0002) /* LCD Segment 41 enable. */
+#define LCDS42_H (0x0004) /* LCD Segment 42 enable. */
+#define LCDS43_H (0x0008) /* LCD Segment 43 enable. */
+#define LCDS44_H (0x0010) /* LCD Segment 44 enable. */
+#define LCDS45_H (0x0020) /* LCD Segment 45 enable. */
+#define LCDS46_H (0x0040) /* LCD Segment 46 enable. */
+#define LCDS47_H (0x0080) /* LCD Segment 47 enable. */
+
+// LCDBPCTL3
+#define LCDS48 (0x0001) /* LCD Segment 48 enable. */
+#define LCDS49 (0x0002) /* LCD Segment 49 enable. */
+#define LCDS50 (0x0004) /* LCD Segment 50 enable. */
+
+// LCDBPCTL3
+#define LCDS48_L (0x0001) /* LCD Segment 48 enable. */
+#define LCDS49_L (0x0002) /* LCD Segment 49 enable. */
+#define LCDS50_L (0x0004) /* LCD Segment 50 enable. */
+
+// LCDBPCTL3
+
+// LCDBCPCTL
+#define LCDCPDIS0 (0x0001) /* LCD charge pump disable */
+#define LCDCPDIS1 (0x0002) /* LCD charge pump disable */
+#define LCDCPDIS2 (0x0004) /* LCD charge pump disable */
+#define LCDCPDIS3 (0x0008) /* LCD charge pump disable */
+#define LCDCPDIS4 (0x0010) /* LCD charge pump disable */
+#define LCDCPDIS5 (0x0020) /* LCD charge pump disable */
+#define LCDCPDIS6 (0x0040) /* LCD charge pump disable */
+#define LCDCPDIS7 (0x0080) /* LCD charge pump disable */
+#define LCDCPCLKSYNC (0x8000) /* LCD charge pump clock synchronization */
+
+// LCDBCPCTL
+#define LCDCPDIS0_L (0x0001) /* LCD charge pump disable */
+#define LCDCPDIS1_L (0x0002) /* LCD charge pump disable */
+#define LCDCPDIS2_L (0x0004) /* LCD charge pump disable */
+#define LCDCPDIS3_L (0x0008) /* LCD charge pump disable */
+#define LCDCPDIS4_L (0x0010) /* LCD charge pump disable */
+#define LCDCPDIS5_L (0x0020) /* LCD charge pump disable */
+#define LCDCPDIS6_L (0x0040) /* LCD charge pump disable */
+#define LCDCPDIS7_L (0x0080) /* LCD charge pump disable */
+
+// LCDBCPCTL
+#define LCDCPCLKSYNC_H (0x0080) /* LCD charge pump clock synchronization */
+
+#define LCDM1_ __MSP430_LCD_B_BASE__ + 0x20 /* LCD Memory 1 */
+sfrb(LCDM1, LCDM1_);
+#define LCDMEM_ LCDM1 /* LCD Memory */
+#ifdef __ASM_HEADER__
+#define LCDMEM LCDM1 /* LCD Memory (for assembler) */
+#else
+#define LCDMEM ((char*) &LCDM1) /* LCD Memory (for C) */
+#endif
+#define LCDM2_ __MSP430_LCD_B_BASE__ + 0x21 /* LCD Memory 2 */
+sfrb(LCDM2, LCDM2_);
+#define LCDM3_ __MSP430_LCD_B_BASE__ + 0x22 /* LCD Memory 3 */
+sfrb(LCDM3, LCDM3_);
+#define LCDM4_ __MSP430_LCD_B_BASE__ + 0x23 /* LCD Memory 4 */
+sfrb(LCDM4, LCDM4_);
+#define LCDM5_ __MSP430_LCD_B_BASE__ + 0x24 /* LCD Memory 5 */
+sfrb(LCDM5, LCDM5_);
+#define LCDM6_ __MSP430_LCD_B_BASE__ + 0x25 /* LCD Memory 6 */
+sfrb(LCDM6, LCDM6_);
+#define LCDM7_ __MSP430_LCD_B_BASE__ + 0x26 /* LCD Memory 7 */
+sfrb(LCDM7, LCDM7_);
+#define LCDM8_ __MSP430_LCD_B_BASE__ + 0x27 /* LCD Memory 8 */
+sfrb(LCDM8, LCDM8_);
+#define LCDM9_ __MSP430_LCD_B_BASE__ + 0x28 /* LCD Memory 9 */
+sfrb(LCDM9, LCDM9_);
+#define LCDM10_ __MSP430_LCD_B_BASE__ + 0x29 /* LCD Memory 10 */
+sfrb(LCDM10, LCDM10_);
+#define LCDM11_ __MSP430_LCD_B_BASE__ + 0x2a /* LCD Memory 11 */
+sfrb(LCDM11, LCDM11_);
+#define LCDM12_ __MSP430_LCD_B_BASE__ + 0x2b /* LCD Memory 12 */
+sfrb(LCDM12, LCDM12_);
+#define LCDM13_ __MSP430_LCD_B_BASE__ + 0x2c /* LCD Memory 13 */
+sfrb(LCDM13, LCDM13_);
+#define LCDM14_ __MSP430_LCD_B_BASE__ + 0x2d /* LCD Memory 14 */
+sfrb(LCDM14, LCDM14_);
+#define LCDM15_ __MSP430_LCD_B_BASE__ + 0x2e /* LCD Memory 15 */
+sfrb(LCDM15, LCDM15_);
+#define LCDM16_ __MSP430_LCD_B_BASE__ + 0x2f /* LCD Memory 16 */
+sfrb(LCDM16, LCDM16_);
+#define LCDM17_ __MSP430_LCD_B_BASE__ + 0x30 /* LCD Memory 17 */
+sfrb(LCDM17, LCDM17_);
+#define LCDM18_ __MSP430_LCD_B_BASE__ + 0x31 /* LCD Memory 18 */
+sfrb(LCDM18, LCDM18_);
+#define LCDM19_ __MSP430_LCD_B_BASE__ + 0x32 /* LCD Memory 19 */
+sfrb(LCDM19, LCDM19_);
+#define LCDM20_ __MSP430_LCD_B_BASE__ + 0x33 /* LCD Memory 20 */
+sfrb(LCDM20, LCDM20_);
+#define LCDM21_ __MSP430_LCD_B_BASE__ + 0x34 /* LCD Memory 20 */
+sfrb(LCDM21, LCDM21_);
+#define LCDM22_ __MSP430_LCD_B_BASE__ + 0x35 /* LCD Memory 20 */
+sfrb(LCDM22, LCDM22_);
+#define LCDM23_ __MSP430_LCD_B_BASE__ + 0x36 /* LCD Memory 20 */
+sfrb(LCDM23, LCDM23_);
+#define LCDM24_ __MSP430_LCD_B_BASE__ + 0x37 /* LCD Memory 20 */
+sfrb(LCDM24, LCDM24_);
+
+#define LCDBM1_ __MSP430_LCD_B_BASE__ + 0x40 /* LCD Blinking Memory 1 */
+sfrb(LCDBM1, LCDBM1_);
+#define LCDBMEM_ LCDBM1 /* LCD Blinking Memory */
+#ifdef __ASM_HEADER__
+#define LCDBMEM (LCDBM1) /* LCD Blinking Memory (for assembler) */
+#else
+#define LCDBMEM ((char*) &LCDBM1) /* LCD Blinking Memory (for C) */
+#endif
+#define LCDBM2_ __MSP430_LCD_B_BASE__ + 0x41 /* LCD Blinking Memory 2 */
+sfrb(LCDBM2, LCDBM2_);
+#define LCDBM3_ __MSP430_LCD_B_BASE__ + 0x42 /* LCD Blinking Memory 3 */
+sfrb(LCDBM3, LCDBM3_);
+#define LCDBM4_ __MSP430_LCD_B_BASE__ + 0x43 /* LCD Blinking Memory 4 */
+sfrb(LCDBM4, LCDBM4_);
+#define LCDBM5_ __MSP430_LCD_B_BASE__ + 0x44 /* LCD Blinking Memory 5 */
+sfrb(LCDBM5, LCDBM5_);
+#define LCDBM6_ __MSP430_LCD_B_BASE__ + 0x45 /* LCD Blinking Memory 6 */
+sfrb(LCDBM6, LCDBM6_);
+#define LCDBM7_ __MSP430_LCD_B_BASE__ + 0x46 /* LCD Blinking Memory 7 */
+sfrb(LCDBM7, LCDBM7_);
+#define LCDBM8_ __MSP430_LCD_B_BASE__ + 0x47 /* LCD Blinking Memory 8 */
+sfrb(LCDBM8, LCDBM8_);
+#define LCDBM9_ __MSP430_LCD_B_BASE__ + 0x48 /* LCD Blinking Memory 9 */
+sfrb(LCDBM9, LCDBM9_);
+#define LCDBM10_ __MSP430_LCD_B_BASE__ + 0x49 /* LCD Blinking Memory 10 */
+sfrb(LCDBM10, LCDBM10_);
+#define LCDBM11_ __MSP430_LCD_B_BASE__ + 0x4a /* LCD Blinking Memory 11 */
+sfrb(LCDBM11, LCDBM11_);
+#define LCDBM12_ __MSP430_LCD_B_BASE__ + 0x4b /* LCD Blinking Memory 12 */
+sfrb(LCDBM12, LCDBM12_);
+#define LCDBM13_ __MSP430_LCD_B_BASE__ + 0x4c /* LCD Blinking Memory 13 */
+sfrb(LCDBM13, LCDBM13_);
+#define LCDBM14_ __MSP430_LCD_B_BASE__ + 0x4d /* LCD Blinking Memory 14 */
+sfrb(LCDBM14, LCDBM14_);
+#define LCDBM15_ __MSP430_LCD_B_BASE__ + 0x4e /* LCD Blinking Memory 15 */
+sfrb(LCDBM15, LCDBM15_);
+#define LCDBM16_ __MSP430_LCD_B_BASE__ + 0x4f /* LCD Blinking Memory 16 */
+sfrb(LCDBM16, LCDBM16_);
+#define LCDBM17_ __MSP430_LCD_B_BASE__ + 0x50 /* LCD Blinking Memory 17 */
+sfrb(LCDBM17, LCDBM17_);
+#define LCDBM18_ __MSP430_LCD_B_BASE__ + 0x51 /* LCD Blinking Memory 18 */
+sfrb(LCDBM18, LCDBM18_);
+#define LCDBM19_ __MSP430_LCD_B_BASE__ + 0x52 /* LCD Blinking Memory 19 */
+sfrb(LCDBM19, LCDBM19_);
+#define LCDBM20_ __MSP430_LCD_B_BASE__ + 0x53 /* LCD Blinking Memory 20 */
+sfrb(LCDBM20, LCDBM20_);
+#define LCDBM21_ __MSP430_LCD_B_BASE__ + 0x54 /* LCD Blinking Memory 20 */
+sfrb(LCDBM21, LCDBM21_);
+#define LCDBM22_ __MSP430_LCD_B_BASE__ + 0x55 /* LCD Blinking Memory 20 */
+sfrb(LCDBM22, LCDBM22_);
+#define LCDBM23_ __MSP430_LCD_B_BASE__ + 0x56 /* LCD Blinking Memory 20 */
+sfrb(LCDBM23, LCDBM23_);
+#define LCDBM24_ __MSP430_LCD_B_BASE__ + 0x57 /* LCD Blinking Memory 20 */
+sfrb(LCDBM24, LCDBM24_);
+
+/* LCDBIV Definitions */
+#define LCDBIV_NONE (0x0000) /* No Interrupt pending */
+#define LCDBIV_LCDNOCAPIFG (0x0002) /* No capacitor connected */
+#define LCDBIV_LCDBLKOFFIFG (0x0004) /* Blink, segments off */
+#define LCDBIV_LCDBLKONIFG (0x0006) /* Blink, segments on */
+#define LCDBIV_LCDFRMIFG (0x0008) /* Frame interrupt */
+
+#endif /* __MSP430_LCD_B_BASE__ */
+
+#endif /* __MSP430_HEADERS_LCD_B_H__ */
+
--- /dev/null
+#ifndef __MSP430_HEADERS_MPY32_H
+#define __MSP430_HEADERS_MPY32_H
+
+/* mpy.h
+ *
+ * mspgcc project: MSP430 device headers
+ * Hardware 32-bit multiplier
+ *
+ * (c) 2008 by Sergey A. Borshch <sb-sf@sourceforge.net>
+ * Originally based in MSP430F543x datasheet (slas609)
+ * and MSP430x5xx Family User's Guide (slau208).
+ *
+ * $Id: mpy32.h,v 1.3 2008/12/15 12:48:20 sb-sf Exp $
+ */
+
+/* Switches:
+
+__MSP430_MPY32_BASE__ - base address of MPY32 module
+
+*/
+#if defined(__MSP430_MPY32_BASE__)
+#define MPY_ __MSP430_MPY32_BASE__ + 0x00 /* 16-bit operand 1 - multiply */
+sfrw(MPY, MPY_);
+#define MPYS_ __MSP430_MPY32_BASE__ + 0x02 /* 16-bit operand 1 - signed multiply */
+sfrw(MPYS, MPYS_);
+#define MAC_ __MSP430_MPY32_BASE__ + 0x04 /* 16-bit operand 1 - multiply accumulate */
+sfrw(MAC, MAC_);
+#define MACS_ __MSP430_MPY32_BASE__ + 0x06 /* 16-bit operand 1 - signed multiply accumulate */
+sfrw(MACS, MACS_);
+#define OP2_ __MSP430_MPY32_BASE__ + 0x08 /* 16-bit operand 2 */
+sfrw(OP2, OP2_);
+#define RESLO_ __MSP430_MPY32_BASE__ + 0x0A /* 16x16 result low word */
+sfrw(RESLO, RESLO_);
+#define RESHI_ __MSP430_MPY32_BASE__ + 0x0C /* 16x16 result high word */
+sfrw(RESHI, RESHI_);
+#define SUMEXT_ __MSP430_MPY32_BASE__ + 0x0E /* 16x16 sum extension */
+sfrw(SUMEXT, SUMEXT_);
+#define MPY32L_ __MSP430_MPY32_BASE__ + 0x10 /* 32-bit operand 1 - multiply low word */
+sfrw(MPY32L, MPY32L_);
+#define MPY32H_ __MSP430_MPY32_BASE__ + 0x12 /* 32-bit operand 1 - multiply high word */
+sfrw(MPY32H, MPY32H_);
+#define MPYS32L_ __MSP430_MPY32_BASE__ + 0x14 /* 32-bit operand 1 - signed multiply low word */
+sfrw(MPYS32L, MPYS32L_);
+#define MPYS32H_ __MSP430_MPY32_BASE__ + 0x16 /* 32-bit operand 1 - signed multiply high word */
+sfrw(MPYS32H, MPYS32H_);
+#define MAC32L_ __MSP430_MPY32_BASE__ + 0x18 /* 32-bit operand 1 - multiply accumulate low word */
+sfrw(MAC32L, MAC32L_);
+#define MAC32H_ __MSP430_MPY32_BASE__ + 0x1A /* 32-bit operand 1 - multiply accumulate high word */
+sfrw(MAC32H, MAC32H_);
+#define MACS32L_ __MSP430_MPY32_BASE__ + 0x1C /* 32-bit operand 1 - signed multiply accumulate low word */
+sfrw(MACS32L, MACS32L_);
+#define MACS32H_ __MSP430_MPY32_BASE__ + 0x1E /* 32-bit operand 1 - signed multiply accumulate high word */
+sfrw(MACS32H, MACS32H_);
+#define OP2L_ __MSP430_MPY32_BASE__ + 0x20 /* 32-bit operand 2 - low word */
+sfrw(OP2L, OP2L_);
+#define OP2H_ __MSP430_MPY32_BASE__ + 0x22 /* 32-bit operand 2 - high word */
+sfrw(OP2H, OP2H_);
+#define RES0_ __MSP430_MPY32_BASE__ + 0x24 /* 32x32 result 3 - least significant word */
+sfrw(RES0,RES0_);
+#define RES1_ __MSP430_MPY32_BASE__ + 0x26
+sfrw(RES1,RES1_);
+#define RES2_ __MSP430_MPY32_BASE__ + 0x28
+sfrw(RES2,RES2_);
+#define RES3_ __MSP430_MPY32_BASE__ + 0x2A /* 32x32 result 3 - most significant word */
+sfrw(RES3,RES3_);
+#define MPY32CTL0_ __MSP430_MPY32_BASE__ + 0x2C /* MPY32 control register 0 */
+sfrw(MPY32CTL0,MPY32CTL0_);
+#endif /* defined(__MSP430_MPY32_BASE__) */
+
+#define MPYDLY32 (1<<9) /* Delayed write mode */
+#define MPYDLYWRTEN (1<<8) /* Delayed write enable */
+#define MPYPO2_32 (1<<7) /* Multiplier bit width of operand 2 */
+#define MPYPO1_32 (1<<6) /* Multiplier bit width of operand 1 */
+#define MPYM1 (1<<5) /* Multiplier mode */
+#define MPYM0 (1<<4) /* -- // -- */
+#define MPYSAT (1<<3) /* Saturation mode */
+#define MPYFRAC (1<<2) /* Fractional mode */
+#define MPYC (1<<0) /* Carry of the multiplier */
+
+#define MPYM_0 (0<<4) /* Multiply */
+#define MPYM_1 (1<<4) /* Signed multiply */
+#define MPYM_2 (2<<4) /* Multiply accumulate */
+#define MPYM_3 (3<<4) /* Signed multiply accumulate */
+
+
+#ifndef __ASSEMBLER__
+/* Structured declaration */
+
+#undef __xstr
+#undef __str
+#define __xstr(x) __str(x)
+#define __str(x) #x
+
+typedef struct
+{
+ volatile unsigned int MPY; /* 16-bit operand 1 - multiply */
+ volatile unsigned int MPYS; /* 16-bit operand 1 - signed multiply */
+ volatile unsigned int MAC; /* 16-bit operand 1 - multiply accumulate */
+ volatile unsigned int MACS; /* 16-bit operand 1 - signed multiply accumulate */
+ volatile unsigned int OP2; /* 16-bit operand 2 */
+ volatile unsigned int RESLO; /* 16x16 result low word */
+ volatile unsigned int RESHI; /* 16x16 result high word */
+ volatile unsigned int SUMEXT; /* 16x16 sum extension */
+ volatile unsigned int MPY32L; /* 32-bit operand 1 - multiply low word */
+ volatile unsigned int MPY32H; /* 32-bit operand 1 - multiply high word */
+ volatile unsigned int MPYS32L; /* 32-bit operand 1 - signed multiply low word */
+ volatile unsigned int MPYS32H; /* 32-bit operand 1 - signed multiply high word */
+ volatile unsigned int MAC32L; /* 32-bit operand 1 - multiply accumulate low word */
+ volatile unsigned int MAC32H; /* 32-bit operand 1 - multiply accumulate high word */
+ volatile unsigned int MACS32L; /* 32-bit operand 1 - signed multiply accumulate low word */
+ volatile unsigned int MACS32H; /* 32-bit operand 1 - signed multiply accumulate high word */
+ volatile unsigned int OP2L; /* 32-bit operand 2 - low word */
+ volatile unsigned int OP2H; /* 32-bit operand 2 - high word */
+ volatile unsigned int RES0; /* 32x32 result 3 - least significant word */
+ volatile unsigned int RES1;
+ volatile unsigned int RES2;
+ volatile unsigned int RES3; /* 32x32 result 3 - most significant word */
+ volatile unsigned int MPY32CTL0; /* MPY32 control register 0 */
+} mpy32_t;
+mpy32_t mpy32 asm(__xstr(__MSP430_MPY32_BASE__));
+#undef __str
+#undef __xstr
+#endif /* __ASSEMBLER__ */
+
+#endif /* __MSP430_HEADERS_MPY32_H */
--- /dev/null
+#ifndef __MSP430_HEADERS_PMCONTROL_H
+#define __MSP430_HEADERS_PMCONTROL_H
+
+/* pmcontrol.h
+ *
+ * mspgcc project: MSP430 device headers
+ * Port Mapping Controller
+ *
+ */
+
+/* Switches:
+
+__MSP430_PORT_MAPPING_BASE__ - base address of the port mapping control module
+__MSP430_PORT1_MAPPING_BASE__ - PORT1 present in device if defined
+__MSP430_PORT2_MAPPING_BASE__ - PORT2 present in device if defined
+__MSP430_PORT3_MAPPING_BASE__ - PORT3 present in device if defined
+
+*/
+
+#if defined(__MSP430_PORT_MAPPING_BASE__)
+
+#define PMAPPWD_ __MSP430_PORT_MAPPING_BASE__ + 0x00 /* Port mapping password register */
+#define PMAPPWD_L_ __MSP430_PORT_MAPPING_BASE__ + 0x00 /* Port mapping control register */
+#define PMAPPWD_H_ __MSP430_PORT_MAPPING_BASE__ + 0x01 /* Port mapping control register */
+sfrw(PMAPPWD, PMAPPWD_); /* Port Mapping password register */
+sfrb(PMAPPWD_L, PMAPPWD_L_); /* Port Mapping password register */
+sfrb(PMAPPWD_H, PMAPPWD_H_); /* Port Mapping password register */
+#define PMAPCTL_ __MSP430_PORT_MAPPING_BASE__ + 0x02 /* Port mapping password register */
+#define PMAPCTL_L_ __MSP430_PORT_MAPPING_BASE__ + 0x02 /* Port mapping control register */
+#define PMAPCTL_H_ __MSP430_PORT_MAPPING_BASE__ + 0x03 /* Port mapping control register */
+sfrw(PMAPCTL, PMAPCTL_); /* Port Mapping control register */
+sfrb(PMAPCTL_L, PMAPCTL_L_); /* Port Mapping control register */
+sfrb(PMAPCTL_H, PMAPCTL_H_); /* Port Mapping control register */
+
+#define PMAPPW (0x2D52) /* Port Mapping Password */
+
+/* PMAPCTL Control Bits */
+#define PMAPLOCKED (0x0001) /* Port Mapping Lock bit. Read only */
+#define PMAPRECFG (0x0002) /* Port Mapping re-configuration control bit */
+
+/* PMAPCTL Control Bits */
+#define PMAPLOCKED_L (0x0001) /* Port Mapping Lock bit. Read only */
+#define PMAPRECFG_L (0x0002) /* Port Mapping re-configuration control bit */
+
+#endif /* __MSP430_PORT_MAPPING_BASE__ */
+
+#if defined(__MSP430_PORT1_MAPPING_BASE__)
+
+#define P1MAP01_ __MSP430_PORT1_MAPPING_BASE__ + 0x00 /* Port P1.0/1 mapping register */
+#define P1MAP01_L_ __MSP430_PORT1_MAPPING_BASE__ + 0x00 /* Port P1.0/1 mapping register */
+#define P1MAP01_H_ __MSP430_PORT1_MAPPING_BASE__ + 0x01 /* Port P1.0/1 mapping register */
+sfrw(P1MAP01, P1MAP01_);
+sfrb(P1MAP01_L, P1MAP01_L_);
+sfrb(P1MAP01_H, P1MAP01_H_);
+#define P1MAP23_ __MSP430_PORT1_MAPPING_BASE__ + 0x02 /* Port P1.2/3 mapping register */
+#define P1MAP23_L_ __MSP430_PORT1_MAPPING_BASE__ + 0x02 /* Port P1.2/3 mapping register */
+#define P1MAP23_H_ __MSP430_PORT1_MAPPING_BASE__ + 0x03 /* Port P1.2/3 mapping register */
+sfrw(P1MAP23, P1MAP23_);
+sfrb(P1MAP23_L, P1MAP23_L_);
+sfrb(P1MAP23_H, P1MAP23_H_);
+#define P1MAP45_ __MSP430_PORT1_MAPPING_BASE__ + 0x04 /* Port P1.4/5 mapping register */
+#define P1MAP45_L_ __MSP430_PORT1_MAPPING_BASE__ + 0x04 /* Port P1.4/5 mapping register */
+#define P1MAP45_H_ __MSP430_PORT1_MAPPING_BASE__ + 0x05 /* Port P1.4/5 mapping register */
+sfrw(P1MAP45, P1MAP45_);
+sfrb(P1MAP45_L, P1MAP45_L_);
+sfrb(P1MAP45_H, P1MAP45_H_);
+#define P1MAP67_ __MSP430_PORT1_MAPPING_BASE__ + 0x06 /* Port P1.6/7 mapping register */
+#define P1MAP67_L_ __MSP430_PORT1_MAPPING_BASE__ + 0x06 /* Port P1.6/7 mapping register */
+#define P1MAP67_H_ __MSP430_PORT1_MAPPING_BASE__ + 0x07 /* Port P1.6/7 mapping register */
+sfrw(P1MAP67, P1MAP67_);
+sfrb(P1MAP67_L, P1MAP67_L_);
+sfrb(P1MAP67_H, P1MAP67_H_);
+
+#define P1MAP0 P1MAP01_L /* Port P1.0 mapping register */
+#define P1MAP1 P1MAP01_H /* Port P1.1 mapping register */
+#define P1MAP2 P1MAP23_L /* Port P1.2 mapping register */
+#define P1MAP3 P1MAP23_H /* Port P1.3 mapping register */
+#define P1MAP4 P1MAP45_L /* Port P1.4 mapping register */
+#define P1MAP5 P1MAP45_H /* Port P1.5 mapping register */
+#define P1MAP6 P1MAP67_L /* Port P1.6 mapping register */
+#define P1MAP7 P1MAP67_H /* Port P1.7 mapping register */
+
+#endif /* __MSP430_PORT1_MAPPING_BASE__ */
+
+#if defined(__MSP430_PORT1_MAPPING_BASE__)
+
+#define P2MAP01_ __MSP430_PORT1_MAPPING_BASE__ + 0x00 /* Port P2.0/1 mapping register */
+#define P2MAP01_L_ __MSP430_PORT1_MAPPING_BASE__ + 0x00 /* Port P2.0/1 mapping register */
+#define P2MAP01_H_ __MSP430_PORT1_MAPPING_BASE__ + 0x01 /* Port P2.0/1 mapping register */
+sfrw(P2MAP01, P2MAP01_);
+sfrb(P2MAP01_L, P2MAP01_L_);
+sfrb(P2MAP01_H, P2MAP01_H_);
+#define P2MAP23_ __MSP430_PORT1_MAPPING_BASE__ + 0x02 /* Port P2.2/3 mapping register */
+#define P2MAP23_L_ __MSP430_PORT1_MAPPING_BASE__ + 0x02 /* Port P2.2/3 mapping register */
+#define P2MAP23_H_ __MSP430_PORT1_MAPPING_BASE__ + 0x03 /* Port P2.2/3 mapping register */
+sfrw(P2MAP23, P2MAP23_);
+sfrb(P2MAP23_L, P2MAP23_L_);
+sfrb(P2MAP23_H, P2MAP23_H_);
+#define P2MAP45_ __MSP430_PORT1_MAPPING_BASE__ + 0x04 /* Port P2.4/5 mapping register */
+#define P2MAP45_L_ __MSP430_PORT1_MAPPING_BASE__ + 0x04 /* Port P2.4/5 mapping register */
+#define P2MAP45_H_ __MSP430_PORT1_MAPPING_BASE__ + 0x05 /* Port P2.4/5 mapping register */
+sfrw(P2MAP45, P2MAP45_);
+sfrb(P2MAP45_L, P2MAP45_L_);
+sfrb(P2MAP45_H, P2MAP45_H_);
+#define P2MAP67_ __MSP430_PORT1_MAPPING_BASE__ + 0x06 /* Port P2.6/7 mapping register */
+#define P2MAP67_L_ __MSP430_PORT1_MAPPING_BASE__ + 0x06 /* Port P2.6/7 mapping register */
+#define P2MAP67_H_ __MSP430_PORT1_MAPPING_BASE__ + 0x07 /* Port P2.6/7 mapping register */
+sfrw(P2MAP67, P2MAP67_);
+sfrb(P2MAP67_L, P2MAP67_L_);
+sfrb(P2MAP67_H, P2MAP67_H_);
+
+#define P2MAP0 P2MAP01_L /* Port P2.0 mapping register */
+#define P2MAP1 P2MAP01_H /* Port P2.1 mapping register */
+#define P2MAP2 P2MAP23_L /* Port P2.2 mapping register */
+#define P2MAP3 P2MAP23_H /* Port P2.3 mapping register */
+#define P2MAP4 P2MAP45_L /* Port P2.4 mapping register */
+#define P2MAP5 P2MAP45_H /* Port P2.5 mapping register */
+#define P2MAP6 P2MAP67_L /* Port P2.6 mapping register */
+#define P2MAP7 P2MAP67_H /* Port P2.7 mapping register */
+
+#endif /* __MSP430_PORT2_MAPPING_BASE__ */
+
+#if defined(__MSP430_PORT3_MAPPING_BASE__)
+
+#define P3MAP01_ __MSP430_PORT1_MAPPING_BASE__ + 0x00 /* Port P3.0/1 mapping register */
+#define P3MAP01_L_ __MSP430_PORT1_MAPPING_BASE__ + 0x00 /* Port P3.0/1 mapping register */
+#define P3MAP01_H_ __MSP430_PORT1_MAPPING_BASE__ + 0x01 /* Port P3.0/1 mapping register */
+sfrw(P3MAP01, P3MAP01_);
+sfrb(P3MAP01_L, P3MAP01_L_);
+sfrb(P3MAP01_H, P3MAP01_H_);
+#define P3MAP23_ __MSP430_PORT1_MAPPING_BASE__ + 0x02 /* Port P3.2/3 mapping register */
+#define P3MAP23_L_ __MSP430_PORT1_MAPPING_BASE__ + 0x02 /* Port P3.2/3 mapping register */
+#define P3MAP23_H_ __MSP430_PORT1_MAPPING_BASE__ + 0x03 /* Port P3.2/3 mapping register */
+sfrw(P3MAP23, P3MAP23_);
+sfrb(P3MAP23_L, P3MAP23_L_);
+sfrb(P3MAP23_H, P3MAP23_H_);
+#define P3MAP45_ __MSP430_PORT1_MAPPING_BASE__ + 0x04 /* Port P3.4/5 mapping register */
+#define P3MAP45_L_ __MSP430_PORT1_MAPPING_BASE__ + 0x04 /* Port P3.4/5 mapping register */
+#define P3MAP45_H_ __MSP430_PORT1_MAPPING_BASE__ + 0x05 /* Port P3.4/5 mapping register */
+sfrw(P3MAP45, P3MAP45_);
+sfrb(P3MAP45_L, P3MAP45_L_);
+sfrb(P3MAP45_H, P3MAP45_H_);
+#define P3MAP67_ __MSP430_PORT1_MAPPING_BASE__ + 0x06 /* Port P3.6/7 mapping register */
+#define P3MAP67_L_ __MSP430_PORT1_MAPPING_BASE__ + 0x06 /* Port P3.6/7 mapping register */
+#define P3MAP67_H_ __MSP430_PORT1_MAPPING_BASE__ + 0x07 /* Port P3.6/7 mapping register */
+sfrw(P3MAP67, P3MAP67_);
+sfrb(P3MAP67_L, P3MAP67_L_);
+sfrb(P3MAP67_H, P3MAP67_H_);
+
+#define P3MAP0 P3MAP01_L /* Port P3.0 mapping register */
+#define P3MAP1 P3MAP01_H /* Port P3.1 mapping register */
+#define P3MAP2 P3MAP23_L /* Port P3.2 mapping register */
+#define P3MAP3 P3MAP23_H /* Port P3.3 mapping register */
+#define P3MAP4 P3MAP45_L /* Port P3.4 mapping register */
+#define P3MAP5 P3MAP45_H /* Port P3.5 mapping register */
+#define P3MAP6 P3MAP67_L /* Port P3.6 mapping register */
+#define P3MAP7 P3MAP67_H /* Port P3.7 mapping register */
+
+#endif /* __MSP430_PORT3_MAPPING_BASE__ */
+
+
+#endif /* __MSP430_HEADERS_PMCONTROL_H */
--- /dev/null
+#if !defined(__MSP430_HEADERS_PMM_H__)
+#define __MSP430_HEADERS_PMM_H__
+
+/* pmm.h
+ *
+ * mspgcc project: MSP430 device headers
+ * PMM module header
+ *
+ * (c) 2009 by J.M.Gross <mspgcc@grossibaer.de>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: $
+ *
+ */
+
+/* Switches:
+__MSP430_PMM_BASE__ - base address of PMM module
+*/
+
+#if defined(__MSP430_PMM_BASE__)
+
+// PMM control register 0 bits (PMMCTL0)
+// the quickstart guide PMM demo code states that writing the password to
+// PMMCTL0_H unlocks the PMM registers for write operation.
+// writing a 0 locks them again. (and indeed causes no RESET/NMI)
+//
+#define PMMPW (0xa500) // PW for writing PMMCTL0
+#define PMMPW_H (0xa5) // single-byte PW for writing directly to PMMCTL0_H
+#define PMMHPMRE (0x80) // enable global PMM high power module request
+#define PMMREGOFF (0x10) // regulator off
+#define PMMSWPOR (0x08) // trigger POR
+#define PMMSWBOR (0x04) // trigger BOR
+#define PMMCOREV1 (0x02) // core voltage bit 1
+#define PMMCOREV0 (0x01) // core voltage bit 0
+//aliases defined by MSPGCC
+#define PMMCOREV_0 (0)
+#define PMMCOREV_1 (1)
+#define PMMCOREV_2 (2)
+#define PMMCOREV_3 (3)
+
+// PMM control register 1 bits (PMMCTL1)
+#define PMMCMD1 (0x20) // voltage regulator current mode bit 1
+#define PMMCMD0 (0x10) // voltage regulator current mode bit 0
+#define PMMREFMD (0x01) // PMM reference mode
+//aliases defined by MSPGCC
+#define PMMCMD_0 (0<<4)
+#define PMMCMD_1 (1<<4)
+#define PMMCMD_2 (2<<4)
+#define PMMCMD_3 (3<<4)
+#define PMMCMD_LPM PMMCMD_0 // VR current range defined by Low power mode
+#define PMMCMD_LOW PMMCMD_2 // VR forced to low current mode
+#define PMMCMD_FULL PMMCMD_3 // VR forced to high current mode
+
+// SV supervisor and monitor high side control register bits (SCSMHCTL)
+#define SVMHFP (0x8000) // SVM high side full performance mode
+#define SVMHE (0x4000) // SVM high side enable
+#define SVMHOVPE (0x1000) // SVM high side overvoltage detection enable
+#define SVSHFP (0x0800) // SVS high side full performance mode
+#define SVSHE (0x0400) // SVS high side enable
+#define SVSHRVL1 (0x0200) // SVS high side reset voltage level bit 1
+#define SVSHRVL0 (0x0100) // SVS high side reset voltage level bit 0
+#define SVSMHACE (0x0080) // SVS/SVM high side automatic control enable
+#define SCSMHEVM (0x0040) // SVS/SVM high side event mask
+#define SVSHMD (0x0010) // SVS high side mode
+#define SVSMHDLYST (0x0008) // SVS/SVM high side delay status
+#define SVSMHRRL2 (0x0004) // SVS/SVM high side release voltage level bit 2
+#define SVSMHRRL1 (0x0002) // SVS/SVM high side release voltage level bit 1
+#define SVSMHRRL0 (0x0001) // SVS/SVM high side release voltage level bit 0
+//aliases defined by MSPGCC
+#define SVSHRVL_0 (0<<8) // SVS high side reset voltage level 0
+#define SVSHRVL_1 (1<<8) // SVS high side reset voltage level 1
+#define SVSHRVL_2 (2<<8) // SVS high side reset voltage level 2
+#define SVSHRVL_3 (3<<8) // SVS high side reset voltage level 3
+#define SVSMHRRL_0 (0) // SVS/SVM high side release voltage level 0
+#define SVSMHRRL_1 (1) // SVS/SVM high side release voltage level 1
+#define SVSMHRRL_2 (2) // SVS/SVM high side release voltage level 2
+#define SVSMHRRL_3 (3) // SVS/SVM high side release voltage level 3
+#define SVSMHRRL_4 (4) // SVS/SVM high side release voltage level 4
+#define SVSMHRRL_5 (5) // SVS/SVM high side release voltage level 5
+#define SVSMHRRL_6 (6) // SVS/SVM high side release voltage level 6
+#define SVSMHRRL_7 (7) // SVS/SVM high side release voltage level 7
+
+// SV supervisor and monitor low side control register bits (SCSMLCTL)
+#define SVMLFP (0x8000) // SVM low side full performance mode
+#define SVMLE (0x4000) // SVM low side enable
+#define SVMLOVPE (0x1000) // SVM low side overvoltage detection enable
+#define SVSLFP (0x0800) // SVS low side full performance mode
+#define SVSLE (0x0400) // SVS low side enable
+#define SVSLRVL1 (0x0200) // SVS low side reset voltage level bit 1
+#define SVSLRVL0 (0x0100) // SVS low side reset voltage level bit 0
+#define SVSMLACE (0x0080) // SVS/SVM low side automatic control enable
+#define SCSMLEVM (0x0040) // SVS/SVM low side event mask
+#define SVSLMD (0x0010) // SVS low side mode
+#define SVSMLDLYST (0x0008) // SVS/SVM low side delay status
+#define SVSMLRRL2 (0x0004) // SVS/SVM low side release voltage level bit 2
+#define SVSMLRRL1 (0x0002) // SVS/SVM low side release voltage level bit 1
+#define SVSMLRRL0 (0x0001) // SVS/SVM low side release voltage level bit 0
+//aliases defined by MSPGCC
+#define SVSLRVL_0 (0<<8) // SVS low side reset voltage level 0
+#define SVSLRVL_1 (1<<8) // SVS low side reset voltage level 1
+#define SVSLRVL_2 (2<<8) // SVS low side reset voltage level 2
+#define SVSLRVL_3 (3<<8) // SVS low side reset voltage level 3
+#define SVSMLRRL_0 (0) // SVS/SVM low side release voltage level 0
+#define SVSMLRRL_1 (1) // SVS/SVM low side release voltage level 1
+#define SVSMLRRL_2 (2) // SVS/SVM low side release voltage level 2
+#define SVSMLRRL_3 (3) // SVS/SVM low side release voltage level 3
+#define SVSMLRRL_4 (4) // SVS/SVM low side release voltage level 4
+#define SVSMLRRL_5 (5) // SVS/SVM low side release voltage level 5
+#define SVSMLRRL_6 (6) // SVS/SVM low side release voltage level 6
+#define SVSMLRRL_7 (7) // SVS/SVM low side release voltage level 7
+
+// SVSIN and SVMOUT control register bits (SVSMIO)
+#define SVMHVLROE (0x1000) // SVM high side voltage level reached output enable
+#define SVMHOE (0x0800) // SVM high side output enable
+#define SVMOUTPOL (0x0020) // SVMOUT pin polarity high
+#define SVMLVLROE (0x0010) // SVM low side voltage level reached output enable
+#define SVMLOE (0x0008) // SVM low side output enable
+
+// PMM interrupt flag register bits (PMMIFG)
+#define PMMLPM5IFG (0x8000) // LPM5 flag
+#define SVSLIFG (0x2000) // SVS low side interrupt flag
+#define SVSHIFG (0x1000) // SVS high side interrupt flag
+#define PMMPORIFG (0x0400) // PMM software POR interrupt flag
+#define PMMRSTIFG (0x0200) // PMM reset pin interrupt flag
+#define PMMBORIFG (0x0100) // PMM software BOR interrupt flag
+#define SVMHVLRIFG (0x0040) // SVM high side voltage level reached interrupt flag
+#define SVMHIFG (0x0020) // SVM high side interrupt flag
+#define SVSMHDLYIFG (0x0010) // SVS/SVM high side delay expired interrupt flag
+#define SVMLVLRIFG (0x0004) // SVM low side voltage level reached intterrupt flag
+#define SVMLIFG (0x0002) // SVM low side interrupt flag
+#define SVSMLDLYIFG (0x0001) // SVS/SVM low side delay expired interrupt flag
+
+// PMM reset and interrupt enable register (PMMRIE)
+#define SVMHVLRPE (0x2000) // SVM high side voltage level reached power on reset enable
+#define SVSHPE (0x1000) // SVS high side power on reset enable
+#define SVMLVLRPE (0x0200) // SVM low side voltage level reached power on reset enable
+#define SVSLPE (0x0100) // SVS low side power on reset enable
+#define SVMHVLRIE (0x0040) // SVM high side reset voltage level interrupt enable
+#define SVMHIE (0x0020) // SVM high side interrupt enable
+#define SVSMHDLYIE (0x0010) // SVS/SVM high side delay expired interrupt enable
+#define SVMLVLRIE (0x0004) // SVM low side reset voltage level interrupt enable
+#define SVMLIE (0x0002) // SVM low side interrupt enable
+#define SVSMLDLYIE (0x0001) // SVS/SVM low side delay expired interrupt enable
+
+// Power mode 5 control register 0
+#define LOCKIO (0x0001) // lock I/O pin configuration
+
+
+#define PMMCTL0_ __MSP430_PMM_BASE__ + 0x00 // PMM control register 0
+sfrw(PMMCTL0, PMMCTL0_);
+sfrb(PMMCTL0_L, PMMCTL0_);
+sfrb(PMMCTL0_H, PMMCTL0_ +1);
+#define PMMCTL1_ __MSP430_PMM_BASE__ + 0x02 // PMM control register 1
+sfrw(PMMCTL1, PMMCTL1_);
+#define SVSMHCTL_ __MSP430_PMM_BASE__ + 0x04 // SVS/SVM high side control register
+sfrw(SVSMHCTL, SVSMHCTL_);
+#define SVSMLCTL_ __MSP430_PMM_BASE__ + 0x06 // SVS/SVM low side control register
+sfrw(SVSMLCTL, SVSMLCTL_);
+#define SVSMIO_ __MSP430_PMM_BASE__ + 0x08 // SVSIN and SVMOUT control register (optional, does not exist in device datasheet peripheral map)
+sfrw(SVSMIO, SVSMIO_);
+#define PMMIFG_ __MSP430_PMM_BASE__ + 0x0C // PMM interrupt flag register // family users guide says 0x0A
+sfrw(PMMIFG, PMMIFG_);
+#define PMMRIE_ __MSP430_PMM_BASE__ + 0x0E // PMM reset and interrupt enable register
+sfrw(PMMRIE, PMMRIE_);
+#define PM5CTL0_ __MSP430_PMM_BASE__ + 0x10 // Power mode 5 control register 0 // only exists in user guide, not in device dataheet peripheral map
+sfrw(PM5CTL0, PM5CTL0_); // errata sheet tells this is not really working at all.
+
+#endif /* __MSP430_PMM_BASE__ */
+
+#endif /* __MSP430_HEADERS_PMM_H__ */
--- /dev/null
+#if !defined(__MSP430_HEADERS_REF_H__)
+#define __MSP430_HEADERS_REF_H__
+
+/* ref.h
+ *
+ * mspgcc project: MSP430 device headers
+ * REF (voltage reference) module
+ *
+ * Based on cc430x613x.h version 1.5 by Texas Instruments
+ *
+ * Peter A. Bigot <pab@peoplepowerco.com>
+ *
+ */
+
+/* Switches:
+__MSP430_HAS_REF__ - definition to show module available
+__MSP430_REF_BASE__ - base address of REF module
+*/
+
+#if defined(__MSP430_REF_BASE__)
+
+#define REFCTL0_ __MSP430_REF_BASE__ + 0x00 /* REF Shared Reference control register 0 */
+sfrw(REFCTL0, REFCTL0_);
+#define REFCTL0_L_ __MSP430_REF_BASE__ + 0x00
+sfrb(REFCTL0_L, REFCTL0_L_);
+#define REFCTL0_H_ __MSP430_REF_BASE__ + 0x01
+sfrb(REFCTL0_H, REFCTL0_H_);
+
+/* REFCTL0 Control Bits */
+#define REFON (0x0001) /* REF Reference On */
+#define REFOUT (0x0002) /* REF Reference output Buffer On */
+//#define RESERVED (0x0004) /* Reserved */
+#define REFTCOFF (0x0008) /* REF Temp.Sensor off */
+#define REFVSEL0 (0x0010) /* REF Reference Voltage Level Select Bit:0 */
+#define REFVSEL1 (0x0020) /* REF Reference Voltage Level Select Bit:1 */
+//#define RESERVED (0x0040) /* Reserved */
+#define REFMSTR (0x0080) /* REF Master Control */
+#define REFGENACT (0x0100) /* REF Reference generator active */
+#define REFBGACT (0x0200) /* REF Reference bandgap active */
+#define REFGENBUSY (0x0400) /* REF Reference generator busy */
+#define BGMODE (0x0800) /* REF Bandgap mode */
+//#define RESERVED (0x1000) /* Reserved */
+//#define RESERVED (0x2000) /* Reserved */
+//#define RESERVED (0x4000) /* Reserved */
+//#define RESERVED (0x8000) /* Reserved */
+
+/* REFCTL0 Control Bits */
+#define REFON_L (0x0001) /* REF Reference On */
+#define REFOUT_L (0x0002) /* REF Reference output Buffer On */
+//#define RESERVED (0x0004) /* Reserved */
+#define REFTCOFF_L (0x0008) /* REF Temp.Sensor off */
+#define REFVSEL0_L (0x0010) /* REF Reference Voltage Level Select Bit:0 */
+#define REFVSEL1_L (0x0020) /* REF Reference Voltage Level Select Bit:1 */
+//#define RESERVED (0x0040) /* Reserved */
+#define REFMSTR_L (0x0080) /* REF Master Control */
+//#define RESERVED (0x1000) /* Reserved */
+//#define RESERVED (0x2000) /* Reserved */
+//#define RESERVED (0x4000) /* Reserved */
+//#define RESERVED (0x8000) /* Reserved */
+
+/* REFCTL0 Control Bits */
+//#define RESERVED (0x0004) /* Reserved */
+//#define RESERVED (0x0040) /* Reserved */
+#define REFGENACT_H (0x0001) /* REF Reference generator active */
+#define REFBGACT_H (0x0002) /* REF Reference bandgap active */
+#define REFGENBUSY_H (0x0004) /* REF Reference generator busy */
+#define BGMODE_H (0x0008) /* REF Bandgap mode */
+//#define RESERVED (0x1000) /* Reserved */
+//#define RESERVED (0x2000) /* Reserved */
+//#define RESERVED (0x4000) /* Reserved */
+//#define RESERVED (0x8000) /* Reserved */
+
+#define REFVSEL_0 (0x0000) /* REF Reference Voltage Level Select 1.5V */
+#define REFVSEL_1 (0x0010) /* REF Reference Voltage Level Select 2.0V */
+#define REFVSEL_2 (0x0020) /* REF Reference Voltage Level Select 2.5V */
+#define REFVSEL_3 (0x0030) /* REF Reference Voltage Level Select 2.5V */
+
+
+#endif /* __MSP430_REF_BASE__ */
+
+#endif /* __MSP430_HEADERS_REF<_H__ */
+
--- /dev/null
+#ifndef __MSP430_HEADERS_RF1A_H
+#define __MSP430_HEADERS_RF1A_H
+
+/* rf1a.h
+ *
+ * mspgcc project: MSP430 device headers
+ * CC1101-based Radio Module
+ * Based on cc430x613x.h version 1.5 from Texas Instruments
+ */
+
+/* Switches:
+
+__MSP430_CC1101_BASE__ - base address of the CC1101 registers
+
+*/
+
+#if defined(__MSP430_CC1101_BASE__)
+
+#define RF1AIFCTL0_ __MSP430_CC1101_BASE__ + 0x00 /* Radio interface control register 0 */
+sfrw(RF1AIFCTL0, RF1AIFCTL0_);
+#define RF1AIFCTL0_L_ __MSP430_CC1101_BASE__ + 0x00
+sfrb(RF1AIFCTL0_L, RF1AIFCTL0_L_);
+#define RF1AIFCTL0_H_ __MSP430_CC1101_BASE__ + 0x01
+sfrb(RF1AIFCTL0_H, RF1AIFCTL0_H_);
+#define RF1AIFCTL1_ __MSP430_CC1101_BASE__ + 0x02 /* Radio interface control register 1 */
+sfrw(RF1AIFCTL1, RF1AIFCTL1_);
+#define RF1AIFCTL1_L_ __MSP430_CC1101_BASE__ + 0x02
+sfrb(RF1AIFCTL1_L, RF1AIFCTL1_L_);
+#define RF1AIFCTL1_H_ __MSP430_CC1101_BASE__ + 0x03
+sfrb(RF1AIFCTL1_H, RF1AIFCTL1_H_);
+#define RF1AIFIFG RF1AIFCTL1_L /* Radio interface interrupt flag register */
+#define RF1AIFIE RF1AIFCTL1_H /* Radio interface interrupt enable register */
+#define RF1AIFCTL2_ __MSP430_CC1101_BASE__ + 0x04 /* (Radio interface control register 2) */
+sfrw(RF1AIFCTL2, RF1AIFCTL2_);
+#define RF1AIFCTL2_L_ __MSP430_CC1101_BASE__ + 0x04
+sfrb(RF1AIFCTL2_L, RF1AIFCTL2_L_);
+#define RF1AIFCTL2_H_ __MSP430_CC1101_BASE__ + 0x05
+sfrb(RF1AIFCTL2_H, RF1AIFCTL2_H_);
+#define RF1AIFERR_ __MSP430_CC1101_BASE__ + 0x06 /* Radio interface error flag register */
+sfrw(RF1AIFERR, RF1AIFERR_);
+#define RF1AIFERR_L_ __MSP430_CC1101_BASE__ + 0x06
+sfrb(RF1AIFERR_L, RF1AIFERR_L_);
+#define RF1AIFERR_H_ __MSP430_CC1101_BASE__ + 0x07
+sfrb(RF1AIFERR_H, RF1AIFERR_H_);
+#define RF1AIFERRV_ __MSP430_CC1101_BASE__ + 0x0c /* Radio interface error vector word register */
+sfrw(RF1AIFERRV, RF1AIFERRV_);
+#define RF1AIFERRV_L_ __MSP430_CC1101_BASE__ + 0x0c
+sfrb(RF1AIFERRV_L, RF1AIFERRV_L_);
+#define RF1AIFERRV_H_ __MSP430_CC1101_BASE__ + 0x0d
+sfrb(RF1AIFERRV_H, RF1AIFERRV_H_);
+#define RF1AIFIV_ __MSP430_CC1101_BASE__ + 0x0e /* Radio interface interrupt vector word register */
+sfrw(RF1AIFIV, RF1AIFIV_);
+#define RF1AIFIV_L_ __MSP430_CC1101_BASE__ + 0x0e
+sfrb(RF1AIFIV_L, RF1AIFIV_L_);
+#define RF1AIFIV_H_ __MSP430_CC1101_BASE__ + 0x0f
+sfrb(RF1AIFIV_H, RF1AIFIV_H_);
+#define RF1AINSTRW_ __MSP430_CC1101_BASE__ + 0x10 /* Radio instruction word register */
+sfrw(RF1AINSTRW, RF1AINSTRW_);
+#define RF1AINSTRW_L_ __MSP430_CC1101_BASE__ + 0x10
+sfrb(RF1AINSTRW_L, RF1AINSTRW_L_);
+#define RF1AINSTRW_H_ __MSP430_CC1101_BASE__ + 0x11
+sfrb(RF1AINSTRW_H, RF1AINSTRW_H_);
+#define RF1ADINB RF1AINSTRW_L /* Radio instruction byte register */
+#define RF1AINSTRB RF1AINSTRW_H /* Radio byte data in register */
+#define RF1AINSTR1W_ __MSP430_CC1101_BASE__ + 0x12 /* Radio instruction 1-byte register with autoread */
+sfrw(RF1AINSTR1W, RF1AINSTR1W_);
+#define RF1AINSTR1W_L_ __MSP430_CC1101_BASE__ + 0x12
+sfrb(RF1AINSTR1W_L, RF1AINSTR1W_L_);
+#define RF1AINSTR1W_H_ __MSP430_CC1101_BASE__ + 0x13
+sfrb(RF1AINSTR1W_H, RF1AINSTR1W_H_);
+#define RF1AINSTR1B RF1AINSTR1W_H /* Radio instruction 1-byte register with autoread */
+#define RF1AINSTR2W_ __MSP430_CC1101_BASE__ + 0x14 /* Radio instruction 2-byte register with autoread */
+sfrw(RF1AINSTR2W, RF1AINSTR2W_);
+#define RF1AINSTR2W_L_ __MSP430_CC1101_BASE__ + 0x14
+sfrb(RF1AINSTR2W_L, RF1AINSTR2W_L_);
+#define RF1AINSTR2W_H_ __MSP430_CC1101_BASE__ + 0x15
+sfrb(RF1AINSTR2W_H, RF1AINSTR2W_H_);
+#define RF1AINSTR2B RF1AINSTR1W_H /* Radio instruction 2-byte register with autoread */
+#define RF1ADINW_ __MSP430_CC1101_BASE__ + 0x16 /* Radio word data in register */
+sfrw(RF1ADINW, RF1ADINW_);
+#define RF1ADINW_L_ __MSP430_CC1101_BASE__ + 0x16
+sfrb(RF1ADINW_L, RF1ADINW_L_);
+#define RF1ADINW_H_ __MSP430_CC1101_BASE__ + 0x17
+sfrb(RF1ADINW_H, RF1ADINW_H_);
+
+#define RF1ASTAT0W_ __MSP430_CC1101_BASE__ + 0x20 /* Radio status word register without auto-read */
+sfrw(RF1ASTAT0W, RF1ASTAT0W_);
+#define RF1ASTAT0W_L_ __MSP430_CC1101_BASE__ + 0x20
+sfrb(RF1ASTAT0W_L, RF1ASTAT0W_L_);
+#define RF1ASTAT0W_H_ __MSP430_CC1101_BASE__ + 0x21
+sfrb(RF1ASTAT0W_H, RF1ASTAT0W_H_);
+#define RF1ADOUT0B RF1ASTAT0W_L /* Radio byte data out register without auto-read */
+#define RF1ASTAT0B RF1ASTAT0W_H /* Radio status byte register without auto-read */
+#define RF1ASTATW RF1ASTAT0W /* Radio status word register without auto-read */
+#define RF1ADOUTB RF1ASTAT0W_L /* Radio byte data out register without auto-read */
+#define RF1ASTATB RF1ASTAT0W_H /* Radio status byte register without auto-read */
+#define RF1ASTAT1W_ __MSP430_CC1101_BASE__ + 0x22 /* Radio status word register with 1-byte auto-read */
+sfrw(RF1ASTAT1W, RF1ASTAT1W_);
+#define RF1ASTAT1W_L_ __MSP430_CC1101_BASE__ + 0x22
+sfrb(RF1ASTAT1W_L, RF1ASTAT1W_L_);
+#define RF1ASTAT1W_H_ __MSP430_CC1101_BASE__ + 0x23
+sfrb(RF1ASTAT1W_H, RF1ASTAT1W_H_);
+#define RF1ADOUT1B RF1ASTAT1W_L /* Radio byte data out register with 1-byte auto-read */
+#define RF1ASTAT1B RF1ASTAT1W_H /* Radio status byte register with 1-byte auto-read */
+#define RF1ASTAT2W_ __MSP430_CC1101_BASE__ + 0x24 /* Radio status word register with 2-byte auto-read */
+sfrw(RF1ASTAT2W, RF1ASTAT2W_);
+#define RF1ASTAT2W_L_ __MSP430_CC1101_BASE__ + 0x24
+sfrb(RF1ASTAT2W_L, RF1ASTAT2W_L_);
+#define RF1ASTAT2W_H_ __MSP430_CC1101_BASE__ + 0x25
+sfrb(RF1ASTAT2W_H, RF1ASTAT2W_H_);
+#define RF1ADOUT2B RF1ASTAT2W_L /* Radio byte data out register with 2-byte auto-read */
+#define RF1ASTAT2B RF1ASTAT2W_H /* Radio status byte register with 2-byte auto-read */
+#define RF1ADOUT0W_ __MSP430_CC1101_BASE__ + 0x28 /* Radio core word data out register without auto-read */
+sfrw(RF1ADOUT0W, RF1ADOUT0W_);
+#define RF1ADOUT0W_L_ __MSP430_CC1101_BASE__ + 0x28
+sfrb(RF1ADOUT0W_L, RF1ADOUT0W_L_);
+#define RF1ADOUT0W_H_ __MSP430_CC1101_BASE__ + 0x29
+sfrb(RF1ADOUT0W_H, RF1ADOUT0W_H_);
+#define RF1ADOUTW RF1ADOUT0W /* Radio core word data out register without auto-read */
+#define RF1ADOUTW_L RF1ADOUT0W_L /* Radio core word data out register without auto-read */
+#define RF1ADOUTW_H RF1ADOUT0W_H /* Radio core word data out register without auto-read */
+#define RF1ADOUT1W_ __MSP430_CC1101_BASE__ + 0x2a /* Radio core word data out register with 1-byte auto-read */
+sfrw(RF1ADOUT1W, RF1ADOUT1W_);
+#define RF1ADOUT1W_L_ __MSP430_CC1101_BASE__ + 0x2a
+sfrb(RF1ADOUT1W_L, RF1ADOUT1W_L_);
+#define RF1ADOUT1W_H_ __MSP430_CC1101_BASE__ + 0x2b
+sfrb(RF1ADOUT1W_H, RF1ADOUT1W_H_);
+#define RF1ADOUT2W_ __MSP430_CC1101_BASE__ + 0x2c /* Radio core word data out register with 2-byte auto-read */
+sfrw(RF1ADOUT2W, RF1ADOUT2W_);
+#define RF1ADOUT2W_L_ __MSP430_CC1101_BASE__ + 0x2c
+sfrb(RF1ADOUT2W_L, RF1ADOUT2W_L_);
+#define RF1ADOUT2W_H_ __MSP430_CC1101_BASE__ + 0x2d
+sfrb(RF1ADOUT2W_H, RF1ADOUT2W_H_);
+#define RF1AIN_ __MSP430_CC1101_BASE__ + 0x30 /* Radio core signal input register */
+sfrw(RF1AIN, RF1AIN_);
+#define RF1AIN_L_ __MSP430_CC1101_BASE__ + 0x30
+sfrb(RF1AIN_L, RF1AIN_L_);
+#define RF1AIN_H_ __MSP430_CC1101_BASE__ + 0x31
+sfrb(RF1AIN_H, RF1AIN_H_);
+#define RF1AIFG_ __MSP430_CC1101_BASE__ + 0x32 /* Radio core interrupt flag register */
+sfrw(RF1AIFG, RF1AIFG_);
+#define RF1AIFG_L_ __MSP430_CC1101_BASE__ + 0x32
+sfrb(RF1AIFG_L, RF1AIFG_L_);
+#define RF1AIFG_H_ __MSP430_CC1101_BASE__ + 0x33
+sfrb(RF1AIFG_H, RF1AIFG_H_);
+#define RF1AIES_ __MSP430_CC1101_BASE__ + 0x34 /* Radio core interrupt edge select register */
+sfrw(RF1AIES, RF1AIES_);
+#define RF1AIES_L_ __MSP430_CC1101_BASE__ + 0x34
+sfrb(RF1AIES_L, RF1AIES_L_);
+#define RF1AIES_H_ __MSP430_CC1101_BASE__ + 0x35
+sfrb(RF1AIES_H, RF1AIES_H_);
+#define RF1AIE_ __MSP430_CC1101_BASE__ + 0x36 /* Radio core interrupt enable register */
+sfrw(RF1AIE, RF1AIE_);
+#define RF1AIE_L_ __MSP430_CC1101_BASE__ + 0x36
+sfrb(RF1AIE_L, RF1AIE_L_);
+#define RF1AIE_H_ __MSP430_CC1101_BASE__ + 0x37
+sfrb(RF1AIE_H, RF1AIE_H_);
+#define RF1AIV_ __MSP430_CC1101_BASE__ + 0x38 /* Radio core interrupt vector word register */
+sfrw(RF1AIV, RF1AIV_);
+#define RF1AIV_L_ __MSP430_CC1101_BASE__ + 0x38
+sfrb(RF1AIV_L, RF1AIV_L_);
+#define RF1AIV_H_ __MSP430_CC1101_BASE__ + 0x39
+sfrb(RF1AIV_H, RF1AIV_H_);
+#define RF1ARXFIFO_ __MSP430_CC1101_BASE__ + 0x3c /* Direct receive FIFO access register */
+sfrw(RF1ARXFIFO, RF1ARXFIFO_);
+#define RF1ARXFIFO_L_ __MSP430_CC1101_BASE__ + 0x3c
+sfrb(RF1ARXFIFO_L, RF1ARXFIFO_L_);
+#define RF1ARXFIFO_H_ __MSP430_CC1101_BASE__ + 0x3d
+sfrb(RF1ARXFIFO_H, RF1ARXFIFO_H_);
+#define RF1ATXFIFO_ __MSP430_CC1101_BASE__ + 0x3e /* Direct transmit FIFO access register */
+sfrw(RF1ATXFIFO, RF1ATXFIFO_);
+#define RF1ATXFIFO_L_ __MSP430_CC1101_BASE__ + 0x3e
+sfrb(RF1ATXFIFO_L, RF1ATXFIFO_L_);
+#define RF1ATXFIFO_H_ __MSP430_CC1101_BASE__ + 0x3f
+sfrb(RF1ATXFIFO_H, RF1ATXFIFO_H_);
+
+/* RF1AIFCTL0 Control Bits */
+#define RFFIFOEN (0x0001) /* CC1101 Direct FIFO access enable */
+#define RFENDIAN (0x0002) /* CC1101 Disable endianness conversion */
+
+/* RF1AIFCTL0 Control Bits */
+#define RFFIFOEN_L (0x0001) /* CC1101 Direct FIFO access enable */
+#define RFENDIAN_L (0x0002) /* CC1101 Disable endianness conversion */
+
+/* RF1AIFCTL0 Control Bits */
+
+/* RF1AIFCTL1 Control Bits */
+#define RFRXIFG (0x0001) /* Radio interface direct FIFO access receive interrupt flag */
+#define RFTXIFG (0x0002) /* Radio interface direct FIFO access transmit interrupt flag */
+#define RFERRIFG (0x0004) /* Radio interface error interrupt flag */
+#define RFINSTRIFG (0x0010) /* Radio interface instruction interrupt flag */
+#define RFDINIFG (0x0020) /* Radio interface data in interrupt flag */
+#define RFSTATIFG (0x0040) /* Radio interface status interrupt flag */
+#define RFDOUTIFG (0x0080) /* Radio interface data out interrupt flag */
+#define RFRXIE (0x0100) /* Radio interface direct FIFO access receive interrupt enable */
+#define RFTXIE (0x0200) /* Radio interface direct FIFO access transmit interrupt enable */
+#define RFERRIE (0x0400) /* Radio interface error interrupt enable */
+#define RFINSTRIE (0x1000) /* Radio interface instruction interrupt enable */
+#define RFDINIE (0x2000) /* Radio interface data in interrupt enable */
+#define RFSTATIE (0x4000) /* Radio interface status interrupt enable */
+#define RFDOUTIE (0x8000) /* Radio interface data out interrupt enable */
+
+/* RF1AIFCTL1 Control Bits */
+#define RFRXIFG_L (0x0001) /* Radio interface direct FIFO access receive interrupt flag */
+#define RFTXIFG_L (0x0002) /* Radio interface direct FIFO access transmit interrupt flag */
+#define RFERRIFG_L (0x0004) /* Radio interface error interrupt flag */
+#define RFINSTRIFG_L (0x0010) /* Radio interface instruction interrupt flag */
+#define RFDINIFG_L (0x0020) /* Radio interface data in interrupt flag */
+#define RFSTATIFG_L (0x0040) /* Radio interface status interrupt flag */
+#define RFDOUTIFG_L (0x0080) /* Radio interface data out interrupt flag */
+
+/* RF1AIFCTL1 Control Bits */
+#define RFRXIE_H (0x0001) /* Radio interface direct FIFO access receive interrupt enable */
+#define RFTXIE_H (0x0002) /* Radio interface direct FIFO access transmit interrupt enable */
+#define RFERRIE_H (0x0004) /* Radio interface error interrupt enable */
+#define RFINSTRIE_H (0x0010) /* Radio interface instruction interrupt enable */
+#define RFDINIE_H (0x0020) /* Radio interface data in interrupt enable */
+#define RFSTATIE_H (0x0040) /* Radio interface status interrupt enable */
+#define RFDOUTIE_H (0x0080) /* Radio interface data out interrupt enable */
+
+/* RF1AIFERR Control Bits */
+#define LVERR (0x0001) /* Low Core Voltage Error Flag */
+#define OPERR (0x0002) /* Operand Error Flag */
+#define OUTERR (0x0004) /* Output data not available Error Flag */
+#define OPOVERR (0x0008) /* Operand Overwrite Error Flag */
+
+/* RF1AIFERR Control Bits */
+#define LVERR_L (0x0001) /* Low Core Voltage Error Flag */
+#define OPERR_L (0x0002) /* Operand Error Flag */
+#define OUTERR_L (0x0004) /* Output data not available Error Flag */
+#define OPOVERR_L (0x0008) /* Operand Overwrite Error Flag */
+
+/* RF1AIFERR Control Bits */
+
+/* RF1AIFERRV Definitions */
+#define RF1AIFERRV_NONE (0x0000) /* No Error pending */
+#define RF1AIFERRV_LVERR (0x0002) /* Low core voltage error */
+#define RF1AIFERRV_OPERR (0x0004) /* Operand Error */
+#define RF1AIFERRV_OUTERR (0x0006) /* Output data not available Error */
+#define RF1AIFERRV_OPOVERR (0x0008) /* Operand Overwrite Error */
+
+/* RF1AIFIV Definitions */
+#define RF1AIFIV_NONE (0x0000) /* No Interrupt pending */
+#define RF1AIFIV_RFERRIFG (0x0002) /* Radio interface error */
+#define RF1AIFIV_RFDOUTIFG (0x0004) /* Radio i/f data out */
+#define RF1AIFIV_RFSTATIFG (0x0006) /* Radio i/f status out */
+#define RF1AIFIV_RFDINIFG (0x0008) /* Radio i/f data in */
+#define RF1AIFIV_RFINSTRIFG (0x000A) /* Radio i/f instruction in */
+#define RF1AIFIV_RFRXIFG (0x000C) /* Radio direct FIFO RX */
+#define RF1AIFIV_RFTXIFG (0x000E) /* Radio direct FIFO TX */
+
+/* RF1AIV Definitions */
+#define RF1AIV_NONE (0x0000) /* No Interrupt pending */
+#define RF1AIV_RFIFG0 (0x0002) /* RFIFG0 */
+#define RF1AIV_RFIFG1 (0x0004) /* RFIFG1 */
+#define RF1AIV_RFIFG2 (0x0006) /* RFIFG2 */
+#define RF1AIV_RFIFG3 (0x0008) /* RFIFG3 */
+#define RF1AIV_RFIFG4 (0x000A) /* RFIFG4 */
+#define RF1AIV_RFIFG5 (0x000C) /* RFIFG5 */
+#define RF1AIV_RFIFG6 (0x000E) /* RFIFG6 */
+#define RF1AIV_RFIFG7 (0x0010) /* RFIFG7 */
+#define RF1AIV_RFIFG8 (0x0012) /* RFIFG8 */
+#define RF1AIV_RFIFG9 (0x0014) /* RFIFG9 */
+#define RF1AIV_RFIFG10 (0x0016) /* RFIFG10 */
+#define RF1AIV_RFIFG11 (0x0018) /* RFIFG11 */
+#define RF1AIV_RFIFG12 (0x001A) /* RFIFG12 */
+#define RF1AIV_RFIFG13 (0x001C) /* RFIFG13 */
+#define RF1AIV_RFIFG14 (0x001E) /* RFIFG14 */
+#define RF1AIV_RFIFG15 (0x0020) /* RFIFG15 */
+
+// Radio Core Registers
+#define IOCFG2 0x00 /* IOCFG2 - GDO2 output pin configuration */
+#define IOCFG1 0x01 /* IOCFG1 - GDO1 output pin configuration */
+#define IOCFG0 0x02 /* IOCFG1 - GDO0 output pin configuration */
+#define FIFOTHR 0x03 /* FIFOTHR - RX FIFO and TX FIFO thresholds */
+#define SYNC1 0x04 /* SYNC1 - Sync word, high byte */
+#define SYNC0 0x05 /* SYNC0 - Sync word, low byte */
+#define PKTLEN 0x06 /* PKTLEN - Packet length */
+#define PKTCTRL1 0x07 /* PKTCTRL1 - Packet automation control */
+#define PKTCTRL0 0x08 /* PKTCTRL0 - Packet automation control */
+#define ADDR 0x09 /* ADDR - Device address */
+#define CHANNR 0x0A /* CHANNR - Channel number */
+#define FSCTRL1 0x0B /* FSCTRL1 - Frequency synthesizer control */
+#define FSCTRL0 0x0C /* FSCTRL0 - Frequency synthesizer control */
+#define FREQ2 0x0D /* FREQ2 - Frequency control word, high byte */
+#define FREQ1 0x0E /* FREQ1 - Frequency control word, middle byte */
+#define FREQ0 0x0F /* FREQ0 - Frequency control word, low byte */
+#define MDMCFG4 0x10 /* MDMCFG4 - Modem configuration */
+#define MDMCFG3 0x11 /* MDMCFG3 - Modem configuration */
+#define MDMCFG2 0x12 /* MDMCFG2 - Modem configuration */
+#define MDMCFG1 0x13 /* MDMCFG1 - Modem configuration */
+#define MDMCFG0 0x14 /* MDMCFG0 - Modem configuration */
+#define DEVIATN 0x15 /* DEVIATN - Modem deviation setting */
+#define MCSM2 0x16 /* MCSM2 - Main Radio Control State Machine configuration */
+#define MCSM1 0x17 /* MCSM1 - Main Radio Control State Machine configuration */
+#define MCSM0 0x18 /* MCSM0 - Main Radio Control State Machine configuration */
+#define FOCCFG 0x19 /* FOCCFG - Frequency Offset Compensation configuration */
+#define BSCFG 0x1A /* BSCFG - Bit Synchronization configuration */
+#define AGCCTRL2 0x1B /* AGCCTRL2 - AGC control */
+#define AGCCTRL1 0x1C /* AGCCTRL1 - AGC control */
+#define AGCCTRL0 0x1D /* AGCCTRL0 - AGC control */
+#define WOREVT1 0x1E /* WOREVT1 - High byte Event0 timeout */
+#define WOREVT0 0x1F /* WOREVT0 - Low byte Event0 timeout */
+#define WORCTRL 0x20 /* WORCTRL - Wake On Radio control */
+#define FREND1 0x21 /* FREND1 - Front end RX configuration */
+#define FREND0 0x22 /* FREDN0 - Front end TX configuration */
+#define FSCAL3 0x23 /* FSCAL3 - Frequency synthesizer calibration */
+#define FSCAL2 0x24 /* FSCAL2 - Frequency synthesizer calibration */
+#define FSCAL1 0x25 /* FSCAL1 - Frequency synthesizer calibration */
+#define FSCAL0 0x26 /* FSCAL0 - Frequency synthesizer calibration */
+//#define RCCTRL1 0x27 /* RCCTRL1 - RC oscillator configuration */
+//#define RCCTRL0 0x28 /* RCCTRL0 - RC oscillator configuration */
+#define FSTEST 0x29 /* FSTEST - Frequency synthesizer calibration control */
+#define PTEST 0x2A /* PTEST - Production test */
+#define AGCTEST 0x2B /* AGCTEST - AGC test */
+#define TEST2 0x2C /* TEST2 - Various test settings */
+#define TEST1 0x2D /* TEST1 - Various test settings */
+#define TEST0 0x2E /* TEST0 - Various test settings */
+
+/* status registers */
+#define PARTNUM 0x30 /* PARTNUM - Chip ID */
+#define VERSION 0x31 /* VERSION - Chip ID */
+#define FREQEST 0x32 /* FREQEST \96 Frequency Offset Estimate from demodulator */
+#define LQI 0x33 /* LQI \96 Demodulator estimate for Link Quality */
+#define RSSI 0x34 /* RSSI \96 Received signal strength indication */
+#define MARCSTATE 0x35 /* MARCSTATE \96 Main Radio Control State Machine state */
+#define WORTIME1 0x36 /* WORTIME1 \96 High byte of WOR time */
+#define WORTIME0 0x37 /* WORTIME0 \96 Low byte of WOR time */
+#define PKTSTATUS 0x38 /* PKTSTATUS \96 Current GDOx status and packet status */
+#define VCO_VC_DAC 0x39 /* VCO_VC_DAC \96 Current setting from PLL calibration module */
+#define TXBYTES 0x3A /* TXBYTES \96 Underflow and number of bytes */
+#define RXBYTES 0x3B /* RXBYTES \96 Overflow and number of bytes */
+
+/* burst write registers */
+#define PATABLE 0x3E /* PATABLE - PA control settings table */
+#define TXFIFO 0x3F /* TXFIFO - Transmit FIFO */
+#define RXFIFO 0x3F /* RXFIFO - Receive FIFO */
+
+/* Radio Core Instructions */
+/* command strobes */
+#define RF_SRES 0x30 /* SRES - Reset chip. */
+#define RF_SFSTXON 0x31 /* SFSTXON - Enable and calibrate frequency synthesizer. */
+#define RF_SXOFF 0x32 /* SXOFF - Turn off crystal oscillator. */
+#define RF_SCAL 0x33 /* SCAL - Calibrate frequency synthesizer and turn it off. */
+#define RF_SRX 0x34 /* SRX - Enable RX. Perform calibration if enabled. */
+#define RF_STX 0x35 /* STX - Enable TX. If in RX state, only enable TX if CCA passes. */
+#define RF_SIDLE 0x36 /* SIDLE - Exit RX / TX, turn off frequency synthesizer. */
+//#define RF_SRSVD 0x37 /* SRVSD - Reserved. Do not use. */
+#define RF_SWOR 0x38 /* SWOR - Start automatic RX polling sequence (Wake-on-Radio) */
+#define RF_SPWD 0x39 /* SPWD - Enter power down mode when CSn goes high. */
+#define RF_SFRX 0x3A /* SFRX - Flush the RX FIFO buffer. */
+#define RF_SFTX 0x3B /* SFTX - Flush the TX FIFO buffer. */
+#define RF_SWORRST 0x3C /* SWORRST - Reset real time clock. */
+#define RF_SNOP 0x3D /* SNOP - No operation. Returns status byte. */
+
+#define RF_RXSTAT 0x80 /* Used in combination with strobe commands delivers number of availabe bytes in RX FIFO with return status */
+#define RF_TXSTAT 0x00 /* Used in combination with strobe commands delivers number of availabe bytes in TX FIFO with return status */
+
+/* other radio instr */
+#define RF_SNGLREGRD 0x80
+#define RF_SNGLREGWR 0x00
+#define RF_REGRD 0xC0
+#define RF_REGWR 0x40
+#define RF_STATREGRD 0xC0 /* Read single radio core status register */
+#define RF_SNGLPATABRD (RF_SNGLREGRD+PATABLE)
+#define RF_SNGLPATABWR (RF_SNGLREGWR+PATABLE)
+#define RF_PATABRD (RF_REGRD+PATABLE)
+#define RF_PATABWR (RF_REGWR+PATABLE)
+#define RF_SNGLRXRD (RF_SNGLREGRD+RXFIFO)
+#define RF_SNGLTXWR (RF_SNGLREGWR+TXFIFO)
+#define RF_RXFIFORD (RF_REGRD+RXFIFO)
+#define RF_TXFIFOWR (RF_REGWR+TXFIFO)
+
+#endif /* __MSP430_CC1101_BASE__ */
+
+#endif /* __MSP430_HEADERS_RF1A_H */
--- /dev/null
+#if !defined(__MSP430_HEADERS_RTC_H__)
+#define __MSP430_HEADERS_RTC_H__
+
+/* rtc.h
+ *
+ * mspgcc project: MSP430 device headers
+ * Real-Time Clock
+ *
+ * Based on cc430x613x.h version 1.5 by Texas Instruments
+ *
+ * Peter A. Bigot <pab@peoplepowerco.com>
+ *
+ */
+
+/* Switches:
+__MSP430_HAS_RTC__ -- defined to indicate availability of module
+__MSP430_RTC_BASE__ - base address of RTC module
+*/
+
+#if defined(__MSP430_RTC_BASE__)
+
+#define RTCCTL01_ __MSP430_RTC_BASE__ + 0x00 /* Real Timer Control 0/1 */
+sfrw(RTCCTL01, RTCCTL01_);
+#define RTCCTL01_L_ __MSP430_RTC_BASE__ + 0x00
+sfrb(RTCCTL01_L, RTCCTL01_L_);
+#define RTCCTL01_H_ __MSP430_RTC_BASE__ + 0x01
+sfrb(RTCCTL01_H, RTCCTL01_H_);
+#define RTCCTL23_ __MSP430_RTC_BASE__ + 0x02 /* Real Timer Control 2/3 */
+sfrw(RTCCTL23, RTCCTL23_);
+#define RTCCTL23_L_ __MSP430_RTC_BASE__ + 0x02
+sfrb(RTCCTL23_L, RTCCTL23_L_);
+#define RTCCTL23_H_ __MSP430_RTC_BASE__ + 0x03
+sfrb(RTCCTL23_H, RTCCTL23_H_);
+#define RTCPS0CTL_ __MSP430_RTC_BASE__ + 0x08 /* Real Timer Prescale Timer 0 Control */
+sfrw(RTCPS0CTL, RTCPS0CTL_);
+#define RTCPS0CTL_L_ __MSP430_RTC_BASE__ + 0x08
+sfrb(RTCPS0CTL_L, RTCPS0CTL_L_);
+#define RTCPS0CTL_H_ __MSP430_RTC_BASE__ + 0x09
+sfrb(RTCPS0CTL_H, RTCPS0CTL_H_);
+#define RTCPS1CTL_ __MSP430_RTC_BASE__ + 0x0a /* Real Timer Prescale Timer 1 Control */
+sfrw(RTCPS1CTL, RTCPS1CTL_);
+#define RTCPS1CTL_L_ __MSP430_RTC_BASE__ + 0x0a
+sfrb(RTCPS1CTL_L, RTCPS1CTL_L_);
+#define RTCPS1CTL_H_ __MSP430_RTC_BASE__ + 0x0b
+sfrb(RTCPS1CTL_H, RTCPS1CTL_H_);
+#define RTCPS_ __MSP430_RTC_BASE__ + 0x0c /* Real Timer Prescale Timer Control */
+sfrw(RTCPS, RTCPS_);
+#define RTCPS_L_ __MSP430_RTC_BASE__ + 0x0c
+sfrb(RTCPS_L, RTCPS_L_);
+#define RTCPS_H_ __MSP430_RTC_BASE__ + 0x0d
+sfrb(RTCPS_H, RTCPS_H_);
+#define RTCIV_ __MSP430_RTC_BASE__ + 0x0e /* Real Time Clock Interrupt Vector */
+sfrw(RTCIV, RTCIV_);
+#define RTCTIM0_ __MSP430_RTC_BASE__ + 0x10 /* Real Time Clock Time 0 */
+sfrw(RTCTIM0, RTCTIM0_);
+#define RTCTIM0_L_ __MSP430_RTC_BASE__ + 0x10
+sfrb(RTCTIM0_L, RTCTIM0_L_);
+#define RTCTIM0_H_ __MSP430_RTC_BASE__ + 0x11
+sfrb(RTCTIM0_H, RTCTIM0_H_);
+#define RTCTIM1_ __MSP430_RTC_BASE__ + 0x12 /* Real Time Clock Time 1 */
+sfrw(RTCTIM1, RTCTIM1_);
+#define RTCTIM1_L_ __MSP430_RTC_BASE__ + 0x12
+sfrb(RTCTIM1_L, RTCTIM1_L_);
+#define RTCTIM1_H_ __MSP430_RTC_BASE__ + 0x13
+sfrb(RTCTIM1_H, RTCTIM1_H_);
+#define RTCDATE_ __MSP430_RTC_BASE__ + 0x14 /* Real Time Clock Date */
+sfrw(RTCDATE, RTCDATE_);
+#define RTCDATE_L_ __MSP430_RTC_BASE__ + 0x14
+sfrb(RTCDATE_L, RTCDATE_L_);
+#define RTCDATE_H_ __MSP430_RTC_BASE__ + 0x15
+sfrb(RTCDATE_H, RTCDATE_H_);
+#define RTCYEAR_ __MSP430_RTC_BASE__ + 0x16 /* Real Time Clock Year */
+sfrw(RTCYEAR, RTCYEAR_);
+#define RTCYEAR_L_ __MSP430_RTC_BASE__ + 0x16
+sfrb(RTCYEAR_L, RTCYEAR_L_);
+#define RTCYEAR_H_ __MSP430_RTC_BASE__ + 0x17
+sfrb(RTCYEAR_H, RTCYEAR_H_);
+#define RTCAMINHR_ __MSP430_RTC_BASE__ + 0x18 /* Real Time Clock Alarm Min/Hour */
+sfrw(RTCAMINHR, RTCAMINHR_);
+#define RTCAMINHR_L_ __MSP430_RTC_BASE__ + 0x18
+sfrb(RTCAMINHR_L, RTCAMINHR_L_);
+#define RTCAMINHR_H_ __MSP430_RTC_BASE__ + 0x19
+sfrb(RTCAMINHR_H, RTCAMINHR_H_);
+#define RTCADOWDAY_ __MSP430_RTC_BASE__ + 0x1a /* Real Time Clock Alarm day of week/day */
+sfrw(RTCADOWDAY, RTCADOWDAY_);
+#define RTCADOWDAY_L_ __MSP430_RTC_BASE__ + 0x1a
+sfrb(RTCADOWDAY_L, RTCADOWDAY_L_);
+#define RTCADOWDAY_H_ __MSP430_RTC_BASE__ + 0x1b
+sfrb(RTCADOWDAY_H, RTCADOWDAY_H_);
+
+#define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */
+#define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */
+#define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */
+#define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */
+#define RTCNT12 RTCTIM0
+#define RTCNT34 RTCTIM1
+#define RTCNT1 RTCTIM0_L
+#define RTCNT2 RTCTIM0_H
+#define RTCNT3 RTCTIM1_L
+#define RTCNT4 RTCTIM1_H
+#define RTCSEC RTCTIM0_L
+#define RTCMIN RTCTIM0_H
+#define RTCHOUR RTCTIM1_L
+#define RTCDOW RTCTIM1_H
+#define RTCDAY RTCDATE_L
+#define RTCMON RTCDATE_H
+#define RTCYEARL RTCYEAR_L
+#define RTCYEARH RTCYEAR_H
+#define RT0PS RTCPS_L
+#define RT1PS RTCPS_H
+#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */
+#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */
+#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */
+#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */
+
+/* RTCCTL01 Control Bits */
+#define RTCBCD (0x8000) /* RTC BCD 0:Binary / 1:BCD */
+#define RTCHOLD (0x4000) /* RTC Hold */
+#define RTCMODE (0x2000) /* RTC Mode 0:Counter / 1: Calendar */
+#define RTCRDY (0x1000) /* RTC Ready */
+#define RTCSSEL1 (0x0800) /* RTC Source Select 1 */
+#define RTCSSEL0 (0x0400) /* RTC Source Select 0 */
+#define RTCTEV1 (0x0200) /* RTC Time Event 1 */
+#define RTCTEV0 (0x0100) /* RTC Time Event 0 */
+//#define Reserved (0x0080)
+#define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */
+#define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */
+#define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */
+//#define Reserved (0x0008)
+#define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */
+#define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */
+#define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */
+
+/* RTCCTL01 Control Bits */
+//#define Reserved (0x0080)
+#define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */
+#define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */
+#define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */
+//#define Reserved (0x0008)
+#define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */
+#define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */
+#define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */
+
+/* RTCCTL01 Control Bits */
+#define RTCBCD_H (0x0080) /* RTC BCD 0:Binary / 1:BCD */
+#define RTCHOLD_H (0x0040) /* RTC Hold */
+#define RTCMODE_H (0x0020) /* RTC Mode 0:Counter / 1: Calendar */
+#define RTCRDY_H (0x0010) /* RTC Ready */
+#define RTCSSEL1_H (0x0008) /* RTC Source Select 1 */
+#define RTCSSEL0_H (0x0004) /* RTC Source Select 0 */
+#define RTCTEV1_H (0x0002) /* RTC Time Event 1 */
+#define RTCTEV0_H (0x0001) /* RTC Time Event 0 */
+//#define Reserved (0x0080)
+//#define Reserved (0x0008)
+
+#define RTCSSEL_0 (0x0000) /* RTC Source Select ACLK */
+#define RTCSSEL_1 (0x0400) /* RTC Source Select SMCLK */
+#define RTCSSEL_2 (0x0800) /* RTC Source Select RT1PS */
+#define RTCSSEL_3 (0x0C00) /* RTC Source Select RT1PS */
+#define RTCSSEL__ACLK (0x0000) /* RTC Source Select ACLK */
+#define RTCSSEL__SMCLK (0x0400) /* RTC Source Select SMCLK */
+#define RTCSSEL__RT1PS (0x0800) /* RTC Source Select RT1PS */
+#define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */
+#define RTCTEV_1 (0x0100) /* RTC Time Event: 1 (Hour changed) */
+#define RTCTEV_2 (0x0200) /* RTC Time Event: 2 (12:00 changed) */
+#define RTCTEV_3 (0x0300) /* RTC Time Event: 3 (00:00 changed) */
+#define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */
+#define RTCTEV__HOUR (0x0100) /* RTC Time Event: 1 (Hour changed) */
+#define RTCTEV__1200 (0x0200) /* RTC Time Event: 2 (12:00 changed) */
+#define RTCTEV__0000 (0x0300) /* RTC Time Event: 3 (00:00 changed) */
+
+/* RTCCTL23 Control Bits */
+#define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */
+#define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */
+#define RTCCALS (0x0080) /* RTC Calibration Sign */
+//#define Reserved (0x0040)
+#define RTCCAL5 (0x0020) /* RTC Calibration Bit 5 */
+#define RTCCAL4 (0x0010) /* RTC Calibration Bit 4 */
+#define RTCCAL3 (0x0008) /* RTC Calibration Bit 3 */
+#define RTCCAL2 (0x0004) /* RTC Calibration Bit 2 */
+#define RTCCAL1 (0x0002) /* RTC Calibration Bit 1 */
+#define RTCCAL0 (0x0001) /* RTC Calibration Bit 0 */
+
+/* RTCCTL23 Control Bits */
+#define RTCCALS_L (0x0080) /* RTC Calibration Sign */
+//#define Reserved (0x0040)
+#define RTCCAL5_L (0x0020) /* RTC Calibration Bit 5 */
+#define RTCCAL4_L (0x0010) /* RTC Calibration Bit 4 */
+#define RTCCAL3_L (0x0008) /* RTC Calibration Bit 3 */
+#define RTCCAL2_L (0x0004) /* RTC Calibration Bit 2 */
+#define RTCCAL1_L (0x0002) /* RTC Calibration Bit 1 */
+#define RTCCAL0_L (0x0001) /* RTC Calibration Bit 0 */
+
+/* RTCCTL23 Control Bits */
+#define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */
+#define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */
+//#define Reserved (0x0040)
+
+#define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */
+#define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */
+#define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */
+#define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */
+
+/* RTCPS0CTL Control Bits */
+//#define Reserved (0x8000)
+#define RT0SSEL (0x4000) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */
+#define RT0PSDIV2 (0x2000) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
+#define RT0PSDIV1 (0x1000) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
+#define RT0PSDIV0 (0x0800) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
+//#define Reserved (0x0400)
+//#define Reserved (0x0200)
+#define RT0PSHOLD (0x0100) /* RTC Prescale Timer 0 Hold */
+//#define Reserved (0x0080)
+//#define Reserved (0x0040)
+//#define Reserved (0x0020)
+#define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
+#define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
+#define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
+#define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enalbe Flag */
+#define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
+
+/* RTCPS0CTL Control Bits */
+//#define Reserved (0x8000)
+//#define Reserved (0x0400)
+//#define Reserved (0x0200)
+//#define Reserved (0x0080)
+//#define Reserved (0x0040)
+//#define Reserved (0x0020)
+#define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
+#define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
+#define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
+#define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enalbe Flag */
+#define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
+
+/* RTCPS0CTL Control Bits */
+//#define Reserved (0x8000)
+#define RT0SSEL_H (0x0040) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */
+#define RT0PSDIV2_H (0x0020) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
+#define RT0PSDIV1_H (0x0010) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
+#define RT0PSDIV0_H (0x0008) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
+//#define Reserved (0x0400)
+//#define Reserved (0x0200)
+#define RT0PSHOLD_H (0x0001) /* RTC Prescale Timer 0 Hold */
+//#define Reserved (0x0080)
+//#define Reserved (0x0040)
+//#define Reserved (0x0020)
+
+#define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */
+#define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */
+#define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */
+#define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */
+#define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */
+#define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */
+#define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */
+#define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */
+
+#define RT0PSDIV_0 (0x0000) /* RTC Prescale Timer 0 Clock Divide /2 */
+#define RT0PSDIV_1 (0x0800) /* RTC Prescale Timer 0 Clock Divide /4 */
+#define RT0PSDIV_2 (0x1000) /* RTC Prescale Timer 0 Clock Divide /8 */
+#define RT0PSDIV_3 (0x1800) /* RTC Prescale Timer 0 Clock Divide /16 */
+#define RT0PSDIV_4 (0x2000) /* RTC Prescale Timer 0 Clock Divide /32 */
+#define RT0PSDIV_5 (0x2800) /* RTC Prescale Timer 0 Clock Divide /64 */
+#define RT0PSDIV_6 (0x3000) /* RTC Prescale Timer 0 Clock Divide /128 */
+#define RT0PSDIV_7 (0x3800) /* RTC Prescale Timer 0 Clock Divide /256 */
+
+/* RTCPS1CTL Control Bits */
+#define RT1SSEL1 (0x8000) /* RTC Prescale Timer 1 Source Select Bit 1 */
+#define RT1SSEL0 (0x4000) /* RTC Prescale Timer 1 Source Select Bit 0 */
+#define RT1PSDIV2 (0x2000) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
+#define RT1PSDIV1 (0x1000) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
+#define RT1PSDIV0 (0x0800) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
+//#define Reserved (0x0400)
+//#define Reserved (0x0200)
+#define RT1PSHOLD (0x0100) /* RTC Prescale Timer 1 Hold */
+//#define Reserved (0x0080)
+//#define Reserved (0x0040)
+//#define Reserved (0x0020)
+#define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
+#define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
+#define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
+#define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enalbe Flag */
+#define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
+
+/* RTCPS1CTL Control Bits */
+//#define Reserved (0x0400)
+//#define Reserved (0x0200)
+//#define Reserved (0x0080)
+//#define Reserved (0x0040)
+//#define Reserved (0x0020)
+#define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
+#define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
+#define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
+#define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enalbe Flag */
+#define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
+
+/* RTCPS1CTL Control Bits */
+#define RT1SSEL1_H (0x0080) /* RTC Prescale Timer 1 Source Select Bit 1 */
+#define RT1SSEL0_H (0x0040) /* RTC Prescale Timer 1 Source Select Bit 0 */
+#define RT1PSDIV2_H (0x0020) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
+#define RT1PSDIV1_H (0x0010) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
+#define RT1PSDIV0_H (0x0008) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
+//#define Reserved (0x0400)
+//#define Reserved (0x0200)
+#define RT1PSHOLD_H (0x0001) /* RTC Prescale Timer 1 Hold */
+//#define Reserved (0x0080)
+//#define Reserved (0x0040)
+//#define Reserved (0x0020)
+
+#define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */
+#define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */
+#define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */
+#define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */
+#define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */
+#define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */
+#define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */
+#define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */
+
+#define RT1PSDIV_0 (0x0000) /* RTC Prescale Timer 1 Clock Divide /2 */
+#define RT1PSDIV_1 (0x0800) /* RTC Prescale Timer 1 Clock Divide /4 */
+#define RT1PSDIV_2 (0x1000) /* RTC Prescale Timer 1 Clock Divide /8 */
+#define RT1PSDIV_3 (0x1800) /* RTC Prescale Timer 1 Clock Divide /16 */
+#define RT1PSDIV_4 (0x2000) /* RTC Prescale Timer 1 Clock Divide /32 */
+#define RT1PSDIV_5 (0x2800) /* RTC Prescale Timer 1 Clock Divide /64 */
+#define RT1PSDIV_6 (0x3000) /* RTC Prescale Timer 1 Clock Divide /128 */
+#define RT1PSDIV_7 (0x3800) /* RTC Prescale Timer 1 Clock Divide /256 */
+
+#define RT1SSEL_0 (0x0000) /* RTC Prescale Timer Source Select ACLK */
+#define RT1SSEL_1 (0x4000) /* RTC Prescale Timer Source Select SMCLK */
+#define RT1SSEL_2 (0x8000) /* RTC Prescale Timer Source Select RT0PS */
+#define RT1SSEL_3 (0xC000) /* RTC Prescale Timer Source Select RT0PS */
+
+/* RTC Definitions */
+#define RTC_NONE (0x0000) /* No Interrupt pending */
+#define RTC_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */
+#define RTC_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */
+#define RTC_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */
+#define RTC_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */
+#define RTC_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */
+
+#define RTC_A_VECTOR RTC_VECTOR /* 0xFFDC RTC */
+
+#endif /* __MSP430_RTC_BASE__ */
+
+#endif /* __MSP430_HEADERS_RTC_H__ */
+
* (c) 2003 by Steve Underwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: scanif.h,v 1.2 2004/04/05 14:05:46 coppice Exp $
+ * $Id: scanif.h,v 1.3 2008/10/09 15:00:14 sb-sf Exp $
*/
/* Switches: none */
sfrw(SIFDACR7, SIFDACR7_);
#define SIFTSM_ 0x01D0 /* SIF, Timing State Machine 0 */
-#ifdef _GNU_ASSEMBLER_
+#ifdef __ASSEMBLER__
#define SIFTSM SIFTSM_ /* SIF, Timing State Machine (for assembler) */
#else
#define SIFTSM ((char*) SIFTSM_) /* SIF, Timing State Machine (for C) */
* (c) 2003 by Steve Underwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: sd16.h,v 1.8 2006/12/26 10:33:14 coppice Exp $
+ * $Id: sd16.h,v 1.10 2009/01/11 23:11:48 sb-sf Exp $
*/
/* Switches:
+__MSP430_SD16IV_BASE__ - SD16IV register address
+__MSP430_SD16MEM_BASE__ - SD16MEM0 register address
-__msp430_have_sd16a - the SD16 is the "A" type
-__msp430_have_sd16_1
-__msp430_have_sd16_2
+__MSP430_HAS_SD16_A__ - the SD16 is the "A" type
+__MSP430_HAS_SD16_BUF__ - the SD16(_A) has input buffer and SD16AE reg.
+__MSP430_HAS_SD16_CH1__ - the SD16(_A) has channel 1
+__MSP430_HAS_SD16_CH2__ - the SD16(_A) has channel 2
+__MSP430_HAS_SD16_CH3__ - the SD16(_A) has channel 3
*/
#define SD16CTL_ 0x0100 /* Sigma Delta ADC 16 Control Register */
sfrw(SD16CTL, SD16CTL_);
-#define SD16IV_ 0x0110 /* SD16 Interrupt Vector Register */
+#define SD16IV_ __MSP430_SD16IV_BASE__ /* SD16 Interrupt Vector Register */
sfrw(SD16IV, SD16IV_);
-#if defined(__msp430_have_sd16a)
+#if defined(__MSP430_HAS_SD16_A__)
+#if defined(__MSP430_HAS_SD16_BUF__)
#define SD16AE_ 0x00B7 /* SD16 Analog Input Enable Register */
sfrb(SD16AE, SD16AE_);
+#endif
#else
#define SD16CONF0_ 0x00B7 /* SD16 Internal Configuration Register 0 */
sfrb(SD16CONF0, SD16CONF0_);
sfrb(SD16PRE0, SD16PRE0_);
#define SD16CCTL0_ 0x0102 /* SD16 Channel 0 Control Register */
sfrw(SD16CCTL0, SD16CCTL0_);
-#define SD16MEM0_ 0x0112 /* SD16 Channel 0 Conversion Memory */
+#define SD16MEM0_ __MSP430_SD16MEM_BASE__ + 0x00 /* SD16 Channel 0 Conversion Memory */
sfrw(SD16MEM0, SD16MEM0_);
-#if defined(__msp430_have_sd16_1)
+#if defined(__MSP430_HAS_SD16_CH1__)
#define SD16INCTL1_ 0x00B1 /* SD16 Input Control Register Channel 1 */
sfrb(SD16INCTL1, SD16INCTL1_);
#define SD16PRE1_ 0x00B9 /* SD16 Preload Register Channel 1 */
sfrb(SD16PRE1, SD16PRE1_);
#define SD16CCTL1_ 0x0104 /* SD16 Channel 1 Control Register */
sfrw(SD16CCTL1, SD16CCTL1_);
-#define SD16MEM1_ 0x0114 /* SD16 Channel 1 Conversion Memory */
+#define SD16MEM1_ __MSP430_SD16MEM_BASE__ + 0x02 /* SD16 Channel 1 Conversion Memory */
sfrw(SD16MEM1, SD16MEM1_);
#endif
-#if defined(__msp430_have_sd16_2)
+#if defined(__MSP430_HAS_SD16_CH2__)
#define SD16INCTL2_ 0x00B2 /* SD16 Input Control Register Channel 2 */
sfrb(SD16INCTL2, SD16INCTL2_);
#define SD16PRE2_ 0x00BA /* SD16 Preload Register Channel 2 */
sfrb(SD16PRE2, SD16PRE2_);
#define SD16CCTL2_ 0x0106 /* SD16 Channel 2 Control Register */
sfrw(SD16CCTL2, SD16CCTL2_);
-#define SD16MEM2_ 0x0116 /* SD16 Channel 2 Conversion Memory */
+#define SD16MEM2_ __MSP430_SD16MEM_BASE__ + 0x04 /* SD16 Channel 2 Conversion Memory */
sfrw(SD16MEM2, SD16MEM2_);
#endif
-#if defined(__msp430_have_sd16a)
+#if defined(__MSP430_HAS_SD16_CH3__)
+#define SD16INCTL3_ 0x00B3 /* SD16 Input Control Register Channel 3 */
+sfrb(SD16INCTL3, SD16INCTL3_);
+#define SD16PRE3_ 0x00BB /* SD16 Preload Register Channel 3 */
+sfrb(SD16PRE3, SD16PRE3_);
+#define SD16CCTL3_ 0x0108 /* SD16 Channel 3 Control Register */
+sfrw(SD16CCTL3, SD16CCTL3_);
+#define SD16MEM3_ __MSP430_SD16MEM_BASE__ + 0x06 /* SD16 Channel 3 Conversion Memory */
+sfrw(SD16MEM3, SD16MEM3_);
+#endif
+
+#if defined(__MSP430_HAS_SD16_CH4__)
+#define SD16INCTL4_ 0x00B4 /* SD16 Input Control Register Channel 4 */
+sfrb(SD16INCTL4, SD16INCTL4_);
+#define SD16PRE4_ 0x00BC /* SD16 Preload Register Channel 4 */
+sfrb(SD16PRE4, SD16PRE4_);
+#define SD16CCTL4_ 0x010A /* SD16 Channel 4 Control Register */
+sfrw(SD16CCTL4, SD16CCTL4_);
+#define SD16MEM4_ __MSP430_SD16MEM_BASE__ + 0x08 /* SD16 Channel 4 Conversion Memory */
+sfrw(SD16MEM4, SD16MEM4_);
+#endif
+
+#if defined(__MSP430_HAS_SD16_CH5__)
+#define SD16INCTL5_ 0x00B5 /* SD16 Input Control Register Channel 5 */
+sfrb(SD16INCTL5, SD16INCTL5_);
+#define SD16PRE5_ 0x00BD /* SD16 Preload Register Channel 5 */
+sfrb(SD16PRE5, SD16PRE5_);
+#define SD16CCTL5_ 0x010C /* SD16 Channel 5 Control Register */
+sfrw(SD16CCTL5, SD16CCTL5_);
+#define SD16MEM5_ __MSP430_SD16MEM_BASE__ + 0x0A /* SD16 Channel 5 Conversion Memory */
+sfrw(SD16MEM5, SD16MEM5_);
+#endif
+
+#if defined(__MSP430_HAS_SD16_CH6__)
+#define SD16INCTL6_ 0x00B6 /* SD16 Input Control Register Channel 6 */
+sfrb(SD16INCTL6, SD16INCTL6_);
+#define SD16PRE6_ 0x00BE /* SD16 Preload Register Channel 6 */
+sfrb(SD16PRE6, SD16PRE6_);
+#define SD16CCTL6_ 0x010E /* SD16 Channel 6 Control Register */
+sfrw(SD16CCTL6, SD16CCTL6_);
+#define SD16MEM6_ __MSP430_SD16MEM_BASE__ + 0x0C /* SD16 Channel 6 Conversion Memory */
+sfrw(SD16MEM6, SD16MEM6_);
+#endif
+
+#if defined(__MSP430_HAS_SD16_A__)
/* SD16AE */
#define SD16AE0 0x0001 /* SD16 External Input Enable 0 */
#define SD16AE1 0x0002 /* SD16 External Input Enable 1 */
#define SD16DIV0 0x0040 /* SD16 Clock Divider Select 0 */
#define SD16DIV1 0x0080 /* SD16 Clock Divider Select 1 */
#define SD16LP 0x0100 /* SD16 Low Power Mode Enable */
-#if defined(__msp430_have_sd16a)
+#if defined(__MSP430_HAS_SD16_A__)
#define SD16XDIV0 0x0200 /* SD16 2.Clock Divider Select 0 */
#define SD16XDIV1 0x0400 /* SD16 2.Clock Divider Select 1 */
//#define SD16XDIV2 0x0800) /* SD16 2.Clock Divider Select 2 */
#define SD16DIV_2 (SD16DIV1) /* SD16 Clock Divider Select /4 */
#define SD16DIV_3 (SD16DIV0|SD16DIV1) /* SD16 Clock Divider Select /8 */
-#if defined(__msp430_have_sd16a)
+#if defined(__MSP430_HAS_SD16_A__)
#define SD16XDIV_0 (0x0000) /* SD16 2.Clock Divider Select /1 */
#define SD16XDIV_1 (SD16XDIV0) /* SD16 2.Clock Divider Select /3 */
#define SD16XDIV_2 (SD16XDIV1) /* SD16 2.Clock Divider Select /16 */
#define SD16OSR0 0x0100 /* SD16 Channel x OverSampling Ratio 0 */
#define SD16OSR1 0x0200 /* SD16 Channel x OverSampling Ratio 1 */
#define SD16SNGL 0x0400 /* SD16 Channel x Single Conversion On/Off */
-#if defined(__msp430_have_sd16a)
+#if defined(__MSP430_HAS_SD16_A__)
#define SD16XOSR 0x0800 /* SD16 Channel x Extended OverSampling Ratio */
#define SD16UNI 0x1000 /* SD16 Channel x Bipolar(0) / Unipolar(1) Mode */
#define SD16BUF0 0x2000 /* SD16 Channel x High Impedance Input Buffer Select: 0 */
#define SD16BUFG 0x8000 /* SD16 Channel x Buffer Gain 0:Gain=1 / 1:Gain=2 */
#endif
-#if defined(__msp430_have_sd16a)
+#if defined(__MSP430_HAS_SD16_A__)
#define SD16OSR_1024 (SD16XOSR|SD16OSR0) /* SD16 Channel x OverSampling Ratio 1024 */
#define SD16OSR_512 (SD16XOSR) /* SD16 Channel x OverSampling Ratio 512 */
#endif
#define SD16OSR_64 (2<<8) /* SD16 Channel x OverSampling Ratio 64 */
#define SD16OSR_32 (3<<8) /* SD16 Channel x OverSampling Ratio 32 */
-#if defined(__msp430_have_sd16a)
+#if defined(__MSP430_HAS_SD16_A__)
#define SD16BUF_0 (0<<13) /* SD16 High Imp. Input Buffer: Disabled */
#define SD16BUF_1 (1<<13) /* SD16 High Imp. Input Buffer: Slow */
#define SD16BUF_2 (2<<13) /* SD16 High Imp. Input Buffer: Meduim */
#define SD16BUF_3 (3<<13) /* SD16 High Imp. Input Buffer: Fast */
#endif
-#if !defined(__msp430_have_sd16a)
+#if !defined(__MSP430_HAS_SD16_A__)
#define AFEINCTL0 SD16INCTL0 /* SD16 Input Control Register Channel 0 */
#define AFEINCTL1 SD16INCTL1 /* SD16 Input Control Register Channel 1 */
#define AFEINCTL2 SD16INCTL2 /* SD16 Input Control Register Channel 2 */
#define SD16DIV_DIV4 SD16DIV_2 /* SD16 Clock Divider Select /4 */
#define SD16DIV_DIV8 SD16DIV_3 /* SD16 Clock Divider Select /8 */
-#if defined(__msp430_have_sd16a)
+#if defined(__MSP430_HAS_SD16_A__)
#define SD16XDIV_DIV1 SD16XDIV_0 /* SD16 2.Clock Divider Select /1 */
#define SD16XDIV_DIV2 SD16XDIV_1 /* SD16 2.Clock Divider Select /3 */
#define SD16XDIV_DIV4 SD16XDIV_2 /* SD16 2.Clock Divider Select /16 */
--- /dev/null
+#if !defined(__MSP430_HEADERS_SFR_H__)
+#define __MSP430_HEADERS_SFR_H__
+
+/* sfr.h
+ *
+ * mspgcc project: MSP430 device headers
+ * SFR (Special Function Registers) module header
+ *
+ * Peter Bigot <pab@peoplepowerco.com>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: $
+ *
+ */
+
+/* Switches:
+__MSP430_SFR_BASE__ - base address of SFR module
+*/
+
+#if defined(__MSP430_SFR_BASE__)
+
+#define SFRIE1_ __MSP430_SFR_BASE__ /* Interrupt Enable 1 */
+#define SFRIE1_L_ SFRIE1_
+#define SFRIE1_H_ SFRIE1_ + 0x01
+sfrw(SFRIE1, SFRIE1_);
+sfrb(SFRIE1_L, SFRIE1_L_);
+sfrb(SFRIE1_H, SFRIE1_H_);
+
+#define SFRIFG1_ __MSP430_SFR_BASE__ + 0x02 /* Interrupt Flag 1 */
+#define SFRIFG1_L_ SFRIFG1_
+#define SFRIFG1_H_ SFRIFG1_ + 0x01
+sfrw(SFRIFG1, SFRIFG1_);
+sfrb(SFRIFG1_L, SFRIFG1_L_);
+sfrb(SFRIFG1_H, SFRIFG1_H_);
+
+#define SFRRPCR1_ __MSP430_SFR_BASE__ + 0x04 /* Reset Pin Control */
+#define SFRRPCR1_L_ SFRRPCR1_
+#define SFRRPCR1_H_ SFRRPCR1_ + 0x01
+sfrw(SFRRPCR1, SFRRPCR1_);
+sfrb(SFRRPCR1_L, SFRRPCR1_L_);
+sfrb(SFRRPCR1_H, SFRRPCR1_H_);
+
+/* SFRIE1 Control Bits */
+#define WDTIE (0x0001) /* Watchdog timer interrupt enable */
+#define OFIE (0x0002) /* Oscillator fault interrupt enable */
+#define VMAIE (0x0008) /* Vacant memory access interrupt enable */
+#define NMIIE (0x0010) /* NMI pin interrupt enable */
+#define ACCVIE (0x0020) /* Flash controller access violation interrupt enable */
+#define JMBINIE (0x0040) /* JTAG mailbox input interrupt enable */
+#define JMBOUTIE (0x0080) /* JTAG mailbox output interrupt enable */
+
+/* SFRIFG1 Control Bits */
+#define WDTIFG (0x0001) /* Watchdog timer interrupt flag */
+#define OFIFG (0x0002) /* Oscillator fault interrupt flag */
+#define VMAIFG (0x0008) /* Vacant memory access interrupt flag */
+#define NMIIFG (0x0010) /* NMI pin interrupt flag */
+#define JMBINIFG (0x0040) /* JTAG mailbox input interrupt flag */
+#define JMBOUTIFG (0x0080) /* JTAG mailbox output interrupt flag */
+
+/* SFRRPCR Control Bits */
+#define SYSNMI (0x0001) /* NMI select */
+#define SYSNMIIES (0x0002) /* NMI edge select */
+#define SYSRSTUP (0x0004) /* Reset resistor pin pullup/pulldown */
+#define SYSRSTRE (0x0008) /* Reset pin resistor enable */
+
+/* Compatibility values for byte access */
+
+#define WDTIE_L WDTIE
+#define OFIE_L OFIE
+#define VMAIE_L VMAIE
+#define NMIIE_L NMIIE
+#define ACCVIE_L ACCVIE
+#define JMBINIE_L JMBINIE
+#define JMBOUTIE_L JMBOUTIE
+#define WDTIFG_L WDTIFG
+#define OFIFG_L OFIFG
+#define VMAIFG_L VMAIFG
+#define NMIIFG_L NMIIFG
+#define JMBINIFG_L JMBINIFG
+#define JMBOUTIFG_L JMBOUTIFG
+#define SYSNMI_L SYSNMI
+#define SYSNMIIES_L SYSNMIIES
+#define SYSRSTUP_L SYSRSTUP
+#define SYSRSTRE_L SYSRSTRE
+
+#endif /* __MSP430_SFR_BASE__ */
+
+#endif /* __MSP430_HEADERS_SFR_H__ */
--- /dev/null
+#ifndef __MSP430_HEADERS_SYS_H
+#define __MSP430_HEADERS_SYS_H
+
+/* sys.h
+ *
+ * mspgcc project: MSP430 device headers
+ * system control module
+ *
+ * (c) 2008 by Sergey A. Borshch <sb-sf@users.sf.net>
+ * Originally based in MSP430F543x datasheet (slas609)
+ * and MSP430x5xx Family User's Guide (slau208).
+ *
+ * $Id: sys.h,v 1.3 2009/02/28 12:14:53 sb-sf Exp $
+ */
+
+/* Switches:
+
+__MSP430_SYS_BASE__ - base address of SYS module
+
+*/
+
+#define SYSCTL_ __MSP430_SYS_BASE__ + 0x00 /* System control register */
+sfrw(SYSCTL, SYSCTL_);
+#define SYSCTL_L_ __MSP430_SYS_BASE__ + 0x00 /* low byte */
+sfrb(SYSCTL_L, SYSCTL_L_);
+#define SYSCTL_H_ __MSP430_SYS_BASE__ + 0x01 /* high byte */
+sfrb(SYSCTL_H, SYSCTL_H_);
+
+#define SYSBSLC_ __MSP430_SYS_BASE__ + 0x02 /* Bootstrap loader configuration register */
+sfrw(SYSBSLC, SYSBSLC_);
+#define SYSBSLC_L_ __MSP430_SYS_BASE__ + 0x02 /* low byte */
+sfrb(SYSBSLC_L, SYSBSLC_L_);
+#define SYSBSLC_H_ __MSP430_SYS_BASE__ + 0x03 /* high byte */
+sfrb(SYSBSLC_H, SYSBSLC_H_);
+
+#define SYSARB_ __MSP430_SYS_BASE__ + 0x04 /* Arbitration configuration register */
+sfrw(SYSARB, SYSARB_);
+#define SYSARB_L_ __MSP430_SYS_BASE__ + 0x04 /* low byte */
+sfrb(SYSARB_L, SYSARB_L_);
+#define SYSARB_H_ __MSP430_SYS_BASE__ + 0x05 /* high byte */
+sfrb(SYSARB_H, SYSARB_H_);
+
+#define SYSJMBC_ __MSP430_SYS_BASE__ + 0x06 /* JTAG Mailbox control register */
+sfrw(SYSJMBC, SYSJMBC_);
+#define SYSJMBC_L_ __MSP430_SYS_BASE__ + 0x06 /* low byte */
+sfrb(SYSJMBC_L, SYSJMBC_L_);
+#define SYSJMBC_H_ __MSP430_SYS_BASE__ + 0x07 /* high byte */
+sfrb(SYSJMBC_H, SYSJMBC_H_);
+
+#define SYSJMBI0_ __MSP430_SYS_BASE__ + 0x08 /* JTAG Mailbox input register #0 */
+sfrw(SYSJMBI0, SYSJMBI0_);
+#define SYSJMBI0_L_ __MSP430_SYS_BASE__ + 0x08 /* low byte */
+sfrb(SYSJMBI0_L, SYSJMBI0_L_);
+#define SYSJMBI0_H_ __MSP430_SYS_BASE__ + 0x09 /* high byte */
+sfrb(SYSJMBI0_H, SYSJMBI0_H_);
+
+#define SYSJMBI1_ __MSP430_SYS_BASE__ + 0x0A /* JTAG Mailbox input register #1 */
+sfrw(SYSJMBI1, SYSJMBI1_);
+#define SYSJMBI1_L_ __MSP430_SYS_BASE__ + 0x0A /* low byte */
+sfrb(SYSJMBI1_L, SYSJMBI1_L_);
+#define SYSJMBI1_H_ __MSP430_SYS_BASE__ + 0x0B /* high byte */
+sfrb(SYSJMBI1_H, SYSJMBI1_H_);
+
+#define SYSJMBO0_ __MSP430_SYS_BASE__ + 0x0C /* JTAG Mailbox output register #0 */
+sfrw(SYSJMBO0, SYSJMBO0_);
+#define SYSJMBO0_L_ __MSP430_SYS_BASE__ + 0x0C /* low byte */
+sfrb(SYSJMBO0_L, SYSJMBO0_L_);
+#define SYSJMBO0_H_ __MSP430_SYS_BASE__ + 0x0D /* high byte */
+sfrb(SYSJMBO0_H, SYSJMBO0_H_);
+
+#define SYSJMBO1_ __MSP430_SYS_BASE__ + 0x0E /* JTAG Mailbox output register #1 */
+sfrw(SYSJMBO1, SYSJMBO1_);
+#define SYSJMBO1_L_ __MSP430_SYS_BASE__ + 0x0E /* low byte */
+sfrb(SYSJMBO1_L, SYSJMBO1_L_);
+#define SYSJMBO1_H_ __MSP430_SYS_BASE__ + 0x0F /* high byte */
+sfrb(SYSJMBO1_H, SYSJMBO1_H_);
+
+#define SYSBERRIV_ __MSP430_SYS_BASE__ + 0x18 /* Bus error vector generator */
+sfrw(SYSBERRIV, SYSBERRIV_);
+#define SYSUNIV_ __MSP430_SYS_BASE__ + 0x1A /* User NMI vector generator */
+sfrw(SYSUNIV, SYSUNIV_);
+#define SYSSNIV_ __MSP430_SYS_BASE__ + 0x1C /* System NMI vector generator */
+sfrw(SYSSNIV, SYSSNIV_);
+#define SYSRSTIV_ __MSP430_SYS_BASE__ + 0x1E /* System reset vector generator */
+sfrw(SYSRSTIV, SYSRSTIV_);
+
+/* SYSCTL, SYSCTL_L */
+#define SYSJTAGPIN (1<<5) /* Dedicated JTAG pins enable */
+#define SYSBSLIND (1<<4) /* TCK/RST entry BSL indication detected */
+#define SYSPMMPE (1<<2) /* PMM access protect */
+#define SYSRIVECT (1<<0) /* RAM based interrupt vectors */
+
+/* SYSBSLC, SYSBSLC_L, SYSBSLC_H */
+#define SYSBSLPE (1<<15) /* BSL memory protection enable */
+#define SYSBSLOFF (1<<14) /* BSL memory disable for size covered in SYSBSLSIZE */
+#define SYSBSLR (1<<2) /* RAM assigned to BSL */
+#define SYSBSLSIZE1 (1<<1) /* BSL size */
+#define SYSBSLSIZE0 (1<<0) /* BSL size */
+
+#define SYSBSLSIZE_0 (0<<0) /* size 512 bytes, BSL_SEG_3 */
+#define SYSBSLSIZE_1 (1<<0) /* size 1024 bytes, BSL_SEG_2,3 */
+#define SYSBSLSIZE_2 (2<<0) /* size 1536 bytes, BSL_SEG_1,2,3 */
+#define SYSBSLSIZE_3 (3<<0) /* size 2048 bytes, BSL_SEG_0,1,2,3 */
+
+/* SYSJMBC, SYSJMBC_L */
+#define JMBCLR1OFF (1<<7) /* Incomming JTAG mailbox 1 flag auto-clear disable */
+#define MBCLR0OFF (1<<6) /* Incomming JTAG mailbox 0 flag auto-clear disable */
+#define JMBMODE (1<<4) /* Operation mode of JMB for JMBI0/1 and JMBO0/1 */
+#define JMBOUT1FG (1<<3) /* Outgoing JTAG mailbox 1 flag */
+#define JMBOUT0FG (1<<2) /* Outgoing JTAG mailbox 0 flag */
+#define JMBIN1FG (1<<1) /* Incoming JTAG mailbox 1 flag */
+#define JMBIN0FG (1<<0) /* Incoming JTAG mailbox 0 flag */
+
+
+#ifndef __ASSEMBLER__
+/* Structured declaration */
+
+#undef __xstr
+#undef __str
+#define __xstr(x) __str(x)
+#define __str(x) #x
+
+typedef struct
+{
+ union
+ {
+ volatile unsigned int CTL; /* System control register */
+ struct
+ {
+ volatile unsigned char CTL_L; /* low byte */
+ volatile unsigned char CTL_H; /* high byte */
+ };
+ };
+ union
+ {
+ volatile unsigned int BSLC; /* Bootstrap loader configuration register */
+ struct
+ {
+ volatile unsigned char BSLC_L; /* low byte */
+ volatile unsigned char BSLC_H; /* high byte */
+ };
+ };
+ union
+ {
+ volatile unsigned int ARB; /* Arbitration configuration register */
+ struct
+ {
+ volatile unsigned char ARB_L; /* low byte */
+ volatile unsigned char ARB_H; /* high byte */
+ };
+ };
+ union
+ {
+ volatile unsigned int JMBC; /* JTAG Mailbox control register */
+ struct
+ {
+ volatile unsigned char JMBC_L; /* low byte */
+ volatile unsigned char JMBC_H; /* high byte */
+ };
+ };
+ union
+ {
+ volatile unsigned int JMBI0; /* JTAG Mailbox input register #0 */
+ struct
+ {
+ volatile unsigned char JMBI0_L; /* low byte */
+ volatile unsigned char JMBI0_H; /* high byte */
+ };
+ };
+ union
+ {
+ volatile unsigned int JMBI1; /* JTAG Mailbox input register #1 */
+ struct
+ {
+ volatile unsigned char JMBI1_L; /* low byte */
+ volatile unsigned char JMBI1_H; /* high byte */
+ };
+ };
+ union
+ {
+ volatile unsigned int JMBO0; /* JTAG Mailbox output register #0 */
+ struct
+ {
+ volatile unsigned char JMBO0_L; /* low byte */
+ volatile unsigned char JMBO0_H; /* high byte */
+ };
+ };
+ union
+ {
+ volatile unsigned int JMBO1; /* JTAG Mailbox output register #1 */
+ struct
+ {
+ volatile unsigned char JMBO1_L; /* low byte */
+ volatile unsigned char JMBO1_H; /* high byte */
+ };
+ };
+ unsigned int dummy[4];
+ volatile unsigned int BERRIV; /* Bus error vector generator */
+ volatile unsigned int UNIV; /* User NMI vector generator */
+ volatile unsigned int SNIV; /* System NMI vector generator */
+ volatile unsigned int RSTIV; /* System reset vector generator */
+} sys_t;
+sys_t SYS asm(__xstr(__MSP430_SYS_BASE__));
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* __MSP430_HEADERS_SYS_H */
-#if !defined(__msp430_headers_timera_h__)
-#define __msp430_headers_timera_h__
+#if !defined(__MSP430_HEADERS_TIMERA_H__)
+#define __MSP430_HEADERS_TIMERA_H__
/* timera.h
*
* (c) 2002 by M. P. Ashton <data@ieee.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: timera.h,v 1.13 2006/04/19 20:09:52 cliechti Exp $
+ * 2009-05-19 - modifications by S. Balling <praktikum@innoventis.de>
+ * - added T0A5
+ * - added T1A3
+ * 2009-10-08 - modifications by J.M.Gross <mspgcc@grossibaer.de>
+ * - added TIV defines for T0A5 and T1A3 (and TB7)
+ * - changed T0A5 and T1A3 to use external base address
+ *
+ * $Id: timera.h,v 1.15 2009/06/04 21:55:18 cliechti Exp $
*/
-/* Switches:
+/* Switches:
__MSP430_HAS_TA2__ - if the device has a timer0 A with 2 channels
__MSP430_HAS_TA3__ - if the device has a timer0 A with 3 channels
-__MSP430_HAS_T1A5__ - if the device has a timer1 A, as well as timer0 A
+__MSP430_HAS_T1A2__ - if the device has a timer1 A with 2 channels, as well as timer0 A
+__MSP430_HAS_T1A5__ - if the device has a timer1 A with 5 channels, as well as timer0 A
+__MSP430_HAS_T0A5__ - if the device has a timer0 A with 5 channels
+__MSP430_T0A_BASE__ - base address for timer 0 A (5)
+__MSP430_HAS_T1A3__ - if the device has a timer1 A with 3 channels
+__MSP430_T1A_BASE__ - base address for timer 1 A (3)
*/
+#if defined(__MSP430_HAS_T0A5__)
+#define TA0CTL_ __MSP430_T0A_BASE__ + 0x00 // Timer A 0 Control
+sfrw (TA0CTL,TA0CTL_);
+#define TA0CTL_L_ __MSP430_T0A_BASE__ + 0x00
+sfrb (TA0CTL_L,TA0CTL_L_);
+#define TA0CTL_H_ __MSP430_T0A_BASE__ + 0x01
+sfrb (TA0CTL_H,TA0CTL_H_);
+#define TA0CCTL0_ __MSP430_T0A_BASE__ + 0x02 // Timer A 0 Capture/Compare Control 0
+sfrw (TA0CCTL0,TA0CCTL0_);
+#define TA0CCTL0_L_ __MSP430_T0A_BASE__ + 0x02
+sfrb (TA0CCTL0_L,TA0CCTL0_L_);
+#define TA0CCTL0_H_ __MSP430_T0A_BASE__ + 0x03
+sfrb (TA0CCTL0_H,TA0CCTL0_H_);
+#define TA0CCTL1_ __MSP430_T0A_BASE__ + 0x04 // Timer A 0 Capture/Compare Control 1
+sfrw (TA0CCTL1,TA0CCTL1_);
+#define TA0CCTL1_L_ __MSP430_T0A_BASE__ + 0x04
+sfrb (TA0CCTL1_L,TA0CCTL1_L_);
+#define TA0CCTL1_H_ __MSP430_T0A_BASE__ + 0x05
+sfrb (TA0CCTL1_H,TA0CCTL1_H_);
+#define TA0CCTL2_ __MSP430_T0A_BASE__ + 0x06 // Timer A 0 Capture/Compare Control 2
+sfrw (TA0CCTL2,TA0CCTL2_);
+#define TA0CCTL2_L_ __MSP430_T0A_BASE__ + 0x06
+sfrb (TA0CCTL2_L,TA0CCTL2_L_);
+#define TA0CCTL2_H_ __MSP430_T0A_BASE__ + 0x07
+sfrb (TA0CCTL2_H,TA0CCTL2_H_);
+#define TA0CCTL3_ __MSP430_T0A_BASE__ + 0x08 // Timer A 0 Capture/Compare Control 3
+sfrw (TA0CCTL3,TA0CCTL3_);
+#define TA0CCTL3_L_ __MSP430_T0A_BASE__ + 0x08
+sfrb (TA0CCTL3_L,TA0CCTL3_L_);
+#define TA0CCTL3_H_ __MSP430_T0A_BASE__ + 0x09
+sfrb (TA0CCTL3_H,TA0CCTL3_H_);
+#define TA0CCTL4_ __MSP430_T0A_BASE__ + 0x0A // Timer A 0 Capture/Compare Control 4
+sfrw (TA0CCTL4,TA0CCTL4_);
+#define TA0CCTL4_L_ __MSP430_T0A_BASE__ + 0x0A
+sfrb (TA0CCTL4_L,TA0CCTL4_L_);
+#define TA0CCTL4_H_ __MSP430_T0A_BASE__ + 0x0B
+sfrb (TA0CCTL4_H,TA0CCTL4_H_);
+#define TA0R_ __MSP430_T0A_BASE__ + 0x10 // Timer A 0
+sfrw (TA0R,TA0R_);
+#define TA0R_L_ __MSP430_T0A_BASE__ + 0x10
+sfrb (TA0R_L,TA0R_L_);
+#define TA0R_H_ __MSP430_T0A_BASE__ + 0x11
+sfrb (TA0R_H,TA0R_H_);
+#define TA0CCR0_ __MSP430_T0A_BASE__ + 0x12 // Timer A 0 Capture/Compare 0
+sfrw (TA0CCR0,TA0CCR0_);
+#define TA0CCR0_L_ __MSP430_T0A_BASE__ + 0x12
+sfrb (TA0CCR0_L,TA0CCR0_L_);
+#define TA0CCR0_H_ __MSP430_T0A_BASE__ + 0x13
+sfrb (TA0CCR0_H,TA0CCR0_H_);
+#define TA0CCR1_ __MSP430_T0A_BASE__ + 0x14 // Timer A 0 Capture/Compare 1
+sfrw (TA0CCR1,TA0CCR1_);
+#define TA0CCR1_L_ __MSP430_T0A_BASE__ + 0x14
+sfrb (TA0CCR1_L,TA0CCR1_L_);
+#define TA0CCR1_H_ __MSP430_T0A_BASE__ + 0x15
+sfrb (TA0CCR1_H,TA0CCR1_H_);
+#define TA0CCR2_ __MSP430_T0A_BASE__ + 0x16 // Timer A 0 Capture/Compare 2
+sfrw (TA0CCR2,TA0CCR2_);
+#define TA0CCR2_L_ __MSP430_T0A_BASE__ + 0x16
+sfrb (TA0CCR2_L,TA0CCR2_L_);
+#define TA0CCR2_H_ __MSP430_T0A_BASE__ + 0x17
+sfrb (TA0CCR2_H,TA0CCR2_H_);
+#define TA0CCR3_ __MSP430_T0A_BASE__ + 0x18 // Timer A 0 Capture/Compare 3
+sfrw (TA0CCR3,TA0CCR3_);
+#define TA0CCR3_L_ __MSP430_T0A_BASE__ + 0x18
+sfrb (TA0CCR3_L,TA0CCR3_L_);
+#define TA0CCR3_H_ __MSP430_T0A_BASE__ + 0x19
+sfrb (TA0CCR3_H,TA0CCR3_H_);
+#define TA0CCR4_ __MSP430_T0A_BASE__ + 0x1A // Timer A 0 Capture/Compare 4
+sfrw (TA0CCR4,TA0CCR4_);
+#define TA0CCR4_L_ __MSP430_T0A_BASE__ + 0x1A
+sfrb (TA0CCR4_L,TA0CCR4_L_);
+#define TA0CCR4_H_ __MSP430_T0A_BASE__ + 0x1B
+sfrb (TA0CCR4_H,TA0CCR4_H_);
+#define TA0EX0_ __MSP430_T0A_BASE__ + 0x20 // Timer A 0 Expansion Register 0
+sfrw (TA0EX0,TA0EX0_);
+#define TA0EX0_L_ __MSP430_T0A_BASE__ + 0x20
+sfrb (TA0EX0_L,TA0EX0_L_);
+#define TA0EX0_H_ __MSP430_T0A_BASE__ + 0x21
+sfrb (TA0EX0_H,TA0EX0_H_);
+#define TA0IV_ __MSP430_T0A_BASE__ + 0x2E // Timer A 0 Interrupt Vector Word
+sfrw (TA0IV,TA0IV_);
+#define TA0IV_L_ __MSP430_T0A_BASE__ + 0x2E
+sfrb (TA0IV_L,TA0IV_L_);
+#define TA0IV_H_ __MSP430_T0A_BASE__ + 0x2F
+sfrb (TA0IV_H,TA0IV_H_);
+#endif /* __MSP430_HAS_T0A5__ */
+
+#if defined(__MSP430_HAS_T1A3__)
+#define TA1CTL_ __MSP430_T1A_BASE__ + 0x00 // Timer A 1 Control
+sfrw (TA1CTL,TA1CTL_);
+#define TA1CTL_L_ __MSP430_T1A_BASE__ + 0x00
+sfrb (TA1CTL_L,TA1CTL_L_);
+#define TA1CTL_H_ __MSP430_T1A_BASE__ + 0x01
+sfrb (TA1CTL_H,TA1CTL_H_);
+#define TA1CCTL0_ __MSP430_T1A_BASE__ + 0x02 // Timer A 1 Capture/Compare Control 0
+sfrw (TA1CCTL0,TA1CCTL0_);
+#define TA1CCTL0_L_ __MSP430_T1A_BASE__ + 0x02
+sfrb (TA1CCTL0_L,TA1CCTL0_L_);
+#define TA1CCTL0_H_ __MSP430_T1A_BASE__ + 0x03
+sfrb (TA1CCTL0_H,TA1CCTL0_H_);
+#define TA1CCTL1_ __MSP430_T1A_BASE__ + 0x04 // Timer A 1 Capture/Compare Control 1
+sfrw (TA1CCTL1,TA1CCTL1_);
+#define TA1CCTL1_L_ __MSP430_T1A_BASE__ + 0x04
+sfrb (TA1CCTL1_L,TA1CCTL1_L_);
+#define TA1CCTL1_H_ __MSP430_T1A_BASE__ + 0x05
+sfrb (TA1CCTL1_H,TA1CCTL1_H_);
+#define TA1CCTL2_ __MSP430_T1A_BASE__ + 0x06 // Timer A 1 Capture/Compare Control 2
+sfrw (TA1CCTL2,TA1CCTL2_);
+#define TA1CCTL2_L_ __MSP430_T1A_BASE__ + 0x06
+sfrb (TA1CCTL2_L,TA1CCTL2_L_);
+#define TA1CCTL2_H_ __MSP430_T1A_BASE__ + 0x07
+sfrb (TA1CCTL2_H,TA1CCTL2_H_);
+#define TA1R_ __MSP430_T1A_BASE__ + 0x10 // Timer A 1
+sfrw (TA1R,TA1R_);
+#define TA1R_L_ __MSP430_T1A_BASE__ + 0x10
+sfrb (TA1R_L,TA1R_L_);
+#define TA1R_H_ __MSP430_T1A_BASE__ + 0x11
+sfrb (TA1R_H,TA1R_H_);
+#define TA1CCR0_ __MSP430_T1A_BASE__ + 0x12 // Timer A 1 Capture/Compare 0
+sfrw (TA1CCR0,TA1CCR0_);
+#define TA1CCR0_L_ __MSP430_T1A_BASE__ + 0x12
+sfrb (TA1CCR0_L,TA1CCR0_L_);
+#define TA1CCR0_H_ __MSP430_T1A_BASE__ + 0x13
+sfrb (TA1CCR0_H,TA1CCR0_H_);
+#define TA1CCR1_ __MSP430_T1A_BASE__ + 0x14 // Timer A 1 Capture/Compare 1
+sfrw (TA1CCR1,TA1CCR1_);
+#define TA1CCR1_L_ __MSP430_T1A_BASE__ + 0x14
+sfrb (TA1CCR1_L,TA1CCR1_L_);
+#define TA1CCR1_H_ __MSP430_T1A_BASE__ + 0x15
+sfrb (TA1CCR1_H,TA1CCR1_H_);
+#define TA1CCR2_ __MSP430_T1A_BASE__ + 0x16 // Timer A 1 Capture/Compare 2
+sfrw (TA1CCR2,TA1CCR2_);
+#define TA1CCR2_L_ __MSP430_T1A_BASE__ + 0x16
+sfrb (TA1CCR2_L,TA1CCR2_L_);
+#define TA1CCR2_H_ __MSP430_T1A_BASE__ + 0x17
+sfrb (TA1CCR2_H,TA1CCR2_H_);
+#define TA1EX0_ __MSP430_T1A_BASE__ + 0x20 // Timer A 1 Expansion Register 0
+sfrw (TA1EX0,TA1EX0_);
+#define TA1EX0_L_ __MSP430_T1A_BASE__ + 0x20
+sfrb (TA1EX0_L,TA1EX0_L_);
+#define TA1EX0_H_ __MSP430_T1A_BASE__ + 0x21
+sfrb (TA1EX0_H,TA1EX0_H_);
+#define TA1IV_ __MSP430_T1A_BASE__ + 0x2E // Timer A 1 Interrupt Vector Word
+sfrw (TA1IV,TA1IV_);
+#define TA1IV_L_ __MSP430_T1A_BASE__ + 0x2E
+sfrb (TA1IV_L,TA1IV_L_);
+#define TA1IV_H_ __MSP430_T1A_BASE__ + 0x2F
+sfrb (TA1IV_H,TA1IV_H_);
+#endif /* __MSP430_HAS_T1A3__ */
+
#if defined(__MSP430_HAS_TA2__) || defined(__MSP430_HAS_TA3__)
#define TA0IV_ 0x012E /* Timer A 0 Interrupt Vector Word */
sfrw (TA0IV,TA0IV_);
#define CCR0_ TA0CCR0_
#define CCR1 TA0CCR1
#define CCR1_ TA0CCR1_
-#endif
+#endif /* __MSP430_HAS_TA2__ || __MSP430_HAS_TA3__ */
#if defined(__MSP430_HAS_TA3__)
#define TA0CCTL2_ 0x0166 /* Timer A 0 Capture/Compare Control 2 */
#define CCTL2_ TA0CCTL2_
#define CCR2 TA0CCR2
#define CCR2_ TA0CCR2_
-#endif
+#endif /* __MSP430_HAS_TA3__ */
-#if defined(__MSP430_HAS_T1A5__)
+#if defined(__MSP430_HAS_T1A2__) || defined(__MSP430_HAS_T1A5__)
#define TA1IV_ 0x011E /* Timer A 1 Interrupt Vector Word */
sfrw (TA1IV, TA1IV_);
#define TA1CTL_ 0x0180 /* Timer A 1 Control */
sfrw (TA1CCTL0, TA1CCTL0_);
#define TA1CCTL1_ 0x0184 /* Timer A 1 Capture/Compare Control 1 */
sfrw (TA1CCTL1, TA1CCTL1_);
+#if defined(__MSP430_HAS_T1A5__)
#define TA1CCTL2_ 0x0186 /* Timer A 1 Capture/Compare Control 2 */
sfrw (TA1CCTL2, TA1CCTL2_);
#define TA1CCTL3_ 0x0188 /* Timer A 1 Capture/Compare Control 3 */
sfrw (TA1CCTL3, TA1CCTL3_);
#define TA1CCTL4_ 0x018A /* Timer A 1 Capture/Compare Control 4 */
sfrw (TA1CCTL4, TA1CCTL4_);
+#endif
#define TAR1_ 0x0190 /* Timer A 1 */
sfrw (TAR1, TAR1_);
#define TA1CCR0_ 0x0192 /* Timer A 1 Capture/Compare 0 */
sfrw (TA1CCR0, TA1CCR0_);
#define TA1CCR1_ 0x0194 /* Timer A 1 Capture/Compare 1 */
sfrw (TA1CCR1, TA1CCR1_);
+#if defined(__MSP430_HAS_T1A5__)
#define TA1CCR2_ 0x0196 /* Timer A 1 Capture/Compare 2 */
sfrw (TA1CCR2, TA1CCR2_);
#define TA1CCR3_ 0x0198 /* Timer A 1 Capture/Compare 3 */
#define TA1CCR4_ 0x019A /* Timer A 1 Capture/Compare 4 */
sfrw (TA1CCR4, TA1CCR4_);
#endif
+#endif
-#if !defined(_GNU_ASSEMBLER_)
+#if !defined(__ASSEMBLER__)
/* Structured declaration */
typedef struct {
volatile unsigned
cm:2;
} __attribute__ ((packed)) tacctl_t;
+#if defined(__MSP430_HAS_TA2__) || defined(__MSP430_HAS_TA3__)
/* The timer A declaration itself */
struct timera_t {
tactl_t ctl;
tacctl_t cctl0;
tacctl_t cctl1;
+#if defined(__MSP430_HAS_TA3__)
tacctl_t cctl2;
- volatile unsigned dummy[4]; /* Pad to the next group of registers */
+#else
+ volatile unsigned dummy1[1]; /* Pad to the next group of registers */
+#endif
+ volatile unsigned dummy2[4]; /* Pad to the next group of registers */
volatile unsigned tar;
volatile unsigned taccr0;
volatile unsigned taccr1;
+#if defined(__MSP430_HAS_TA3__)
volatile unsigned taccr2;
+#endif
};
#ifdef __cplusplus
extern "C" struct timera_t timera asm("0x0160");
#else //__cplusplus
struct timera_t timera asm("0x0160");
#endif //__cplusplus
+#endif // __MSP430_HAS_TA2__ || __MSP430_HAS_TA3__
-#if defined(__MSP430_HAS_T1A5__)
+#if defined(__MSP430_HAS_T1A2__) || defined(__MSP430_HAS_T1A5__)
/* The timer A1 declaration itself */
struct timera1_t {
tactl_t ctl;
tacctl_t cctl0;
tacctl_t cctl1;
+#if defined(__MSP430_HAS_T1A5__)
tacctl_t cctl2;
tacctl_t cctl3;
tacctl_t cctl4;
- volatile unsigned dummy[2]; /* Pad to the next group of registers */
+#else
+ volatile unsigned dummy1[3]; /* Pad to the next group of registers */
+#endif
+ volatile unsigned dummy2[2]; /* Pad to the next group of registers */
volatile unsigned tar;
volatile unsigned taccr0;
volatile unsigned taccr1;
+#if defined(__MSP430_HAS_T1A5__)
volatile unsigned taccr2;
volatile unsigned taccr3;
volatile unsigned taccr4;
+#endif
};
#ifdef __cplusplus
extern "C" struct timera1_t timera1 asm("0x0180");
#define TAIFG 0x0001 /* Timer A counter interrupt flag */
#define MC_0 (0<<4) /* Timer A mode control: 0 - Stop */
+#define MC__STOP MC_0
#define MC_1 (1<<4) /* Timer A mode control: 1 - Up to CCR0 */
+#define MC__UP MC_1
#define MC_2 (2<<4) /* Timer A mode control: 2 - Continous up */
+#define MC__CONTINOUS MC_2 /* (sic) */
#define MC_3 (3<<4) /* Timer A mode control: 3 - Up/Down */
+#define MC__UPDOWN MC_3
#define ID_0 (0<<6) /* Timer A input divider: 0 - /1 */
#define ID_1 (1<<6) /* Timer A input divider: 1 - /2 */
#define ID_2 (2<<6) /* Timer A input divider: 2 - /4 */
#define ID_3 (3<<6) /* Timer A input divider: 3 - /8 */
#define TASSEL_0 (0<<8) /* Timer A clock source select: 0 - TACLK */
+#define TASSEL__TACLK TASSEL_0
#define TASSEL_1 (1<<8) /* Timer A clock source select: 1 - ACLK */
+#define TASSEL__ACLK TASSEL_1
#define TASSEL_2 (2<<8) /* Timer A clock source select: 2 - SMCLK */
+#define TASSEL__SMCLK TASSEL_2
#define TASSEL_3 (3<<8) /* Timer A clock source select: 3 - INCLK */
+#define TASSEL__INCLK TASSEL_3
#define CM1 0x8000 /* Capture mode 1 */
#define CM0 0x4000 /* Capture mode 0 */
#define CM_NEG CM_2
#define CM_BOTH CM_3
+#define CCIS_CCIA CCIS_0
+#define CCIS_CCIB CCIS_1
+#define CCIS_GND CCIS_2
+#define CCIS_VCC CCIS_3
+
+
/* TimerA IV names */
#if defined(__MSP430_HAS_TA3__) || defined(__MSP430_HAS_TA2____)
#define TAIV_NONE 0x00 /* No interrupt pending */
#define TAIV_OVERFLOW 0x0A /* Timer overflow TAIFG Lowest */
#endif /*__MSP430_HAS_TA3__ || __MSP430_HAS_TA2__*/
+/* on newer devices, TIMERA0, TIMERA1 and TIMERB have identical TIV registers */
+#if defined(__MSP430_HAS_T0A5__) || defined(__MSP430_HAS_T1A3__) || !defined(TIV_NONE) /* in case already defined for new TIMERB(7) */
+ #define TIV_NONE 0x00 /* No interrupt pending */
+ #define TIV_CCR1 0x02 /* Capture/compare 1 TACCR1 CCIFG Highest */
+ #define TIV_CCR2 0x04 /* Capture/compare 2 TACCR2 CCIFG */
+ #define TIV_CCR3 0x06 /* Capture/compare 2 TACCR2 CCIFG */
+ #define TIV_CCR4 0x08 /* Capture/compare 2 TACCR2 CCIFG */
+ #define TIV_CCR5 0x0A /* Capture/compare 2 TACCR2 CCIFG */
+ #define TIV_CCR6 0x0C /* Capture/compare 2 TACCR2 CCIFG */
+ #define TIV_OVERFLOW 0x0E /* Timer overflow TAIFG Lowest */
#endif
+
+
+#endif /*__MSP430_HEADERS_TIMERA_H__*/
-#if !defined(__msp430_headers_timerb_h__)
-#define __msp430_headers_timerb_h__
+#if !defined(__MSP430_HEADERS_TIMERB_H__)
+#define __MSP430_HEADERS_TIMERB_H__
/* timerb.h
*
* (c) 2002 by M. P. Ashton <data@ieee.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: timerb.h,v 1.11 2006/04/19 20:09:52 cliechti Exp $
+ * 2009-10-08 - modifications by J.M.Gross <mspgcc@grossibaer.de>
+ * - added basic support for TB7 on MSP430F54xx
+ *
+ * $Id: timerb.h,v 1.12 2008/10/09 15:00:14 sb-sf Exp $
*/
/* Switches:
-__MSP430_HAS_TB7__ - if timer B has 7 capture/compare registers (default is 3)
-
+__MSP430_HAS_TB7__ - if timer B has 7 capture/compare registers (default is 3)
+__MSP430_HAS_TB7_5__ - if timer B is part of Series 5 devices (and has 7 CC registers)
+__MSP430_TB7_BASE__ - base address TB7_5
*/
+#if defined (__MSP430_HAS_TB7_5__)
+
+#define TBCTL_ __MSP430_TB7_BASE__ + 0x00 // Timer B Control
+sfrw (TBCTL,TBCTL_);
+#define TBCCTL0_ __MSP430_TB7_BASE__ + 0x02 // Timer B Capture/Compare Control 0
+sfrw (TBCCTL0,TBCCTL0_);
+#define TBCCTL1_ __MSP430_TB7_BASE__ + 0x04 // Timer B Capture/Compare Control 1
+sfrw (TBCCTL1,TBCCTL1_);
+#define TBCCTL2_ __MSP430_TB7_BASE__ + 0x06 // Timer B Capture/Compare Control 2
+sfrw (TBCCTL2,TBCCTL2_);
+#define TBCCTL3_ __MSP430_TB7_BASE__ + 0x08 // Timer B Capture/Compare Control 3
+sfrw (TBCCTL3,TBCCTL3_);
+#define TBCCTL4_ __MSP430_TB7_BASE__ + 0x0A // Timer B Capture/Compare Control 4
+sfrw (TBCCTL4,TBCCTL4_);
+#define TBCCTL5_ __MSP430_TB7_BASE__ + 0x0C // Timer B Capture/Compare Control 5
+sfrw (TBCCTL5,TBCCTL5_);
+#define TBCCTL6_ __MSP430_TB7_BASE__ + 0x0E // Timer B Capture/Compare Control 6
+sfrw (TBCCTL6,TBCCTL6_);
+#define TBR_ __MSP430_TB7_BASE__ + 0x10 // Timer B
+sfrw (TBR,TBR_);
+#define TBCCR0_ __MSP430_TB7_BASE__ + 0x12 // Timer B Capture/Compare 0
+sfrw (TBCCR0,TBCCR0_);
+#define TBCCR1_ __MSP430_TB7_BASE__ + 0x14 // Timer B Capture/Compare 1
+sfrw (TBCCR1,TBCCR1_);
+#define TBCCR2_ __MSP430_TB7_BASE__ + 0x16 // Timer B Capture/Compare 2
+sfrw (TBCCR2,TBCCR2_);
+#define TBCCR3_ __MSP430_TB7_BASE__ + 0x18 // Timer B Capture/Compare 3
+sfrw (TBCCR3,TBCCR3_);
+#define TBCCR4_ __MSP430_TB7_BASE__ + 0x1A // Timer B Capture/Compare 4
+sfrw (TBCCR4,TBCCR4_);
+#define TBCCR5_ __MSP430_TB7_BASE__ + 0x1C // Timer B Capture/Compare 5
+sfrw (TBCCR5,TBCCR5_);
+#define TBCCR6_ __MSP430_TB7_BASE__ + 0x1E // Timer B Capture/Compare 6
+sfrw (TBCCR6,TBCCR6_);
+#define TBEX0_ __MSP430_TB7_BASE__ + 0x20 // Timer B Expansion Register 0
+sfrw (TBEX0,TBEX0_);
+#define TBIV_ __MSP430_TB7_BASE__ + 0x2E // Timer B Interrupt Vector Word
+sfrw (TBIV,TBIV_);
+
+
+#define TBCLGRP1 0x4000 /* Timer B compare latch load group 1 */
+#define TBCLGRP0 0x2000 /* Timer B compare latch load group 0 */
+#define CNTL1 0x1000 /* Counter length 1 */
+#define CNTL0 0x0800 /* Counter length 0 */
+#define TBSSEL1 0x0200 /* Clock source 1 */
+#define TBSSEL0 0x0100 /* Clock source 0 */
+#define TBCLR 0x0004 /* Timer B counter clear */
+#define TBIE 0x0002 /* Timer B interrupt enable */
+#define TBIFG 0x0001 /* Timer B interrupt flag */
+
+#define TBSSEL_0 (0<<8) /* Clock source: TBCLK */
+#define TBSSEL_1 (1<<8) /* Clock source: ACLK */
+#define TBSSEL_2 (2<<8) /* Clock source: SMCLK */
+#define TBSSEL_3 (3<<8) /* Clock source: INCLK */
+#define CNTL_0 (0<<11) /* Counter length: 16 bit */
+#define CNTL_1 (1<<11) /* Counter length: 12 bit */
+#define CNTL_2 (2<<11) /* Counter length: 10 bit */
+#define CNTL_3 (3<<11) /* Counter length: 8 bit */
+#define TBCLGRP_0 (0<<13) /* Timer B Group: 0 - individually */
+#define TBCLGRP_1 (1<<13) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
+#define TBCLGRP_2 (2<<13) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
+#define TBCLGRP_3 (3<<13) /* Timer B Group: 3 - 1 group (all) */
+
+/* Additional Timer B Control Register bits are defined in Timer A */
+
+#define CLLD1 0x0400 /* Compare latch load source 1 */
+#define CLLD0 0x0200 /* Compare latch load source 0 */
+
+#define CLLD_0 (0<<9) /* Compare latch load source 0 - immediate */
+#define CLLD_1 (1<<9) /* Compare latch load source 1 - TBR counts to 0 */
+#define CLLD_2 (2<<9) /* Compare latch load source 2 - up/down */
+#define CLLD_3 (3<<9) /* Compare latch load source 3 - TBR counts to TBCTL0 */
+
+/* Aliases by mspgcc */
+#define TBSSEL_TBCLK TBSSEL_0
+#define TBSSEL_ACLK TBSSEL_1
+#define TBSSEL_SMCLK TBSSEL_2
+#define TBSSEL_INCLK TBSSEL_3
+
+#define CNTL_16 CNTL_0
+#define CNTL_12 CNTL_1
+#define CNTL_10 CNTL_2
+#define CNTL_8 CNTL_3
+
+
+/* on newer devices, TIMERA0, TIMERA1 and TIMERB have identical TIV registers */
+#if !defined(TIV_NONE) /* in case already defined by TIMERA */
+ #define TIV_NONE 0x00 /* No interrupt pending */
+ #define TIV_CCR1 0x02 /* Capture/compare 1 TACCR1 CCIFG Highest */
+ #define TIV_CCR2 0x04 /* Capture/compare 2 TACCR2 CCIFG */
+ #define TIV_CCR3 0x06 /* Capture/compare 2 TACCR2 CCIFG */
+ #define TIV_CCR4 0x08 /* Capture/compare 2 TACCR2 CCIFG */
+ #define TIV_CCR5 0x0A /* Capture/compare 2 TACCR2 CCIFG */
+ #define TIV_CCR6 0x0C /* Capture/compare 2 TACCR2 CCIFG */
+ #define TIV_OVERFLOW 0x0E /* Timer overflow TAIFG Lowest */
+#endif
+
+#else /* not a series 5 device */
+
#define TBIV_ 0x011E /* Timer B Interrupt Vector Word */
sfrw(TBIV,TBIV_);
#define TBCTL_ 0x0180 /* Timer B Control */
#endif
-#ifndef _GNU_ASSEMBLER_
+#ifndef __ASSEMBLER__
/* Structured declaration */
typedef struct {
volatile unsigned
#endif /*__MSP430_HAS_TB7__B7*/
#define TBIV_OVERFLOW 0x0E /* Timer overflow TBIFG Lowest */
-#endif
+#endif /* old TimerB */
+
+#endif /* __MSP430_HEADERS_TIMERB_H__ */
--- /dev/null
+#ifndef __msp430_headers_tlv_h
+#define __msp430_headers_tlv_h
+
+/* tlv.h
+ *
+ * mspgcc project: MSP430 device headers
+ * tlv structures
+ *
+ * (c) 2008 by Sergey A. Borshch <sb-sf@users.sf.net>
+ *
+ * $Id: tlv.h,v 1.2 2009/01/11 23:11:48 sb-sf Exp $
+ */
+
+/* Switches: none */
+
+
+/* TLV Calibration Data Structure */
+#define TAG_DCO_30 0x01 /* Tag for DCO30 Calibration Data */
+#define TAG_ADC12_1 0x10 /* Tag for ADC12_1 Calibration Data */
+#define TAG_EMPTY 0xFE /* Tag for Empty Data Field in Calibration Data */
+
+#define TLV_CHECKSUM_ 0x10C0 /* TLV CHECK SUM */
+sfrw(TLV_CHECKSUM, TLV_CHECKSUM_);
+#define TLV_DCO_30_TAG_ 0x10F6 /* TLV TAG_DCO30 TAG */
+sfrb(TLV_DCO_30_TAG, TLV_DCO_30_TAG_);
+#define TLV_DCO_30_LEN_ 0x10F7 /* TLV TAG_DCO30 LEN */
+sfrb(TLV_DCO_30_LEN, TLV_DCO_30_LEN_);
+#define TLV_ADC12_1_TAG_ 0x10DA /* TLV ADC12_1 TAG */
+sfrb(TLV_ADC12_1_TAG, TLV_ADC12_1_TAG_);
+#define TLV_ADC12_1_LEN_ 0x10DB /* TLV ADC12_1 LEN */
+sfrb(TLV_ADC12_1_LEN, TLV_ADC12_1_LEN_);
+
+#define CAL_ADC_25T85 0x0007 /* Index for 2.5V/85Deg Cal. Value */
+#define CAL_ADC_25T30 0x0006 /* Index for 2.5V/30Deg Cal. Value */
+#define CAL_ADC_25VREF_FACTOR 0x0005 /* Index for 2.5V Ref. Factor */
+#define CAL_ADC_15T85 0x0004 /* Index for 1.5V/85Deg Cal. Value */
+#define CAL_ADC_15T30 0x0003 /* Index for 1.5V/30Deg Cal. Value */
+#define CAL_ADC_15VREF_FACTOR 0x0002 /* Index for ADC 1.5V Ref. Factor */
+#define CAL_ADC_OFFSET 0x0001 /* Index for ADC Offset */
+#define CAL_ADC_GAIN_FACTOR 0x0000 /* Index for ADC Gain Factor */
+
+#define CALDCO_16MHZ_ 0x10F8 /* DCOCTL Calibration Data for 16MHz */
+sfrb(CALDCO_16MHZ, CALDCO_16MHZ_);
+#define CALBC1_16MHZ_ 0x10F9 /* BCSCTL1 Calibration Data for 16MHz */
+sfrb(CALBC1_16MHZ, CALBC1_16MHZ_);
+#define CALDCO_12MHZ_ 0x10FA /* DCOCTL Calibration Data for 12MHz */
+sfrb(CALDCO_12MHZ, CALDCO_12MHZ_);
+#define CALBC1_12MHZ_ 0x10FB /* BCSCTL1 Calibration Data for 12MHz */
+sfrb(CALBC1_12MHZ, CALBC1_12MHZ_);
+#define CALDCO_8MHZ_ 0x10FC /* DCOCTL Calibration Data for 8MHz */
+sfrb(CALDCO_8MHZ, CALDCO_8MHZ_);
+#define CALBC1_8MHZ_ 0x10FD /* BCSCTL1 Calibration Data for 8MHz */
+sfrb(CALBC1_8MHZ, CALBC1_8MHZ_);
+#define CALDCO_1MHZ_ 0x10FE /* DCOCTL Calibration Data for 1MHz */
+sfrb(CALDCO_1MHZ, CALDCO_1MHZ_);
+#define CALBC1_1MHZ_ 0x10FF /* BCSCTL1 Calibration Data for 1MHz */
+sfrb(CALBC1_1MHZ, CALBC1_1MHZ_);
+
+#define CAL_DCO_16MHZ 0x0000 /* Index for DCOCTL Calibration Data for 16MHz */
+#define CAL_BC1_16MHZ 0x0001 /* Index for BCSCTL1 Calibration Data for 16MHz */
+#define CAL_DCO_12MHZ 0x0002 /* Index for DCOCTL Calibration Data for 12MHz */
+#define CAL_BC1_12MHZ 0x0003 /* Index for BCSCTL1 Calibration Data for 12MHz */
+#define CAL_DCO_8MHZ 0x0004 /* Index for DCOCTL Calibration Data for 8MHz */
+#define CAL_BC1_8MHZ 0x0005 /* Index for BCSCTL1 Calibration Data for 8MHz */
+#define CAL_DCO_1MHZ 0x0006 /* Index for DCOCTL Calibration Data for 1MHz */
+#define CAL_BC1_1MHZ 0x0007 /* Index for BCSCTL1 Calibration Data for 1MHz */
+
+#ifndef __ASSEMBLER__
+/* Structured declaration */
+typedef enum
+{
+ DCO_30_TAG = 0x01,
+ ADC12_1_TAG = 0x10,
+ EMPTY_TAG = 0xFE,
+
+} tlv_tags_t;
+
+typedef struct
+{
+ unsigned char tag;
+ unsigned char length;
+ struct
+ {
+ unsigned char DCO_16MHZ;
+ unsigned char BC1_16MHZ;
+ unsigned char DCO_12MHZ;
+ unsigned char BC1_12MHZ;
+ unsigned char DCO_8MHZ;
+ unsigned char BC1_8MHZ;
+ unsigned char DCO_1MHZ;
+ unsigned char BC1_1MHZ;
+ } value;
+} const dco_30_tag_t;
+
+typedef struct
+{
+ unsigned char tag;
+ unsigned char length;
+ struct
+ {
+ unsigned int ADC_GAIN_FACTOR;
+ unsigned int ADC_OFFSET;
+ unsigned int ADC_15VREF_FACTOR;
+ unsigned int ADC_15T30;
+ unsigned int ADC_15T85;
+ unsigned int ADC_25VREF_FACTOR;
+ unsigned int ADC_25T30;
+ unsigned int ADC_25T85;
+ } value;
+} const adc12_1_tag_t;
+
+typedef struct
+{
+ unsigned char tag;
+ unsigned char length;
+} const empty_tag_t;
+
+struct
+{
+ unsigned int checksum;
+ empty_tag_t empty;
+ unsigned int dummy[11];
+ adc12_1_tag_t adc12_1;
+ dco_30_tag_t dco_30;
+} const volatile TLV_bits asm("0x10c0");
+#endif // __ASSEMBLER__
+
+#endif /* __msp430_headers_tlv_h */
--- /dev/null
+#ifndef __MSP430_HEADERS_UNIFIED_CLOCK_SYSTEM_H
+#define __MSP430_HEADERS_UNIFIED_CLOCK_SYSTEM_H
+
+/* unified_clock_system.h
+ *
+ * mspgcc project: MSP430 device headers
+ * UNIFIED_CLOCK_SYSTEM module header
+ *
+ * (c) 2002 by S. Balling <praktikum@innoventis.de>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * 2009-10-08 - modifications by J.M.Gross <mspgcc@grossibaer.de>
+ * - define registers relative to base address
+ * - added some 54xx series specific defines and comments
+ *
+ * $Id: unified_clock_system.h,v 1.1 2009/06/04 21:55:18 cliechti Exp $
+ */
+
+/* Switches:
+__MSP430_HAS_UCS__
+__MSP430_UCS_BASE__ - base address of UCS module
+
+*/
+
+#if defined(__MSP430_UCS_BASE__)
+
+#define UCSCTL0_ __MSP430_UCS_BASE__ + 0x00
+sfrw (UCSCTL0,UCSCTL0_);
+#define UCSCTL0_L_ __MSP430_UCS_BASE__ + 0x00
+sfrb (UCSCTL0_L,UCSCTL0_L_);
+#define UCSCTL0_H_ __MSP430_UCS_BASE__ + 0x01
+sfrb (UCSCTL0_H,UCSCTL0_H_);
+#define UCSCTL1_ __MSP430_UCS_BASE__ + 0x02
+sfrw (UCSCTL1,UCSCTL1_);
+#define UCSCTL1_ __MSP430_UCS_BASE__ + 0x02
+sfrw (UCSCTL1,UCSCTL1_);
+#define UCSCTL1_L_ __MSP430_UCS_BASE__ + 0x02
+sfrb (UCSCTL1_L,UCSCTL1_L_);
+#define UCSCTL1_H_ __MSP430_UCS_BASE__ + 0x03
+sfrb (UCSCTL1_H,UCSCTL1_H_);
+#define UCSCTL2_ __MSP430_UCS_BASE__ + 0x04
+sfrw (UCSCTL2,UCSCTL2_);
+#define UCSCTL2_L_ __MSP430_UCS_BASE__ + 0x04
+sfrb (UCSCTL2_L,UCSCTL2_L_);
+#define UCSCTL2_H_ __MSP430_UCS_BASE__ + 0x05
+sfrb (UCSCTL2_H,UCSCTL2_H_);
+#define UCSCTL3_ __MSP430_UCS_BASE__ + 0x06
+sfrw (UCSCTL3,UCSCTL3_);
+#define UCSCTL3_L_ __MSP430_UCS_BASE__ + 0x06
+sfrb (UCSCTL3_L,UCSCTL3_L_);
+#define UCSCTL3_H_ __MSP430_UCS_BASE__ + 0x07
+sfrb (UCSCTL3_H,UCSCTL3_H_);
+#define UCSCTL4_ __MSP430_UCS_BASE__ + 0x08
+sfrw (UCSCTL4,UCSCTL4_);
+#define UCSCTL4_L_ __MSP430_UCS_BASE__ + 0x08
+sfrb (UCSCTL4_L,UCSCTL4_L_);
+#define UCSCTL4_H_ __MSP430_UCS_BASE__ + 0x09
+sfrb (UCSCTL4_H,UCSCTL4_H_);
+#define UCSCTL5_ __MSP430_UCS_BASE__ + 0x0A
+sfrw (UCSCTL5,UCSCTL5_);
+#define UCSCTL5_L_ __MSP430_UCS_BASE__ + 0x0A
+sfrb (UCSCTL5_L,UCSCTL5_L_);
+#define UCSCTL5_H_ __MSP430_UCS_BASE__ + 0x0B
+sfrb (UCSCTL5_H,UCSCTL5_H_);
+#define UCSCTL6_ __MSP430_UCS_BASE__ + 0x0C
+sfrw (UCSCTL6,UCSCTL6_);
+#define UCSCTL6_L_ __MSP430_UCS_BASE__ + 0x0C
+sfrb (UCSCTL6_L,UCSCTL6_L_);
+#define UCSCTL6_H_ __MSP430_UCS_BASE__ + 0x0D
+sfrb (UCSCTL6_H,UCSCTL6_H_);
+#define UCSCTL7_ __MSP430_UCS_BASE__ + 0x0E
+sfrw (UCSCTL7,UCSCTL7_);
+#define UCSCTL7_L_ __MSP430_UCS_BASE__ + 0x0E
+sfrb (UCSCTL7_L,UCSCTL7_L_);
+#define UCSCTL7_H_ __MSP430_UCS_BASE__ + 0x0F
+sfrb (UCSCTL7_H,UCSCTL7_H_);
+#define UCSCTL8_ __MSP430_UCS_BASE__ + 0x10
+sfrw (UCSCTL8,UCSCTL8_);
+#define UCSCTL8_L_ __MSP430_UCS_BASE__ + 0x10
+sfrb (UCSCTL8_L,UCSCTL8_L_);
+#define UCSCTL8_H_ __MSP430_UCS_BASE__ + 0x10
+sfrb (UCSCTL8_H,UCSCTL8_H_);
+
+/* UCSCTL0 Control Bits */
+//#define RESERVED (0x0001) /* RESERVED */
+//#define RESERVED (0x0002) /* RESERVED */
+//#define RESERVED (0x0004) /* RESERVED */
+#define MOD0 (0x0008) /* Modulation Bit Counter Bit : 0 */
+#define MOD1 (0x0010) /* Modulation Bit Counter Bit : 1 */
+#define MOD2 (0x0020) /* Modulation Bit Counter Bit : 2 */
+#define MOD3 (0x0040) /* Modulation Bit Counter Bit : 3 */
+#define MOD4 (0x0080) /* Modulation Bit Counter Bit : 4 */
+#define DCO0 (0x0100) /* DCO TAP Bit : 0 */
+#define DCO1 (0x0200) /* DCO TAP Bit : 1 */
+#define DCO2 (0x0400) /* DCO TAP Bit : 2 */
+#define DCO3 (0x0800) /* DCO TAP Bit : 3 */
+#define DCO4 (0x1000) /* DCO TAP Bit : 4 */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL0 Control Bits */
+//#define RESERVED (0x0001) /* RESERVED */
+//#define RESERVED (0x0002) /* RESERVED */
+//#define RESERVED (0x0004) /* RESERVED */
+#define MOD0_L (0x0008) /* Modulation Bit Counter Bit : 0 */
+#define MOD1_L (0x0010) /* Modulation Bit Counter Bit : 1 */
+#define MOD2_L (0x0020) /* Modulation Bit Counter Bit : 2 */
+#define MOD3_L (0x0040) /* Modulation Bit Counter Bit : 3 */
+#define MOD4_L (0x0080) /* Modulation Bit Counter Bit : 4 */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL0 Control Bits */
+//#define RESERVED (0x0001) /* RESERVED */
+//#define RESERVED (0x0002) /* RESERVED */
+//#define RESERVED (0x0004) /* RESERVED */
+#define DCO0_H (0x0001) /* DCO TAP Bit : 0 */
+#define DCO1_H (0x0002) /* DCO TAP Bit : 1 */
+#define DCO2_H (0x0004) /* DCO TAP Bit : 2 */
+#define DCO3_H (0x0008) /* DCO TAP Bit : 3 */
+#define DCO4_H (0x0010) /* DCO TAP Bit : 4 */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL1 Control Bits */
+#define DISMOD (0x0001) /* Disable Modulation */
+#define DCOR (0x0002) /* DCO External Resistor Select */
+//#define RESERVED (0x0004) /* RESERVED */
+//#define RESERVED (0x0008) /* RESERVED */
+#define DCORSEL0 (0x0010) /* DCO Freq. Range Select Bit : 0 */
+#define DCORSEL1 (0x0020) /* DCO Freq. Range Select Bit : 1 */
+#define DCORSEL2 (0x0040) /* DCO Freq. Range Select Bit : 2 */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0100) /* RESERVED */
+//#define RESERVED (0x0200) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL1 Control Bits */
+#define DISMOD_L (0x0001) /* Disable Modulation */
+#define DCOR_L (0x0002) /* DCO External Resistor Select */
+//#define RESERVED (0x0004) /* RESERVED */
+//#define RESERVED (0x0008) /* RESERVED */
+#define DCORSEL0_L (0x0010) /* DCO Freq. Range Select Bit : 0 */
+#define DCORSEL1_L (0x0020) /* DCO Freq. Range Select Bit : 1 */
+#define DCORSEL2_L (0x0040) /* DCO Freq. Range Select Bit : 2 */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0100) /* RESERVED */
+//#define RESERVED (0x0200) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL1 Control Bits */
+//#define RESERVED (0x0004) /* RESERVED */
+//#define RESERVED (0x0008) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0100) /* RESERVED */
+//#define RESERVED (0x0200) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+#define DCORSEL_0 (0x0000) /* DCO RSEL 0 */
+#define DCORSEL_1 (0x0010) /* DCO RSEL 1 */
+#define DCORSEL_2 (0x0020) /* DCO RSEL 2 */
+#define DCORSEL_3 (0x0030) /* DCO RSEL 3 */
+#define DCORSEL_4 (0x0040) /* DCO RSEL 4 */
+#define DCORSEL_5 (0x0050) /* DCO RSEL 5 */
+#define DCORSEL_6 (0x0060) /* DCO RSEL 6 */
+#define DCORSEL_7 (0x0070) /* DCO RSEL 7 */
+
+/* UCSCTL2 Control Bits */
+#define FLLN0 (0x0001) /* FLL Multipier Bit : 0 */
+#define FLLN1 (0x0002) /* FLL Multipier Bit : 1 */
+#define FLLN2 (0x0004) /* FLL Multipier Bit : 2 */
+#define FLLN3 (0x0008) /* FLL Multipier Bit : 3 */
+#define FLLN4 (0x0010) /* FLL Multipier Bit : 4 */
+#define FLLN5 (0x0020) /* FLL Multipier Bit : 5 */
+#define FLLN6 (0x0040) /* FLL Multipier Bit : 6 */
+#define FLLN7 (0x0080) /* FLL Multipier Bit : 7 */
+#define FLLN8 (0x0100) /* FLL Multipier Bit : 8 */
+#define FLLN9 (0x0200) /* FLL Multipier Bit : 9 */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+#define FLLD0 (0x1000) /* Loop Divider Bit : 0 */
+#define FLLD1 (0x2000) /* Loop Divider Bit : 1 */
+#define FLLD2 (0x4000) /* Loop Divider Bit : 1 */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL2 Control Bits */
+#define FLLN0_L (0x0001) /* FLL Multipier Bit : 0 */
+#define FLLN1_L (0x0002) /* FLL Multipier Bit : 1 */
+#define FLLN2_L (0x0004) /* FLL Multipier Bit : 2 */
+#define FLLN3_L (0x0008) /* FLL Multipier Bit : 3 */
+#define FLLN4_L (0x0010) /* FLL Multipier Bit : 4 */
+#define FLLN5_L (0x0020) /* FLL Multipier Bit : 5 */
+#define FLLN6_L (0x0040) /* FLL Multipier Bit : 6 */
+#define FLLN7_L (0x0080) /* FLL Multipier Bit : 7 */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL2 Control Bits */
+#define FLLN8_H (0x0001) /* FLL Multipier Bit : 8 */
+#define FLLN9_H (0x0002) /* FLL Multipier Bit : 9 */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+#define FLLD0_H (0x0010) /* Loop Divider Bit : 0 */
+#define FLLD1_H (0x0020) /* Loop Divider Bit : 1 */
+#define FLLD2_H (0x0040) /* Loop Divider Bit : 1 */
+//#define RESERVED (0x8000) /* RESERVED */
+
+#define FLLD_0 (0x0000) /* Multiply Selected Loop Freq. 1 */
+#define FLLD_1 (0x1000) /* Multiply Selected Loop Freq. 2 */
+#define FLLD_2 (0x2000) /* Multiply Selected Loop Freq. 4 */
+#define FLLD_3 (0x3000) /* Multiply Selected Loop Freq. 8 */
+#define FLLD_4 (0x4000) /* Multiply Selected Loop Freq. 16 */
+#define FLLD_5 (0x5000) /* Multiply Selected Loop Freq. 32 */
+#define FLLD_6 (0x6000) /* Multiply Selected Loop Freq. 32 */
+#define FLLD_7 (0x7000) /* Multiply Selected Loop Freq. 32 */
+#define FLLD__1 (0x0000) /* Multiply Selected Loop Freq. By 1 */
+#define FLLD__2 (0x1000) /* Multiply Selected Loop Freq. By 2 */
+#define FLLD__4 (0x2000) /* Multiply Selected Loop Freq. By 4 */
+#define FLLD__8 (0x3000) /* Multiply Selected Loop Freq. By 8 */
+#define FLLD__16 (0x4000) /* Multiply Selected Loop Freq. By 16 */
+#define FLLD__32 (0x5000) /* Multiply Selected Loop Freq. By 32 */
+
+/* UCSCTL3 Control Bits */
+#define FLLREFDIV0 (0x0001) /* Reference Divider Bit : 0 */
+#define FLLREFDIV1 (0x0002) /* Reference Divider Bit : 1 */
+#define FLLREFDIV2 (0x0004) /* Reference Divider Bit : 2 */
+//#define RESERVED (0x0008) /* RESERVED */
+#define SELREF0 (0x0010) /* FLL Reference Clock Select Bit : 0 */
+#define SELREF1 (0x0020) /* FLL Reference Clock Select Bit : 1 */
+#define SELREF2 (0x0040) /* FLL Reference Clock Select Bit : 2 */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0100) /* RESERVED */
+//#define RESERVED (0x0200) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL3 Control Bits */
+#define FLLREFDIV0_L (0x0001) /* Reference Divider Bit : 0 */
+#define FLLREFDIV1_L (0x0002) /* Reference Divider Bit : 1 */
+#define FLLREFDIV2_L (0x0004) /* Reference Divider Bit : 2 */
+//#define RESERVED (0x0008) /* RESERVED */
+#define SELREF0_L (0x0010) /* FLL Reference Clock Select Bit : 0 */
+#define SELREF1_L (0x0020) /* FLL Reference Clock Select Bit : 1 */
+#define SELREF2_L (0x0040) /* FLL Reference Clock Select Bit : 2 */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0100) /* RESERVED */
+//#define RESERVED (0x0200) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL3 Control Bits */
+//#define RESERVED (0x0008) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0100) /* RESERVED */
+//#define RESERVED (0x0200) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+#define FLLREFDIV_0 (0x0000) /* Reference Divider: f(LFCLK)/1 */
+#define FLLREFDIV_1 (0x0001) /* Reference Divider: f(LFCLK)/2 */
+#define FLLREFDIV_2 (0x0002) /* Reference Divider: f(LFCLK)/4 */
+#define FLLREFDIV_3 (0x0003) /* Reference Divider: f(LFCLK)/8 */
+#define FLLREFDIV_4 (0x0004) /* Reference Divider: f(LFCLK)/12 */
+#define FLLREFDIV_5 (0x0005) /* Reference Divider: f(LFCLK)/16 */
+#define FLLREFDIV_6 (0x0006) /* Reference Divider: f(LFCLK)/16 */
+#define FLLREFDIV_7 (0x0007) /* Reference Divider: f(LFCLK)/16 */
+#define FLLREFDIV__1 (0x0000) /* Reference Divider: f(LFCLK)/1 */
+#define FLLREFDIV__2 (0x0001) /* Reference Divider: f(LFCLK)/2 */
+#define FLLREFDIV__4 (0x0002) /* Reference Divider: f(LFCLK)/4 */
+#define FLLREFDIV__8 (0x0003) /* Reference Divider: f(LFCLK)/8 */
+#define FLLREFDIV__12 (0x0004) /* Reference Divider: f(LFCLK)/12 */
+#define FLLREFDIV__16 (0x0005) /* Reference Divider: f(LFCLK)/16 */
+#define SELREF_0 (0x0000) /* FLL Reference Clock Select 0 */
+#define SELREF_1 (0x0010) /* FLL Reference Clock Select 1 */
+#define SELREF_2 (0x0020) /* FLL Reference Clock Select 2 */
+#define SELREF_3 (0x0030) /* FLL Reference Clock Select 3 */
+#define SELREF_4 (0x0040) /* FLL Reference Clock Select 4 */
+#define SELREF_5 (0x0050) /* FLL Reference Clock Select 5 */
+#define SELREF_6 (0x0060) /* FLL Reference Clock Select 6 */
+#define SELREF_7 (0x0070) /* FLL Reference Clock Select 7 */
+#define SELREF__XT1CLK (0x0000) /* Multiply Selected Loop Freq. By XT1CLK */
+#define SELREF__VLOCLK (0x0010) /* Multiply Selected Loop Freq. By VLOCLK */
+#define SELREF__REFOCLK (0x0020) /* Multiply Selected Loop Freq. By REFOCLK */
+#define SELREF__XT2CLK (0x0050) /* Multiply Selected Loop Freq. By XT2CLK */
+
+/* UCSCTL4 Control Bits */
+#define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */
+#define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */
+#define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */
+//#define RESERVED (0x0008) /* RESERVED */
+#define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */
+#define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */
+#define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */
+//#define RESERVED (0x0080) /* RESERVED */
+#define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */
+#define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */
+#define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL4 Control Bits */
+#define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */
+#define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */
+#define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */
+//#define RESERVED (0x0008) /* RESERVED */
+#define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */
+#define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */
+#define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL4 Control Bits */
+//#define RESERVED (0x0008) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+#define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */
+#define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */
+#define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+#define SELM_0 (0x0000) /* MCLK Source Select 0 */
+#define SELM_1 (0x0001) /* MCLK Source Select 1 */
+#define SELM_2 (0x0002) /* MCLK Source Select 2 */
+#define SELM_3 (0x0003) /* MCLK Source Select 3 */
+#define SELM_4 (0x0004) /* MCLK Source Select 4 */
+#define SELM_5 (0x0005) /* MCLK Source Select 5 */
+#define SELM_6 (0x0006) /* MCLK Source Select 6 */
+#define SELM_7 (0x0007) /* MCLK Source Select 7 */
+#define SELM__XT1CLK (0x0000) /* MCLK Source Select XT1CLK */
+#define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */
+#define SELM__REFOCLK (0x0002) /* MCLK Source Select REFOCLK */
+#define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */
+#define SELM__DCOCLKDIV (0x0004) /* MCLK Source Select DCOCLKDIV */
+#define SELM__XT2CLK (0x0005) /* MCLK Source Select XT2CLK */
+
+#define SELS_0 (0x0000) /* SMCLK Source Select 0 */
+#define SELS_1 (0x0010) /* SMCLK Source Select 1 */
+#define SELS_2 (0x0020) /* SMCLK Source Select 2 */
+#define SELS_3 (0x0030) /* SMCLK Source Select 3 */
+#define SELS_4 (0x0040) /* SMCLK Source Select 4 */
+#define SELS_5 (0x0050) /* SMCLK Source Select 5 */
+#define SELS_6 (0x0060) /* SMCLK Source Select 6 */
+#define SELS_7 (0x0070) /* SMCLK Source Select 7 */
+#define SELS__XT1CLK (0x0000) /* SMCLK Source Select XT1CLK */
+#define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */
+#define SELS__REFOCLK (0x0020) /* SMCLK Source Select REFOCLK */
+#define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */
+#define SELS__DCOCLKDIV (0x0040) /* SMCLK Source Select DCOCLKDIV */
+#define SELS__XT2CLK (0x0050) /* SMCLK Source Select XT2CLK */
+
+#define SELA_0 (0x0000) /* ACLK Source Select 0 */
+#define SELA_1 (0x0100) /* ACLK Source Select 1 */
+#define SELA_2 (0x0200) /* ACLK Source Select 2 */
+#define SELA_3 (0x0300) /* ACLK Source Select 3 */
+#define SELA_4 (0x0400) /* ACLK Source Select 4 */
+#define SELA_5 (0x0500) /* ACLK Source Select 5 */
+#define SELA_6 (0x0600) /* ACLK Source Select 6 */
+#define SELA_7 (0x0700) /* ACLK Source Select 7 */
+#define SELA__XT1CLK (0x0000) /* ACLK Source Select XT1CLK */
+#define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */
+#define SELA__REFOCLK (0x0200) /* ACLK Source Select REFOCLK */
+#define SELA__DCOCLK (0x0300) /* ACLK Source Select DCOCLK */
+#define SELA__DCOCLKDIV (0x0400) /* ACLK Source Select DCOCLKDIV */
+#define SELA__XT2CLK (0x0500) /* ACLK Source Select XT2CLK */
+
+/* UCSCTL5 Control Bits */
+#define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */
+#define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */
+#define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */
+//#define RESERVED (0x0008) /* RESERVED */
+#define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */
+#define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */
+#define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */
+//#define RESERVED (0x0080) /* RESERVED */
+#define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */
+#define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */
+#define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */
+//#define RESERVED (0x0800) /* RESERVED */
+#define DIVPA0 (0x1000) /* ACLK from Pin Divider Bit: 0 */
+#define DIVPA1 (0x2000) /* ACLK from Pin Divider Bit: 1 */
+#define DIVPA2 (0x4000) /* ACLK from Pin Divider Bit: 2 */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL5 Control Bits */
+#define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */
+#define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */
+#define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */
+//#define RESERVED (0x0008) /* RESERVED */
+#define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */
+#define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */
+#define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL5 Control Bits */
+//#define RESERVED (0x0008) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+#define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */
+#define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */
+#define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */
+//#define RESERVED (0x0800) /* RESERVED */
+#define DIVPA0_H (0x0010) /* ACLK from Pin Divider Bit: 0 */
+#define DIVPA1_H (0x0020) /* ACLK from Pin Divider Bit: 1 */
+#define DIVPA2_H (0x0040) /* ACLK from Pin Divider Bit: 2 */
+//#define RESERVED (0x8000) /* RESERVED */
+
+#define DIVM_0 (0x0000) /* MCLK Source Divider 0 */
+#define DIVM_1 (0x0001) /* MCLK Source Divider 1 */
+#define DIVM_2 (0x0002) /* MCLK Source Divider 2 */
+#define DIVM_3 (0x0003) /* MCLK Source Divider 3 */
+#define DIVM_4 (0x0004) /* MCLK Source Divider 4 */
+#define DIVM_5 (0x0005) /* MCLK Source Divider 5 */
+#define DIVM_6 (0x0006) /* MCLK Source Divider 6 */
+#define DIVM_7 (0x0007) /* MCLK Source Divider 7 */
+#define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */
+#define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */
+#define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */
+#define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */
+#define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */
+#define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */
+
+#define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */
+#define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */
+#define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */
+#define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */
+#define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */
+#define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */
+#define DIVS_6 (0x0060) /* SMCLK Source Divider 6 */
+#define DIVS_7 (0x0070) /* SMCLK Source Divider 7 */
+#define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */
+#define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */
+#define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */
+#define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */
+#define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */
+#define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */
+
+#define DIVA_0 (0x0000) /* ACLK Source Divider 0 */
+#define DIVA_1 (0x0100) /* ACLK Source Divider 1 */
+#define DIVA_2 (0x0200) /* ACLK Source Divider 2 */
+#define DIVA_3 (0x0300) /* ACLK Source Divider 3 */
+#define DIVA_4 (0x0400) /* ACLK Source Divider 4 */
+#define DIVA_5 (0x0500) /* ACLK Source Divider 5 */
+#define DIVA_6 (0x0600) /* ACLK Source Divider 6 */
+#define DIVA_7 (0x0700) /* ACLK Source Divider 7 */
+#define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */
+#define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */
+#define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */
+#define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */
+#define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */
+#define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */
+
+#define DIVPA_0 (0x0000) /* ACLK from Pin Source Divider 0 */
+#define DIVPA_1 (0x1000) /* ACLK from Pin Source Divider 1 */
+#define DIVPA_2 (0x2000) /* ACLK from Pin Source Divider 2 */
+#define DIVPA_3 (0x3000) /* ACLK from Pin Source Divider 3 */
+#define DIVPA_4 (0x4000) /* ACLK from Pin Source Divider 4 */
+#define DIVPA_5 (0x5000) /* ACLK from Pin Source Divider 5 */
+#define DIVPA_6 (0x6000) /* ACLK from Pin Source Divider 6 */
+#define DIVPA_7 (0x7000) /* ACLK from Pin Source Divider 7 */
+#define DIVPA__1 (0x0000) /* ACLK from Pin Source Divider f(ACLK)/1 */
+#define DIVPA__2 (0x1000) /* ACLK from Pin Source Divider f(ACLK)/2 */
+#define DIVPA__4 (0x2000) /* ACLK from Pin Source Divider f(ACLK)/4 */
+#define DIVPA__8 (0x3000) /* ACLK from Pin Source Divider f(ACLK)/8 */
+#define DIVPA__16 (0x4000) /* ACLK from Pin Source Divider f(ACLK)/16 */
+#define DIVPA__32 (0x5000) /* ACLK from Pin Source Divider f(ACLK)/32 */
+
+/* UCSCTL6 Control Bits */
+#define XT1OFF (0x0001) /* High Frequency Oscillator 1 (XT1) disable */
+#define SMCLKOFF (0x0002) /* SMCLK Off */
+#define XCAP0 (0x0004) /* XIN/XOUT Cap Bit: 0 */
+#define XCAP1 (0x0008) /* XIN/XOUT Cap Bit: 1 */
+#define XT1BYPASS (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
+#define XTS (0x0020) /* 1: Selects high-freq. oscillator */
+#define XT1DRIVE0 (0x0040) /* XT1 Drive Level mode Bit 0 */
+#define XT1DRIVE1 (0x0080) /* XT1 Drive Level mode Bit 1 */
+#define XT2OFF (0x0100) /* High Frequency Oscillator 2 (XT2) disable */
+//#define RESERVED (0x0200) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+#define XT2BYPASS (0x1000) /* XT2 bypass mode : 0: internal 1:sourced from external pin */
+//#define RESERVED (0x2000) /* RESERVED */
+#define XT2DRIVE0 (0x4000) /* XT2 Drive Level mode Bit 0 */
+#define XT2DRIVE1 (0x8000) /* XT2 Drive Level mode Bit 1 */
+
+/* UCSCTL6 Control Bits */
+#define XT1OFF_L (0x0001) /* High Frequency Oscillator 1 (XT1) disable */
+#define SMCLKOFF_L (0x0002) /* SMCLK Off */
+#define XCAP0_L (0x0004) /* XIN/XOUT Cap Bit: 0 */
+#define XCAP1_L (0x0008) /* XIN/XOUT Cap Bit: 1 */
+#define XT1BYPASS_L (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
+#define XTS_L (0x0020) /* 1: Selects high-freq. oscillator */
+#define XT1DRIVE0_L (0x0040) /* XT1 Drive Level mode Bit 0 */
+#define XT1DRIVE1_L (0x0080) /* XT1 Drive Level mode Bit 1 */
+//#define RESERVED (0x0200) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+
+/* UCSCTL6 Control Bits */
+#define XT2OFF_H (0x0001) /* High Frequency Oscillator 2 (XT2) disable */
+//#define RESERVED (0x0200) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+#define XT2BYPASS_H (0x0010) /* XT2 bypass mode : 0: internal 1:sourced from external pin */
+//#define RESERVED (0x2000) /* RESERVED */
+#define XT2DRIVE0_H (0x0040) /* XT2 Drive Level mode Bit 0 */
+#define XT2DRIVE1_H (0x0080) /* XT2 Drive Level mode Bit 1 */
+
+#define XCAP_0 (0x0000) /* XIN/XOUT Cap 0 */
+#define XCAP_1 (0x0004) /* XIN/XOUT Cap 1 */
+#define XCAP_2 (0x0008) /* XIN/XOUT Cap 2 */
+#define XCAP_3 (0x000C) /* XIN/XOUT Cap 3 */
+#define XT1DRIVE_0 (0x0000) /* XT1 Drive Level mode: 0 */
+#define XT1DRIVE_1 (0x0040) /* XT1 Drive Level mode: 1 */
+#define XT1DRIVE_2 (0x0080) /* XT1 Drive Level mode: 2 */
+#define XT1DRIVE_3 (0x00C0) /* XT1 Drive Level mode: 3 */
+#define XT2DRIVE_0 (0x0000) /* XT2 Drive Level mode: 0 */
+#define XT2DRIVE_1 (0x4000) /* XT2 Drive Level mode: 1 */
+#define XT2DRIVE_2 (0x8000) /* XT2 Drive Level mode: 2 */
+#define XT2DRIVE_3 (0xC000) /* XT2 Drive Level mode: 3 */
+
+/* UCSCTL7 Control Bits */
+#define DCOFFG (0x0001) /* DCO Fault Flag */
+#define XT1LFOFFG (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */
+#define XT1HFOFFG (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */
+#define XT2OFFG (0x0008) /* High Frequency Oscillator 2 Fault Flag */
+#define FLLULIFG (0x0010) /* FLL Unlock Interrupt Flag (not on 54xx) */
+//#define RESERVED (0x0020) /* RESERVED */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+#define FLLUNLOCK0 (0x0100) /* FLL Unlock Bit 0 (not on 54xx) */
+#define FLLUNLOCK1 (0x0200) /* FLL Unlock Bit 1 (not on 54xx) */
+#define FLLUNLOCKHIS0 (0x0400) /* FLL Unlock History Bit 0 (not on 54xx) */
+#define FLLUNLOCKHIS1 (0x08000) /* FLL Unlock History Bit 1 (not on 54xx) */
+#define FLLULIE (0x01000) /* FLL Unlock Interrupt Enable (not on 54xx) */
+#define FLLWARNEN (0x02000) /* FLL Warning Enable (not on 54xx) */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL7 Control Bits */
+#define DCOFFG_L (0x0001) /* DCO Fault Flag */
+#define XT1LFOFFG_L (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */
+#define XT1HFOFFG_L (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */
+#define XT2OFFG_L (0x0008) /* High Frequency Oscillator 2 Fault Flag */
+#define FLLULIFG_L (0x0010) /* FLL Unlock Interrupt Flag (not on 54xx)*/
+//#define RESERVED (0x0020) /* RESERVED */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL7 Control Bits */
+//#define RESERVED (0x0020) /* RESERVED */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+#define FLLUNLOCK0_H (0x0001) /* FLL Unlock Bit 0 (not on 54xx) */
+#define FLLUNLOCK1_H (0x0002) /* FLL Unlock Bit 1 (not on 54xx) */
+#define FLLUNLOCKHIS0_H (0x0004) /* FLL Unlock History Bit 0 (not on 54xx) */
+#define FLLUNLOCKHIS1_H (0x0080) /* FLL Unlock History Bit 1 (not on 54xx) */
+#define FLLULIE_H (0x0010) /* FLL Unlock Interrupt Enable (not on 54xx) */
+#define FLLWARNEN_H (0x0020) /* FLL Warning Enable (not on 54xx) */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL8 Control Bits */
+#define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */
+#define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */
+#define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */
+#define MODOSCREQEN (0x0008) /* MODOSC Clock Request Enable */
+#define IFCLKSEN (0x0010) /* Enable Interface Clock slow down mechanism (not on 54xx) */
+//#define RESERVED (0x0020) /* RESERVED */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+#define SMCLK_FSEN (0x0100) /* Enable fail safe enable for SMCLK source (not on 54xx)*/
+#define ACLK_FSEN (0x0200) /* Enable fail safe enable for ACLK source (not on 54xx)*/
+#define MASKREQEN (0x0700) /* always REQUIRED on 54xx devices when writing to UCSCTL8*/
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL8 Control Bits */
+#define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */
+#define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */
+#define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */
+#define MODOSCREQEN_L (0x0008) /* MODOSC Clock Request Enable */
+#define IFCLKSEN_L (0x0010) /* Enable Interface Clock slow down mechanism (not on 54xx)*/
+//#define RESERVED (0x0020) /* RESERVED */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL8 Control Bits */
+//#define RESERVED (0x0020) /* RESERVED */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+#define SMCLK_FSEN_H (0x0001) /* Enable fail safe enable for SMCLK source (not on 54xx)*/
+#define ACLK_FSEN_H (0x0002) /* Enable fail safe enable for ACLK source (not on 54xx)*/
+#define MASKREQEN_H (0x0007) /* always REQUIRED on 54xx devices when writing to UCSCTL8_H*/
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+#endif
+
+#endif /*__MSP430_HEADERS_UNIFIED_CLOCK_SYSTEM_H */
-#if !defined(__msp430_headers_usci_h__)
-#define __msp430_headers_usci_h__
+#if !defined(__MSP430_HEADERS_USCI_H__)
+#define __MSP430_HEADERS_USCI_H__
-/* usi.h
+/* usci.h
*
* mspgcc project: MSP430 device headers
* USCI module header
* (c) 2006 by Steve Underwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: usci.h,v 1.6 2008/06/18 22:25:52 cliechti Exp $
+ * $Id: usci.h,v 1.7 2009/06/04 21:55:18 cliechti Exp $
*
* 2008-02-05 - modifications by G.Lemm <msp430@daqtix.com>
* - added UC1IE and UC1IFG registers
* - added UC*1*IE and UC*1*IFG bit definitions
+ * 2009-05-19 - modifications by S. Balling <praktikum@innoventis.de>
+ * - added switch for USCI0
+ * 2009-11-17 - modifications by J.M.Gross <mspgcc@grossibaer.de>
+ * - added complete support for USCI5_0..3 (MSP430F54xx family)
+ * - removed old USI bit defines (belong to USI.H, not USCI.H)
*/
/* Switches:
-
-__MSP430_HAS_USCI1__ - if device has USCI1
-
+__MSP430_HAS_USCI0__ - if device has USCI0 (NOT part of family 5)
+__MSP430_HAS_USCI1__ - if device has USCI1 (NOT part of family 5)
+__MSP430_HAS_USCI_A0__ - definition to show module is available
+__MSP430_HAS_USCI_B0__ - definition to show module is available
+__MSP430_USCI5_BASE_0__ - USCI module base address for A0/B0
+__MSP430_HAS_USCI_A1__ - definition to show module is available
+__MSP430_HAS_USCI_B1__ - definition to show module is available
+__MSP430_USCI5_BASE_1__ - USCI module base address for A1/B1
+__MSP430_HAS_USCI_A2__ - definition to show module is available
+__MSP430_HAS_USCI_B2__ - definition to show module is available
+__MSP430_USCI5_BASE_2__ - USCI module base address for A2/B2
+__MSP430_HAS_USCI_A3__ - definition to show module is available
+__MSP430_HAS_USCI_B3__ - definition to show module is available
+__MSP430_USCI5_BASE_3__ - USCI module base address for A3/B3
*/
-#define USIPE7 (0x80) /* USI Port Enable Px.7 */
-#define USIPE6 (0x40) /* USI Port Enable Px.6 */
-#define USIPE5 (0x20) /* USI Port Enable Px.5 */
-#define USILSB (0x10) /* USI LSB first 1:LSB / 0:MSB */
-#define USIMST (0x08) /* USI Master Select 0:Slave / 1:Master */
-#define USIGE (0x04) /* USI General Output Enable Latch */
-#define USIOE (0x02) /* USI Output Enable */
-#define USISWRST (0x01) /* USI Software Reset */
-
-#define USICKPH (0x80) /* USI Sync. Mode: Clock Phase */
-#define USII2C (0x40) /* USI I2C Mode */
-#define USISTTIE (0x20) /* USI START Condition interrupt enable */
-#define USIIE (0x10) /* USI Counter Interrupt enable */
-#define USIAL (0x08) /* USI Arbitration Lost */
-#define USISTP (0x04) /* USI STOP Condition received */
-#define USISTTIFG (0x02) /* USI START Condition interrupt Flag */
-#define USIIFG (0x01) /* USI Counter Interrupt Flag */
-
-#define USIDIV2 (0x80) /* USI Clock Divider 2 */
-#define USIDIV1 (0x40) /* USI Clock Divider 1 */
-#define USIDIV0 (0x20) /* USI Clock Divider 0 */
-#define USISSEL2 (0x10) /* USI Clock Source Select 2 */
-#define USISSEL1 (0x08) /* USI Clock Source Select 1 */
-#define USISSEL0 (0x04) /* USI Clock Source Select 0 */
-#define USICKPL (0x02) /* USI Clock Polarity 0:Inactive=Low / 1:Inactive=High */
-#define USISWCLK (0x01) /* USI Software Clock */
-
-#define USIDIV_0 (0x00) /* USI Clock Divider: 0 */
-#define USIDIV_1 (0x20) /* USI Clock Divider: 1 */
-#define USIDIV_2 (0x40) /* USI Clock Divider: 2 */
-#define USIDIV_3 (0x60) /* USI Clock Divider: 3 */
-#define USIDIV_4 (0x80) /* USI Clock Divider: 4 */
-#define USIDIV_5 (0xA0) /* USI Clock Divider: 5 */
-#define USIDIV_6 (0xC0) /* USI Clock Divider: 6 */
-#define USIDIV_7 (0xE0) /* USI Clock Divider: 7 */
-
-#define USISSEL_0 (0x00) /* USI Clock Source: 0 */
-#define USISSEL_1 (0x04) /* USI Clock Source: 1 */
-#define USISSEL_2 (0x08) /* USI Clock Source: 2 */
-#define USISSEL_3 (0x0C) /* USI Clock Source: 3 */
-#define USISSEL_4 (0x10) /* USI Clock Source: 4 */
-#define USISSEL_5 (0x14) /* USI Clock Source: 5 */
-#define USISSEL_6 (0x18) /* USI Clock Source: 6 */
-#define USISSEL_7 (0x1C) /* USI Clock Source: 7 */
-
-#define USISCLREL (0x80) /* USI SCL Released */
-#define USI16B (0x40) /* USI 16 Bit Shift Register Enable */
-#define USIFGDC (0x20) /* USI Interrupt Flag don't clear */
-#define USICNT4 (0x10) /* USI Bit Count 4 */
-#define USICNT3 (0x08) /* USI Bit Count 3 */
-#define USICNT2 (0x04) /* USI Bit Count 2 */
-#define USICNT1 (0x02) /* USI Bit Count 1 */
-#define USICNT0 (0x01) /* USI Bit Count 0 */
-
-// UART-Mode Bits
+/* Common bits for USCI and USCI5 */
+
+// Control register 0 bits (UCAxCTL0/UCBxCTL0)
#define UCPEN (0x80) /* Async. Mode: Parity enable */
+#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */
+#define UCA10 (0x80) /* I2C Mode: 10-bit Address Mode */
#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */
-#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */
+#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */
+#define UCSLA10 (0x40) /* I2C-Mode:10-bit Slave Address Mode */
+#define UCMSB (0x20) /* Async./Sync. Mode: MSB first 0:LSB / 1:MSB */
+#define UCMM (0x20) /* I2C Mode: Multi-Master Environment */
#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */
+#define UCMST (0x08) /* Sync. Mode/ SPI Mode: Master Select */
#define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */
#define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */
#define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
-// SPI-Mode Bits
-#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */
-#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */
-#define UCMST (0x08) /* Sync. Mode: Master Select */
-
-// I2C-Mode Bits
-#define UCA10 (0x80) /* 10-bit Address Mode */
-#define UCSLA10 (0x40) /* 10-bit Slave Address Mode */
-#define UCMM (0x20) /* Multi-Master Environment */
-//#define res (0x10) /* reserved */
#define UCMODE_0 (0<<1) /* Sync. Mode: USCI Mode: 0 */
#define UCMODE_1 (1<<1) /* Sync. Mode: USCI Mode: 1 */
#define UCMODE_2 (2<<1) /* Sync. Mode: USCI Mode: 2 */
#define UCMODE_3 (3<<1) /* Sync. Mode: USCI Mode: 3 */
-// UART-Mode Bits
+// aliases by MSPGCC (ASYNC mode, UCSYNC=0)
+#define UCMODE_UART (0<<1) /* normal Async mode */
+#define UCMODE_IDLE (1<<1) /* Idle line multiprocessor mode */
+#define UCMODE_ADDRESS (2<<1) /* Address bit multiprocessor mode */
+#define UCMODE_AUTOBAUD (3<<1) /* autobaud Async mode */
+// aliases by MSPGCC (SYNC mode, UCSYNC=1)
+#define UCMODE_SPI3 (0<<1) /* 3-Pin SPI mode */
+#define UCMODE_SPI4H (1<<1) /* 4-Pin SPI mode (STE active high)*/
+#define UCMODE_SPI4L (2<<1) /* 4-Pin SPI mode (STE active low) */
+#define UCMODE_I2C (3<<1) /* I2C mode */
+
+
+// Control register 1 bits (UCAxCTL1/UCBxCTL1)
#define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */
#define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */
-#define UCRXEIE (0x20) /* RX Error interrupt enable */
-#define UCBRKIE (0x10) /* Break interrupt enable */
-#define UCDORM (0x08) /* Dormant (Sleep) Mode */
-#define UCTXADDR (0x04) /* Send next Data as Address */
-#define UCTXBRK (0x02) /* Send next Data as Break */
+#define UCRXEIE (0x20) /* Async. Mode: RX Error interrupt enable */
+#define UCBRKIE (0x10) /* Async. Mode: Break interrupt enable */
+#define UCTR (0x10) /* I2C Mode: Transmit/Receive Select/Flag */
+#define UCDORM (0x08) /* Async. Mode: Dormant (Sleep) Mode */
+#define UCTXNACK (0x08) /* I2C Mode: Transmit NACK */
+#define UCTXADDR (0x04) /* Async. Mode: Send next Data as Address */
+#define UCTXSTP (0x04) /* I2C Mode: Transmit STOP */
+#define UCTXBRK (0x02) /* Async. Mode: Send next Data as Break */
+#define UCTXSTT (0x02) /* I2C Mode: Transmit START */
#define UCSWRST (0x01) /* USCI Software Reset */
+// aliases by MSPGCC
+#define UCSSEL_0 (0<<6) /* USCI Clock Source: 0 */
+#define UCSSEL_1 (1<<6) /* USCI Clock Source: 1 */
+#define UCSSEL_2 (2<<6) /* USCI Clock Source: 2 */
+#define UCSSEL_3 (3<<6) /* USCI Clock Source: 3 */
+#define UCSSEL_UCLKI UCSSEL_0 /* not in SPI Mode */
+#define UCSSEL_ACLK UCSSEL_1
+#define UCSSEL_SMCLK UCSSEL_2
-// SPI-Mode Bits
-//#define res (0x20) /* reserved */
-//#define res (0x10) /* reserved */
-//#define res (0x08) /* reserved */
-//#define res (0x04) /* reserved */
-//#define res (0x02) /* reserved */
-
-// I2C-Mode Bits
-//#define res (0x20) /* reserved */
-#define UCTR (0x10) /* Transmit/Receive Select/Flag */
-#define UCTXNACK (0x08) /* Transmit NACK */
-#define UCTXSTP (0x04) /* Transmit STOP */
-#define UCTXSTT (0x02) /* Transmit START */
-#define UCSSEL_0 (0<<6) /* USCI 0 Clock Source: 0 */
-#define UCSSEL_1 (1<<6) /* USCI 0 Clock Source: 1 */
-#define UCSSEL_2 (2<<6) /* USCI 0 Clock Source: 2 */
-#define UCSSEL_3 (3<<6) /* USCI 0 Clock Source: 3 */
+// UART modulation bits (UCAxMCTL)
#define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */
#define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */
#define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */
#define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */
#define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */
#define UCOS16 (0x01) /* USCI 16-times Oversampling enable */
-
+// aliases by MSPGCC
#define UCBRF_0 (0x0<<4) /* USCI First Stage Modulation: 0 */
#define UCBRF_1 (0x1<<4) /* USCI First Stage Modulation: 1 */
#define UCBRF_2 (0x2<<4) /* USCI First Stage Modulation: 2 */
#define UCBRF_13 (0xD<<4) /* USCI First Stage Modulation: D */
#define UCBRF_14 (0xE<<4) /* USCI First Stage Modulation: E */
#define UCBRF_15 (0xF<<4) /* USCI First Stage Modulation: F */
-
#define UCBRS_0 (0<<1) /* USCI Second Stage Modulation: 0 */
#define UCBRS_1 (1<<1) /* USCI Second Stage Modulation: 1 */
#define UCBRS_2 (2<<1) /* USCI Second Stage Modulation: 2 */
#define UCBRS_6 (6<<1) /* USCI Second Stage Modulation: 6 */
#define UCBRS_7 (7<<1) /* USCI Second Stage Modulation: 7 */
-#define UCLISTEN (0x80) /* USCI Listen mode */
-#define UCFE (0x40) /* USCI Frame Error Flag */
-#define UCOE (0x20) /* USCI Overrun Error Flag */
-#define UCPE (0x10) /* USCI Parity Error Flag */
-#define UCBRK (0x08) /* USCI Break received */
-#define UCRXERR (0x04) /* USCI RX Error Flag */
-#define UCADDR (0x02) /* USCI Address received Flag */
+// UART status register bits (UCAxSTAT/UCBxSTAT)
+#define UCLISTEN (0x80) /* Async./SPI Mode: Listen (loopback) */
+#define UCFE (0x40) /* Async./SPI Mode: Frame Error Flag */
+#define UCSCLLOW (0x40) /* I2C Mode: SCL low */
+#define UCOE (0x20) /* Async./SPI Mode: USCI Overrun Error Flag */
+#define UCGC (0x20) /* I2C Mode: general call address received */
+#define UCPE (0x10) /* Async. Mode: Parity Error Flag */
+#define UCBBUSY (0x10) /* I2C Mode: Bus busy */
+#define UCBRK (0x08) /* Async. Mode: Break received */
+#define UCRXERR (0x04) /* Async. Mode: RX Error Flag */
+#define UCADDR (0x02) /* Async. Mode: Address received Flag (address bit multiprocessor mode)*/
+#define UCIDLE (0x02) /* Async. Mode: Idle line detected Flag (idle line multiprocessor mode)*/
#define UCBUSY (0x01) /* USCI Busy Flag */
-#define UCIDLE (0x02) /* USCI Idle line detected Flag */
-
-//#define res (0x80) /* reserved */
-//#define res (0x40) /* reserved */
-//#define res (0x20) /* reserved */
-//#define res (0x10) /* reserved */
-#define UCNACKIE (0x08) /* NACK Condition interrupt enable */
-#define UCSTPIE (0x04) /* STOP Condition interrupt enable */
-#define UCSTTIE (0x02) /* START Condition interrupt enable */
-#define UCALIE (0x01) /* Arbitration Lost interrupt enable */
-
-#define UCSCLLOW (0x40) /* SCL low */
-#define UCGC (0x20) /* General Call address received Flag */
-#define UCBBUSY (0x10) /* Bus Busy Flag */
-#define UCNACKIFG (0x08) /* NAK Condition interrupt Flag */
-#define UCSTPIFG (0x04) /* STOP Condition interrupt Flag */
-#define UCSTTIFG (0x02) /* START Condition interrupt Flag */
-#define UCALIFG (0x01) /* Arbitration Lost interrupt Flag */
+// IrDA transmit control register bits (UCAxIRTCTL)
#define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */
#define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */
#define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */
#define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */
#define UCIREN (0x01) /* IRDA Encoder/Decoder enable */
+// IrDA receive control register bits (UCAxIRRCTL)
#define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */
#define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */
#define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */
#define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */
#define UCIRRXFE (0x01) /* IRDA Receive Filter enable */
-//#define res (0x80) /* reserved */
-//#define res (0x40) /* reserved */
+// Auto baud rate register bits (UCAxABCTL)
#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
#define UCSTOE (0x08) /* Sync-Field Timeout error */
#define UCBTOE (0x04) /* Break Timeout error */
-//#define res (0x02) /* reserved */
#define UCABDEN (0x01) /* Auto Baud Rate detect enable */
+// aliases by MSPGCC
+#define UCDELIM_1 (0<<4) /* Break/synch delimiter = 1 bit time */
+#define UCDELIM_2 (1<<4) /* Break/synch delimiter = 2 bit times */
+#define UCDELIM_3 (2<<4) /* Break/synch delimiter = 3 bit times */
+#define UCDELIM_4 (3<<4) /* Break/synch delimiter = 4 bit times */
-#define UCGCEN (0x8000) /* I2C General Call enable */
-#define UCOA9 (0x0200) /* I2C Own Address 9 */
-#define UCOA8 (0x0100) /* I2C Own Address 8 */
-#define UCOA7 (0x0080) /* I2C Own Address 7 */
-#define UCOA6 (0x0040) /* I2C Own Address 6 */
-#define UCOA5 (0x0020) /* I2C Own Address 5 */
-#define UCOA4 (0x0010) /* I2C Own Address 4 */
-#define UCOA3 (0x0008) /* I2C Own Address 3 */
-#define UCOA2 (0x0004) /* I2C Own Address 2 */
-#define UCOA1 (0x0002) /* I2C Own Address 1 */
-#define UCOA0 (0x0001) /* I2C Own Address 0 */
-
-#define UCSA9 (0x0200) /* I2C Slave Address 9 */
-#define UCSA8 (0x0100) /* I2C Slave Address 8 */
-#define UCSA7 (0x0080) /* I2C Slave Address 7 */
-#define UCSA6 (0x0040) /* I2C Slave Address 6 */
-#define UCSA5 (0x0020) /* I2C Slave Address 5 */
-#define UCSA4 (0x0010) /* I2C Slave Address 4 */
-#define UCSA3 (0x0008) /* I2C Slave Address 3 */
-#define UCSA2 (0x0004) /* I2C Slave Address 2 */
-#define UCSA1 (0x0002) /* I2C Slave Address 1 */
-#define UCSA0 (0x0001) /* I2C Slave Address 0 */
-
-/* Aliases by mspgcc */
-#define UCSSEL_UCLKI UCSSEL_0
-#define UCSSEL_ACLK UCSSEL_1
-#define UCSSEL_SMCLK UCSSEL_2
+// I2C own address register (UCBxI2COA)
+#define UCGCEN (0x8000) /* I2C General Call Response enable */
+
+
+// Interrupt enable register bits (UCyxIE)
+#if defined(__MSP430_HAS_USCI0__) || defined(__MSP430_HAS_USCI1__) // bits different for USCI and USCI5 (USCI not checked!)
+#define UCNACKIE (0x08) /* NACK Condition interrupt enable */
+#define UCSTPIE (0x04) /* STOP Condition interrupt enable */
+#define UCSTTIE (0x02) /* START Condition interrupt enable */
+#define UCALIE (0x01) /* Arbitration Lost interrupt enable */
+#else
+#define UCNACKIE (0x20) /* NACK Condition interrupt enable */
+#define UCALIE (0x10) /* Arbitration Lost interrupt enable */
+#define UCSTPIE (0x08) /* STOP Condition interrupt enable */
+#define UCSTTIE (0x04) /* START Condition interrupt enable */
+#define UCTXIE (0x02) /* transmit interrupt enable */
+#define UCRXIE (0x01) /* receive interrupt enable */
+#endif
+
+// Interrupt flag register bits (UCyxIFG)
+#if defined(__MSP430_HAS_USCI0__) || defined(__MSP430_HAS_USCI1__) // bits different for USCI and USCI5 (USCI not checked!)
+#define UCNACKIFG (0x08) /* NAK Condition interrupt Flag */
+#define UCSTPIFG (0x04) /* STOP Condition interrupt Flag */
+#define UCSTTIFG (0x02) /* START Condition interrupt Flag */
+#define UCALIFG (0x01) /* Arbitration Lost interrupt Flag */
+#else
+#define UCNACKIFG (0x20) /* NAK Condition interrupt Flag */
+#define UCALIFG (0x10) /* Arbitration Lost interrupt Flag */
+#define UCSTPIFG (0x08) /* STOP Condition interrupt Flag */
+#define UCSTTIFG (0x04) /* START Condition interrupt Flag */
+#define UCTXIFG (0x02) /* transmit interrupt flag (set when UCxxTXBUF empty) */
+#define UCRXIFG (0x01) /* receive interrupt flag (set when UCxxRXBUF has received a char) */
+#endif
+
+
+#if defined(__MSP430_HAS_USCI0__)
/* -------- USCI0 */
#define UCB0I2CSA_ 0x011A /* USCI B0 I2C Slave Address */
sfrw(UCB0I2CSA, UCB0I2CSA_);
+#define UCA0RXIE (1<<0)
+#define UCA0TXIE (1<<1)
+#define UCB0RXIE (1<<2)
+#define UCB0TXIE (1<<3)
+
+#define UCA0RXIFG (1<<0)
+#define UCA0TXIFG (1<<1)
+#define UCB0RXIFG (1<<2)
+#define UCB0TXIFG (1<<3)
+#endif /* __MSP430_HAS_USCI0__ */
+
#if defined(__MSP430_HAS_USCI1__)
/* -------- USCI1 */
#define UCB1TXIFG (1<<3)
#endif /* __MSP430_HAS_USCI1__ */
-#endif
+/******************************************************************************
+ USCI0 on MSP430F54xx
+ ******************************************************************************/
+
+#if defined(__MSP430_USCI5_BASE_0__)
+
+#define UCA0CTL0_ __MSP430_USCI5_BASE_0__ + 0x01 // USCI control 0 (sic)
+sfrb(UCA0CTL0, UCA0CTL0_);
+#define UCA0CTL1_ __MSP430_USCI5_BASE_0__ + 0x00 // USCI control 1 (sic)
+sfrb(UCA0CTL1, UCA0CTL1_);
+#define UCA0BRW_ __MSP430_USCI5_BASE_0__ + 0x06 // USCI baud rate word
+sfrw(UCA0BRW, UCA0BRW_);
+#define UCA0BR0_ __MSP430_USCI5_BASE_0__ + 0x06 // USCI baud rate 0
+sfrb(UCA0BR0, UCA0BR0_);
+#define UCA0BR1_ __MSP430_USCI5_BASE_0__ + 0x07 // USCI baud rate 1
+sfrb(UCA0BR1, UCA0BR1_);
+#define UCA0MCTL_ __MSP430_USCI5_BASE_0__ + 0x08 // USCI modulation control
+sfrb(UCA0MCTL, UCA0MCTL_);
+#define UCA0STAT_ __MSP430_USCI5_BASE_0__ + 0x0A // USCI status
+sfrb(UCA0STAT, UCA0STAT_);
+#define UCA0RXBUF_ __MSP430_USCI5_BASE_0__ + 0x0C // USCI receive buffer
+sfrb(UCA0RXBUF, UCA0RXBUF_);
+#define UCA0TXBUF_ __MSP430_USCI5_BASE_0__ + 0x0E // USCI transmit buffer
+sfrb(UCA0TXBUF, UCA0TXBUF_);
+#define UCA0ABCTL_ __MSP430_USCI5_BASE_0__ + 0x10 // USCI LIN control
+sfrb(UCA0ABCTL, UCA0ABCTL_);
+#define UCA0IRTCTL_ __MSP430_USCI5_BASE_0__ + 0x12 // USCI IrDA transmit control
+sfrb(UCA0IRTCTL, UCA0IRTCTL_);
+#define UCA0IRRCTL_ __MSP430_USCI5_BASE_0__ + 0x13 // USCI IrDA receive control
+sfrb(UCA0IRRCTL, UCA0IRRCTL_);
+#define UCA0IE_ __MSP430_USCI5_BASE_0__ + 0x1C // USCI interrupt enable
+sfrb(UCA0IE, UCA0IE_);
+#define UCA0IFG_ __MSP430_USCI5_BASE_0__ + 0x1D // USCI interrupt flags
+sfrb(UCA0IFG, UCA0IFG_);
+#define UCA0IV_ __MSP430_USCI5_BASE_0__ + 0x1E // USCI interrupt vector word
+sfrw(UCA0IV, UCA0IV_);
+#define UCA0IV_L_ __MSP430_USCI5_BASE_0__ + 0x1E
+sfrb(UCA0IV_L, UCA0IV_L_);
+#define UCA0IV_H_ __MSP430_USCI5_BASE_0__ + 0x1F
+sfrb(UCA0IV_H, UCA0IV_H_);
+
+#define UCB0CTL0_ __MSP430_USCI5_BASE_0__ + 0x20 // USCI synchronous control 0
+sfrb(UCB0CTL0, UCB0CTL0_);
+#define UCB0CTL1_ __MSP430_USCI5_BASE_0__ + 0x21 // USCI synchronous control 1
+sfrb(UCB0CTL1, UCB0CTL1_);
+#define UCB0BR0_ __MSP430_USCI5_BASE_0__ + 0x26 // USCI synchronous bit rate 0
+sfrb(UCB0BR0, UCB0BR0_);
+#define UCB0BR1_ __MSP430_USCI5_BASE_0__ + 0x27 // USCI synchronous bit rate 1
+sfrb(UCB0BR1, UCB0BR1_);
+#define UCB0MCTL_ __MSP430_USCI5_BASE_0__ + 0x28 // USCI I2C interrupt enable
+sfrb(UCB0MCTL, UCB0MCTL_);
+#define UCB0STAT_ __MSP430_USCI5_BASE_0__ + 0x2A // USCI synchronous status
+sfrb(UCB0STAT, UCB0STAT_);
+#define UCB0RXBUF_ __MSP430_USCI5_BASE_0__ + 0x2C // USCI synchronous receive buffer
+sfrb(UCB0RXBUF, UCB0RXBUF_);
+#define UCB0TXBUF_ __MSP430_USCI5_BASE_0__ + 0x2E // USCI synchronous transmit buffer
+sfrb(UCB0TXBUF, UCB0TXBUF_);
+#define UCB0I2COA_ __MSP430_USCI5_BASE_0__ + 0x30 // USCI I2C own address
+sfrb(UCB0I2COA, UCB0I2COA_);
+#define UCB0I2CSA_ __MSP430_USCI5_BASE_0__ + 0x32 // USCI I2C slave address
+sfrb(UCB0I2CSA, UCB0I2CSA_);
+#define UCB0IE_ __MSP430_USCI5_BASE_0__ + 0x3C // USCI interrupt enable
+sfrb(UCB0IE, UCB0IE_);
+#define UCB0IFG_ __MSP430_USCI5_BASE_0__ + 0x3D // USCI interrupt flags
+sfrb(UCB0IFG, UCB0IFG_);
+#define UCB0IV_ __MSP430_USCI5_BASE_0__ + 0x3E // USCI interrupt vector word
+sfrw(UCB0IV, UCB0IV_);
+#define UCB0IV_L_ __MSP430_USCI5_BASE_0__ + 0x3E
+sfrb(UCB0IV_L, UCB0IV_L_);
+#define UCB0IV_H_ __MSP430_USCI5_BASE_0__ + 0x3F
+sfrb(UCB0IV_H, UCB0IV_H_);
+
+#endif /* __MSP430_USCI5_BASE_0__ */
+
+/******************************************************************************
+ USCI1 on MSP430F54xx
+ ******************************************************************************/
+
+#if defined(__MSP430_USCI5_BASE_1__)
+
+#define UCA1CTL0_ __MSP430_USCI5_BASE_1__ + 0x01 // USCI control 0 (sic)
+sfrb(UCA1CTL0, UCA1CTL0_);
+#define UCA1CTL1_ __MSP430_USCI5_BASE_1__ + 0x00 // USCI control 1 (sic)
+sfrb(UCA1CTL1, UCA1CTL1_);
+#define UCA1BRW_ __MSP430_USCI5_BASE_1__ + 0x06 // USCI baud rate word
+sfrw(UCA1BRW, UCA1BRW_);
+#define UCA1BR0_ __MSP430_USCI5_BASE_1__ + 0x06 // USCI baud rate 0
+sfrb(UCA1BR0, UCA1BR0_);
+#define UCA1BR1_ __MSP430_USCI5_BASE_1__ + 0x07 // USCI baud rate 1
+sfrb(UCA1BR1, UCA1BR1_);
+#define UCA1MCTL_ __MSP430_USCI5_BASE_1__ + 0x08 // USCI modulation control
+sfrb(UCA1MCTL, UCA1MCTL_);
+#define UCA1STAT_ __MSP430_USCI5_BASE_1__ + 0x0A // USCI status
+sfrb(UCA1STAT, UCA1STAT_);
+#define UCA1RXBUF_ __MSP430_USCI5_BASE_1__ + 0x0C // USCI receive buffer
+sfrb(UCA1RXBUF, UCA1RXBUF_);
+#define UCA1TXBUF_ __MSP430_USCI5_BASE_1__ + 0x0E // USCI transmit buffer
+sfrb(UCA1TXBUF, UCA1TXBUF_);
+#define UCA1ABCTL_ __MSP430_USCI5_BASE_1__ + 0x10 // USCI LIN control
+sfrb(UCA1ABCTL, UCA1ABCTL_);
+#define UCA1IRTCTL_ __MSP430_USCI5_BASE_1__ + 0x12 // USCI IrDA transmit control
+sfrb(UCA1IRTCTL, UCA1IRTCTL_);
+#define UCA1IRRCTL_ __MSP430_USCI5_BASE_1__ + 0x13 // USCI IrDA receive control
+sfrb(UCA1IRRCTL, UCA1IRRCTL_);
+#define UCA1IE_ __MSP430_USCI5_BASE_1__ + 0x1C // USCI interrupt enable
+sfrb(UCA1IE, UCA1IE_);
+#define UCA1IFG_ __MSP430_USCI5_BASE_1__ + 0x1D // USCI interrupt flags
+sfrb(UCA1IFG, UCA1IFG_);
+#define UCA1IV_ __MSP430_USCI5_BASE_1__ + 0x1E // USCI interrupt vector word
+sfrw(UCA1IV, UCA1IV_);
+#define UCA1IV_L_ __MSP430_USCI5_BASE_1__ + 0x1E
+sfrb(UCA1IV_L, UCA1IV_L_);
+#define UCA1IV_H_ __MSP430_USCI5_BASE_1__ + 0x1F
+sfrb(UCA1IV_H, UCA1IV_H_);
+
+#define UCB1CTL0_ __MSP430_USCI5_BASE_1__ + 0x20 // USCI synchronous control 0
+sfrb(UCB1CTL0, UCB1CTL0_);
+#define UCB1CTL1_ __MSP430_USCI5_BASE_1__ + 0x21 // USCI synchronous control 1
+sfrb(UCB1CTL1, UCB1CTL1_);
+#define UCB1BR0_ __MSP430_USCI5_BASE_1__ + 0x26 // USCI synchronous bit rate 0
+sfrb(UCB1BR0, UCB1BR0_);
+#define UCB1BR1_ __MSP430_USCI5_BASE_1__ + 0x27 // USCI synchronous bit rate 1
+sfrb(UCB1BR1, UCB1BR1_);
+#define UCB1MCTL_ __MSP430_USCI5_BASE_1__ + 0x28 // USCI I2C interrupt enable
+sfrb(UCB1MCTL, UCB1MCTL_);
+#define UCB1STAT_ __MSP430_USCI5_BASE_1__ + 0x2A // USCI synchronous status
+sfrb(UCB1STAT, UCB1STAT_);
+#define UCB1RXBUF_ __MSP430_USCI5_BASE_1__ + 0x2C // USCI synchronous receive buffer
+sfrb(UCB1RXBUF, UCB1RXBUF_);
+#define UCB1TXBUF_ __MSP430_USCI5_BASE_1__ + 0x2E // USCI synchronous transmit buffer
+sfrb(UCB1TXBUF, UCB1TXBUF_);
+#define UCB1I2COA_ __MSP430_USCI5_BASE_1__ + 0x30 // USCI I2C own address
+sfrb(UCB1I2COA, UCB1I2COA_);
+#define UCB1I2CSA_ __MSP430_USCI5_BASE_1__ + 0x32 // USCI I2C slave address
+sfrb(UCB1I2CSA, UCB1I2CSA_);
+#define UCB1IE_ __MSP430_USCI5_BASE_1__ + 0x3C // USCI interrupt enable
+sfrb(UCB1IE, UCB1IE_);
+#define UCB1IFG_ __MSP430_USCI5_BASE_1__ + 0x3D // USCI interrupt flags
+sfrb(UCB1IFG, UCB1IFG_);
+#define UCB1IV_ __MSP430_USCI5_BASE_1__ + 0x3E // USCI interrupt vector word
+sfrw(UCB1IV, UCB1IV_);
+#define UCB1IV_L_ __MSP430_USCI5_BASE_1__ + 0x3E
+sfrb(UCB1IV_L, UCB1IV_L_);
+#define UCB1IV_H_ __MSP430_USCI5_BASE_1__ + 0x3F
+sfrb(UCB1IV_H, UCB1IV_H_);
+
+#endif /* __MSP430_USCI5_BASE_1__ */
+
+/******************************************************************************
+ USCI2 on MSP430F54xx
+ ******************************************************************************/
+
+#if defined(__MSP430_USCI5_BASE_2__)
+
+#define UCA2CTL0_ __MSP430_USCI5_BASE_2__ + 0x01 // USCI control 0 (sic)
+sfrb(UCA2CTL0, UCA2CTL0_);
+#define UCA2CTL1_ __MSP430_USCI5_BASE_2__ + 0x00 // USCI control 1 (sic)
+sfrb(UCA2CTL1, UCA2CTL1_);
+#define UCA2BRW_ __MSP430_USCI5_BASE_2__ + 0x06 // USCI baud rate word
+sfrw(UCA2BRW, UCA2BRW_);
+#define UCA2BR0_ __MSP430_USCI5_BASE_2__ + 0x06 // USCI baud rate 0
+sfrb(UCA2BR0, UCA2BR0_);
+#define UCA2BR1_ __MSP430_USCI5_BASE_2__ + 0x07 // USCI baud rate 1
+sfrb(UCA2BR1, UCA2BR1_);
+#define UCA2MCTL_ __MSP430_USCI5_BASE_2__ + 0x08 // USCI modulation control
+sfrb(UCA2MCTL, UCA2MCTL_);
+#define UCA2STAT_ __MSP430_USCI5_BASE_2__ + 0x0A // USCI status
+sfrb(UCA2STAT, UCA2STAT_);
+#define UCA2RXBUF_ __MSP430_USCI5_BASE_2__ + 0x0C // USCI receive buffer
+sfrb(UCA2RXBUF, UCA2RXBUF_);
+#define UCA2TXBUF_ __MSP430_USCI5_BASE_2__ + 0x0E // USCI transmit buffer
+sfrb(UCA2TXBUF, UCA2TXBUF_);
+#define UCA2ABCTL_ __MSP430_USCI5_BASE_2__ + 0x10 // USCI LIN control
+sfrb(UCA2ABCTL, UCA2ABCTL_);
+#define UCA2IRTCTL_ __MSP430_USCI5_BASE_2__ + 0x12 // USCI IrDA transmit control
+sfrb(UCA2IRTCTL, UCA2IRTCTL_);
+#define UCA2IRRCTL_ __MSP430_USCI5_BASE_2__ + 0x13 // USCI IrDA receive control
+sfrb(UCA2IRRCTL, UCA2IRRCTL_);
+#define UCA2IE_ __MSP430_USCI5_BASE_2__ + 0x1C // USCI interrupt enable
+sfrb(UCA2IE, UCA2IE_);
+#define UCA2IFG_ __MSP430_USCI5_BASE_2__ + 0x1D // USCI interrupt flags
+sfrb(UCA2IFG, UCA2IFG_);
+#define UCA2IV_ __MSP430_USCI5_BASE_2__ + 0x1E // USCI interrupt vector word
+sfrw(UCA2IV, UCA2IV_);
+#define UCA2IV_L_ __MSP430_USCI5_BASE_2__ + 0x1E
+sfrb(UCA2IV_L, UCA2IV_L_);
+#define UCA2IV_H_ __MSP430_USCI5_BASE_2__ + 0x1F
+sfrb(UCA2IV_H, UCA2IV_H_);
+
+#define UCB2CTL0_ __MSP430_USCI5_BASE_2__ + 0x20 // USCI synchronous control 0
+sfrb(UCB2CTL0, UCB2CTL0_);
+#define UCB2CTL1_ __MSP430_USCI5_BASE_2__ + 0x21 // USCI synchronous control 1
+sfrb(UCB2CTL1, UCB2CTL1_);
+#define UCB2BR0_ __MSP430_USCI5_BASE_2__ + 0x26 // USCI synchronous bit rate 0
+sfrb(UCB2BR0, UCB2BR0_);
+#define UCB2BR1_ __MSP430_USCI5_BASE_2__ + 0x27 // USCI synchronous bit rate 1
+sfrb(UCB2BR1, UCB2BR1_);
+#define UCB2MCTL_ __MSP430_USCI5_BASE_2__ + 0x28 // USCI I2C interrupt enable
+sfrb(UCB2MCTL, UCB2MCTL_);
+#define UCB2STAT_ __MSP430_USCI5_BASE_2__ + 0x2A // USCI synchronous status
+sfrb(UCB2STAT, UCB2STAT_);
+#define UCB2RXBUF_ __MSP430_USCI5_BASE_2__ + 0x2C // USCI synchronous receive buffer
+sfrb(UCB2RXBUF, UCB2RXBUF_);
+#define UCB2TXBUF_ __MSP430_USCI5_BASE_2__ + 0x2E // USCI synchronous transmit buffer
+sfrb(UCB2TXBUF, UCB2TXBUF_);
+#define UCB2I2COA_ __MSP430_USCI5_BASE_2__ + 0x30 // USCI I2C own address
+sfrb(UCB2I2COA, UCB2I2COA_);
+#define UCB2I2CSA_ __MSP430_USCI5_BASE_2__ + 0x32 // USCI I2C slave address
+sfrb(UCB2I2CSA, UCB2I2CSA_);
+#define UCB2IE_ __MSP430_USCI5_BASE_2__ + 0x3C // USCI interrupt enable
+sfrb(UCB2IE, UCB2IE_);
+#define UCB2IFG_ __MSP430_USCI5_BASE_2__ + 0x3D // USCI interrupt flags
+sfrb(UCB2IFG, UCB2IFG_);
+#define UCB2IV_ __MSP430_USCI5_BASE_2__ + 0x3E // USCI interrupt vector word
+sfrw(UCB2IV, UCB2IV_);
+#define UCB2IV_L_ __MSP430_USCI5_BASE_2__ + 0x3E
+sfrb(UCB2IV_L, UCB2IV_L_);
+#define UCB2IV_H_ __MSP430_USCI5_BASE_2__ + 0x3F
+sfrb(UCB2IV_H, UCB2IV_H_);
+
+#endif /* __MSP430_USCI5_BASE_2__ */
+
+/******************************************************************************
+ USCI3 on MSP430F54xx
+ ******************************************************************************/
+
+#if defined(__MSP430_USCI5_BASE_3__)
+
+#define UCA3CTL0_ __MSP430_USCI5_BASE_3__ + 0x01 // USCI control 0 (sic)
+sfrb(UCA3CTL0, UCA3CTL0_);
+#define UCA3CTL1_ __MSP430_USCI5_BASE_3__ + 0x00 // USCI control 1 (sic)
+sfrb(UCA3CTL1, UCA3CTL1_);
+#define UCA3BRW_ __MSP430_USCI5_BASE_3__ + 0x06 // USCI baud rate word
+sfrw(UCA3BRW, UCA3BRW_)
+#define UCA3BR0_ __MSP430_USCI5_BASE_3__ + 0x06 // USCI baud rate 0
+sfrb(UCA3BR0, UCA3BR0_);
+#define UCA3BR1_ __MSP430_USCI5_BASE_3__ + 0x07 // USCI baud rate 1
+sfrb(UCA3BR1, UCA3BR1_);
+#define UCA3MCTL_ __MSP430_USCI5_BASE_3__ + 0x08 // USCI modulation control
+sfrb(UCA3MCTL, UCA3MCTL_);
+#define UCA3STAT_ __MSP430_USCI5_BASE_3__ + 0x0A // USCI status
+sfrb(UCA3STAT, UCA3STAT_);
+#define UCA3RXBUF_ __MSP430_USCI5_BASE_3__ + 0x0C // USCI receive buffer
+sfrb(UCA3RXBUF, UCA3RXBUF_);
+#define UCA3TXBUF_ __MSP430_USCI5_BASE_3__ + 0x0E // USCI transmit buffer
+sfrb(UCA3TXBUF, UCA3TXBUF_);
+#define UCA3ABCTL_ __MSP430_USCI5_BASE_3__ + 0x10 // USCI LIN control
+sfrb(UCA3ABCTL, UCA3ABCTL_);
+#define UCA3IRTCTL_ __MSP430_USCI5_BASE_3__ + 0x12 // USCI IrDA transmit control
+sfrb(UCA3IRTCTL, UCA3IRTCTL_);
+#define UCA3IRRCTL_ __MSP430_USCI5_BASE_3__ + 0x13 // USCI IrDA receive control
+sfrb(UCA3IRRCTL, UCA3IRRCTL_);
+#define UCA3IE_ __MSP430_USCI5_BASE_3__ + 0x1C // USCI interrupt enable
+sfrb(UCA3IE, UCA3IE_);
+#define UCA3IFG_ __MSP430_USCI5_BASE_3__ + 0x1D // USCI interrupt flags
+sfrb(UCA3IFG, UCA3IFG_);
+#define UCA3IV_ __MSP430_USCI5_BASE_3__ + 0x1E // USCI interrupt vector word
+sfrw(UCA3IV, UCA3IV_);
+#define UCA3IV_L_ __MSP430_USCI5_BASE_3__ + 0x1E
+sfrb(UCA3IV_L, UCA3IV_L_);
+#define UCA3IV_H_ __MSP430_USCI5_BASE_3__ + 0x1F
+sfrb(UCA3IV_H, UCA3IV_H_);
+
+#define UCB3CTL0_ __MSP430_USCI5_BASE_3__ + 0x20 // USCI synchronous control 0
+sfrb(UCB3CTL0, UCB3CTL0_);
+#define UCB3CTL1_ __MSP430_USCI5_BASE_3__ + 0x21 // USCI synchronous control 1
+sfrb(UCB3CTL1, UCB3CTL1_);
+#define UCB3BR0_ __MSP430_USCI5_BASE_3__ + 0x26 // USCI synchronous bit rate 0
+sfrb(UCB3BR0, UCB3BR0_);
+#define UCB3BR1_ __MSP430_USCI5_BASE_3__ + 0x27 // USCI synchronous bit rate 1
+sfrb(UCB3BR1, UCB3BR1_);
+#define UCB3MCTL_ __MSP430_USCI5_BASE_3__ + 0x28 // USCI I2C interrupt enable
+sfrb(UCB3MCTL, UCB3MCTL_);
+#define UCB3STAT_ __MSP430_USCI5_BASE_3__ + 0x2A // USCI synchronous status
+sfrb(UCB3STAT, UCB3STAT_);
+#define UCB3RXBUF_ __MSP430_USCI5_BASE_3__ + 0x2C // USCI synchronous receive buffer
+sfrb(UCB3RXBUF, UCB3RXBUF_);
+#define UCB3TXBUF_ __MSP430_USCI5_BASE_3__ + 0x2E // USCI synchronous transmit buffer
+sfrb(UCB3TXBUF, UCB3TXBUF_);
+#define UCB3I2COA_ __MSP430_USCI5_BASE_3__ + 0x30 // USCI I2C own address
+sfrb(UCB3I2COA, UCB3I2COA_);
+#define UCB3I2CSA_ __MSP430_USCI5_BASE_3__ + 0x32 // USCI I2C slave address
+sfrb(UCB3I2CSA, UCB3I2CSA_);
+#define UCB3IE_ __MSP430_USCI5_BASE_3__ + 0x3C // USCI interrupt enable
+sfrb(UCB3IE, UCB3IE_);
+#define UCB3IFG_ __MSP430_USCI5_BASE_3__ + 0x3D // USCI interrupt flags
+sfrb(UCB3IFG, UCB3IFG_);
+#define UCB3IV_ __MSP430_USCI5_BASE_3__ + 0x3E // USCI interrupt vector word
+sfrw(UCB3IV, UCB3IV_);
+#define UCB3IV_L_ __MSP430_USCI5_BASE_3__ + 0x3E
+sfrb(UCB3IV_L, UCB3IV_L_);
+#define UCB3IV_H_ __MSP430_USCI5_BASE_3__ + 0x3F
+sfrb(UCB3IV_H, UCB3IV_H_);
+
+#endif /* __MSP430_USCI5_BASE_3__ */
+
+#endif /* __MSP430_HEADERS_USCI_H__ */
--- /dev/null
+#if !defined(__MSP430_HEADERS_USCI_5XX_H__)
+#define __MSP430_HEADERS_USCI_5XX_H__
+
+/* usci_5xx.h
+ *
+ * mspgcc project: MSP430 device headers
+ * Universal Serial Communication Interface (USCI) module
+ * Variant for MSP430-5xx architecture chips
+ *
+ * Based on msp430x54x.h version 1.10 by Texas Instruments
+ *
+ * Peter A. Bigot <pab@peoplepowerco.com>
+ *
+ */
+
+/* Switches:
+__MSP430_HAS_USCI_A0__ -- definition indicates availability
+__MSP430_HAS_USCI_B0__ -- definition indicates availability
+__MSP430_USCI0_BASE__ -- USCI module base address for A0/B0; definition indicates availability
+__MSP430_HAS_USCI_A1__ -- definition indicates availability
+__MSP430_HAS_USCI_B1__ -- definition indicates availability
+__MSP430_USCI1_BASE__ -- USCI module base address for A1/B1; definition indicates availability
+__MSP430_HAS_USCI_A2__ -- definition indicates availability
+__MSP430_HAS_USCI_B2__ -- definition indicates availability
+__MSP430_USCI2_BASE__ -- USCI module base address for A2/B2; definition indicates availability
+__MSP430_HAS_USCI_A3__ -- definition indicates availability
+__MSP430_HAS_USCI_B3__ -- definition indicates availability
+__MSP430_USCI3_BASE__ -- USCI module base address for A3/B3; definition indicates availability
+*/
+
+#if defined(__MSP430_USCI0_BASE__)
+
+#if defined(__MSP430_HAS_USCI_A0__)
+/************************************************************
+* USCI A0
+************************************************************/
+#define UCA0CTLW0_ __MSP430_USCI0_BASE__ + 0x00 /* USCI A0 Control Word Register 0 */
+sfrw(UCA0CTLW0, UCA0CTLW0_);
+#define UCA0CTLW0_L_ __MSP430_USCI0_BASE__ + 0x00
+sfrb(UCA0CTLW0_L, UCA0CTLW0_L_);
+#define UCA0CTLW0_H_ __MSP430_USCI0_BASE__ + 0x01
+sfrb(UCA0CTLW0_H, UCA0CTLW0_H_);
+#define UCA0CTL1 UCA0CTLW0_L /* USCI A0 Control Register 1 */
+#define UCA0CTL0 UCA0CTLW0_H /* USCI A0 Control Register 0 */
+#define UCA0BRW_ __MSP430_USCI0_BASE__ + 0x06 /* USCI A0 Baud Word Rate 0 */
+sfrw(UCA0BRW, UCA0BRW_);
+#define UCA0BRW_L_ __MSP430_USCI0_BASE__ + 0x06
+sfrb(UCA0BRW_L, UCA0BRW_L_);
+#define UCA0BRW_H_ __MSP430_USCI0_BASE__ + 0x07
+sfrb(UCA0BRW_H, UCA0BRW_H_);
+#define UCA0BR0 UCA0BRW_L /* USCI A0 Baud Rate 0 */
+#define UCA0BR1 UCA0BRW_H /* USCI A0 Baud Rate 1 */
+#define UCA0MCTL_ __MSP430_USCI0_BASE__ + 0x08 /* USCI A0 Modulation Control */
+sfrb(UCA0MCTL, UCA0MCTL_);
+#define UCA0STAT_ __MSP430_USCI0_BASE__ + 0x0a /* USCI A0 Status Register */
+sfrb(UCA0STAT, UCA0STAT_);
+#define UCA0RXBUF_ __MSP430_USCI0_BASE__ + 0x0c /* USCI A0 Receive Buffer */
+sfrb(UCA0RXBUF, UCA0RXBUF_);
+#define UCA0TXBUF_ __MSP430_USCI0_BASE__ + 0x0e /* USCI A0 Transmit Buffer */
+sfrb(UCA0TXBUF, UCA0TXBUF_);
+#define UCA0ABCTL_ __MSP430_USCI0_BASE__ + 0x10 /* USCI A0 LIN Control */
+sfrb(UCA0ABCTL, UCA0ABCTL_);
+#define UCA0IRCTL_ __MSP430_USCI0_BASE__ + 0x12 /* USCI A0 IrDA Transmit Control */
+sfrw(UCA0IRCTL, UCA0IRCTL_);
+#define UCA0IRCTL_L_ __MSP430_USCI0_BASE__ + 0x12
+sfrb(UCA0IRCTL_L, UCA0IRCTL_L_);
+#define UCA0IRCTL_H_ __MSP430_USCI0_BASE__ + 0x13
+sfrb(UCA0IRCTL_H, UCA0IRCTL_H_);
+#define UCA0IRTCTL UCA0IRCTL_L /* USCI A0 IrDA Transmit Control */
+#define UCA0IRRCTL UCA0IRCTL_H /* USCI A0 IrDA Receive Control */
+#define UCA0ICTL_ __MSP430_USCI0_BASE__ + 0x1c /* USCI A0 Interrupt Enable Register */
+sfrw(UCA0ICTL, UCA0ICTL_);
+#define UCA0ICTL_L_ __MSP430_USCI0_BASE__ + 0x1c
+sfrb(UCA0ICTL_L, UCA0ICTL_L_);
+#define UCA0ICTL_H_ __MSP430_USCI0_BASE__ + 0x1d
+sfrb(UCA0ICTL_H, UCA0ICTL_H_);
+#define UCA0IE UCA0ICTL_L /* USCI A0 Interrupt Enable Register */
+#define UCA0IFG UCA0ICTL_H /* USCI A0 Interrupt Flags Register */
+#define UCA0IV_ __MSP430_USCI0_BASE__ + 0x1e /* USCI A0 Interrupt Vector Register */
+sfrw(UCA0IV, UCA0IV_);
+#endif // __MSP430_HAS_USCI_A0__
+
+#if defined(__MSP430_HAS_USCI_B0__)
+/************************************************************
+* USCI B0
+************************************************************/
+#define UCB0CTLW0_ __MSP430_USCI0_BASE__ + 0x20 /* USCI B0 Control Word Register 0 */
+sfrw(UCB0CTLW0, UCB0CTLW0_);
+#define UCB0CTLW0_L_ __MSP430_USCI0_BASE__ + 0x20
+sfrb(UCB0CTLW0_L, UCB0CTLW0_L_);
+#define UCB0CTLW0_H_ __MSP430_USCI0_BASE__ + 0x21
+sfrb(UCB0CTLW0_H, UCB0CTLW0_H_);
+#define UCB0CTL1 UCB0CTLW0_L /* USCI B0 Control Register 1 */
+#define UCB0CTL0 UCB0CTLW0_H /* USCI B0 Control Register 0 */
+#define UCB0BRW_ __MSP430_USCI0_BASE__ + 0x26 /* USCI B0 Baud Word Rate 0 */
+sfrw(UCB0BRW, UCB0BRW_);
+#define UCB0BRW_L_ __MSP430_USCI0_BASE__ + 0x26
+sfrb(UCB0BRW_L, UCB0BRW_L_);
+#define UCB0BRW_H_ __MSP430_USCI0_BASE__ + 0x27
+sfrb(UCB0BRW_H, UCB0BRW_H_);
+#define UCB0BR0 UCB0BRW_L /* USCI B0 Baud Rate 0 */
+#define UCB0BR1 UCB0BRW_H /* USCI B0 Baud Rate 1 */
+#define UCB0STAT_ __MSP430_USCI0_BASE__ + 0x2a /* USCI B0 Status Register */
+sfrb(UCB0STAT, UCB0STAT_);
+#define UCB0RXBUF_ __MSP430_USCI0_BASE__ + 0x2c /* USCI B0 Receive Buffer */
+sfrb(UCB0RXBUF, UCB0RXBUF_);
+#define UCB0TXBUF_ __MSP430_USCI0_BASE__ + 0x2e /* USCI B0 Transmit Buffer */
+sfrb(UCB0TXBUF, UCB0TXBUF_);
+#define UCB0I2COA_ __MSP430_USCI0_BASE__ + 0x30 /* USCI B0 I2C Own Address */
+sfrw(UCB0I2COA, UCB0I2COA_);
+#define UCB0I2COA_L_ __MSP430_USCI0_BASE__ + 0x30
+sfrb(UCB0I2COA_L, UCB0I2COA_L_);
+#define UCB0I2COA_H_ __MSP430_USCI0_BASE__ + 0x31
+sfrb(UCB0I2COA_H, UCB0I2COA_H_);
+#define UCB0I2CSA_ __MSP430_USCI0_BASE__ + 0x32 /* USCI B0 I2C Slave Address */
+sfrw(UCB0I2CSA, UCB0I2CSA_);
+#define UCB0I2CSA_L_ __MSP430_USCI0_BASE__ + 0x32
+sfrb(UCB0I2CSA_L, UCB0I2CSA_L_);
+#define UCB0I2CSA_H_ __MSP430_USCI0_BASE__ + 0x33
+sfrb(UCB0I2CSA_H, UCB0I2CSA_H_);
+#define UCB0ICTL_ __MSP430_USCI0_BASE__ + 0x3c /* USCI B0 Interrupt Enable Register */
+sfrw(UCB0ICTL, UCB0ICTL_);
+#define UCB0ICTL_L_ __MSP430_USCI0_BASE__ + 0x3c
+sfrb(UCB0ICTL_L, UCB0ICTL_L_);
+#define UCB0ICTL_H_ __MSP430_USCI0_BASE__ + 0x3d
+sfrb(UCB0ICTL_H, UCB0ICTL_H_);
+#define UCB0IE UCB0ICTL_L /* USCI B0 Interrupt Enable Register */
+#define UCB0IFG UCB0ICTL_H /* USCI B0 Interrupt Flags Register */
+#define UCB0IV_ __MSP430_USCI0_BASE__ + 0x3e /* USCI B0 Interrupt Vector Register */
+sfrw(UCB0IV, UCB0IV_);
+#endif // __MSP430_HAS_USCI_B0__
+
+#endif // __MSP430_USCI0_BASE__
+
+
+// UCAxCTL0 UART-Mode Control Bits
+#define UCPEN (0x80) /* Async. Mode: Parity enable */
+#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */
+#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */
+#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
+#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */
+#define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */
+#define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */
+#define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
+
+// UCxxCTL0 SPI-Mode Control Bits
+#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */
+#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */
+#define UCMST (0x08) /* Sync. Mode: Master Select */
+
+// UCBxCTL0 I2C-Mode Control Bits
+#define UCA10 (0x80) /* 10-bit Address Mode */
+#define UCSLA10 (0x40) /* 10-bit Slave Address Mode */
+#define UCMM (0x20) /* Multi-Master Environment */
+//#define res (0x10) /* reserved */
+#define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */
+#define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */
+#define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */
+#define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */
+
+// UCAxCTL1 UART-Mode Control Bits
+#define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */
+#define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */
+#define UCRXEIE (0x20) /* RX Error interrupt enable */
+#define UCBRKIE (0x10) /* Break interrupt enable */
+#define UCDORM (0x08) /* Dormant (Sleep) Mode */
+#define UCTXADDR (0x04) /* Send next Data as Address */
+#define UCTXBRK (0x02) /* Send next Data as Break */
+#define UCSWRST (0x01) /* USCI Software Reset */
+
+// UCxxCTL1 SPI-Mode Control Bits
+//#define res (0x20) /* reserved */
+//#define res (0x10) /* reserved */
+//#define res (0x08) /* reserved */
+//#define res (0x04) /* reserved */
+//#define res (0x02) /* reserved */
+
+// UCBxCTL1 I2C-Mode Control Bits
+//#define res (0x20) /* reserved */
+#define UCTR (0x10) /* Transmit/Receive Select/Flag */
+#define UCTXNACK (0x08) /* Transmit NACK */
+#define UCTXSTP (0x04) /* Transmit STOP */
+#define UCTXSTT (0x02) /* Transmit START */
+#define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */
+#define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */
+#define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */
+#define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */
+#define UCSSEL__UCLK (0x00) /* USCI 0 Clock Source: UCLK */
+#define UCSSEL__ACLK (0x40) /* USCI 0 Clock Source: ACLK */
+#define UCSSEL__SMCLK (0x80) /* USCI 0 Clock Source: SMCLK */
+
+/* UCAxMCTL Control Bits */
+#define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */
+#define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */
+#define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */
+#define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */
+#define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */
+#define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */
+#define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */
+#define UCOS16 (0x01) /* USCI 16-times Oversampling enable */
+
+#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */
+#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */
+#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */
+#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */
+#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */
+#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */
+#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */
+#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */
+#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */
+#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */
+#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */
+#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */
+#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */
+#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */
+#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */
+#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */
+
+#define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */
+#define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */
+#define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */
+#define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */
+#define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */
+#define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */
+#define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */
+#define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */
+
+/* UCAxSTAT Control Bits */
+#define UCLISTEN (0x80) /* USCI Listen mode */
+#define UCFE (0x40) /* USCI Frame Error Flag */
+#define UCOE (0x20) /* USCI Overrun Error Flag */
+#define UCPE (0x10) /* USCI Parity Error Flag */
+#define UCBRK (0x08) /* USCI Break received */
+#define UCRXERR (0x04) /* USCI RX Error Flag */
+#define UCADDR (0x02) /* USCI Address received Flag */
+#define UCBUSY (0x01) /* USCI Busy Flag */
+#define UCIDLE (0x02) /* USCI Idle line detected Flag */
+
+/* UCBxSTAT Control Bits */
+#define UCSCLLOW (0x40) /* SCL low */
+#define UCGC (0x20) /* General Call address received Flag */
+#define UCBBUSY (0x10) /* Bus Busy Flag */
+
+/* UCAxIRTCTL Control Bits */
+#define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */
+#define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */
+#define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */
+#define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */
+#define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */
+#define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */
+#define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */
+#define UCIREN (0x01) /* IRDA Encoder/Decoder enable */
+
+/* UCAxIRRCTL Control Bits */
+#define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */
+#define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */
+#define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */
+#define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */
+#define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */
+#define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */
+#define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */
+#define UCIRRXFE (0x01) /* IRDA Receive Filter enable */
+
+/* UCAxABCTL Control Bits */
+//#define res (0x80) /* reserved */
+//#define res (0x40) /* reserved */
+#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
+#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
+#define UCSTOE (0x08) /* Sync-Field Timeout error */
+#define UCBTOE (0x04) /* Break Timeout error */
+//#define res (0x02) /* reserved */
+#define UCABDEN (0x01) /* Auto Baud Rate detect enable */
+
+/* UCBxI2COA Control Bits */
+#define UCGCEN (0x8000) /* I2C General Call enable */
+#define UCOA9 (0x0200) /* I2C Own Address 9 */
+#define UCOA8 (0x0100) /* I2C Own Address 8 */
+#define UCOA7 (0x0080) /* I2C Own Address 7 */
+#define UCOA6 (0x0040) /* I2C Own Address 6 */
+#define UCOA5 (0x0020) /* I2C Own Address 5 */
+#define UCOA4 (0x0010) /* I2C Own Address 4 */
+#define UCOA3 (0x0008) /* I2C Own Address 3 */
+#define UCOA2 (0x0004) /* I2C Own Address 2 */
+#define UCOA1 (0x0002) /* I2C Own Address 1 */
+#define UCOA0 (0x0001) /* I2C Own Address 0 */
+
+/* UCBxI2COA Control Bits */
+#define UCOA7_L (0x0080) /* I2C Own Address 7 */
+#define UCOA6_L (0x0040) /* I2C Own Address 6 */
+#define UCOA5_L (0x0020) /* I2C Own Address 5 */
+#define UCOA4_L (0x0010) /* I2C Own Address 4 */
+#define UCOA3_L (0x0008) /* I2C Own Address 3 */
+#define UCOA2_L (0x0004) /* I2C Own Address 2 */
+#define UCOA1_L (0x0002) /* I2C Own Address 1 */
+#define UCOA0_L (0x0001) /* I2C Own Address 0 */
+
+/* UCBxI2COA Control Bits */
+#define UCGCEN_H (0x0080) /* I2C General Call enable */
+#define UCOA9_H (0x0002) /* I2C Own Address 9 */
+#define UCOA8_H (0x0001) /* I2C Own Address 8 */
+
+/* UCBxI2CSA Control Bits */
+#define UCSA9 (0x0200) /* I2C Slave Address 9 */
+#define UCSA8 (0x0100) /* I2C Slave Address 8 */
+#define UCSA7 (0x0080) /* I2C Slave Address 7 */
+#define UCSA6 (0x0040) /* I2C Slave Address 6 */
+#define UCSA5 (0x0020) /* I2C Slave Address 5 */
+#define UCSA4 (0x0010) /* I2C Slave Address 4 */
+#define UCSA3 (0x0008) /* I2C Slave Address 3 */
+#define UCSA2 (0x0004) /* I2C Slave Address 2 */
+#define UCSA1 (0x0002) /* I2C Slave Address 1 */
+#define UCSA0 (0x0001) /* I2C Slave Address 0 */
+
+/* UCBxI2CSA Control Bits */
+#define UCSA7_L (0x0080) /* I2C Slave Address 7 */
+#define UCSA6_L (0x0040) /* I2C Slave Address 6 */
+#define UCSA5_L (0x0020) /* I2C Slave Address 5 */
+#define UCSA4_L (0x0010) /* I2C Slave Address 4 */
+#define UCSA3_L (0x0008) /* I2C Slave Address 3 */
+#define UCSA2_L (0x0004) /* I2C Slave Address 2 */
+#define UCSA1_L (0x0002) /* I2C Slave Address 1 */
+#define UCSA0_L (0x0001) /* I2C Slave Address 0 */
+
+/* UCBxI2CSA Control Bits */
+#define UCSA9_H (0x0002) /* I2C Slave Address 9 */
+#define UCSA8_H (0x0001) /* I2C Slave Address 8 */
+
+/* UCAxIE Control Bits */
+#define UCTXIE (0x0002) /* USCI Transmit Interrupt Enable */
+#define UCRXIE (0x0001) /* USCI Receive Interrupt Enable */
+
+/* UCBxIE Control Bits */
+#define UCNACKIE (0x0020) /* NACK Condition interrupt enable */
+#define UCALIE (0x0010) /* Arbitration Lost interrupt enable */
+#define UCSTPIE (0x0008) /* STOP Condition interrupt enable */
+#define UCSTTIE (0x0004) /* START Condition interrupt enable */
+#define UCTXIE (0x0002) /* USCI Transmit Interrupt Enable */
+#define UCRXIE (0x0001) /* USCI Receive Interrupt Enable */
+
+/* UCAxIFG Control Bits */
+#define UCTXIFG (0x0002) /* USCI Transmit Interrupt Flag */
+#define UCRXIFG (0x0001) /* USCI Receive Interrupt Flag */
+
+/* UCBxIFG Control Bits */
+#define UCNACKIFG (0x0020) /* NAK Condition interrupt Flag */
+#define UCALIFG (0x0010) /* Arbitration Lost interrupt Flag */
+#define UCSTPIFG (0x0008) /* STOP Condition interrupt Flag */
+#define UCSTTIFG (0x0004) /* START Condition interrupt Flag */
+#define UCTXIFG (0x0002) /* USCI Transmit Interrupt Flag */
+#define UCRXIFG (0x0001) /* USCI Receive Interrupt Flag */
+
+/* USCI Definitions */
+#define USCI_NONE (0x0000) /* No Interrupt pending */
+#define USCI_UCRXIFG (0x0002) /* USCI UCRXIFG */
+#define USCI_UCTXIFG (0x0004) /* USCI UCTXIFG */
+#define USCI_I2C_UCALIFG (0x0002) /* USCI I2C Mode: UCALIFG */
+#define USCI_I2C_UCNACKIFG (0x0004) /* USCI I2C Mode: UCNACKIFG */
+#define USCI_I2C_UCSTTIFG (0x0006) /* USCI I2C Mode: UCSTTIFG*/
+#define USCI_I2C_UCSTPIFG (0x0008) /* USCI I2C Mode: UCSTPIFG*/
+#define USCI_I2C_UCRXIFG (0x000A) /* USCI I2C Mode: UCRXIFG */
+#define USCI_I2C_UCTXIFG (0x000C) /* USCI I2C Mode: UCTXIFG */
+
+#if defined(__MSP430_USCI1_BASE__)
+
+#if defined(__MSP430_HAS_USCI_A1__)
+/************************************************************
+* USCI A1
+************************************************************/
+#define UCA1CTLW0_ __MSP430_USCI1_BASE__ + 0x00 /* USCI A1 Control Word Register 0 */
+sfrw(UCA1CTLW0, UCA1CTLW0_);
+#define UCA1CTLW0_L_ __MSP430_USCI1_BASE__ + 0x00
+sfrb(UCA1CTLW0_L, UCA1CTLW0_L_);
+#define UCA1CTLW0_H_ __MSP430_USCI1_BASE__ + 0x01
+sfrb(UCA1CTLW0_H, UCA1CTLW0_H_);
+#define UCA1CTL1 UCA1CTLW0_L /* USCI A1 Control Register 1 */
+#define UCA1CTL0 UCA1CTLW0_H /* USCI A1 Control Register 0 */
+#define UCA1BRW_ __MSP430_USCI1_BASE__ + 0x06 /* USCI A1 Baud Word Rate 0 */
+sfrw(UCA1BRW, UCA1BRW_);
+#define UCA1BRW_L_ __MSP430_USCI1_BASE__ + 0x06
+sfrb(UCA1BRW_L, UCA1BRW_L_);
+#define UCA1BRW_H_ __MSP430_USCI1_BASE__ + 0x07
+sfrb(UCA1BRW_H, UCA1BRW_H_);
+#define UCA1BR0 UCA1BRW_L /* USCI A1 Baud Rate 0 */
+#define UCA1BR1 UCA1BRW_H /* USCI A1 Baud Rate 1 */
+#define UCA1MCTL_ __MSP430_USCI1_BASE__ + 0x08 /* USCI A1 Modulation Control */
+sfrb(UCA1MCTL, UCA1MCTL_);
+#define UCA1STAT_ __MSP430_USCI1_BASE__ + 0x0a /* USCI A1 Status Register */
+sfrb(UCA1STAT, UCA1STAT_);
+#define UCA1RXBUF_ __MSP430_USCI1_BASE__ + 0x0c /* USCI A1 Receive Buffer */
+sfrb(UCA1RXBUF, UCA1RXBUF_);
+#define UCA1TXBUF_ __MSP430_USCI1_BASE__ + 0x0e /* USCI A1 Transmit Buffer */
+sfrb(UCA1TXBUF, UCA1TXBUF_);
+#define UCA1ABCTL_ __MSP430_USCI1_BASE__ + 0x10 /* USCI A1 LIN Control */
+sfrb(UCA1ABCTL, UCA1ABCTL_);
+#define UCA1IRCTL_ __MSP430_USCI1_BASE__ + 0x12 /* USCI A1 IrDA Transmit Control */
+sfrw(UCA1IRCTL, UCA1IRCTL_);
+#define UCA1IRCTL_L_ __MSP430_USCI1_BASE__ + 0x12
+sfrb(UCA1IRCTL_L, UCA1IRCTL_L_);
+#define UCA1IRCTL_H_ __MSP430_USCI1_BASE__ + 0x13
+sfrb(UCA1IRCTL_H, UCA1IRCTL_H_);
+#define UCA1IRTCTL UCA1IRCTL_L /* USCI A1 IrDA Transmit Control */
+#define UCA1IRRCTL UCA1IRCTL_H /* USCI A1 IrDA Receive Control */
+#define UCA1ICTL_ __MSP430_USCI1_BASE__ + 0x1c /* USCI A1 Interrupt Enable Register */
+sfrw(UCA1ICTL, UCA1ICTL_);
+#define UCA1ICTL_L_ __MSP430_USCI1_BASE__ + 0x1c
+sfrb(UCA1ICTL_L, UCA1ICTL_L_);
+#define UCA1ICTL_H_ __MSP430_USCI1_BASE__ + 0x1d
+sfrb(UCA1ICTL_H, UCA1ICTL_H_);
+#define UCA1IE UCA1ICTL_L /* USCI A1 Interrupt Enable Register */
+#define UCA1IFG UCA1ICTL_H /* USCI A1 Interrupt Flags Register */
+#define UCA1IV_ __MSP430_USCI1_BASE__ + 0x1e /* USCI A1 Interrupt Vector Register */
+sfrw(UCA1IV, UCA1IV_);
+#endif // __MSP430_HAS_USCI_A1__
+
+#if defined(__MSP430_HAS_USCI_B1__)
+/************************************************************
+* USCI B1
+************************************************************/
+#define UCB1CTLW0_ __MSP430_USCI1_BASE__ + 0x20 /* USCI B1 Control Word Register 0 */
+sfrw(UCB1CTLW0, UCB1CTLW0_);
+#define UCB1CTLW0_L_ __MSP430_USCI1_BASE__ + 0x20
+sfrb(UCB1CTLW0_L, UCB1CTLW0_L_);
+#define UCB1CTLW0_H_ __MSP430_USCI1_BASE__ + 0x21
+sfrb(UCB1CTLW0_H, UCB1CTLW0_H_);
+#define UCB1CTL1 UCB1CTLW0_L /* USCI B1 Control Register 1 */
+#define UCB1CTL0 UCB1CTLW0_H /* USCI B1 Control Register 0 */
+#define UCB1BRW_ __MSP430_USCI1_BASE__ + 0x26 /* USCI B1 Baud Word Rate 0 */
+sfrw(UCB1BRW, UCB1BRW_);
+#define UCB1BRW_L_ __MSP430_USCI1_BASE__ + 0x26
+sfrb(UCB1BRW_L, UCB1BRW_L_);
+#define UCB1BRW_H_ __MSP430_USCI1_BASE__ + 0x27
+sfrb(UCB1BRW_H, UCB1BRW_H_);
+#define UCB1BR0 UCB1BRW_L /* USCI B1 Baud Rate 0 */
+#define UCB1BR1 UCB1BRW_H /* USCI B1 Baud Rate 1 */
+#define UCB1STAT_ __MSP430_USCI1_BASE__ + 0x2a /* USCI B1 Status Register */
+sfrb(UCB1STAT, UCB1STAT_);
+#define UCB1RXBUF_ __MSP430_USCI1_BASE__ + 0x2c /* USCI B1 Receive Buffer */
+sfrb(UCB1RXBUF, UCB1RXBUF_);
+#define UCB1TXBUF_ __MSP430_USCI1_BASE__ + 0x2e /* USCI B1 Transmit Buffer */
+sfrb(UCB1TXBUF, UCB1TXBUF_);
+#define UCB1I2COA_ __MSP430_USCI1_BASE__ + 0x30 /* USCI B1 I2C Own Address */
+sfrw(UCB1I2COA, UCB1I2COA_);
+#define UCB1I2COA_L_ __MSP430_USCI1_BASE__ + 0x30
+sfrb(UCB1I2COA_L, UCB1I2COA_L_);
+#define UCB1I2COA_H_ __MSP430_USCI1_BASE__ + 0x31
+sfrb(UCB1I2COA_H, UCB1I2COA_H_);
+#define UCB1I2CSA_ __MSP430_USCI1_BASE__ + 0x32 /* USCI B1 I2C Slave Address */
+sfrw(UCB1I2CSA, UCB1I2CSA_);
+#define UCB1I2CSA_L_ __MSP430_USCI1_BASE__ + 0x32
+sfrb(UCB1I2CSA_L, UCB1I2CSA_L_);
+#define UCB1I2CSA_H_ __MSP430_USCI1_BASE__ + 0x33
+sfrb(UCB1I2CSA_H, UCB1I2CSA_H_);
+#define UCB1ICTL_ __MSP430_USCI1_BASE__ + 0x3c /* USCI B1 Interrupt Enable Register */
+sfrw(UCB1ICTL, UCB1ICTL_);
+#define UCB1ICTL_L_ __MSP430_USCI1_BASE__ + 0x3c
+sfrb(UCB1ICTL_L, UCB1ICTL_L_);
+#define UCB1ICTL_H_ __MSP430_USCI1_BASE__ + 0x3d
+sfrb(UCB1ICTL_H, UCB1ICTL_H_);
+#define UCB1IE UCB1ICTL_L /* USCI B1 Interrupt Enable Register */
+#define UCB1IFG UCB1ICTL_H /* USCI B1 Interrupt Flags Register */
+#define UCB1IV_ __MSP430_USCI1_BASE__ + 0x3e /* USCI B1 Interrupt Vector Register */
+sfrw(UCB1IV, UCB1IV_);
+#endif // __MSP430_HAS_USCI_B1__
+
+#endif // __MSP430_USCI1_BASE__
+
+#if defined(__MSP430_USCI2_BASE__)
+
+#if defined(__MSP430_HAS_USCI_A2__)
+/************************************************************
+* USCI A2
+************************************************************/
+#define UCA2CTLW0_ __MSP430_USCI2_BASE__ + 0x00 /* USCI A2 Control Word Register 0 */
+sfrw(UCA2CTLW0, UCA2CTLW0_);
+#define UCA2CTLW0_L_ __MSP430_USCI2_BASE__ + 0x00
+sfrb(UCA2CTLW0_L, UCA2CTLW0_L_);
+#define UCA2CTLW0_H_ __MSP430_USCI2_BASE__ + 0x01
+sfrb(UCA2CTLW0_H, UCA2CTLW0_H_);
+#define UCA2CTL1 UCA2CTLW0_L /* USCI A2 Control Register 1 */
+#define UCA2CTL0 UCA2CTLW0_H /* USCI A2 Control Register 0 */
+#define UCA2BRW_ __MSP430_USCI2_BASE__ + 0x06 /* USCI A2 Baud Word Rate 0 */
+sfrw(UCA2BRW, UCA2BRW_);
+#define UCA2BRW_L_ __MSP430_USCI2_BASE__ + 0x06
+sfrb(UCA2BRW_L, UCA2BRW_L_);
+#define UCA2BRW_H_ __MSP430_USCI2_BASE__ + 0x07
+sfrb(UCA2BRW_H, UCA2BRW_H_);
+#define UCA2BR0 UCA2BRW_L /* USCI A2 Baud Rate 0 */
+#define UCA2BR1 UCA2BRW_H /* USCI A2 Baud Rate 1 */
+#define UCA2MCTL_ __MSP430_USCI2_BASE__ + 0x08 /* USCI A2 Modulation Control */
+sfrb(UCA2MCTL, UCA2MCTL_);
+#define UCA2STAT_ __MSP430_USCI2_BASE__ + 0x0a /* USCI A2 Status Register */
+sfrb(UCA2STAT, UCA2STAT_);
+#define UCA2RXBUF_ __MSP430_USCI2_BASE__ + 0x0c /* USCI A2 Receive Buffer */
+sfrb(UCA2RXBUF, UCA2RXBUF_);
+#define UCA2TXBUF_ __MSP430_USCI2_BASE__ + 0x0e /* USCI A2 Transmit Buffer */
+sfrb(UCA2TXBUF, UCA2TXBUF_);
+#define UCA2ABCTL_ __MSP430_USCI2_BASE__ + 0x10 /* USCI A2 LIN Control */
+sfrb(UCA2ABCTL, UCA2ABCTL_);
+#define UCA2IRCTL_ __MSP430_USCI2_BASE__ + 0x12 /* USCI A2 IrDA Transmit Control */
+sfrw(UCA2IRCTL, UCA2IRCTL_);
+#define UCA2IRCTL_L_ __MSP430_USCI2_BASE__ + 0x12
+sfrb(UCA2IRCTL_L, UCA2IRCTL_L_);
+#define UCA2IRCTL_H_ __MSP430_USCI2_BASE__ + 0x13
+sfrb(UCA2IRCTL_H, UCA2IRCTL_H_);
+#define UCA2IRTCTL UCA2IRCTL_L /* USCI A2 IrDA Transmit Control */
+#define UCA2IRRCTL UCA2IRCTL_H /* USCI A2 IrDA Receive Control */
+#define UCA2ICTL_ __MSP430_USCI2_BASE__ + 0x1c /* USCI A2 Interrupt Enable Register */
+sfrw(UCA2ICTL, UCA2ICTL_);
+#define UCA2ICTL_L_ __MSP430_USCI2_BASE__ + 0x1c
+sfrb(UCA2ICTL_L, UCA2ICTL_L_);
+#define UCA2ICTL_H_ __MSP430_USCI2_BASE__ + 0x1d
+sfrb(UCA2ICTL_H, UCA2ICTL_H_);
+#define UCA2IE UCA2ICTL_L /* USCI A2 Interrupt Enable Register */
+#define UCA2IFG UCA2ICTL_H /* USCI A2 Interrupt Flags Register */
+#define UCA2IV_ __MSP430_USCI2_BASE__ + 0x1e /* USCI A2 Interrupt Vector Register */
+sfrw(UCA2IV, UCA2IV_);
+#endif // __MSP430_HAS_USCI_A2__
+
+#if defined(__MSP430_HAS_USCI_B2__)
+/************************************************************
+* USCI B2
+************************************************************/
+#define UCB2CTLW0_ __MSP430_USCI2_BASE__ + 0x20 /* USCI B2 Control Word Register 0 */
+sfrw(UCB2CTLW0, UCB2CTLW0_);
+#define UCB2CTLW0_L_ __MSP430_USCI2_BASE__ + 0x20
+sfrb(UCB2CTLW0_L, UCB2CTLW0_L_);
+#define UCB2CTLW0_H_ __MSP430_USCI2_BASE__ + 0x21
+sfrb(UCB2CTLW0_H, UCB2CTLW0_H_);
+#define UCB2CTL1 UCB2CTLW0_L /* USCI B2 Control Register 1 */
+#define UCB2CTL0 UCB2CTLW0_H /* USCI B2 Control Register 0 */
+#define UCB2BRW_ __MSP430_USCI2_BASE__ + 0x26 /* USCI B2 Baud Word Rate 0 */
+sfrw(UCB2BRW, UCB2BRW_);
+#define UCB2BRW_L_ __MSP430_USCI2_BASE__ + 0x26
+sfrb(UCB2BRW_L, UCB2BRW_L_);
+#define UCB2BRW_H_ __MSP430_USCI2_BASE__ + 0x27
+sfrb(UCB2BRW_H, UCB2BRW_H_);
+#define UCB2BR0 UCB2BRW_L /* USCI B2 Baud Rate 0 */
+#define UCB2BR1 UCB2BRW_H /* USCI B2 Baud Rate 1 */
+#define UCB2STAT_ __MSP430_USCI2_BASE__ + 0x2a /* USCI B2 Status Register */
+sfrb(UCB2STAT, UCB2STAT_);
+#define UCB2RXBUF_ __MSP430_USCI2_BASE__ + 0x2c /* USCI B2 Receive Buffer */
+sfrb(UCB2RXBUF, UCB2RXBUF_);
+#define UCB2TXBUF_ __MSP430_USCI2_BASE__ + 0x2e /* USCI B2 Transmit Buffer */
+sfrb(UCB2TXBUF, UCB2TXBUF_);
+#define UCB2I2COA_ __MSP430_USCI2_BASE__ + 0x30 /* USCI B2 I2C Own Address */
+sfrw(UCB2I2COA, UCB2I2COA_);
+#define UCB2I2COA_L_ __MSP430_USCI2_BASE__ + 0x30
+sfrb(UCB2I2COA_L, UCB2I2COA_L_);
+#define UCB2I2COA_H_ __MSP430_USCI2_BASE__ + 0x31
+sfrb(UCB2I2COA_H, UCB2I2COA_H_);
+#define UCB2I2CSA_ __MSP430_USCI2_BASE__ + 0x32 /* USCI B2 I2C Slave Address */
+sfrw(UCB2I2CSA, UCB2I2CSA_);
+#define UCB2I2CSA_L_ __MSP430_USCI2_BASE__ + 0x32
+sfrb(UCB2I2CSA_L, UCB2I2CSA_L_);
+#define UCB2I2CSA_H_ __MSP430_USCI2_BASE__ + 0x33
+sfrb(UCB2I2CSA_H, UCB2I2CSA_H_);
+#define UCB2ICTL_ __MSP430_USCI2_BASE__ + 0x3c /* USCI B2 Interrupt Enable Register */
+sfrw(UCB2ICTL, UCB2ICTL_);
+#define UCB2ICTL_L_ __MSP430_USCI2_BASE__ + 0x3c
+sfrb(UCB2ICTL_L, UCB2ICTL_L_);
+#define UCB2ICTL_H_ __MSP430_USCI2_BASE__ + 0x3d
+sfrb(UCB2ICTL_H, UCB2ICTL_H_);
+#define UCB2IE UCB2ICTL_L /* USCI B2 Interrupt Enable Register */
+#define UCB2IFG UCB2ICTL_H /* USCI B2 Interrupt Flags Register */
+#define UCB2IV_ __MSP430_USCI2_BASE__ + 0x3e /* USCI B2 Interrupt Vector Register */
+sfrw(UCB2IV, UCB2IV_);
+#endif // __MSP430_HAS_USCI_B2__
+
+#endif // __MSP430_USCI2_BASE__
+
+#if defined(__MSP430_USCI3_BASE__)
+
+#if defined(__MSP430_HAS_USCI_A3__)
+/************************************************************
+* USCI A3
+************************************************************/
+#define UCA3CTLW0_ __MSP430_USCI3_BASE__ + 0x00 /* USCI A3 Control Word Register 0 */
+sfrw(UCA3CTLW0, UCA3CTLW0_);
+#define UCA3CTLW0_L_ __MSP430_USCI3_BASE__ + 0x00
+sfrb(UCA3CTLW0_L, UCA3CTLW0_L_);
+#define UCA3CTLW0_H_ __MSP430_USCI3_BASE__ + 0x01
+sfrb(UCA3CTLW0_H, UCA3CTLW0_H_);
+#define UCA3CTL1 UCA3CTLW0_L /* USCI A3 Control Register 1 */
+#define UCA3CTL0 UCA3CTLW0_H /* USCI A3 Control Register 0 */
+#define UCA3BRW_ __MSP430_USCI3_BASE__ + 0x06 /* USCI A3 Baud Word Rate 0 */
+sfrw(UCA3BRW, UCA3BRW_);
+#define UCA3BRW_L_ __MSP430_USCI3_BASE__ + 0x06
+sfrb(UCA3BRW_L, UCA3BRW_L_);
+#define UCA3BRW_H_ __MSP430_USCI3_BASE__ + 0x07
+sfrb(UCA3BRW_H, UCA3BRW_H_);
+#define UCA3BR0 UCA3BRW_L /* USCI A3 Baud Rate 0 */
+#define UCA3BR1 UCA3BRW_H /* USCI A3 Baud Rate 1 */
+#define UCA3MCTL_ __MSP430_USCI3_BASE__ + 0x08 /* USCI A3 Modulation Control */
+sfrb(UCA3MCTL, UCA3MCTL_);
+#define UCA3STAT_ __MSP430_USCI3_BASE__ + 0x0a /* USCI A3 Status Register */
+sfrb(UCA3STAT, UCA3STAT_);
+#define UCA3RXBUF_ __MSP430_USCI3_BASE__ + 0x0c /* USCI A3 Receive Buffer */
+sfrb(UCA3RXBUF, UCA3RXBUF_);
+#define UCA3TXBUF_ __MSP430_USCI3_BASE__ + 0x0e /* USCI A3 Transmit Buffer */
+sfrb(UCA3TXBUF, UCA3TXBUF_);
+#define UCA3ABCTL_ __MSP430_USCI3_BASE__ + 0x10 /* USCI A3 LIN Control */
+sfrb(UCA3ABCTL, UCA3ABCTL_);
+#define UCA3IRCTL_ __MSP430_USCI3_BASE__ + 0x12 /* USCI A3 IrDA Transmit Control */
+sfrw(UCA3IRCTL, UCA3IRCTL_);
+#define UCA3IRCTL_L_ __MSP430_USCI3_BASE__ + 0x12
+sfrb(UCA3IRCTL_L, UCA3IRCTL_L_);
+#define UCA3IRCTL_H_ __MSP430_USCI3_BASE__ + 0x13
+sfrb(UCA3IRCTL_H, UCA3IRCTL_H_);
+#define UCA3IRTCTL UCA3IRCTL_L /* USCI A3 IrDA Transmit Control */
+#define UCA3IRRCTL UCA3IRCTL_H /* USCI A3 IrDA Receive Control */
+#define UCA3ICTL_ __MSP430_USCI3_BASE__ + 0x1c /* USCI A3 Interrupt Enable Register */
+sfrw(UCA3ICTL, UCA3ICTL_);
+#define UCA3ICTL_L_ __MSP430_USCI3_BASE__ + 0x1c
+sfrb(UCA3ICTL_L, UCA3ICTL_L_);
+#define UCA3ICTL_H_ __MSP430_USCI3_BASE__ + 0x1d
+sfrb(UCA3ICTL_H, UCA3ICTL_H_);
+#define UCA3IE UCA3ICTL_L /* USCI A3 Interrupt Enable Register */
+#define UCA3IFG UCA3ICTL_H /* USCI A3 Interrupt Flags Register */
+#define UCA3IV_ __MSP430_USCI3_BASE__ + 0x1e /* USCI A3 Interrupt Vector Register */
+sfrw(UCA3IV, UCA3IV_);
+#endif // __MSP430_HAS_USCI_A3__
+
+#if defined(__MSP430_HAS_USCI_B3__)
+/************************************************************
+* USCI B3
+************************************************************/
+#define UCB3CTLW0_ __MSP430_USCI3_BASE__ + 0x20 /* USCI B3 Control Word Register 0 */
+sfrw(UCB3CTLW0, UCB3CTLW0_);
+#define UCB3CTLW0_L_ __MSP430_USCI3_BASE__ + 0x20
+sfrb(UCB3CTLW0_L, UCB3CTLW0_L_);
+#define UCB3CTLW0_H_ __MSP430_USCI3_BASE__ + 0x21
+sfrb(UCB3CTLW0_H, UCB3CTLW0_H_);
+#define UCB3CTL1 UCB3CTLW0_L /* USCI B3 Control Register 1 */
+#define UCB3CTL0 UCB3CTLW0_H /* USCI B3 Control Register 0 */
+#define UCB3BRW_ __MSP430_USCI3_BASE__ + 0x26 /* USCI B3 Baud Word Rate 0 */
+sfrw(UCB3BRW, UCB3BRW_);
+#define UCB3BRW_L_ __MSP430_USCI3_BASE__ + 0x26
+sfrb(UCB3BRW_L, UCB3BRW_L_);
+#define UCB3BRW_H_ __MSP430_USCI3_BASE__ + 0x27
+sfrb(UCB3BRW_H, UCB3BRW_H_);
+#define UCB3BR0 UCB3BRW_L /* USCI B3 Baud Rate 0 */
+#define UCB3BR1 UCB3BRW_H /* USCI B3 Baud Rate 1 */
+#define UCB3STAT_ __MSP430_USCI3_BASE__ + 0x2a /* USCI B3 Status Register */
+sfrb(UCB3STAT, UCB3STAT_);
+#define UCB3RXBUF_ __MSP430_USCI3_BASE__ + 0x2c /* USCI B3 Receive Buffer */
+sfrb(UCB3RXBUF, UCB3RXBUF_);
+#define UCB3TXBUF_ __MSP430_USCI3_BASE__ + 0x2e /* USCI B3 Transmit Buffer */
+sfrb(UCB3TXBUF, UCB3TXBUF_);
+#define UCB3I2COA_ __MSP430_USCI3_BASE__ + 0x30 /* USCI B3 I2C Own Address */
+sfrw(UCB3I2COA, UCB3I2COA_);
+#define UCB3I2COA_L_ __MSP430_USCI3_BASE__ + 0x30
+sfrb(UCB3I2COA_L, UCB3I2COA_L_);
+#define UCB3I2COA_H_ __MSP430_USCI3_BASE__ + 0x31
+sfrb(UCB3I2COA_H, UCB3I2COA_H_);
+#define UCB3I2CSA_ __MSP430_USCI3_BASE__ + 0x32 /* USCI B3 I2C Slave Address */
+sfrw(UCB3I2CSA, UCB3I2CSA_);
+#define UCB3I2CSA_L_ __MSP430_USCI3_BASE__ + 0x32
+sfrb(UCB3I2CSA_L, UCB3I2CSA_L_);
+#define UCB3I2CSA_H_ __MSP430_USCI3_BASE__ + 0x33
+sfrb(UCB3I2CSA_H, UCB3I2CSA_H_);
+#define UCB3ICTL_ __MSP430_USCI3_BASE__ + 0x3c /* USCI B3 Interrupt Enable Register */
+sfrw(UCB3ICTL, UCB3ICTL_);
+#define UCB3ICTL_L_ __MSP430_USCI3_BASE__ + 0x3c
+sfrb(UCB3ICTL_L, UCB3ICTL_L_);
+#define UCB3ICTL_H_ __MSP430_USCI3_BASE__ + 0x3d
+sfrb(UCB3ICTL_H, UCB3ICTL_H_);
+#define UCB3IE UCB3ICTL_L /* USCI B3 Interrupt Enable Register */
+#define UCB3IFG UCB3ICTL_H /* USCI B3 Interrupt Flags Register */
+#define UCB3IV_ __MSP430_USCI3_BASE__ + 0x3e /* USCI B3 Interrupt Vector Register */
+sfrw(UCB3IV, UCB3IV_);
+#endif // __MSP430_HAS_USCI_B3__
+
+#endif // __MSP430_USCI3_BASE__
+
+#endif /* __MSP430_HEADERS_USCI_5XX_H__ */
+
--- /dev/null
+#ifndef __MSP430_HEADERS_WDT_A_H
+#define __MSP430_HEADERS_WDT_A_H
+
+/* wdt_a.h
+ *
+ * mspgcc project: MSP430 device headers
+ * watchdog timer module
+ *
+ * (c) 2008 by Sergey A. Borshch <sb-sf@users.sf.net>
+ * Originally based in MSP430F543x datasheet (slas609)
+ * and MSP430x5xx Family User's Guide (slau208).
+ *
+ * $Id: wdt_a.h,v 1.6 2009/02/28 12:14:53 sb-sf Exp $
+ */
+
+/* Switches:
+
+__MSP430_WDT_A_BASE__ - base address of WDT_A module
+
+*/
+
+#define WDTCTL_ __MSP430_WDT_A_BASE__ + 0x0C /* Watchdog timer control register */
+sfrw(WDTCTL, WDTCTL_);
+
+/* WDTCTL */
+#define WDTPW (0x5A<<8) /* Watchdog timer password. Always read as 069h. Must be written as 05Ah, or a PUC will be generated */
+#define WDTHOLD (1<<7) /* Watchdog timer hold */
+#define WDTSSEL1 (1<<6) /* Watchdog timer clock source select */
+#define WDTSSEL0 (1<<5) /* Watchdog timer clock source select */
+#define WDTTMSEL (1<<4) /* Watchdog timer mode select */
+#define WDTCNTCL (1<<3) /* Watchdog timer counter clear */
+#define WDTIS2 (1<<2) /* Watchdog timer interval select */
+#define WDTIS1 (1<<1) /* Watchdog timer interval select */
+#define WDTIS0 (1<<0) /* Watchdog timer interval select */
+
+/* Aliases by mspgcc */
+#define WDTIS_0 (0<<0) /* Watchdog timer /2G */
+#define WDTIS__2G WDTIS_0
+#define WDTIS_1 (1<<0) /* Watchdog timer /128M */
+#define WDTIS__128M WDTIS_1
+#define WDTIS_2 (2<<0) /* Watchdog timer /8192K */
+#define WDTIS__8192K WDTIS_2
+#define WDTIS_3 (3<<0) /* Watchdog timer /512K */
+#define WDTIS__512K WDTIS_3
+#define WDTIS_4 (4<<0) /* Watchdog timer /32K */
+#define WDTIS__32K WDTIS_4
+#define WDTIS_5 (5<<0) /* Watchdog timer /8192 */
+#define WDTIS__8192 WDTIS_5
+#define WDTIS_6 (6<<0) /* Watchdog timer /512 */
+#define WDTIS__512 WDTIS_6
+#define WDTIS_7 (7<<0) /* Watchdog timer /64 */
+#define WDTIS__64 WDTIS_7
+
+#define WDTSSEL_0 (0<<5) /* Watchdog clock SMCLK */
+#define WDTSSEL__SMCLK WDTSSEL_0
+#define WDTSSEL_1 (1<<5) /* Watchdog clock ACLK */
+#define WDTSSEL__ACLK WDTSSEL_1
+#define WDTSSEL_2 (2<<5) /* Watchdog clock VLOCLK */
+#define WDTSSEL__VLO WDTSSEL_2
+#define WDTSSEL_3 (3<<5) /* Watchdog clock X_CLK */
+
+/* WDT-interval times [1ms] coded with Bits 0-2 */
+/* WDT is clocked by fMCLK (assumed 1MHz) */
+#define WDT_SMDLY_2147S (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_0) /* 2147s */
+#define WDT_SMDLY_134S (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_1) /* 134s */
+#define WDT_SMDLY_8S (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_2) /* 8.38s */
+#define WDT_SMDLY_500MS (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_3) /* 524ms */
+#define WDT_SMDLY_32 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_4) /* 32ms interval (default) */
+#define WDT_SMDLY_8 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_5) /* 8ms */
+#define WDT_SMDLY_0_5 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_6) /* 0.5ms */
+#define WDT_SMDLY_0_064 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_7) /* 0.064ms */
+/* WDT is clocked by fACLK (assumed 32KHz) */
+#define WDT_ADLY_65536S (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_0) /* 65536s */
+#define WDT_ADLY_4096S (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_1) /* 4096s */
+#define WDT_ADLY_256S (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_2) /* 256s */
+#define WDT_ADLY_16S (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_3) /* 16s */
+#define WDT_ADLY_1000 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_4) /* 1000ms */
+#define WDT_ADLY_250 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_5) /* 250ms */
+#define WDT_ADLY_16 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_6) /* 16ms */
+#define WDT_ADLY_1_9 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_7) /* 1.9ms */
+/* Watchdog mode -> reset after expired time */
+/* WDT is clocked by fSMCLK (assumed 1MHz) */
+#define WDT_SMRST_2147S (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_0) /* 2147s */
+#define WDT_SMRST_134S (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_1) /* 134s */
+#define WDT_SMRST_8S (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_2) /* 8.38s */
+#define WDT_SMRST_500MS (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_3) /* 524ms */
+#define WDT_SMRST_32 (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_4) /* 32ms interval (default) */
+#define WDT_SMRST_8 (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_5) /* 8ms */
+#define WDT_SMRST_0_5 (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_6) /* 0.5ms */
+#define WDT_SMRST_0_064 (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_7) /* 0.064ms */
+/* WDT is clocked by fACLK (assumed 32KHz) */
+#define WDT_ARST_65536S (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_0) /* 65536s */
+#define WDT_ARST_4096S (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_1) /* 4096s */
+#define WDT_ARST_256S (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_2) /* 256s */
+#define WDT_ARST_16S (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_3) /* 16s */
+#define WDT_ARST_1000 (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_4) /* 1s */
+#define WDT_ARST_250 (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_5) /* 250ms */
+#define WDT_ARST_16 (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_6) /* 16ms */
+#define WDT_ARST_1_9 (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_7) /* 1.9ms */
+
+#ifndef __ASSEMBLER__
+/* Structured declaration */
+
+#undef __xstr
+#undef __str
+#define __xstr(x) __str(x)
+#define __str(x) #x
+struct
+{
+ volatile unsigned
+ IS0:3,
+ CNTCL:1,
+ TMSEL:1,
+ SSEL:2,
+ HOLD:1,
+ PW:8;
+} const WDTCTL_bits asm(__xstr(__MSP430_WDT_A_BASE__ + 0x0C)); /* Watchdog timer control register */
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* __MSP430_HEADERS_SYS_H */
* (c) 2005 by Steve Underwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: msp430x20x3.h,v 1.5 2006/11/16 01:19:37 coppice Exp $
+ * $Id: msp430x20x3.h,v 1.7 2009/01/11 23:11:48 sb-sf Exp $
*/
#include <iomacros.h>
#define __MSP430_HAS_TA2__
#define __MSP430_HAS_BC2__
#define __MSP430_HAS_FLASH2__
-#define __MSP430_HAS_SD16_1__
+#define __MSP430_HAS_SD16_A__
+#define __MSP430_HAS_SD16_BUF__
+#define __MSP430_HAS_SD16_CH1__
+#define __MSP430_SD16IV_BASE__ 0x110
+#define __MSP430_SD16MEM_BASE__ 0x112
#define __MSP430_HAS_USI__
-#define __msp430_have_sd16a
#include <msp430/basic_clock.h>
#include <msp430/flash.h>
--- /dev/null
+#ifndef __msp430x21x2
+#define __msp430x21x2
+
+/* msp430x21x2.h
+ *
+ * mspgcc project: MSP430 device headers
+ * MSP430x11x2 family header
+ *
+ * (c) 2005 by Steve Underwood <steveu@coppice.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * 2008-09-17 - sb-sf (sb-sf@users.sf.net)
+ * - created, based on msp430x21x1.h
+ *
+ * $Id: msp430x21x2.h,v 1.2 2009/02/27 02:16:38 cliechti Exp $
+ */
+
+#include <iomacros.h>
+
+#define __MSP430_HAS_WDT__
+#define __MSP430_HAS_PORT1_R__
+#define __MSP430_HAS_PORT2_R__
+#define __MSP430_HAS_PORT3_R__
+#define __MSP430_HAS_USCI_AB0__
+#define __MSP430_HAS_TA3__
+#define __MSP430_HAS_T1A2__
+#define __MSP430_HAS_BC2__
+#define __MSP430_HAS_FLASH2__
+#define __MSP430_HAS_CAPLUS__
+#define __MSP430_HAS_ADC10__
+#define __MSP430_HAS_TLV__
+
+#include <msp430/basic_clock.h>
+#include <msp430/flash.h>
+#include <msp430/eprom.h>
+#include <msp430/timera.h>
+#include <msp430/gpio.h>
+#include <msp430/compa.h>
+#include <msp430/usci.h>
+#include <msp430/adc10.h>
+#include <msp430/tlv.h>
+
+#include <msp430/common.h>
+
+#define IE1_ 0x0000 /* Interrupt Enable 1 */
+sfrb(IE1,IE1_);
+#define WDTIE (1<<0)
+#define OFIE (1<<1)
+#define NMIIE (1<<4)
+#define ACCVIE (1<<5)
+
+#define IFG1_ 0x0002 /* Interrupt Flag 1 */
+sfrb(IFG1,IFG1_);
+#define WDTIFG (1<<0)
+#define OFIFG (1<<1)
+#define NMIIFG (1<<4)
+
+#define IE2_ 0x0001 /* Interrupt Enable 2 */
+sfrb(IE2,IE2_);
+#define UC0IE IE2
+#define UCA0RXIE (1<<0)
+#define UCA0TXIE (1<<1)
+#define UCB0RXIE (1<<2)
+#define UCB0TXIE (1<<3)
+
+#define IFG2_ 0x0003 /* Interrupt Flag 2 */
+sfrb(IFG2,IFG2_);
+#define UC0IFG IFG2
+#define UCA0RXIFG (1<<0)
+#define UCA0TXIFG (1<<1)
+#define UCB0RXIFG (1<<2)
+#define UCB0TXIFG (1<<3)
+
+#define PORT1_VECTOR 4 /* 0xFFE4 Port 1 */
+#define PORT2_VECTOR 6 /* 0xFFE6 Port 2 */
+#define ADC10_VECTOR 10 /* 0xFFEA ADC10 */
+#define USCIAB0TX_VECTOR 12 /* 0xFFEC USCI A0/B0 Transmit */
+#define USCIAB0RX_VECTOR 14 /* 0xFFEE USCI A0/B0 Receive */
+#define TIMER0_A1_VECTOR 16 /* 0xFFF0 Timer A0 CC1-2, TA */
+#define TIMER0_A0_VECTOR 18 /* 0xFFF2 Timer A0 CC0 */
+#define WDT_VECTOR 20 /* 0xFFF4 Watchdog Timer */
+#define COMPARATORA_VECTOR 22 /* 0xFFF6 Comparator A */
+#define TIMER1_A1_VECTOR 24 /* 0xFFF8 Timer A1 CC1, TA */
+#define TIMER1_A0_VECTOR 26 /* 0xFFFA Timer A1 CC0 */
+#define NMI_VECTOR 28 /* 0xFFFC Non-maskable */
+
+#define BSLSKEY_ 0xFFDE /* The address is used as bootstrap loader security key */
+#define BSLSKEY_DISABLE 0xAA55 /* Disables the BSL completely */
+#define BSLSKEY_NO_ERASE 0x0000 /* Disables the erasure of the flash if an invalid password is supplied */
+
+#endif /* #ifndef __msp430x21x2 */
+
* (c) 2007 by Steve Underwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: msp430x22x2.h,v 1.2 2008/06/18 00:54:02 cliechti Exp $
+ * $Id: msp430x22x2.h,v 1.3 2009/07/26 05:53:27 pjansen Exp $
*/
#include <iomacros.h>
#define __MSP430_HAS_BC2__
#define __MSP430_HAS_FLASH2__
#define __MSP430_HAS_USCI__
+#define __MSP430_HAS_USCI0__
#include <msp430/basic_clock.h>
#include <msp430/flash.h>
* (c) 2005 by Steve Underwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: msp430x22x4.h,v 1.7 2008/06/18 00:54:02 cliechti Exp $
+ * $Id: msp430x22x4.h,v 1.8 2009/07/26 05:53:27 pjansen Exp $
*/
#include <iomacros.h>
#define __MSP430_HAS_FLASH2__
#define __MSP430_HAS_OA_2__
#define __MSP430_HAS_USCI__
+#define __MSP430_HAS_USCI0__
#define __msp430_have_opamp_1
#define __msp430_have_opamp_output_select
* (c) 2007 by Steve Underwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: msp430x23x.h,v 1.1 2008/06/18 00:04:40 cliechti Exp $
+ * $Id: msp430x23x.h,v 1.2 2009/07/26 05:53:27 pjansen Exp $
*/
#include <iomacros.h>
#define __MSP430_HAS_BC2__
#define __MSP430_HAS_FLASH2__
#define __MSP430_HAS_USCI__
+#define __MSP430_HAS_USCI0__
#define __MSP430_HAS_CAPLUS__
#define __MSP430_HAS_MPY__
* (c) 2007 by Steve Underwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: msp430x23x0.h,v 1.3 2008/06/18 00:54:03 cliechti Exp $
+ * $Id: msp430x23x0.h,v 1.4 2009/07/26 05:53:27 pjansen Exp $
*/
#include <iomacros.h>
#define __MSP430_HAS_BC2__
#define __MSP430_HAS_FLASH2__
#define __MSP430_HAS_USCI__
+#define __MSP430_HAS_USCI0__
#define __MSP430_HAS_CAPLUS__
#define __MSP430_HAS_MPY__
* (c) 2007 by Steve Underwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: msp430x241x.h,v 1.5 2008/06/18 22:25:51 cliechti Exp $
+ * $Id: msp430x241x.h,v 1.8 2009/07/26 05:53:27 pjansen Exp $
*
* 2008-03-06 - modifications by M Barnes
* - changed to 241x series, in line with patch by G. Lemm
#define __MSP430_HAS_PORT6_R__
#define __MSP430_HAS_SVS__
#define __MSP430_HAS_USCI__
+#define __MSP430_HAS_USCI0__
#define __MSP430_HAS_USCI1__
#define __MSP430_HAS_USCI_AB0__
#define __MSP430_HAS_USCI_AB1__
#define __MSP430_HAS_FLASH2__
#define __MSP430_HAS_CAPLUS__
#define __MSP430_HAS_ADC12__
-#define __MSP430_HAS_DAC12__
-#define __MSP430_HAS_DMA__
#include <msp430/mpy.h>
#include <msp430/gpio.h>
+#include <msp430/svs.h>
#include <msp430/usci.h>
#include <msp430/timera.h>
#include <msp430/timerb.h>
#include <msp430/flash.h>
#include <msp430/compa.h>
#include <msp430/adc12.h>
-#include <msp430/dac12.h>
-#include <msp430/dma.h>
#include <msp430/common.h>
#define IE1_ 0x0000 /* Interrupt Enable 1 */
* (c) 2007 by Steve Underwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: msp430x24x.h,v 1.6 2008/06/18 22:25:51 cliechti Exp $
+ * $Id: msp430x24x.h,v 1.8 2009/07/26 05:53:27 pjansen Exp $
*
* 2008-02-05 - modifications by G.Lemm <msp430@daqtix.com>
* - defined __DisableCalData to get rid of assembler errors
#define __MSP430_HAS_PORT6_R__
#define __MSP430_HAS_SVS__
#define __MSP430_HAS_USCI__
+#define __MSP430_HAS_USCI0__
#define __MSP430_HAS_USCI1__
#define __MSP430_HAS_USCI_AB0__
#define __MSP430_HAS_USCI_AB1__
#include <msp430/mpy.h>
#include <msp430/gpio.h>
+#include <msp430/svs.h>
#include <msp430/usci.h>
#include <msp430/timera.h>
#include <msp430/timerb.h>
* (c) 2007 by Steve Underwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: msp430x24x1.h,v 1.6 2008/06/18 22:25:52 cliechti Exp $
+ * $Id: msp430x24x1.h,v 1.8 2009/07/26 05:53:27 pjansen Exp $
*/
#include <iomacros.h>
#define __MSP430_HAS_PORT6_R__
#define __MSP430_HAS_SVS__
#define __MSP430_HAS_USCI__
+#define __MSP430_HAS_USCI0__
#define __MSP430_HAS_USCI1__
#define __MSP430_HAS_USCI_AB0__
#define __MSP430_HAS_USCI_AB1__
#include <msp430/mpy.h>
#include <msp430/gpio.h>
+#include <msp430/svs.h>
#include <msp430/usci.h>
#include <msp430/timera.h>
#include <msp430/timerb.h>
#define __MSP430_HAS_PORT8_R__
#define __MSP430_HAS_SVS__
#define __MSP430_HAS_USCI__
+#define __MSP430_HAS_USCI0__
#define __MSP430_HAS_USCI1__
#define __MSP430_HAS_USCI_AB0__
#define __MSP430_HAS_USCI_AB1__
#define __MSP430_HAS_CAPLUS__
#define __MSP430_HAS_ADC12__
#define __MSP430_HAS_DMAX_3__
+#define __MSP430_HAS_DMAIV__
#define __MSP430_HAS_DAC12__
#include <msp430/mpy.h>
#include <msp430/gpio.h>
+#include <msp430/svs.h>
#include <msp430/usci.h>
#include <msp430/timera.h>
#include <msp430/timerb.h>
* (c) 2003 by Steve Underwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: msp430x42x.h,v 1.3 2006/06/07 13:01:30 coppice Exp $
+ * $Id: msp430x42x.h,v 1.5 2009/01/11 23:11:48 sb-sf Exp $
*/
#include <iomacros.h>
#define __MSP430_HAS_TA3__
#define __MSP430_HAS_FLASH__
#define __MSP430_HAS_MPY__
-#define __MSP430_HAS_SD16_3__
+#define __MSP430_HAS_SD16_CH1__
+#define __MSP430_HAS_SD16_CH2__
+#define __MSP430_SD16IV_BASE__ 0x110
+#define __MSP430_SD16MEM_BASE__ 0x112
#define __msp430_have_lcd_16_20
#define LCD_BASE 0x90
-#define __msp430_have_sd16_1
-#define __msp430_have_sd16_2
#include <msp430/basic_timer.h>
#include <msp430/system_clock.h>
* (c) 2005 by Steve Underwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: msp430x42x0.h,v 1.5 2006/06/07 13:01:30 coppice Exp $
+ * $Id: msp430x42x0.h,v 1.8 2009/04/03 05:25:33 sb-sf Exp $
*/
#include <iomacros.h>
#define __MSP430_HAS_LCD_A__
#define __MSP430_HAS_TA3__
#define __MSP430_HAS_FLASH__
-#define __MSP430_HAS_SD16_1__
+#define __MSP430_HAS_SD16_A__
+#define __MSP430_HAS_SD16_BUF__
+#define __MSP430_SD16IV_BASE__ 0x110
+#define __MSP430_SD16MEM_BASE__ 0x112
+
#define __MSP430_HAS_DAC12_1__
#define __msp430_have_lcd_a
#define __msp430_have_lcd_16_20
#define LCD_BASE 0x90
-#define __msp430_have_sd16a
#define __msp430_have_dac12_op_amp
#include <msp430/basic_timer.h>
#include <msp430/system_clock.h>
-#include <msp430/svs.h>
#include <msp430/lcd_a.h>
#include <msp430/flash.h>
#include <msp430/timera.h>
* (c) 2002 by M. P. Ashton <data@ieee.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: msp430x43x.h,v 1.9 2006/06/07 13:01:30 coppice Exp $
+ * 2008-09-17 - sb-sf (sb-sf@users.sf.net)
+ * - msp430x43x1 added
+ *
+ * $Id: msp430x43x.h,v 1.10 2008/10/09 15:00:13 sb-sf Exp $
*/
#include <iomacros.h>
#include <msp430/timera.h>
#include <msp430/timerb.h>
#include <msp430/usart.h>
+#if !defined(__MSP430_4351__) && !defined(__MSP430_4361__) && !defined(__MSP430_4371__)
#include <msp430/adc12.h>
+#endif
#include <msp430/gpio.h>
#include <msp430/compa.h>
--- /dev/null
+#if !defined(__msp430x47xx)
+#define __msp430x47xx
+
+/* msp430x47xx.h
+ *
+ * mspgcc project: MSP430 device headers
+ * MSP430x47xx family header
+ *
+ * (c) 2006 by Steve Underwood <steveu@coppice.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * 2008-10-08 - sb-sf (sb-sf@users.sf.net)
+ * - created, based on msp430xG461x.h
+ *
+ * 2009-06-04 - THLN
+ * - for msp430x47xx
+ * - __MSP430_HAS_PORT??_R__ updated
+ *
+ * $Id: msp430x47xx.h,v 1.7 2009/07/26 05:53:27 pjansen Exp $
+ */
+
+#include <iomacros.h>
+
+#define __MSP430_HAS_WDT__
+#define __MSP430_MPY32_BASE__ 0x140
+#define __MSP430_HAS_PORT1_R__
+#define __MSP430_HAS_PORT2_R__
+#define __MSP430_HAS_PORT3_R__
+#define __MSP430_HAS_PORT4_R__
+#define __MSP430_HAS_PORT5_R__
+#define __MSP430_HAS_PORT7_R__
+#define __MSP430_HAS_PORT8_R__
+#define __MSP430_HAS_PORT9_R__
+#define __MSP430_HAS_PORT10_R__
+#define __MSP430_HAS_PORTA__
+#define __MSP430_HAS_PORTB__
+#define __MSP430_HAS_FLLPLUS__
+#define __MSP430_HAS_BT_RTC__
+#define __MSP430_HAS_LCD_A__
+#define __MSP430_HAS_USCI__
+#define __MSP430_HAS_USCI0__
+#define __MSP430_HAS_USCI1__
+#define __MSP430_HAS_USCI_AB0__
+#define __MSP430_HAS_USCI_AB1__
+#define __MSP430_HAS_TA3__
+#define __MSP430_HAS_TB3__
+#define __MSP430_HAS_FLASH__
+#define __MSP430_HAS_COMPA__
+#define __MSP430_HAS_SVS__
+#define __MSP430_HAS_SD16_A__
+#define __MSP430_HAS_SD16_CH1__
+#define __MSP430_HAS_SD16_CH2__
+#if defined(__MSP430_4783__) || defined(__MSP430_4793__)
+#define __MSP430_HAS_SD16_CH3__
+#endif /* __MSP430_47x3__ */
+
+#if defined(__MSP430_47166__) || defined(__MSP430_47176__) || \
+defined(__MSP430_47186__) || defined(__MSP430_47196__)
+#define __MSP430_HAS_SD16_CH3__
+#define __MSP430_HAS_SD16_CH4__
+#define __MSP430_HAS_SD16_CH5__
+#endif
+#if defined(__MSP430_47167__) || defined(__MSP430_47177__) || \
+defined(__MSP430_47187__) || defined(__MSP430_47197__)
+#define __MSP430_HAS_SD16_CH3__
+#define __MSP430_HAS_SD16_CH4__
+#define __MSP430_HAS_SD16_CH5__
+#define __MSP430_HAS_SD16_CH6__
+#endif
+
+#if defined(__MSP430_4784__) || defined(__MSP430_4794__) \
+ || defined(__MSP430_4783__) || defined(__MSP430_4793__)
+#define __MSP430_SD16IV_BASE__ 0x110
+#define __MSP430_SD16MEM_BASE__ 0x112
+#elif defined(__MSP430_47166__) || defined(__MSP430_47176__) \
+ || defined(__MSP430_47186__) || defined(__MSP430_47196__) \
+ || defined(__MSP430_47167__) || defined(__MSP430_47177__) \
+ || defined(__MSP430_47187__) || defined(__MSP430_47197__)
+#define __MSP430_SD16IV_BASE__ 0x1AE
+#define __MSP430_SD16MEM_BASE__ 0x110
+#endif
+
+
+
+
+#define __msp430_have_lcd_16_20
+#define LCD_BASE 0x90
+
+#include <msp430/basic_timer.h>
+#include <msp430/system_clock.h>
+#include <msp430/svs.h>
+#include <msp430/lcd_a.h>
+#include <msp430/flash.h>
+#include <msp430/compa.h>
+#include <msp430/timera.h>
+#include <msp430/timerb.h>
+#include <msp430/usci.h>
+#include <msp430/gpio.h>
+#include <msp430/mpy32.h>
+#include <msp430/sd16.h>
+
+#include <msp430/common.h>
+
+#define IE1_ 0x0000 /* Interrupt Enable 1 */
+sfrb(IE1,IE1_);
+#define WDTIE (1<<0)
+#define OFIE (1<<1)
+#define NMIIE (1<<4)
+#define ACCVIE (1<<5)
+
+#define IFG1_ 0x0002 /* Interrupt Flag 1 */
+sfrb(IFG1,IFG1_);
+#define WDTIFG (1<<0)
+#define OFIFG (1<<1)
+#define NMIIFG (1<<4)
+
+#define IE2_ 0x0001 /* Interrupt Enable 2 */
+sfrb(IE2,IE2_);
+#define UCA0RXIE (1<<0)
+#define UCA0TXIE (1<<1)
+#define UCB0RXIE (1<<2)
+#define UCB0TXIE (1<<3)
+#define BTIE (1<<7)
+
+#define IFG2_ 0x0003 /* Interrupt Flag 2 */
+sfrb(IFG2,IFG2_);
+#define UCA0RXIFG (1<<0)
+#define UCA0TXIFG (1<<1)
+#define UCB0RXIFG (1<<2)
+#define UCB0TXIFG (1<<3)
+#define BTIFG (1<<7)
+
+
+#if !defined(__MSP430X__)
+/* __MSP430_47x3__, __MSP430_47x4__ */
+#define BASICTIMER_VECTOR 0 /* 0xFFE0 Basic Timer / RTC */
+#define PORT2_VECTOR 2 /* 0xFFE2 Port 2 */
+#define USCIAB1TX_VECTOR 4 /* 0xFFE4 USCI A1/B1 Transmit */
+#define USCIAB1RX_VECTOR 6 /* 0xFFE6 USCI A1/B1 Receive */
+#define PORT1_VECTOR 8 /* 0xFFE8 Port 1 */
+#define TIMER0_A1_VECTOR 10 /* 0xFFEA Timer A CC1-2, TA */
+#define TIMER0_A0_VECTOR 12 /* 0xFFEC Timer A CC0 */
+#define SD16_VECTOR 14 /* 0xFFEE ADC */
+#define USCIAB0TX_VECTOR 16 /* 0xFFF0 USCI A0/B0 Transmit */
+#define USCIAB0RX_VECTOR 18 /* 0xFFF2 USCI A0/B0 Receive */
+#define WDT_VECTOR 20 /* 0xFFF4 Watchdog Timer */
+#define COMPARATORA_VECTOR 22 /* 0xFFF6 Comparator A */
+#define TIMER0_B1_VECTOR 24 /* 0xFFF8 Timer B CC1-2, TB */
+#define TIMER0_B0_VECTOR 26 /* 0xFFFA Timer B CC0 */
+#define NMI_VECTOR 28 /* 0xFFFC Non-maskable */
+#else
+/* __MSP430_471x6__, __MSP430_471x7__ */
+#define DMA_VECTOR 30 /* 0xFFDE DMA */
+#define BASICTIMER_VECTOR 32 /* 0xFFE0 Basic Timer / RTC */
+#define PORT2_VECTOR 34 /* 0xFFE2 Port 2 */
+#define USCIAB1TX_VECTOR 36 /* 0xFFE4 USCI A1/B1 Transmit */
+#define USCIAB1RX_VECTOR 38 /* 0xFFE6 USCI A1/B1 Receive */
+#define PORT1_VECTOR 40 /* 0xFFE8 Port 1 */
+#define TIMER0_A1_VECTOR 42 /* 0xFFEA Timer A CC1-2, TA */
+#define TIMER0_A0_VECTOR 44 /* 0xFFEC Timer A CC0 */
+#define SD16_VECTOR 46 /* 0xFFEE ADC */
+#define USCIAB0TX_VECTOR 48 /* 0xFFF0 USCI A0/B0 Transmit */
+#define USCIAB0RX_VECTOR 50 /* 0xFFF2 USCI A0/B0 Receive */
+#define WDT_VECTOR 52 /* 0xFFF4 Watchdog Timer */
+#define COMPARATORA_VECTOR 54 /* 0xFFF6 Comparator A */
+#define TIMER0_B1_VECTOR 56 /* 0xFFF8 Timer B CC1-2, TB */
+#define TIMER0_B0_VECTOR 58 /* 0xFFFA Timer B CC0 */
+#define NMI_VECTOR 60 /* 0xFFFC Non-maskable */
+#endif
+
+#define TIMERA1_VECTOR TIMER0_A1_VECTOR
+#define TIMERA0_VECTOR TIMER0_A0_VECTOR
+#define TIMERB1_VECTOR TIMER0_B1_VECTOR
+#define TIMERB0_VECTOR TIMER0_B0_VECTOR
+
+#endif /* #ifndef __msp430x47xx */
--- /dev/null
+#if !defined(__msp430x54xx)
+#define __msp430x54xx
+
+/* msp430x54xx.h
+ *
+ * mspgcc project: MSP430 device headers
+ * MSP430x54xx family header
+ *
+ * (c) 2006 by Steve Underwood <steveu@coppice.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * 2008-10-08 - sb-sf (sb-sf@users.sf.net)
+ * - created, based on msp430xG461x.h
+ *
+ * 2009-10-08 - modifications by J.M.Gross <mspgcc@grossibaer.de>
+ * - addeditional includes (TimerB, CRC)
+ * - added usage of base addresses for UCS, timers etc.
+ * - added SR bit constants from common.h (temporary solution)
+ * 2009-11-20 - modifications by J.M.Gross <mspgcc@grossibaer.de>
+ * - split definitions for 8/11port and 2/4 USCI CPUs
+ * - added PMM module
+ *
+ * $Id: msp430x54xx.h,v 1.5 2009/06/04 21:55:18 cliechti Exp $
+ */
+
+#include <iomacros.h>
+
+#define __MSP430_PMM5_BASE__ 0x120
+#define __MSP430_CRC16_BASE__ 0x150
+#define __MSP430_WDT_A_BASE__ 0x150
+#define __MSP430_UCS_BASE__ 0x160
+#define __MSP430_SYS_BASE__ 0x180
+#define __MSP430_PORT1_BASE__ 0x200
+#define __MSP430_PORT2_BASE__ 0x200
+#define __MSP430_PORT3_BASE__ 0x220
+#define __MSP430_PORT4_BASE__ 0x220
+#define __MSP430_PORT5_BASE__ 0x240
+#define __MSP430_PORT6_BASE__ 0x240
+#define __MSP430_PORT7_BASE__ 0x260
+#define __MSP430_PORT8_BASE__ 0x260
+#define __MSP430_PORTJ_BASE__ 0x320
+#define __MSP430_HAS_T0A5__
+#define __MSP430_T0A_BASE__ 0x340
+#define __MSP430_HAS_T1A3__
+#define __MSP430_T1A_BASE__ 0x380
+#define __MSP430_HAS_TB7_5__
+#define __MSP430_TB7_BASE__ 0x3c0
+#define __MSP430_MPY32_BASE__ 0x4C0
+#define __MSP430_USCI5_BASE_0__ 0x5C0
+#define __MSP430_USCI5_BASE_1__ 0x600
+
+#if defined(__MSP430_5438__) || defined(__MSP430_5436__) || defined(__MSP430_5419__)
+#define __MSP430_PORT9_BASE__ 0x280
+#define __MSP430_PORT10_BASE__ 0x280
+#define __MSP430_PORT11_BASE__ 0x2A0
+#define __MSP430_USCI5_BASE_2__ 0x640
+#define __MSP430_USCI5_BASE_3__ 0x680
+#endif
+
+
+#include <msp430/wdt_a.h>
+#include <msp430/sys.h>
+#include <msp430/pmm.h>
+#include <msp430/gpio_5xxx.h>
+#include <msp430/mpy32.h>
+#include <msp430/timera.h>
+#include <msp430/timerb.h>
+#include <msp430/crc16.h>
+#include <msp430/unified_clock_system.h>
+#include <msp430/usci.h>
+
+/*
+
+ Empty yet :(
+
+*/
+#define C 0x0001
+#define Z 0x0002
+#define N 0x0004
+#define V 0x0100
+#define GIE 0x0008
+#define CPUOFF 0x0010
+#define OSCOFF 0x0020
+#define SCG0 0x0040
+#define SCG1 0x0080
+
+
+#define SFRIE1_ 0x0100 /* Interrupt Enable 1 */
+#define SFRIE1_L_ SFRIE1_
+#define SFRIE1_H_ SFRIE1_ + 0x01
+sfrw(SFRIE1, SFRIE1_);
+sfrb(SFRIE1_L, SFRIE1_L_);
+sfrb(IE1, SFRIE1_L_);
+sfrb(SFRIE1_H, SFRIE1_H_);
+sfrb(IE2, SFRIE1_H_);
+#define WDTIE (1<<0)
+#define OFIE (1<<1)
+/* RESERVED (1<<2)*/
+#define VMAIE (1<<3)
+#define NMIIE (1<<4)
+#define ACCVIE (1<<5)
+#define JMBINIE (1<<6)
+#define JMBOUTIE (1<<7)
+
+#define SFRIFG1_ 0x0102 /* Interrupt Flag 1 */
+#define SFRIFG1_L_ SFRIFG1_
+#define SFRIFG1_H_ SFRIFG1_ + 0x01
+sfrw(SFRIFG1, SFRIFG1_);
+sfrb(SFRIFG1_L, SFRIFG1_L_);
+sfrb(IFG1, SFRIFG1_L_);
+sfrb(SFRIFG1_H, SFRIFG1_H_);
+sfrb(IFG2, SFRIFG1_H_);
+#define WDTIFG (1<<0)
+#define OFIFG (1<<1)
+/* RESERVED (1<<2)*/
+#define VMAIFG (1<<3)
+#define NMIIFG (1<<4)
+/* RESERVED (1<<5)*/
+#define JMBINIFG (1<<6)
+#define JMBOUTIFG (1<<7)
+
+#define SFRRPCR_ 0x0104 /* Reset pin control */
+sfrw(SFRRPCR, SFRRPCR_);
+#define SFRRPCR_L_ SFRRPCR_
+#define SFRRPCR_H_ SFRRPCR_ + 0x01
+sfrb(SFRRPCR_L, SFRRPCR_L_);
+sfrb(SFRRPCR_H, SFRRPCR_H_);
+#define SYSNMI (1<<0) /* RST/NMI pin (0:Reset, 1: NMI) */
+#define SYSNMIIES (1<<1) /* NMI edge select (0:rising edge). Can trigger NMI */
+#define SYSRSTUP (1<<2) /* Reset resistor pin pullup (0: pulldown, 1: pullup) */
+#define SYSRSTRE (1<<3) /* Reset pin resistor enable (0: disabled, 1: enabled) */
+
+
+#define RTC_A_VECTOR 0x52 /* 0xFFD2 Basic Timer / RTC */
+#define PORT2_VECTOR 0x54 /* 0xFFD4 Port 2 */
+#define USCIB3_RXTX_VECTOR 0x56 /* 0xFFD6 USCI B3 RX/TX */
+#define USCIA3_RXTX_VECTOR 0x58 /* 0xFFD8 USCI A3 RX/TX */
+#define USCIB1_RXTX_VECTOR 0x5A /* 0xFFDA USCI B1 RX/TX */
+#define USCIA1_RXTX_VECTOR 0x5C /* 0xFFDC USCI A1 RX/TX */
+#define PORT1_VECTOR 0x5E /* 0xFFDE Port 1 */
+#define TIMER1_A1_VECTOR 0x60 /* 0xFFE0 Timer1_A3 CC1-2, TA1 */
+#define TIMER1_A0_VECTOR 0x62 /* 0xFFE2 Timer1_A3 CC0 */
+#define DMA_VECTOR 0x64 /* 0xFFE4 DMA */
+#define USCIB2_RXTX_VECTOR 0x66 /* 0xFFE6 USCI B2 RX/TX */
+#define USCIA2_RXTX_VECTOR 0x68 /* 0xFFE8 USCI A2 RX/TX */
+#define TIMER0_A1_VECTOR 0x6A /* 0xFFEA Timer0_A5 CC1-4, TA0 */
+#define TIMER0_A0_VECTOR 0x6C /* 0xFFEC Timer0_A5 CC0 */
+#define AD12_A_VECTOR 0x6E /* 0xFFEE ADC */
+#define USCIB0_RXTX_VECTOR 0x70 /* 0xFFF0 USCI B0 RX/TX */
+#define USCIA0_RXTX_VECTOR 0x72 /* 0xFFF2 USCI A0 RX/TX */
+#define WDT_VECTOR 0x74 /* 0xFFF4 Watchdog Timer */
+#define TIMER0_B1_VECTOR 0x76 /* 0xFFF6 Timer_B7 CC1-6, TB */
+#define TIMER0_B0_VECTOR 0x78 /* 0xFFF8 Timer_B7 CC0 */
+#define USER_NMI_VECTOR 0x7A /* 0xFFFA Non-maskable */
+#define NMI_VECTOR 0x7C /* 0xFFFC Non-maskable */
+
+#endif /* #ifndef __msp430x54xx */
* (c) 2003 by Steve Underwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: msp430xE42x.h,v 1.4 2005/08/17 14:28:46 coppice Exp $
+ * $Id: msp430xE42x.h,v 1.6 2009/01/11 23:11:48 sb-sf Exp $
*/
#include <iomacros.h>
#define __MSP430_HAS_TA3__
#define __MSP430_HAS_FLASH__
#define __MSP430_HAS_MPY__
-#define __MSP430_HAS_SD16_3__
-#define __MSP430_HAS_ESP430E__
+#define __MSP430_HAS_SD16_CH1__
+#define __MSP430_HAS_SD16_CH2__
+#define __MSP430_SD16IV_BASE__ 0x110
+#define __MSP430_SD16MEM_BASE__ 0x112
+
+#if defined(__MSP430_E423__) || defined(__MSP430_E425__) || defined(__MSP430_E427__)
+#define __MSP430_HAS_ESP430E__ // for backward compability
+#define __MSP430_HAS_ESP430E1A__
+#elif defined(__MSP430_E4232__) || defined(__MSP430_E4242__) || defined(__MSP430_E4252__) || defined(__MSP430_E4272__)
+#define __MSP430_HAS_ESP430E1B__
+#endif
#define __msp430_have_lcd_16_20
#define LCD_BASE 0x90
-#define __msp430_have_sd16_1
-#define __msp430_have_sd16_2
#include <msp430/basic_timer.h>
#include <msp430/system_clock.h>
* (c) 2007 by Steve Underwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: msp430xG42x0.h,v 1.1 2007/10/02 11:33:15 coppice Exp $
+ * $Id: msp430xG42x0.h,v 1.4 2009/04/03 05:25:33 sb-sf Exp $
*/
#include <iomacros.h>
#define __MSP430_HAS_LCD_A__
#define __MSP430_HAS_TA3__
#define __MSP430_HAS_FLASH__
-#define __MSP430_HAS_SD16_1__
+#define __MSP430_HAS_SD16_A__
+#define __MSP430_HAS_SD16_BUF__
+#define __MSP430_SD16IV_BASE__ 0x110
+#define __MSP430_SD16MEM_BASE__ 0x112
#define __MSP430_HAS_DAC12_1__
#define __MSP430_HAS_OA_2__
#define __msp430_have_lcd_a
#define __msp430_have_lcd_16_20
#define LCD_BASE 0x90
-#define __msp430_have_sd16a
#define __msp430_have_dac12_op_amp
#define __msp430_have_opamp_offset_cal
#define __msp430_have_opamp_switches
#include <msp430/basic_timer.h>
#include <msp430/system_clock.h>
-#include <msp430/svs.h>
#include <msp430/lcd_a.h>
#include <msp430/flash.h>
#include <msp430/timera.h>
* (c) 2003 by Steve Underwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: msp430xG43x.h,v 1.7 2006/06/07 13:01:30 coppice Exp $
+ * $Id: msp430xG43x.h,v 1.8 2008/11/07 08:28:40 sb-sf Exp $
*/
#include <iomacros.h>
#define __MSP430_HAS_COMPA__
#define __MSP430_HAS_ADC12__
#define __MSP430_HAS_DAC12_3__
-#define __MSP430_HAS_DMA_1__
+#define __MSP430_HAS_DMA_3__
#define __MSP430_HAS_OA_3__
#define __msp430_have_lcd_16_20
* (c) 2006 by Steve Underwood <steveu@coppice.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: msp430xG461x.h,v 1.8 2007/06/17 15:43:25 coppice Exp $
+ * $Id: msp430xG461x.h,v 1.11 2009/07/26 05:53:27 pjansen Exp $
*/
#include <iomacros.h>
#define __MSP430_HAS_LCD_A__
#define __MSP430_HAS_UART0__
#define __MSP430_HAS_USCI__
+#define __MSP430_HAS_USCI0__
#define __MSP430_HAS_TA3__
#define __MSP430_HAS_TB7__
#define __MSP430_HAS_FLASH__
-#define __MSP430_HAS_CA__
+#define __MSP430_HAS_COMPA__
#define __MSP430_HAS_SVS__
#define __MSP430_HAS_ADC12__
#define __MSP430_HAS_DAC12__
#define __MSP430_HAS_DMAX_3__
+#define __MSP430_HAS_DMAIV__
#define __MSP430_HAS_OA_3__
#define __MSP430_HAS_UART1__
#include <msp430/svs.h>
#include <msp430/lcd_a.h>
#include <msp430/flash.h>
+#include <msp430/compa.h>
#include <msp430/timera.h>
#include <msp430/timerb.h>
#include <msp430/usart.h>
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $Id: signal.h,v 1.15 2006/11/15 14:34:57 coppice Exp $
+ * $Id: signal.h,v 1.17 2009/06/04 21:55:18 cliechti Exp $
*/
#if !defined(__SIGNAL_H_)
#if defined(__MSP430X__)
#define INTERRUPT_VECTOR_SLOTS 32
#define RESET_VECTOR 62
+#elif defined(__MSP430X2__)
+#warning X2 ist da
+#define INTERRUPT_VECTOR_SLOTS 64
+#define RESET_VECTOR 126
#else
#define INTERRUPT_VECTOR_SLOTS 16
#define RESET_VECTOR 30
#endif
-#if !defined(_GNU_ASSEMBLER_)
+#if !defined(__ASSEMBLER__)
#define Interrupt(x) void __attribute__((interrupt (x)))
#define INTERRUPT(x) void __attribute__((interrupt (x)))
#define UNEXPECTED() interrupt (NOVECTOR) _unexpected_(void)
-#else /*_GNU_ASSEMBLER_ / assember definitions*/
+#else /*__ASSEMBLER__ / assember definitions*/
/* Double macro trick to achieve that the x gets expanded*/
#define interrupt(x) xinterrupt(x)
/* Direct generation of the labels is impossible, so just replace the dummy ones
with the real ones through those defs:*/
-#if INTERRUPT_VECTOR_SLOTS == 32
+#if INTERRUPT_VECTOR_SLOTS == 64
+#define vector_0 vector_ff80
+#define vector_2 vector_ff82
+#define vector_4 vector_ff84
+#define vector_6 vector_ff86
+#define vector_8 vector_ff88
+#define vector_10 vector_ff8a
+#define vector_12 vector_ff8c
+#define vector_14 vector_ff8e
+#define vector_16 vector_ff90
+#define vector_18 vector_ff92
+#define vector_20 vector_ff94
+#define vector_22 vector_ff96
+#define vector_24 vector_ff98
+#define vector_26 vector_ff9a
+#define vector_28 vector_ff9c
+#define vector_30 vector_ff9e
+#define vector_32 vector_ffa0
+#define vector_34 vector_ffa2
+#define vector_36 vector_ffa4
+#define vector_38 vector_ffa6
+#define vector_40 vector_ffa8
+#define vector_42 vector_ffaa
+#define vector_44 vector_ffac
+#define vector_46 vector_ffae
+#define vector_48 vector_ffb0
+#define vector_50 vector_ffb2
+#define vector_52 vector_ffb4
+#define vector_54 vector_ffb6
+#define vector_56 vector_ffb8
+#define vector_58 vector_ffba
+#define vector_60 vector_ffbc
+#define vector_62 vector_ffbe
+#define vector_64 vector_ffc0
+#define vector_66 vector_ffc2
+#define vector_68 vector_ffc4
+#define vector_70 vector_ffc6
+#define vector_72 vector_ffc8
+#define vector_74 vector_ffca
+#define vector_76 vector_ffcc
+#define vector_78 vector_ffce
+#define vector_80 vector_ffd0
+#define vector_82 vector_ffd2
+#define vector_84 vector_ffd4
+#define vector_86 vector_ffd6
+#define vector_88 vector_ffd8
+#define vector_90 vector_ffda
+#define vector_92 vector_ffdc
+#define vector_94 vector_ffde
+#define vector_96 vector_ffe0
+#define vector_98 vector_ffe2
+#define vector_100 vector_ffe4
+#define vector_102 vector_ffe6
+#define vector_104 vector_ffe8
+#define vector_106 vector_ffea
+#define vector_108 vector_ffec
+#define vector_110 vector_ffee
+#define vector_112 vector_fff0
+#define vector_114 vector_fff2
+#define vector_116 vector_fff4
+#define vector_118 vector_fff6
+#define vector_120 vector_fff8
+#define vector_122 vector_fffa
+#define vector_124 vector_fffc
+#define vector_126 vector_fffe
+#elif INTERRUPT_VECTOR_SLOTS == 32
#define vector_0 vector_ffc0
#define vector_2 vector_ffc2
#define vector_4 vector_ffc4
#define vector_30 vector_fffe
#endif
-#endif /*_GNU_ASSEMBLER_*/
+#endif /*__ASSEMBLER__*/
#endif
#
# MSP430 libc
#
-# $Id: Makefile,v 1.47 2008/05/17 02:44:59 cliechti Exp $
-#
-VERSION = 20050812
+VERSION = 20090126
# installation prefix (set this if you don't install by hand)
-
-#prefix = /usr
-prefix = /usr/local/msp430
+ifndef PREFIX
+PREFIX = /usr/local/msp430
+endif
# name of target architecture (used for conform naming)
target = msp430
-prefix_target = ${prefix}/${target}
-bindir = ${prefix_target}/bin
+prefix_target = $(PREFIX)/${target}
+bindir = $(PREFIX)/bin
includedir = ${prefix_target}/include
libdir = ${prefix_target}/lib
-srcdir = .
+SRC_ROOT := .
+BUILD_ROOT = ./Build
-CC = ${target}-gcc
-AS = ${target}-gcc -x assembler-with-cpp
-AR = ${target}-ar
+override CC = ${bindir}/msp430-gcc
+override AS = ${bindir}/msp430-gcc -x assembler-with-cpp
+override AR = ${bindir}/msp430-ar
RM = rm
MD = mkdir -p $@
INSTALL = install -c -m644 $^/
-ASFLAGS = -Wa,-gstabs -D_GNU_ASSEMBLER_
-CFLAGS = -Wall -O2 -g
-
+COMMON := $(LIB_OPTIONS)
# make sure we can find our header files (not the installed ones)
+COMMON += -I$(SRC_ROOT)/../include
+COMMON += -I$(SRC_ROOT)
-ALL_ASFLAGS += -I$(srcdir)/../include -I$(srcdir) ${ASFLAGS}
-ALL_CFLAGS += -I$(srcdir)/../include -I$(srcdir) ${CFLAGS}
+override ASFLAGS = $(COMMON)
+ASFLAGS += -Wa,-gdwarf-2
+#ASFLAGS += -Wa,-ahlmsd=$(<:.S=.lst)
+#ASFLAGS += -v
+override CFLAGS = $(COMMON)
+CFLAGS += -Wall -Os -gdwarf-2
-opt_speed_cflags = -O2
-# further declaration...
+# further declaration...
+SRCDIRS = .
ifdef gnu
- source_dirs = gnu
+ SRCDIRS += gnu
else
- source_dirs = bsd
+ SRCDIRS = bsd
endif
+SRCDIRS += stdlib
+SRCDIRS += string
+SRCDIRS += libm
+
+VPATH := $(addprefix $(SRC_ROOT)/, $(SRCDIRS))
+
+
+all: build
+print:
+ @$(CC) --print-multi-lib
+build: build-crt build-multilib
+install: install-crt install-headers install-multilib
+clean:
+ ${RM} -rf $(BUILD_ROOT)
-source_dirs =
-
-VPATH = $(addprefix $(srcdir)/, $(source_dirs))
-
-all: build-crt build-libc build-libm
-
-install: install-crt install-libc install-headers install-libm
-
-clean: clean-crt clean-libc clean-libm
-
-
-crt_all_objs = \
- crt430x110.o crt430x112.o \
- crt430x1101.o crt430x1111.o crt430x1121.o \
- crt430x1122.o crt430x1132.o \
- crt430x122.o crt430x123.o \
- crt430x1222.o crt430x1232.o \
- crt430x133.o crt430x135.o \
- crt430x1331.o crt430x1351.o \
- crt430x147.o crt430x148.o crt430x149.o \
- crt430x1471.o crt430x1481.o crt430x1491.o \
- crt430x155.o crt430x156.o crt430x157.o \
- crt430x167.o crt430x168.o crt430x169.o crt430x1610.o crt430x1611.o crt430x1612.o \
- crt430x2001.o crt430x2011.o \
- crt430x2002.o crt430x2012.o \
- crt430x2003.o crt430x2013.o \
- crt430x2101.o crt430x2111.o crt430x2121.o crt430x2131.o \
- crt430x2234.o crt430x2254.o crt430x2274.o \
- crt430x247.o crt430x248.o crt430x249.o crt430x2410.o \
- crt430x2471.o crt430x2481.o crt430x2491.o \
- crt430x2416.o crt430x2417.o crt430x2418.o crt430x2419.o \
- crt430x2616.o crt430x2617.o crt430x2618.o crt430x2619.o \
- crt430x311.o crt430x312.o crt430x313.o crt430x314.o crt430x315.o \
- crt430x323.o crt430x325.o crt430x336.o crt430x337.o \
- crt430x412.o crt430x413.o crt430x415.o crt430x417.o \
- crt430x423.o crt430x425.o crt430x427.o \
- crt430x4250.o crt430x4260.o crt430x4270.o \
- crt430xE423.o crt430xE425.o crt430xE427.o \
- crt430xW423.o crt430xW425.o crt430xW427.o \
- crt430xG437.o crt430xG438.o crt430xG439.o \
- crt430x435.o crt430x436.o crt430x437.o \
- crt430x447.o crt430x448.o crt430x449.o \
- crt430xG4616.o crt430xG4617.o crt430xG4618.o crt430xG4619.o
-
-build-crt: ${crt_all_objs}
+.PHONY: clean clean-crt clean-multilib
+
+#--------- crt ---------------------------------------
+BUILDDIR := $(BUILD_ROOT)
+MCU_MSP_LIST := $(strip $(shell $(CC) --target-help | sed -n '/Known MCU names/,/no/p' | sed -n '/msp430/p' 2>/dev/null))
+MCU_CC430_LIST := $(strip $(shell $(CC) --target-help | sed -n '/Known MCU names/,/no/p' | sed -n '/cc430/p' 2>/dev/null))
+CRT_MSP_OBJS := $(addprefix $(BUILDDIR)/, $(addsuffix .o,$(subst msp,crt,$(MCU_MSP_LIST))))
+CRT_CC430_OBJS := $(addprefix $(BUILDDIR)/, $(addsuffix .o,$(subst cc430,crtcc430,$(MCU_CC430_LIST))))
# match by name
+$(CRT_MSP_OBJS): $(BUILDDIR)/crt%.o: gcrt0.S stdlib/__low_level_init.S
+ ${AS} $(ASFLAGS) $(subst crt, -mmcu=msp, $(subst .o,,$(notdir $@))) -c $< -o $@
+
+$(CRT_CC430_OBJS): $(BUILDDIR)/crt%.o: gcrt0.S stdlib/__low_level_init.S
+ ${AS} $(ASFLAGS) $(subst crtcc, -mmcu=cc, $(subst .o,,$(notdir $@))) -c $< -o $@
+
+CRT_OBJS := $(CRT_MSP_OBJS) $(CRT_CC430_OBJS)
-${crt_all_objs}: crt%.o: gcrt0.S
- ${AS} ${CPPFLAGS} -mmcu=msp$* ${ALL_ASFLAGS} -c $(ABSPATH)$< -o $@
+crt: build-crt install-crt
+
+build-crt: makedir-crt $(CRT_OBJS)
clean-crt:
- ${RM} -f ${crt_all_objs}
+ ${RM} -f $(CRT_OBJS)
+
+install-crt: $(CRT_OBJS) ${libdir}
+ ${INSTALL}
-install-crt: ${crt_all_objs} ${libdir}
+makedir-crt:
+ mkdir -p $(BUILDDIR)
+
+#------- multilib --------
+multilib: build-multilib install-multilib
+build-multilib:
+ for i in `$(CC) --print-multi-lib 2>/dev/null`; do \
+ dir=`echo $$i | sed -e 's/;.*$$//'` ; \
+ options=`echo $$i | sed -e 's/[^@]*//' -e 's/@/ -/g'`; \
+ $(MAKE) "MULTILIB_DIR=$$dir" "LIB_OPTIONS=$$options" build-libc build-libm ; \
+ done;
+
+install-multilib:
+ for i in `$(CC) --print-multi-lib 2>/dev/null`; do \
+ dir=`echo $$i | sed -e 's/;.*$$//'` ; \
+ mkdir -p $(libdir)/$$dir; \
+ $(MAKE) MULTILIB_DIR="$$dir" install-libc install-libm ; \
+ done;
+
+.PHONY: clean-multilib clean-libc clean-libm
+clean-multilib:
+ for i in `$(CC) --print-multi-lib 2>/dev/null`; do \
+ dir=`echo $$i | sed -e 's/;.*$$//'` ; \
+ $(MAKE) "MULTILIB_DIR=$$dir" clean-libc clean-libm; \
+ done;
+
+#--------------- headers ---------------
+
+install-headers: ins-hr ins-hs ins-msp430
+
+ins-hr: $(wildcard $(SRC_ROOT)/../include/*.h) ${includedir}
${INSTALL}
-#--------------- a bit of libc
+ins-hs: $(wildcard $(SRC_ROOT)/../include/sys/*.h) ${includedir}/sys
+ ${INSTALL}
-libc_libs = msp1/libc.a msp2/libc.a
+ins-msp430: $(wildcard $(SRC_ROOT)/../include/msp430/*.h) ${includedir}/msp430
+ ${INSTALL}
+
+fix-limits: $(wildcard $(SRC_ROOT)/../include/limits.h) ${includedir}/../../lib/gcc-lib/msp430/3.0/include
+ ${INSTALL}
+
+#--------------- directories ---------------
+$(includedir) $(includedir)/sys $(includedir)/msp430:
+ $(MD)
+#------------------------------------------------------------------------
+#------------------------------------------------------------------------
+#------------------------------------------------------------------------
+#--------------- libc ------------------------
+BUILDDIR=$(BUILD_ROOT)/$(subst .,msp1,$(MULTILIB_DIR))
+LIBC = $(BUILDDIR)/libc.a
libc_c_sources = abs.c atol.c bsearch.c errno.c labs.c \
_init_section__.c malloc.c atoi.c strtol.c strtoul.c \
printf.c vprintf.c vuprintf.c uprintf.c puts.c \
rand.c itoa.c ltoa.c utoa.c ultoa.c
-libc_asm_sources = abort.S div.S exit.S ldiv.S setjmp.S
+libc_asm_sources = abort.S div.S exit.S ldiv.S setjmp.S \
+__do_clear_bss.S __do_copy_data.S __do_global_ctors.S \
+__do_global_dtors.S __init_stack.S __jump_to_main.S \
+__stop_progexec__.S _reset_vector__.S \
+_unexpected_.S
+
libc_str_sources = \
isascii.c memccpy.c strchr.c strncat.c swab.c \
isalpha.c isxdigit.c strcat.c strncasecmp.c strtok.c \
ispunct.c
+LIBC_OBJS = $(addprefix $(BUILDDIR)/,$(libc_str_sources:.c=.o) $(libc_c_sources:.c=.o) $(libc_asm_sources:.S=.o) )
+build-libc: create_libdir $(LIBC)
+create_libdir:
+ mkdir -p $(BUILDDIR)
-libc_msp430_ct_objs_1 = ${libc_c_sources:%.c=%.o}
-libc_msp430_ct_objs_2 = ${libc_c_sources:%.c=%.o}
-
-libc_msp430_asmt_objs_1 = ${libc_asm_sources:%.S=%.o}
-libc_msp430_asmt_objs_2 = ${libc_asm_sources:%.S=%.o}
-
-
-
-libc_msp430_c_objs_1 = $(addprefix msp1/, $(libc_msp430_ct_objs_1))
-libc_msp430_c_objs_2 = $(addprefix msp2/, $(libc_msp430_ct_objs_2))
-
-libc_msp430_S_objs_1 = $(addprefix msp1/, $(libc_msp430_asmt_objs_1))
-libc_msp430_S_objs_2 = $(addprefix msp2/, $(libc_msp430_asmt_objs_2))
-
-
-libc_msp430_objs_1 = ${libc_msp430_c_objs_1}
-libc_msp430_objs_2 = ${libc_msp430_c_objs_2}
-
-
-build-libc: mspdirs ${libc_libs}
-
-mspdirs:
- mkdir -p msp1 msp2
+$(BUILDDIR)/%.o: %.c
+ ${CC} -c $(CFLAGS) $< -o $@
-${libc_msp430_objs_1}: msp1/%.o: stdlib/%.c
- ${CC} -c ${CPPFLAGS} ${ALL_CFLAGS} -mmcu=msp1 -c $(ABSPATH)$< -o $@
-
-${libc_msp430_objs_2}: msp2/%.o: stdlib/%.c
- ${CC} -c ${CPPFLAGS} ${ALL_CFLAGS} -mmcu=msp2 -c $(ABSPATH)$< -o $@
-
-${libc_msp430_S_objs_1}: msp1/%.o: stdlib/%.S
- ${AS} -D_GNU_ASSEMBLER_ -mmcu=msp1 -c $(ABSPATH)$< -o $@
-
-${libc_msp430_S_objs_2}: msp2/%.o: stdlib/%.S
- ${AS} -D_GNU_ASSEMBLER_ -mmcu=msp2 -c $(ABSPATH)$< -o $@
-
-libc_msp430_cstr_objs_1 = ${libc_str_sources:%.c=%.o}
-libc_msp430_cstr_objs_2 = ${libc_str_sources:%.c=%.o}
-
-libc_msp430_str_objs_1 = $(addprefix msp1/, $(libc_msp430_cstr_objs_1))
-libc_msp430_str_objs_2 = $(addprefix msp2/, $(libc_msp430_cstr_objs_2))
-
-
-${libc_msp430_str_objs_1}: msp1/%.o: string/%.c
- ${CC} -c ${CPPFLAGS} ${ALL_CFLAGS} -mmcu=msp1 -c $(ABSPATH)$< -o $@
-
-${libc_msp430_str_objs_2}: msp2/%.o: string/%.c
- ${CC} -c ${CPPFLAGS} ${ALL_CFLAGS} -mmcu=msp2 -c $(ABSPATH)$< -o $@
-
-
-all_objs1 = ${libc_msp430_objs_1} ${libc_msp430_str_objs_1} ${libc_msp430_S_objs_1}
-all_objs2 = ${libc_msp430_objs_2} ${libc_msp430_str_objs_2} ${libc_msp430_S_objs_2}
-
-msp1/libc.a: ${all_objs1}
- ${AR} rc $@ $?
+$(BUILDDIR)/%.o: %.S
+ ${AS} -c $(ASFLAGS) $< -o $@
-msp2/libc.a: ${all_objs2}
+$(LIBC): $(LIBC_OBJS)
${AR} rc $@ $?
.PHONY: clean-libc
clean-libc:
- ${RM} -f msp1/libc.a msp2/libc.a msp1/*.o msp2/*.o
+ ${RM} -f $(LIBC) $(LIBC_OBJS)
-install-libc: ins-msp1 ins-msp2 ins-lib
-
-ins-msp1: msp1/libc.a ${libdir}/msp1
- ${INSTALL}
-
-ins-msp2: msp2/libc.a ${libdir}/msp2
- ${INSTALL}
-
-ins-lib: msp1/libc.a ${libdir}
- ${INSTALL}
-
-#--------------- headers ---------------
-
-install-headers: ins-hr ins-hs ins-msp430
-
-ins-hr: $(wildcard $(srcdir)/../include/*.h) ${includedir}
- ${INSTALL}
-
-ins-hs: $(wildcard $(srcdir)/../include/sys/*.h) ${includedir}/sys
+install-libc: $(LIBC) $(libdir)/$(MULTILIB_DIR)
${INSTALL}
-
-ins-msp430: $(wildcard $(srcdir)/../include/msp430/*.h) ${includedir}/msp430
- ${INSTALL}
-
-fix-limits: $(wildcard $(srcdir)/../include/limits.h) ${includedir}/../../lib/gcc-lib/msp430/3.0/include
- ${INSTALL}
-
-#--------------- directories ---------------
-libc_dirs = msp1 msp2
-install_lib_dirs = $(libdir) $(libdir)/msp1 $(libdir)/msp2
-
-$(libc_dirs) $(install_lib_dirs) $(includedir) $(includedir)/sys $(includedir)/msp430:
- $(MD)
-
-
-#------------------------------------------------------------------------
-#------------------------------------------------------------------------
-#------------------------------------------------------------------------
#------------------------------------------------------------------------
#-------------- Math & FP libs ---------------
math: build-libm
-
basic_fp = divsf.c fixsfsi.c floatdisf.c gtsf.c mulsf.c \
addsf.c eqsf.c fixunssfdi.c floatsisf.c lesf.c negsf.c \
cmpsf.c fixsfdi.c fixunssfsi.c gesf.c ltsf.c subsf.c nesf.c
ef_fmod.c ef_rem_pio2.c kf_rem_pio2.c sf_cos.c sf_infinity.c sf_nextafter.c
-libm_libs = msp1/libm.a msp2/libm.a msp1/libfp.a msp2/libfp.a
-
-libm_msp430_fp_objs_1 = ${basic_fp:%.c=%.o}
-libm_msp430_fp_objs_2 = ${basic_fp:%.c=%.o}
-
-libm_msp430_fc_objs_1 = ${fppfunc:%.c=%.o}
-libm_msp430_fc_objs_2 = ${fppfunc:%.c=%.o}
-
-
-libm_msp430_c_objs_1 = $(addprefix msp1/, $(libm_msp430_fp_objs_1))
-libm_msp430_c_objs_2 = $(addprefix msp2/, $(libm_msp430_fp_objs_2))
-
-libm_msp430_cf_objs_1 = $(addprefix msp1/, $(libm_msp430_fc_objs_1))
-libm_msp430_cf_objs_2 = $(addprefix msp2/, $(libm_msp430_fc_objs_2))
-
-
-build-libm: ${libm_libs}
-
-${libm_msp430_c_objs_1}: msp1/%.o: libm/%.c
- ${CC} -c ${CPPFLAGS} ${ALL_CFLAGS} -mmcu=msp1 -c $(ABSPATH)$< -o $@
-
-${libm_msp430_c_objs_2}: msp2/%.o: libm/%.c
- ${CC} -c ${CPPFLAGS} ${ALL_CFLAGS} -mmcu=msp2 -c $(ABSPATH)$< -o $@
-
-
-${libm_msp430_cf_objs_1}: msp1/%.o: libm/%.c
- ${CC} ${CPPFLAGS} -mmcu=msp1 ${ALL_CFLAGS} -c $(ABSPATH)$< -o $@
+LIBM = $(BUILDDIR)/libm.a
+LIBFP = $(BUILDDIR)/libfp.a
+LIBM_OBJS = $(addprefix $(BUILDDIR)/,$(notdir $(fppfunc:%.c=%.o)))
+LIBFP_OBJS = $(addprefix $(BUILDDIR)/,$(notdir $(basic_fp:%.c=%.o)))
-${libm_msp430_cf_objs_2}: msp2/%.o: libm/%.c
- ${CC} ${CPPFLAGS} -mmcu=msp2 ${ALL_CFLAGS} -c $(ABSPATH)$< -o $@
+build-libm: create_libdir $(LIBM) $(LIBFP)
-
-allm_objs1 = ${libm_msp430_cf_objs_1}
-allm_objs2 = ${libm_msp430_cf_objs_2}
-
-msp1/libm.a: ${allm_objs1}
- ${AR} rc $@ $?
-
-msp2/libm.a: ${allm_objs2}
- ${AR} rc $@ $?
-
-msp1/libfp.a:${libm_msp430_c_objs_1}
+$(LIBM): $(LIBM_OBJS)
${AR} rc $@ $?
-
-msp2/libfp.a:${libm_msp430_c_objs_2}
+$(LIBFP): $(LIBFP_OBJS)
${AR} rc $@ $?
-install-libm: insm-msp1 insm-msp2 insm-lib
-
-insm-msp1: msp1/libm.a msp1/libfp.a ${libdir}/msp1
- ${INSTALL}
-
-insm-msp2: msp2/libm.a msp2/libfp.a ${libdir}/msp2
- ${INSTALL}
-
-insm-lib: msp1/libm.a ${libdir}
+install-libm: $(LIBM) $(LIBFP) $(libdir)/$(MULTILIB_DIR)
${INSTALL}
-.PHONY: clean-libm
clean-libm:
- ${RM} -f msp1/libm.a msp2/libm.a msp1/libfp.a msp2/libfp.a msp1/*.o msp2/*.o
+ ${RM} -f $(LIBM) $(LIBFP) $(LIBM_OBJS) $(LIBFP_OBJS)
--- /dev/null
+#ifndef __CORE_COMMON_H__
+#define __CORE_COMMON_H__
+#if defined (__ASSEMBLER__)
+
+/*
+ * if __MSP430X2__ defined, __MSP430X__ is defined too
+ * so we check for __MSP430X__ only
+ */
+#if defined(__MSP430X__)
+ #if defined(__MSP430X_ADDR_16BIT__)
+ #define XBR br
+ #define XCALL call
+ #define XRET ret
+ #define XMOVA mov
+ #define XCMP cmp
+ #else
+ #define XBR bra
+ #define XCALL calla
+ #define XRET reta
+ #define XMOVA mova
+ #define XCMP cmpa
+ #endif
+ #if defined(__MSP430X_REGS_16BIT__)
+ #define XPUSH pushx.w
+ #define XPOP popx.w
+ #define XPUSHM pushm.w
+ #define XPOPM popm.w
+ #define XMOV movx.w
+ .equ PUSH_BYTES, 2
+ #else
+ #define XPUSH pushx.a
+ #define XPOP popx.a
+ #define XPUSHM pushm.a
+ #define XPOPM popm.a
+ #define XMOV movx.a
+ .equ PUSH_BYTES, 4
+ #endif
+#else
+ #define XBR br
+ #define XCALL call
+ #define XRET ret
+ #define XMOV mov
+ #define XCMP cmp
+ #define XPUSH push
+ #define XPOP pop
+ #define XMOVA mov
+ .equ PUSH_BYTES, 2
+#endif
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* __CORE_COMMON_H__ */
;; -*- mode: asm -*-
+
#include <io.h>
+#include "core_common.inc"
+/***************************************************************
+ * Declare registers used in library routines
+ ***************************************************************/
+.macro MAKE_WEAK name
+ .weak __\name
+ .set __\name, \name
+.endm
+ MAKE_WEAK WDTCTL
+#if defined (__MSP430_HAS_HW_MUL__)
+ MAKE_WEAK MPY
+ MAKE_WEAK MPYS
+ MAKE_WEAK MAC
+ MAKE_WEAK MACS
+ MAKE_WEAK OP2
+ MAKE_WEAK RESLO
+ MAKE_WEAK RESHI
+ MAKE_WEAK SUMEXT
+#if defined (__MSP430_HAS_HW_MUL32__)
+ MAKE_WEAK MPY32L
+ MAKE_WEAK MPY32H
+ MAKE_WEAK MPYS32L
+ MAKE_WEAK MPYS32H
+ MAKE_WEAK MAC32L
+ MAKE_WEAK MAC32H
+ MAKE_WEAK MACS32L
+ MAKE_WEAK MACS32H
+ MAKE_WEAK OP2L
+ MAKE_WEAK OP2H
+ MAKE_WEAK RES0
+ MAKE_WEAK RES1
+ MAKE_WEAK RES2
+ MAKE_WEAK RES3
+ MAKE_WEAK MPY32CTL0
+#endif
+#endif
+
+/***************************************************************
+ * Include routines that reference chip-specific values
+ ***************************************************************/
+#include "stdlib/__low_level_init.S"
/***************************************************************
* Interrupt Vectors:
* WARNING!!! All vectors must be defined here!!!
* User may not define its interrupt service routines!
***************************************************************/
-
- .weak _unexpected_
- .global _unexpected_1_
-
- .text
+ .text
.p2align 1,0
+_branch_to_unexpected_:
+ XBR #_unexpected_
-_unexpected_1_:
- br #_unexpected_
-_unexpected_:
- reti
-
-.section .vectors, "ax", @progbits
+ .section .vectors, "ax", @progbits
.macro VEC name
- .weak \name
- .set \name, _unexpected_1_
+ .weak \name
+ .equ \name, _branch_to_unexpected_
.word \name
.endm
.global InterruptVectors
.type InterruptVectors, @object
-#if defined(__MSP430X__)
- .size InterruptVectors, 0x40
+#if defined(__MSP430X2__)
+ .size InterruptVectors, 0x80
+#elif defined(__MSP430X__)
+ .size InterruptVectors, 0x40
+#else
+ .size InterruptVectors, 0x20
+#endif
+
InterruptVectors:
+#if defined(__MSP430X2__)
+/* 80 */ VEC vector_ff80
+/* 82 */ VEC vector_ff82
+/* 84 */ VEC vector_ff84
+/* 86 */ VEC vector_ff86
+/* 88 */ VEC vector_ff88
+/* 8a */ VEC vector_ff8a
+/* 8c */ VEC vector_ff8c
+/* 8e */ VEC vector_ff8e
+/* 90 */ VEC vector_ff90
+/* 92 */ VEC vector_ff92
+/* 94 */ VEC vector_ff94
+/* 96 */ VEC vector_ff96
+/* 98 */ VEC vector_ff98
+/* 9a */ VEC vector_ff9a
+/* 9c */ VEC vector_ff9c
+/* 9e */ VEC vector_ff9e
+/* a0 */ VEC vector_ffa0
+/* a2 */ VEC vector_ffa2
+/* a4 */ VEC vector_ffa4
+/* a6 */ VEC vector_ffa6
+/* a8 */ VEC vector_ffa8
+/* aa */ VEC vector_ffaa
+/* ac */ VEC vector_ffac
+/* ae */ VEC vector_ffae
+/* b0 */ VEC vector_ffb0
+/* b2 */ VEC vector_ffb2
+/* b4 */ VEC vector_ffb4
+/* b6 */ VEC vector_ffb6
+/* b8 */ VEC vector_ffb8
+/* ba */ VEC vector_ffba
+/* bc */ VEC vector_ffbc
+/* be */ VEC vector_ffbe
+#endif
+#if defined(__MSP430X__) || defined(__MSP430X2__)
/* c0 */ VEC vector_ffc0
/* c2 */ VEC vector_ffc2
/* c4 */ VEC vector_ffc4
/* da */ VEC vector_ffda
/* dc */ VEC vector_ffdc
/* de */ VEC vector_ffde
-#else
- .size InterruptVectors, 0x20
-InterruptVectors:
#endif
/* e0 */ VEC vector_ffe0
/* e2 */ VEC vector_ffe2
/* f8 */ VEC vector_fff8
/* fa */ VEC vector_fffa
/* fc */ VEC vector_fffc
- .word _reset_vector__
+ .word _reset_vector__
/* end of Interrupt vectors declarations */
+2009-01-23 Sergey A. Borshch <sb-sf (_at_) users.sourceforge.net>
+ Modified files:
+ sqrt.S
+
+ * sqrt.S: 430X core compability added. -msave-prologue compiler
+ option compability added.
+
2003-08-07 Chris Takahashi <ctakahashi (_at_) users.sourceforge.net>
Modified files:
subsf.c
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $Id: sqrt.S,v 1.1 2002/08/30 11:53:44 diwil Exp $
+ * $Id: sqrt.S,v 1.1.2.1 2009/01/26 15:47:13 sb-sf Exp $
*/
+ #include "../core_common.inc"
.file "sqrt.S"
-
+
.text
.p2align 1,0
.global sqrt
tst r15
jn .Lsqrt_err
- push argsave_lo
- push argsave_hi
- push y_lo
- push y_hi
- push yprev_lo
- push yprev_hi
+#if defined(__MSP430X__)
+ XPUSHM #6, r11
+#else
+ push yprev_hi
+ push yprev_lo
+ push y_hi
+ push y_lo
+ push argsave_hi
+ push argsave_lo
+#endif
mov r14, argsave_lo
mov r15, argsave_hi
mov y_hi, r13
mov argsave_lo, r14 ; arg/y
mov argsave_hi, r15
- call #__divsf3
+ XCALL #__divsf3
mov y_lo, r12 ; +y
mov y_hi, r13
- call #__addsf3
+ XCALL #__addsf3
mov #llo(0x3f000000), r12 ; *0.5
mov #lhi(0x3f000000), r13
call #__mulsf3
mov y_lo, r14
mov y_hi, r15
- pop yprev_hi
- pop yprev_lo
- pop y_hi
- pop y_lo
- pop argsave_hi
- pop argsave_lo
- ret
+#if defined(__MSP430X__)
+ XPOPM #6, r11
+ XRET
+#elif defined(__MSP430_SAVE_PROLOGUE__)
+ br #__epilogue_restorer + 2 * 2
+#else
+ pop argsave_lo
+ pop argsave_hi
+ pop y_lo
+ pop y_hi
+ pop yprev_lo
+ pop yprev_hi
+ ret
+#endif
.Lsqrt_err:
mov #0xffff, r14
--- /dev/null
+/*****************************************************************
+ * Initialize data: clear .bss
+ * can be overwriten by user function with the same name
+ *****************************************************************/
+ .section .init4, "ax", @progbits
+
+ .weak __do_clear_bss
+ .func __do_clear_bss
+
+__do_clear_bss:
+ mov #__bss_size, r15
+ tst r15
+ jz .L__clear_bss_end
+.L__clear_bss_loop:
+ dec r15
+ clr.b __bss_start(r15) ; RAM is always in lower 64K, so 430 instruction
+ ; is acceptable here for 430X core too.
+ jne .L__clear_bss_loop
+.L__clear_bss_end:
+
+ .endfunc
--- /dev/null
+/*****************************************************************
+ * Initialize data: copy data
+ * from __data_load_start ( = _etext) to __data_start
+ * can be overwriten by user function with the same name
+ *****************************************************************/
+ .section .init4, "ax", @progbits
+
+ .weak __do_copy_data
+ .func __do_copy_data
+
+__do_copy_data:
+ mov #__data_size, r15
+ tst r15
+ jz .L__copy_data_end
+.L__copy_data_loop:
+ decd r15
+#if defined(__MSP430X__) && !defined(__MSP430X_ADDR_16BIT__)
+ ; __data_load_start can be anywhere, use 430X instruction
+ movx.w __data_load_start(r15), __data_start(r15) ; data section is word-aligned, so word transfer is acceptable
+#else
+ ; __data_load_start is in lower 64K, RAM is in lower 64K, use 430 instruction
+ mov.w __data_load_start(r15), __data_start(r15) ; data section is word-aligned, so word transfer is acceptable
+#endif
+ jne .L__copy_data_loop
+.L__copy_data_end:
+
+ .endfunc
--- /dev/null
+#include "../core_common.inc"
+/*****************************************************************
+ * Call C++ global and static objects constructors
+ * can be overwriten by user function with the same name
+ *****************************************************************/
+ .section .init6, "ax", @progbits
+
+ .weak __do_global_ctors
+ .func __do_global_ctors
+
+
+__do_global_ctors:
+
+ XMOVA #__ctors_start, r11
+ XMOVA #__ctors_end, r10
+.L__ctors_loop:
+ XCALL @r11+ ; call constructor
+ XCMP r10, r11
+ jne .L__ctors_loop
+
+ ; require linking of stack initialization
+ .global __init_stack ; stack has to be set before constructors calling
+
+ .endfunc
--- /dev/null
+#include "../core_common.inc"
+/*****************************************************************
+ * Call C++ global and static objects destructors
+ * can be overwriten by user function with the same name
+ *****************************************************************/
+ .section .fini6,"ax",@progbits
+
+ .weak __do_global_dtors
+ .func __do_global_dtors
+
+__do_global_dtors:
+ XMOVA #__dtors_start, r11
+ XMOVA #__dtors_end, r10
+.L__dtors_loop:
+ XCALL @r11+
+ XCMP r10, r11
+ jne .L__dtors_loop
+
+ .endfunc
--- /dev/null
+/*****************************************************************
+ * Set stack pointer
+ * can be overwriten by user function with the same name
+ *****************************************************************/
+ .section .init2, "ax", @progbits
+
+ .weak __init_stack
+ .func __init_stack
+
+__init_stack:
+ mov #__stack, r1 ; stack always located on first 64K, so 430 instruction
+ ; is acceptable here for 430X core too.
+
+ .endfunc
--- /dev/null
+#include "../core_common.inc"
+/*****************************************************************
+ * jump to main.
+ * can be overwriten by user function with the same name
+ *****************************************************************/
+ .section .init9, "ax", @progbits
+
+ .weak __jump_to_main
+ .func __jump_to_main
+
+__jump_to_main:
+ XBR #main
+
+ .endfunc
--- /dev/null
+/*****************************************************************
+ * Initialize peripherial, particularly disable watchdog
+ * can be overwriten by user function with the same name
+ *****************************************************************/
+ .section .init3, "ax", @progbits
+
+ .weak __low_level_init
+ .func __low_level_init
+
+__low_level_init:
+ mov #0x5a80, &__WDTCTL
+
+ .endfunc
--- /dev/null
+/*****************************************************************
+ * return from main.
+ * can be overwriten by user function with the same name
+ *****************************************************************/
+ .section .fini9, "ax", @progbits
+
+ .weak __stop_progExec__
+ .func __stop_progExec__
+
+__stop_progExec__:
+
+ .endfunc
+
+/*****************************************************************
+ * endless loop
+ * can be overwriten by user together with __stop_progExec__
+ * this function always linked together with __stop_progExec__,
+ * because both are located in single source file.
+ *****************************************************************/
+ .section .fini0, "ax", @progbits
+
+ .func _endless_loop__
+_endless_loop__:
+ jmp _endless_loop__
+
+ .endfunc
int _init_section__(int section)
{
uint16_t start, stop, size, stack, ret = 0;
- void *from, *where;
+ char *from, *where;
if(section == MSP430_SECTION_BSS)
{
- (uint16_t *)start = &__bss_start;
- (uint16_t *)stop = &__bss_end;
+ start = (uint16_t)&__bss_start;
+ stop = (uint16_t)&__bss_end;
bzero(&__bss_start,stop-start);
return ret;
}
else if(section == MSP430_SECTION_DATA)
{
- (uint16_t *)start = &__data_start_rom;
- (uint16_t *)stop = &_edata;
- from = (void *)&_etext;
- where = (void *)&__data_start;
+ start = (uint16_t)&__data_start_rom;
+ stop = (uint16_t)&_edata;
+ from = (char *)&_etext;
+ where = (char *)&__data_start;
size = ret = stop - start;
}
else if(section == MSP430_SECTION_NOINIT)
{
- (uint16_t *)start = &__noinit_start_rom;
- (uint16_t *)stop = &__noinit_end_rom;
- from = (void *)&__noinit_start_rom;
- where = (void *)&__bss_end;
+ start = (uint16_t)&__noinit_start_rom;
+ stop = (uint16_t)&__noinit_end_rom;
+ from = (char *)&__noinit_start_rom;
+ where = (char *)&__bss_end;
size = ret = stop - start;
}
else
while(size--)
{
- *((char *)where)++ = *((char *)from)++;
+ *(where)++ = *(from)++;
}
return ret;
--- /dev/null
+/*****************************************************************
+ * Program starts here.
+ * overwriting this label in the user program
+ * causes removing all startup code except __do_global_ctors
+ *****************************************************************/
+ .section .init0, "ax", @progbits
+ .weak _reset_vector__
+ .func _reset_vector__
+
+ .p2align 1,0
+_reset_vector__:
+
+; stack can be initialized in main() prologue,
+; but setting stack pointer here allows to call subroutines
+; from startup code and call constructors of statically allocated C++ objects.
+; Stack pointer will have the same value entering main() as here,
+; so -mno-stack-init can be used to reduce code size.
+; initial stack value can be set in ld script as __stack symbol
+; (end of RAM by default), or via -defsym __stack=<address> ld option
+; or via -Wl,defsym,__stack=<address> gcc option, or by redefining
+; __init_stack function as fololws:
+;
+;#if defined (__cplusplus)
+;extern "C"
+;#endif
+;__attribute__((__naked__)) __attribute__((section(".init2"))) void __init_stack()
+;{
+; asm volatile("\tmov\t#stack_addr, r1\n");
+;}
+;
+ /* request following functions to be linked if library _reset_vector__ used */
+
+ .global __init_stack
+
+ .global __low_level_init
+ .global __do_copy_data
+ .global __do_clear_bss
+ .global __jump_to_main
+
+ .endfunc
--- /dev/null
+/*****************************************************************
+ * unexpected interrupt vector handler
+ * can be overwriten by user function with the same name:
+ * interrupt(NOVECTOR) _unexpected_()
+ * {
+ *
+ * }
+ *
+ *****************************************************************/
+
+ .weak _unexpected_
+
+ .text
+ .p2align 1,0
+
+_unexpected_:
+ reti
+#include "../core_common.inc"
/* ldiv() is the same as __divmodsi4() in libgcc */
.section .text
.global div
div:
;; save clobbers first
- push r10
+#if defined(__MSP430X__)
+ XPUSHM #2, r11
+#else
push r11
+ push r10
+#endif
;; mov registers.
mov r14, r10 ;; denom
mov r15, r12 ;; num
;; divide
- call #__divmodhi4
- mov r14, r15
- mov r12, r14
+ XCALL #__divmodhi4
+ mov r14, r15
+ mov r12, r14
;; result is in there already...
;; restore regs and return.
- pop r11
+#if defined(__MSP430X__)
+ XPOPM #2, r11
+ XRET
+#elif defined(__MSP430_SAVE_PROLOGUE__)
+ br #__epilogue_restorer + 6 * 2
+#else
pop r10
+ pop r11
ret
-
+#endif
temp[temp_loc++] = digit + '0';
else
temp[temp_loc++] = digit - 10 + 'A';
- ((unsigned int)num) /= radix;
+ num = (((unsigned int)num) / radix);
} while ((unsigned int)num > 0);
//now add the sign for radix 10
+#include "../core_common.inc"
/* ldiv() is the same as __divmodsi4() in libgcc */
.section .text
.global ldiv
ldiv:
;; save clobbers first
- push r8
- push r9
- push r10
+#if defined(__MSP430X__)
+ XPUSHM #2, r11
+#else
push r11
+ push r10
+ push r9
+ push r8
+#endif
;; mov registers.
mov r13, r11 ;; denom
mov r12, r10
call #__divmodsi4
;; result is in there already...
;; restore regs and return.
- pop r11
- pop r10
- pop r9
+#if defined(__MSP430X__)
+ XPOPM #4, r11
+ XRET
+#elif defined(__MSP430_SAVE_PROLOGUE__)
+ br #__epilogue_restorer + 4 * 2
+#else
pop r8
+ pop r9
+ pop r10
+ pop r11
ret
-
+#endif
temp[temp_loc++] = digit + '0';
else
temp[temp_loc++] = digit - 10 + 'A';
- ((unsigned long)num) /= radix;
+ num = ((unsigned long)num) / radix;
} while ((unsigned long)num > 0);
//now add the sign for radix 10
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $Id: mul10.S,v 1.2 2002/01/16 14:06:35 diwil Exp $
+ * $Id: mul10.S,v 1.2.2.1 2009/01/26 15:47:13 sb-sf Exp $
*/
/*
* int mul10(int)
* Actually, the compiler does it better!
*/
-
+#include "../core_common.inc"
.section .text
.global __mulhi_const_10
__mulhi_const_10:
rla r15
add r14, r15
rla r15
- ret
+ XRET
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details. */
+/*
+ 2009-01-25 Sergey A. Borshch (sb-sf@users-sourceforge.net)
+ - 430X compability added.
+ - storage order changed, code improved:
+ now: 87 cycles, 76 bytes (430) / 98 cycles, 78 bytes (430X)
+ was: 101 cycles, 98 bytes (430) / 120 cycles, 108 bytes (430X)
+*/
/*
extern int setjmp(jmp_buf __jmpb);
extern void longjmp(jmp_buf __jmpb, int __ret) __ATTR_NORETURN__;
*/
-
+#include "../core_common.inc"
.section .text
.global setjmp
.global longjmp
-
setjmp:
- mov @r1, 0(r15) ; save return address
- mov r1, 2(r15) ; stack pointer
- incd 2(r15) ; postdec saved SP cause it contains ret addr
- mov r2, 4(r15) ; status register
- mov r4, 6(r15)
- mov r5, 8(r15)
- mov r6, 10(r15)
- mov r7, 12(r15)
- mov r8, 14(r15)
- mov r9, 16(r15)
- mov r10, 18(r15)
- mov r11, 20(r15)
- mov #0, r15 ; return value
- ret
-
-
-longjmp:
- mov r15, r13
- mov r14, r15 ; r15 now contains a return value
- mov 2(r13), r1 ; restore registers
- mov 4(r13), r2
- mov 6(r13), r4
- mov 8(r13), r5
- mov 10(r13), r6
- mov 12(r13), r7
- mov 14(r13), r8
- mov 16(r13), r9
- mov 18(r13), r10
- mov 20(r13), r11
- br 0(r13) ; jump...
-
+ XPOP PUSH_BYTES * 10(r15) ; save return address and adjust sp
+ XMOVA r1, PUSH_BYTES * 0(r15) ; stack pointer
+ XMOVA r2, PUSH_BYTES * 1(r15) ; status register
+ XMOVA r4, PUSH_BYTES * 2(r15)
+ XMOVA r5, PUSH_BYTES * 3(r15)
+ XMOVA r6, PUSH_BYTES * 4(r15)
+ XMOVA r7, PUSH_BYTES * 5(r15)
+ XMOVA r8, PUSH_BYTES * 6(r15)
+ XMOVA r9, PUSH_BYTES * 7(r15)
+ XMOVA r10, PUSH_BYTES * 8(r15)
+ XMOVA r11, PUSH_BYTES * 9(r15)
+ XMOVA #0, r15 ; return value
+ XBR -PUSH_BYTES(r1)
+
+longjump:
+ XMOVA r15, r13
+ XMOVA r14, r15 ; r15 now contains a return value
+ XMOVA @r13+, r1 ; restore registers
+ XMOVA @R13+, r2
+ XMOVA @R13+, r4
+ XMOVA @R13+, r5
+ XMOVA @R13+, r6
+ XMOVA @R13+, r7
+ XMOVA @R13+, r8
+ XMOVA @R13+, r9
+ XMOVA @R13+, r10
+ XMOVA @R13+, r11
+ XBR @R13 ; jump...
temp[temp_loc++] = digit + '0';
else
temp[temp_loc++] = digit - 10 + 'A';
- ((unsigned long)num) /= radix;
+ num = ((unsigned long)num) / radix;
} while ((unsigned long)num > 0);
temp_loc--;
temp[temp_loc++] = digit + '0';
else
temp[temp_loc++] = digit - 10 + 'A';
- ((unsigned int)num) /= radix;
+ num = ((unsigned int)num) / radix;
} while ((unsigned int)num > 0);
temp_loc--;
projects / msp430-libc.git / commitdiff