--- /dev/null
+# Copyright (c) 2009-2010 People Power Co.
+# All rights reserved.
+#
+# This open source code was developed with funding from People Power Company.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# - Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# - Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the
+# distribution.
+# - Neither the name of the People Power Corporation nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# PEOPLE POWER CO. OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+# OF THE POSSIBILITY OF SUCH DAMAGE
+#
+
+"""Convert Texas Instruments header file sections to MSPGCC-format
+header files.
+
+To generate an MSPGCC header file derived from a TI header file,
+create a foo.h.in file containing the MSPGCC header for module foo,
+along with the necessary conditional inclusion directives. Into the
+body, stick the extracted text from the relevant section of the TI
+chip-specific header for a chip that incorporates the module. Update
+the address maps in this script to define the offsets for memory
+locations in this module, and run the script on the input file to
+generate the header.
+
+@author Peter A. Bigot <pab@peoplepowerco.com>
+"""
+
+import sys
+import re
+
+inf = file(sys.argv[1])
+
+# Regular expressions to recognize and extract the relevant pieces of
+# TI address definitions
+re20 = re.compile('^SFR_20BIT\((\w*)\);\s*(/\*.*\*/)')
+re16 = re.compile('^SFR_16BIT\((\w*)\);\s*(/\*.*\*/)')
+re8 = re.compile('^SFR_8BIT\((\w*)\);\s*(/\*.*\*/)')
+
+tagmap = { }
+addrmap = { }
+
+def addAddressMap (module_tag, local_map, map_tag=None):
+ global addrmap
+ global tagmap
+ if map_tag is None:
+ map_tag = module_tag
+ for (tag, offset) in local_map.items():
+ gtag = '%s%s' % (module_tag, tag)
+ addrmap[gtag] = offset
+ tagmap[gtag] = map_tag
+
+addAddressMap('RF1A', { 'IFCTL0' : 0,
+ 'IFCTL1' : 2,
+ 'IFCTL2' : 4,
+ 'IFERR' : 6,
+ 'IFERRV' : 0x0c,
+ 'IFIV' : 0x0e,
+ 'INSTRW' : 0x10,
+ 'INSTR1W' : 0x12,
+ 'INSTR2W' : 0x14,
+ 'DINW' : 0x16,
+ 'STAT0W' : 0x20,
+ 'STAT1W' : 0x22,
+ 'STAT2W' : 0x24,
+ 'DOUT0W' : 0x28,
+ 'DOUT1W' : 0x2A,
+ 'DOUT2W' : 0x2C,
+ 'IN' : 0x30,
+ 'IFG' : 0x32,
+ 'IES' : 0x34,
+ 'IE' : 0x36,
+ 'IV' : 0x38,
+ 'RXFIFO' : 0x3c,
+ 'TXFIFO' : 0x3e })
+addAddressMap('AES', { 'ACTL0' : 0x00,
+ 'ASTAT' : 0x04,
+ 'AKEY' : 0x06,
+ 'ADIN' : 0x08,
+ 'ADOUT' : 0x0a })
+addAddressMap('RTC', { 'CTL01' : 0x00,
+ 'CTL23' : 0x02,
+ 'PS0CTL' : 0x08,
+ 'PS1CTL' : 0x0a,
+ 'PS' : 0x0c,
+ 'IV' : 0x0e,
+ 'TIM0': 0x10,
+ 'TIM1' : 0x12,
+ 'DATE' : 0x14,
+ 'YEAR' : 0x16,
+ 'AMINHR' : 0x18,
+ 'ADOWDAY' : 0x1A })
+
+addAddressMap('LCDB', { 'CTL0' : 0x00,
+ 'CTL1' : 0x02,
+ 'BLKCTL' : 0x04,
+ 'MEMCTL' : 0x06,
+ 'VCTL' : 0x08,
+ 'PCTL0' : 0x0a,
+ 'PCTL1' : 0x0c,
+ 'PCTL2' : 0x0e,
+ 'PCTL3' : 0x10,
+ 'CPCTL' : 0x12,
+ 'IV' : 0x1e }, map_tag='LCD_B' )
+# LCD memory
+addAddressMap('LCD', dict([( 'M%d' % (1+_i), 0x20 + _i) for _i in xrange(26) ]), 'LCD_B')
+# LCD blinking memory
+addAddressMap('LCDB', dict([( 'M%d' % (1+_i), 0x40 + _i) for _i in xrange(26) ]), 'LCD_B')
+
+addAddressMap('REF', { 'CTL0' : 0x00 })
+
+addAddressMap('ADC12', { 'CTL0' : 0x00,
+ 'CTL1' : 0x02,
+ 'CTL2' : 0x04,
+ 'IFG' : 0x0a,
+ 'IE' : 0x0c,
+ 'IV' : 0x0e }, map_tag='ADC12_PLUS')
+addAddressMap('ADC12MEM', dict([( '%d' % (_i,), 0x20 + _i) for _i in xrange(16) ]), map_tag='ADC12_PLUS')
+addAddressMap('ADC12MCTL', dict([( '%d' % (_i,), 0x10 + _i) for _i in xrange(16) ]), map_tag='ADC12_PLUS')
+
+addAddressMap('DMA', { 'CTL0' : 0x00,
+ 'CTL1' : 0x02,
+ 'CTL2' : 0x04,
+ 'CTL3' : 0x06,
+ 'CTL4' : 0x08,
+ 'IV' : 0x0e })
+for ch in xrange(8):
+ offset = 0x0 * (1 + ch)
+ addAddressMap('DMA%d' % ch, { 'CTL' : 0x00 + offset,
+ 'SA' : 0x02 + offset,
+ 'DA' : 0x06 + offset,
+ 'SZ' : 0x0a + offset },
+ map_tag='DMA')
+
+for usci in xrange(4):
+ for (mtype, offs) in ( ('A', 0x00) , ( 'B', 0x20) ):
+ addAddressMap('UC%c%d' % (mtype, usci),
+ { 'CTLW0' : 0x00 + offs,
+ 'CTL1' : 0x00 + offs, # yes, CTL1 is at offset 0
+ 'CTL0' : 0x01 + offs, # yes, CTL0 is at offset 1
+ 'BRW' : 0x06 + offs,
+ 'BR0' : 0x06 + offs,
+ 'BR1' : 0x07 + offs,
+ 'MCTL' : 0x08 + offs,
+ 'STAT' : 0x0a + offs,
+ 'RXBUF' : 0x0c + offs,
+ 'TXBUF' : 0x0e + offs,
+ 'ICTL' : 0x1c + offs,
+ 'IFG' : 0x1d + offs,
+ 'IV' : 0x1e + offs },
+ map_tag='USCI%d' % (usci,))
+ # USCI UART-mode
+ addAddressMap('UCA%d' % (usci,),
+ { 'ABCTL' : 0x10,
+ 'IRCTL' : 0x12,
+ 'IRTCTL' : 0x12,
+ 'IRRCTL' : 0x13 },
+ map_tag='USCI%d' % (usci,))
+ # USCI I2C mode
+ addAddressMap('UCB%d' % (usci,),
+ { 'I2COA' : 0x30,
+ 'I2CSA' : 0x32 },
+ map_tag='USCI%d' % (usci,))
+
+addAddressMap('CB', { 'CTL0' : 0x00,
+ 'CTL1' : 0x02,
+ 'CTL2' : 0x04,
+ 'CTL3' : 0x06,
+ 'INT' : 0x0c,
+ 'IV' : 0x0e },
+ map_tag='COMPB')
+
+
+for ln in inf.readlines():
+ word_id = 'w'
+ mo = re16.match(ln)
+ if not mo:
+ # NOTE: Headers generated for MSP430X will need hand-editing
+ # to support on MSP430. If __MSP430_HAS_DMAX_3__ is defined,
+ # include both the 20- and 16-bit names as generated.
+ # Otherwise, use the 20-bit name on the 16-bit register.
+ mo = re20.match(ln)
+ word_id = 'a'
+ if mo:
+ (tag, comment) = mo.groups()
+ xtag = tag
+ addr = addrmap.get(xtag)
+ if (addr is None) and xtag.endswith('L'):
+ xtag = xtag[:-1]
+ addr = addrmap[xtag]
+ maptag = tagmap[xtag]
+ if 'a' == word_id:
+ print '#if defined(__MSP430_HAS_DMAX_3__)'
+ print '''#define %s_ __MSP430_%s_BASE__ + 0x%02x %s
+sfr%s(%s, %s_);''' % (tag, maptag, addr, comment, word_id, tag, tag)
+ if 'a' == word_id:
+ print '#endif // __MSP430_HAS_DMAX_3__'
+ continue
+ mo = re8.match(ln)
+ if mo:
+ (tag, comment) = mo.groups()
+ assert tag.find('_'), tag
+ maptag = tagmap.get(tag)
+ if tag.find('_'):
+ try:
+ (rtag, stag) = tag.split('_')
+ addr = addrmap[rtag]
+ maptag = tagmap[rtag]
+ if 'H' == stag:
+ addr += 1
+ comment = ''
+ except ValueError:
+ addr = addrmap[tag]
+ else:
+ addr = addrmap[tag]
+ print '''#define %s_ __MSP430_%s_BASE__ + 0x%02x %s
+sfrb(%s, %s_);''' % (tag, maptag, addr, comment, tag, tag)
+ continue
+ print ln[:-1]
projects / msp430-libc.git / blobdiff